hw/display/ati.c

   1 /*
   2  * QEMU ATI SVGA emulation
   3  *
   4  * Copyright (c) 2019 BALATON Zoltan
   5  *
   6  * This work is licensed under the GNU GPL license version 2 or later.
   7  */
   8
   9 /*
  10  * WARNING:
  11  * This is very incomplete and only enough for Linux console and some
  12  * unaccelerated X output at the moment.
  13  * Currently it's little more than a frame buffer with minimal functions,
  14  * other more advanced features of the hardware are yet to be implemented.
  15  * We only aim for Rage 128 Pro (and some RV100) and 2D only at first,
  16  * No 3D at all yet (maybe after 2D works, but feel free to improve it)
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "ati_int.h"
  21 #include "ati_regs.h"
  22 #include "vga_regs.h"
  23 #include "qemu/log.h"
  24 #include "qemu/module.h"
  25 #include "qemu/error-report.h"
  26 #include "qapi/error.h"
  27 #include "hw/hw.h"
  28 #include "ui/console.h"
  29 #include "hw/display/i2c-ddc.h"
  30 #include "trace.h"
  31
  32 #define ATI_DEBUG_HW_CURSOR 0
  33
  34 static const struct {
  35     const char *name;
  36     uint16_t dev_id;
  37 } ati_model_aliases[] = {
  38     { "rage128p", PCI_DEVICE_ID_ATI_RAGE128_PF },
  39     { "rv100", PCI_DEVICE_ID_ATI_RADEON_QY },
  40 };
  41
  42 enum { VGA_MODE, EXT_MODE };
  43
  44 static void ati_vga_switch_mode(ATIVGAState *s)
  45 {
  46     DPRINTF("%d -> %d\n",
  47             s->mode, !!(s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN));
  48     if (s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN) {
  49         /* Extended mode enabled */
  50         s->mode = EXT_MODE;
  51         if (s->regs.crtc_gen_cntl & CRTC2_EN) {
  52             /* CRT controller enabled, use CRTC values */
  53             uint32_t offs = s->regs.crtc_offset & 0x07ffffff;
  54             int stride = (s->regs.crtc_pitch & 0x7ff) * 8;
  55             int bpp = 0;
  56             int h, v;
  57
  58             if (s->regs.crtc_h_total_disp == 0) {
  59                 s->regs.crtc_h_total_disp = ((640 / 8) - 1) << 16;
  60             }
  61             if (s->regs.crtc_v_total_disp == 0) {
  62                 s->regs.crtc_v_total_disp = (480 - 1) << 16;
  63             }
  64             h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8;
  65             v = (s->regs.crtc_v_total_disp >> 16) + 1;
  66             switch (s->regs.crtc_gen_cntl & CRTC_PIX_WIDTH_MASK) {
  67             case CRTC_PIX_WIDTH_4BPP:
  68                 bpp = 4;
  69                 break;
  70             case CRTC_PIX_WIDTH_8BPP:
  71                 bpp = 8;
  72                 break;
  73             case CRTC_PIX_WIDTH_15BPP:
  74                 bpp = 15;
  75                 break;
  76             case CRTC_PIX_WIDTH_16BPP:
  77                 bpp = 16;
  78                 break;
  79             case CRTC_PIX_WIDTH_24BPP:
  80                 bpp = 24;
  81                 break;
  82             case CRTC_PIX_WIDTH_32BPP:
  83                 bpp = 32;
  84                 break;
  85             default:
  86                 qemu_log_mask(LOG_UNIMP, "Unsupported bpp value\n");
  87             }
  88             assert(bpp != 0);
  89             DPRINTF("Switching to %dx%d %d %d @ %x\n", h, v, stride, bpp, offs);
  90             vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE);
  91             vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED);
  92             /* reset VBE regs then set up mode */
  93             s->vga.vbe_regs[VBE_DISPI_INDEX_XRES] = h;
  94             s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] = v;
  95             s->vga.vbe_regs[VBE_DISPI_INDEX_BPP] = bpp;
  96             /* enable mode via ioport so it updates vga regs */
  97             vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE);
  98             vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_ENABLED |
  99                 VBE_DISPI_LFB_ENABLED | VBE_DISPI_NOCLEARMEM |
 100                 (s->regs.dac_cntl & DAC_8BIT_EN ? VBE_DISPI_8BIT_DAC : 0));
 101             /* now set offset and stride after enable as that resets these */
 102             if (stride) {
 103                 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_VIRT_WIDTH);
 104                 vbe_ioport_write_data(&s->vga, 0, stride);
 105                 if (offs % stride == 0) {
 106                     vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_Y_OFFSET);
 107                     vbe_ioport_write_data(&s->vga, 0, offs / stride);
 108                 } else {
 109                     /* FIXME what to do with this? */
 110                     error_report("VGA offset is not multiple of pitch, "
 111                                  "expect bad picture");
 112                 }
 113             }
 114         }
 115     } else {
 116         /* VGA mode enabled */
 117         s->mode = VGA_MODE;
 118         vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE);
 119         vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED);
 120     }
 121 }
 122
 123 /* Used by host side hardware cursor */
 124 static void ati_cursor_define(ATIVGAState *s)
 125 {
 126     uint8_t data[1024];
 127     uint8_t *src;
 128     int i, j, idx = 0;
 129
 130     if ((s->regs.cur_offset & BIT(31)) || s->cursor_guest_mode) {
 131         return; /* Do not update cursor if locked or rendered by guest */
 132     }
 133     /* FIXME handle cur_hv_offs correctly */
 134     src = s->vga.vram_ptr + (s->regs.crtc_offset & 0x07ffffff) +
 135           s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) -
 136           (s->regs.cur_hv_offs & 0xffff) * 16;
 137     for (i = 0; i < 64; i++) {
 138         for (j = 0; j < 8; j++, idx++) {
 139             data[idx] = src[i * 16 + j];
 140             data[512 + idx] = src[i * 16 + j + 8];
 141         }
 142     }
 143     if (!s->cursor) {
 144         s->cursor = cursor_alloc(64, 64);
 145     }
 146     cursor_set_mono(s->cursor, s->regs.cur_color1, s->regs.cur_color0,
 147                     &data[512], 1, &data[0]);
 148     dpy_cursor_define(s->vga.con, s->cursor);
 149 }
 150
 151 /* Alternatively support guest rendered hardware cursor */
 152 static void ati_cursor_invalidate(VGACommonState *vga)
 153 {
 154     ATIVGAState *s = container_of(vga, ATIVGAState, vga);
 155     int size = (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) ? 64 : 0;
 156
 157     if (s->regs.cur_offset & BIT(31)) {
 158         return; /* Do not update cursor if locked */
 159     }
 160     if (s->cursor_size != size ||
 161         vga->hw_cursor_x != s->regs.cur_hv_pos >> 16 ||
 162         vga->hw_cursor_y != (s->regs.cur_hv_pos & 0xffff) ||
 163         s->cursor_offset != s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) -
 164         (s->regs.cur_hv_offs & 0xffff) * 16) {
 165         /* Remove old cursor then update and show new one if needed */
 166         vga_invalidate_scanlines(vga, vga->hw_cursor_y, vga->hw_cursor_y + 63);
 167         vga->hw_cursor_x = s->regs.cur_hv_pos >> 16;
 168         vga->hw_cursor_y = s->regs.cur_hv_pos & 0xffff;
 169         s->cursor_offset = s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) -
 170                            (s->regs.cur_hv_offs & 0xffff) * 16;
 171         s->cursor_size = size;
 172         if (size) {
 173             vga_invalidate_scanlines(vga,
 174                                      vga->hw_cursor_y, vga->hw_cursor_y + 63);
 175         }
 176     }
 177 }
 178
 179 static void ati_cursor_draw_line(VGACommonState *vga, uint8_t *d, int scr_y)
 180 {
 181     ATIVGAState *s = container_of(vga, ATIVGAState, vga);
 182     uint8_t *src;
 183     uint32_t *dp = (uint32_t *)d;
 184     int i, j, h;
 185
 186     if (!(s->regs.crtc_gen_cntl & CRTC2_CUR_EN) ||
 187         scr_y < vga->hw_cursor_y || scr_y >= vga->hw_cursor_y + 64 ||
 188         scr_y > s->regs.crtc_v_total_disp >> 16) {
 189         return;
 190     }
 191     /* FIXME handle cur_hv_offs correctly */
 192     src = s->vga.vram_ptr + (s->regs.crtc_offset & 0x07ffffff) +
 193           s->cursor_offset + (scr_y - vga->hw_cursor_y) * 16;
 194     dp = &dp[vga->hw_cursor_x];
 195     h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8;
 196     for (i = 0; i < 8; i++) {
 197         uint32_t color;
 198         uint8_t abits = src[i];
 199         uint8_t xbits = src[i + 8];
 200         for (j = 0; j < 8; j++, abits <<= 1, xbits <<= 1) {
 201             if (abits & BIT(7)) {
 202                 if (xbits & BIT(7)) {
 203                     color = dp[i * 8 + j] ^ 0xffffffff; /* complement */
 204                 } else {
 205                     continue; /* transparent, no change */
 206                 }
 207             } else {
 208                 color = (xbits & BIT(7) ? s->regs.cur_color1 :
 209                                           s->regs.cur_color0) << 8 | 0xff;
 210             }
 211             if (vga->hw_cursor_x + i * 8 + j >= h) {
 212                 return; /* end of screen, don't span to next line */
 213             }
 214             dp[i * 8 + j] = color;
 215         }
 216     }
 217 }
 218
 219 static uint64_t ati_i2c(bitbang_i2c_interface *i2c, uint64_t data, int base)
 220 {
 221     bool c = (data & BIT(base + 17) ? !!(data & BIT(base + 1)) : 1);
 222     bool d = (data & BIT(base + 16) ? !!(data & BIT(base)) : 1);
 223
 224     bitbang_i2c_set(i2c, BITBANG_I2C_SCL, c);
 225     d = bitbang_i2c_set(i2c, BITBANG_I2C_SDA, d);
 226
 227     data &= ~0xf00ULL;
 228     if (c) {
 229         data |= BIT(base + 9);
 230     }
 231     if (d) {
 232         data |= BIT(base + 8);
 233     }
 234     return data;
 235 }
 236
 237 static inline uint64_t ati_reg_read_offs(uint32_t reg, int offs,
 238                                          unsigned int size)
 239 {
 240     if (offs == 0 && size == 4) {
 241         return reg;
 242     } else {
 243         return extract32(reg, offs * BITS_PER_BYTE, size * BITS_PER_BYTE);
 244     }
 245 }
 246
 247 static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size)
 248 {
 249     ATIVGAState *s = opaque;
 250     uint64_t val = 0;
 251
 252     switch (addr) {
 253     case MM_INDEX:
 254         val = s->regs.mm_index;
 255         break;
 256     case MM_DATA ... MM_DATA + 3:
 257         /* indexed access to regs or memory */
 258         if (s->regs.mm_index & BIT(31)) {
 259             uint32_t idx = s->regs.mm_index & ~BIT(31);
 260             if (idx <= s->vga.vram_size - size) {
 261                 val = ldn_le_p(s->vga.vram_ptr + idx, size);
 262             }
 263         } else {
 264             val = ati_mm_read(s, s->regs.mm_index + addr - MM_DATA, size);
 265         }
 266         break;
 267     case BIOS_0_SCRATCH ... BUS_CNTL - 1:
 268     {
 269         int i = (addr - BIOS_0_SCRATCH) / 4;
 270         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) {
 271             break;
 272         }
 273         val = ati_reg_read_offs(s->regs.bios_scratch[i],
 274                                 addr - (BIOS_0_SCRATCH + i * 4), size);
 275         break;
 276     }
 277     case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3:
 278         val = ati_reg_read_offs(s->regs.crtc_gen_cntl,
 279                                 addr - CRTC_GEN_CNTL, size);
 280         break;
 281     case CRTC_EXT_CNTL ... CRTC_EXT_CNTL + 3:
 282         val = ati_reg_read_offs(s->regs.crtc_ext_cntl,
 283                                 addr - CRTC_EXT_CNTL, size);
 284         break;
 285     case DAC_CNTL:
 286         val = s->regs.dac_cntl;
 287         break;
 288     case GPIO_VGA_DDC:
 289         val = s->regs.gpio_vga_ddc;
 290         break;
 291     case GPIO_DVI_DDC:
 292         val = s->regs.gpio_dvi_ddc;
 293         break;
 294     case GPIO_MONID ... GPIO_MONID + 3:
 295         val = ati_reg_read_offs(s->regs.gpio_monid,
 296                                 addr - GPIO_MONID, size);
 297         break;
 298     case PALETTE_INDEX:
 299         /* FIXME unaligned access */
 300         val = vga_ioport_read(&s->vga, VGA_PEL_IR) << 16;
 301         val |= vga_ioport_read(&s->vga, VGA_PEL_IW) & 0xff;
 302         break;
 303     case PALETTE_DATA:
 304         val = vga_ioport_read(&s->vga, VGA_PEL_D);
 305         break;
 306     case CNFG_MEMSIZE:
 307         val = s->vga.vram_size;
 308         break;
 309     case MC_STATUS:
 310         val = 5;
 311         break;
 312     case RBBM_STATUS:
 313     case GUI_STAT:
 314         val = 64; /* free CMDFIFO entries */
 315         break;
 316     case CRTC_H_TOTAL_DISP:
 317         val = s->regs.crtc_h_total_disp;
 318         break;
 319     case CRTC_H_SYNC_STRT_WID:
 320         val = s->regs.crtc_h_sync_strt_wid;
 321         break;
 322     case CRTC_V_TOTAL_DISP:
 323         val = s->regs.crtc_v_total_disp;
 324         break;
 325     case CRTC_V_SYNC_STRT_WID:
 326         val = s->regs.crtc_v_sync_strt_wid;
 327         break;
 328     case CRTC_OFFSET:
 329         val = s->regs.crtc_offset;
 330         break;
 331     case CRTC_OFFSET_CNTL:
 332         val = s->regs.crtc_offset_cntl;
 333         break;
 334     case CRTC_PITCH:
 335         val = s->regs.crtc_pitch;
 336         break;
 337     case 0xf00 ... 0xfff:
 338         val = pci_default_read_config(&s->dev, addr - 0xf00, size);
 339         break;
 340     case CUR_OFFSET:
 341         val = s->regs.cur_offset;
 342         break;
 343     case CUR_HORZ_VERT_POSN:
 344         val = s->regs.cur_hv_pos;
 345         val |= s->regs.cur_offset & BIT(31);
 346         break;
 347     case CUR_HORZ_VERT_OFF:
 348         val = s->regs.cur_hv_offs;
 349         val |= s->regs.cur_offset & BIT(31);
 350         break;
 351     case CUR_CLR0:
 352         val = s->regs.cur_color0;
 353         break;
 354     case CUR_CLR1:
 355         val = s->regs.cur_color1;
 356         break;
 357     case DST_OFFSET:
 358         val = s->regs.dst_offset;
 359         break;
 360     case DST_PITCH:
 361         val = s->regs.dst_pitch;
 362         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
 363             val &= s->regs.dst_tile << 16;
 364         }
 365         break;
 366     case DST_WIDTH:
 367         val = s->regs.dst_width;
 368         break;
 369     case DST_HEIGHT:
 370         val = s->regs.dst_height;
 371         break;
 372     case SRC_X:
 373         val = s->regs.src_x;
 374         break;
 375     case SRC_Y:
 376         val = s->regs.src_y;
 377         break;
 378     case DST_X:
 379         val = s->regs.dst_x;
 380         break;
 381     case DST_Y:
 382         val = s->regs.dst_y;
 383         break;
 384     case DP_GUI_MASTER_CNTL:
 385         val = s->regs.dp_gui_master_cntl;
 386         break;
 387     case SRC_OFFSET:
 388         val = s->regs.src_offset;
 389         break;
 390     case SRC_PITCH:
 391         val = s->regs.src_pitch;
 392         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
 393             val &= s->regs.src_tile << 16;
 394         }
 395         break;
 396     case DP_BRUSH_BKGD_CLR:
 397         val = s->regs.dp_brush_bkgd_clr;
 398         break;
 399     case DP_BRUSH_FRGD_CLR:
 400         val = s->regs.dp_brush_frgd_clr;
 401         break;
 402     case DP_SRC_FRGD_CLR:
 403         val = s->regs.dp_src_frgd_clr;
 404         break;
 405     case DP_SRC_BKGD_CLR:
 406         val = s->regs.dp_src_bkgd_clr;
 407         break;
 408     case DP_CNTL:
 409         val = s->regs.dp_cntl;
 410         break;
 411     case DP_DATATYPE:
 412         val = s->regs.dp_datatype;
 413         break;
 414     case DP_MIX:
 415         val = s->regs.dp_mix;
 416         break;
 417     case DP_WRITE_MASK:
 418         val = s->regs.dp_write_mask;
 419         break;
 420     case DEFAULT_OFFSET:
 421         val = s->regs.default_offset;
 422         break;
 423     case DEFAULT_PITCH:
 424         val = s->regs.default_pitch;
 425         break;
 426     case DEFAULT_SC_BOTTOM_RIGHT:
 427         val = s->regs.default_sc_bottom_right;
 428         break;
 429     default:
 430         break;
 431     }
 432     if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) {
 433         trace_ati_mm_read(size, addr, ati_reg_name(addr & ~3ULL), val);
 434     }
 435     return val;
 436 }
 437
 438 static inline void ati_reg_write_offs(uint32_t *reg, int offs,
 439                                       uint64_t data, unsigned int size)
 440 {
 441     if (offs == 0 && size == 4) {
 442         *reg = data;
 443     } else {
 444         *reg = deposit32(*reg, offs * BITS_PER_BYTE, size * BITS_PER_BYTE,
 445                          data);
 446     }
 447 }
 448
 449 static void ati_mm_write(void *opaque, hwaddr addr,
 450                            uint64_t data, unsigned int size)
 451 {
 452     ATIVGAState *s = opaque;
 453
 454     if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) {
 455         trace_ati_mm_write(size, addr, ati_reg_name(addr & ~3ULL), data);
 456     }
 457     switch (addr) {
 458     case MM_INDEX:
 459         s->regs.mm_index = data;
 460         break;
 461     case MM_DATA ... MM_DATA + 3:
 462         /* indexed access to regs or memory */
 463         if (s->regs.mm_index & BIT(31)) {
 464             uint32_t idx = s->regs.mm_index & ~BIT(31);
 465             if (idx <= s->vga.vram_size - size) {
 466                 stn_le_p(s->vga.vram_ptr + idx, size, data);
 467             }
 468         } else {
 469             ati_mm_write(s, s->regs.mm_index + addr - MM_DATA, data, size);
 470         }
 471         break;
 472     case BIOS_0_SCRATCH ... BUS_CNTL - 1:
 473     {
 474         int i = (addr - BIOS_0_SCRATCH) / 4;
 475         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) {
 476             break;
 477         }
 478         ati_reg_write_offs(&s->regs.bios_scratch[i],
 479                            addr - (BIOS_0_SCRATCH + i * 4), data, size);
 480         break;
 481     }
 482     case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3:
 483     {
 484         uint32_t val = s->regs.crtc_gen_cntl;
 485         ati_reg_write_offs(&s->regs.crtc_gen_cntl,
 486                            addr - CRTC_GEN_CNTL, data, size);
 487         if ((val & CRTC2_CUR_EN) != (s->regs.crtc_gen_cntl & CRTC2_CUR_EN)) {
 488             if (s->cursor_guest_mode) {
 489                 s->vga.force_shadow = !!(s->regs.crtc_gen_cntl & CRTC2_CUR_EN);
 490             } else {
 491                 if (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) {
 492                     ati_cursor_define(s);
 493                 }
 494                 dpy_mouse_set(s->vga.con, s->regs.cur_hv_pos >> 16,
 495                               s->regs.cur_hv_pos & 0xffff,
 496                               (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) != 0);
 497             }
 498         }
 499         if ((val & (CRTC2_EXT_DISP_EN | CRTC2_EN)) !=
 500             (s->regs.crtc_gen_cntl & (CRTC2_EXT_DISP_EN | CRTC2_EN))) {
 501             ati_vga_switch_mode(s);
 502         }
 503         break;
 504     }
 505     case CRTC_EXT_CNTL ... CRTC_EXT_CNTL + 3:
 506     {
 507         uint32_t val = s->regs.crtc_ext_cntl;
 508         ati_reg_write_offs(&s->regs.crtc_ext_cntl,
 509                            addr - CRTC_EXT_CNTL, data, size);
 510         if (s->regs.crtc_ext_cntl & CRT_CRTC_DISPLAY_DIS) {
 511             DPRINTF("Display disabled\n");
 512             s->vga.ar_index &= ~BIT(5);
 513         } else {
 514             DPRINTF("Display enabled\n");
 515             s->vga.ar_index |= BIT(5);
 516             ati_vga_switch_mode(s);
 517         }
 518         if ((val & CRT_CRTC_DISPLAY_DIS) !=
 519             (s->regs.crtc_ext_cntl & CRT_CRTC_DISPLAY_DIS)) {
 520             ati_vga_switch_mode(s);
 521         }
 522         break;
 523     }
 524     case DAC_CNTL:
 525         s->regs.dac_cntl = data & 0xffffe3ff;
 526         s->vga.dac_8bit = !!(data & DAC_8BIT_EN);
 527         break;
 528     case GPIO_VGA_DDC:
 529         if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) {
 530             /* FIXME: Maybe add a property to select VGA or DVI port? */
 531         }
 532         break;
 533     case GPIO_DVI_DDC:
 534         if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) {
 535             s->regs.gpio_dvi_ddc = ati_i2c(s->bbi2c, data, 0);
 536         }
 537         break;
 538     case GPIO_MONID ... GPIO_MONID + 3:
 539         /* FIXME What does Radeon have here? */
 540         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
 541             ati_reg_write_offs(&s->regs.gpio_monid,
 542                                addr - GPIO_MONID, data, size);
 543             /*
 544              * Rage128p accesses DDC used to get EDID via these bits.
 545              * Only touch i2c when write overlaps 3rd byte because some
 546              * drivers access this reg via multiple partial writes and
 547              * without this spurious bits would be sent.
 548              */
 549             if ((s->regs.gpio_monid & BIT(25)) &&
 550                 addr <= GPIO_MONID + 2 && addr + size > GPIO_MONID + 2) {
 551                 s->regs.gpio_monid = ati_i2c(s->bbi2c, s->regs.gpio_monid, 1);
 552             }
 553         }
 554         break;
 555     case PALETTE_INDEX ... PALETTE_INDEX + 3:
 556         if (size == 4) {
 557             vga_ioport_write(&s->vga, VGA_PEL_IR, (data >> 16) & 0xff);
 558             vga_ioport_write(&s->vga, VGA_PEL_IW, data & 0xff);
 559         } else {
 560             if (addr == PALETTE_INDEX) {
 561                 vga_ioport_write(&s->vga, VGA_PEL_IW, data & 0xff);
 562             } else {
 563                 vga_ioport_write(&s->vga, VGA_PEL_IR, data & 0xff);
 564             }
 565         }
 566         break;
 567     case PALETTE_DATA ... PALETTE_DATA + 3:
 568         data <<= addr - PALETTE_DATA;
 569         data = bswap32(data) >> 8;
 570         vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff);
 571         data >>= 8;
 572         vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff);
 573         data >>= 8;
 574         vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff);
 575         break;
 576     case CRTC_H_TOTAL_DISP:
 577         s->regs.crtc_h_total_disp = data & 0x07ff07ff;
 578         break;
 579     case CRTC_H_SYNC_STRT_WID:
 580         s->regs.crtc_h_sync_strt_wid = data & 0x17bf1fff;
 581         break;
 582     case CRTC_V_TOTAL_DISP:
 583         s->regs.crtc_v_total_disp = data & 0x0fff0fff;
 584         break;
 585     case CRTC_V_SYNC_STRT_WID:
 586         s->regs.crtc_v_sync_strt_wid = data & 0x9f0fff;
 587         break;
 588     case CRTC_OFFSET:
 589         s->regs.crtc_offset = data & 0xc7ffffff;
 590         break;
 591     case CRTC_OFFSET_CNTL:
 592         s->regs.crtc_offset_cntl = data; /* FIXME */
 593         break;
 594     case CRTC_PITCH:
 595         s->regs.crtc_pitch = data & 0x07ff07ff;
 596         break;
 597     case 0xf00 ... 0xfff:
 598         /* read-only copy of PCI config space so ignore writes */
 599         break;
 600     case CUR_OFFSET:
 601         if (s->regs.cur_offset != (data & 0x87fffff0)) {
 602             s->regs.cur_offset = data & 0x87fffff0;
 603             ati_cursor_define(s);
 604         }
 605         break;
 606     case CUR_HORZ_VERT_POSN:
 607         s->regs.cur_hv_pos = data & 0x3fff0fff;
 608         if (data & BIT(31)) {
 609             s->regs.cur_offset |= data & BIT(31);
 610         } else if (s->regs.cur_offset & BIT(31)) {
 611             s->regs.cur_offset &= ~BIT(31);
 612             ati_cursor_define(s);
 613         }
 614         if (!s->cursor_guest_mode &&
 615             (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) && !(data & BIT(31))) {
 616             dpy_mouse_set(s->vga.con, s->regs.cur_hv_pos >> 16,
 617                           s->regs.cur_hv_pos & 0xffff, 1);
 618         }
 619         break;
 620     case CUR_HORZ_VERT_OFF:
 621         s->regs.cur_hv_offs = data & 0x3f003f;
 622         if (data & BIT(31)) {
 623             s->regs.cur_offset |= data & BIT(31);
 624         } else if (s->regs.cur_offset & BIT(31)) {
 625             s->regs.cur_offset &= ~BIT(31);
 626             ati_cursor_define(s);
 627         }
 628         break;
 629     case CUR_CLR0:
 630         if (s->regs.cur_color0 != (data & 0xffffff)) {
 631             s->regs.cur_color0 = data & 0xffffff;
 632             ati_cursor_define(s);
 633         }
 634         break;
 635     case CUR_CLR1:
 636         /*
 637          * Update cursor unconditionally here because some clients set up
 638          * other registers before actually writing cursor data to memory at
 639          * offset so we would miss cursor change unless always updating here
 640          */
 641         s->regs.cur_color1 = data & 0xffffff;
 642         ati_cursor_define(s);
 643         break;
 644     case DST_OFFSET:
 645         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
 646             s->regs.dst_offset = data & 0xfffffff0;
 647         } else {
 648             s->regs.dst_offset = data & 0xfffffc00;
 649         }
 650         break;
 651     case DST_PITCH:
 652         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
 653             s->regs.dst_pitch = data & 0x3fff;
 654             s->regs.dst_tile = (data >> 16) & 1;
 655         } else {
 656             s->regs.dst_pitch = data & 0x3ff0;
 657         }
 658         break;
 659     case DST_TILE:
 660         if (s->dev_id == PCI_DEVICE_ID_ATI_RADEON_QY) {
 661             s->regs.dst_tile = data & 3;
 662         }
 663         break;
 664     case DST_WIDTH:
 665         s->regs.dst_width = data & 0x3fff;
 666         ati_2d_blt(s);
 667         break;
 668     case DST_HEIGHT:
 669         s->regs.dst_height = data & 0x3fff;
 670         break;
 671     case SRC_X:
 672         s->regs.src_x = data & 0x3fff;
 673         break;
 674     case SRC_Y:
 675         s->regs.src_y = data & 0x3fff;
 676         break;
 677     case DST_X:
 678         s->regs.dst_x = data & 0x3fff;
 679         break;
 680     case DST_Y:
 681         s->regs.dst_y = data & 0x3fff;
 682         break;
 683     case SRC_PITCH_OFFSET:
 684         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
 685             s->regs.src_offset = (data & 0x1fffff) << 5;
 686             s->regs.src_pitch = (data >> 21) & 0x3ff;
 687             s->regs.src_tile = data >> 31;
 688         } else {
 689             s->regs.src_offset = (data & 0x3fffff) << 11;
 690             s->regs.src_pitch = (data & 0x3fc00000) >> 16;
 691             s->regs.src_tile = (data >> 30) & 1;
 692         }
 693         break;
 694     case DST_PITCH_OFFSET:
 695         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
 696             s->regs.dst_offset = (data & 0x1fffff) << 5;
 697             s->regs.dst_pitch = (data >> 21) & 0x3ff;
 698             s->regs.dst_tile = data >> 31;
 699         } else {
 700             s->regs.dst_offset = (data & 0x3fffff) << 11;
 701             s->regs.dst_pitch = (data & 0x3fc00000) >> 16;
 702             s->regs.dst_tile = data >> 30;
 703         }
 704         break;
 705     case SRC_Y_X:
 706         s->regs.src_x = data & 0x3fff;
 707         s->regs.src_y = (data >> 16) & 0x3fff;
 708         break;
 709     case DST_Y_X:
 710         s->regs.dst_x = data & 0x3fff;
 711         s->regs.dst_y = (data >> 16) & 0x3fff;
 712         break;
 713     case DST_HEIGHT_WIDTH:
 714         s->regs.dst_width = data & 0x3fff;
 715         s->regs.dst_height = (data >> 16) & 0x3fff;
 716         ati_2d_blt(s);
 717         break;
 718     case DP_GUI_MASTER_CNTL:
 719         s->regs.dp_gui_master_cntl = data & 0xf800000f;
 720         s->regs.dp_datatype = (data & 0x0f00) >> 8 | (data & 0x30f0) << 4 |
 721                               (data & 0x4000) << 16;
 722         s->regs.dp_mix = (data & GMC_ROP3_MASK) | (data & 0x7000000) >> 16;
 723         break;
 724     case DST_WIDTH_X:
 725         s->regs.dst_x = data & 0x3fff;
 726         s->regs.dst_width = (data >> 16) & 0x3fff;
 727         ati_2d_blt(s);
 728         break;
 729     case SRC_X_Y:
 730         s->regs.src_y = data & 0x3fff;
 731         s->regs.src_x = (data >> 16) & 0x3fff;
 732         break;
 733     case DST_X_Y:
 734         s->regs.dst_y = data & 0x3fff;
 735         s->regs.dst_x = (data >> 16) & 0x3fff;
 736         break;
 737     case DST_WIDTH_HEIGHT:
 738         s->regs.dst_height = data & 0x3fff;
 739         s->regs.dst_width = (data >> 16) & 0x3fff;
 740         ati_2d_blt(s);
 741         break;
 742     case DST_HEIGHT_Y:
 743         s->regs.dst_y = data & 0x3fff;
 744         s->regs.dst_height = (data >> 16) & 0x3fff;
 745         break;
 746     case SRC_OFFSET:
 747         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
 748             s->regs.src_offset = data & 0xfffffff0;
 749         } else {
 750             s->regs.src_offset = data & 0xfffffc00;
 751         }
 752         break;
 753     case SRC_PITCH:
 754         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
 755             s->regs.src_pitch = data & 0x3fff;
 756             s->regs.src_tile = (data >> 16) & 1;
 757         } else {
 758             s->regs.src_pitch = data & 0x3ff0;
 759         }
 760         break;
 761     case DP_BRUSH_BKGD_CLR:
 762         s->regs.dp_brush_bkgd_clr = data;
 763         break;
 764     case DP_BRUSH_FRGD_CLR:
 765         s->regs.dp_brush_frgd_clr = data;
 766         break;
 767     case DP_CNTL:
 768         s->regs.dp_cntl = data;
 769         break;
 770     case DP_DATATYPE:
 771         s->regs.dp_datatype = data & 0xe0070f0f;
 772         break;
 773     case DP_MIX:
 774         s->regs.dp_mix = data & 0x00ff0700;
 775         break;
 776     case DP_WRITE_MASK:
 777         s->regs.dp_write_mask = data;
 778         break;
 779     case DEFAULT_OFFSET:
 780         data &= (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF ?
 781                  0x03fffc00 : 0xfffffc00);
 782         s->regs.default_offset = data;
 783         break;
 784     case DEFAULT_PITCH:
 785         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
 786             s->regs.default_pitch = data & 0x103ff;
 787         }
 788         break;
 789     case DEFAULT_SC_BOTTOM_RIGHT:
 790         s->regs.default_sc_bottom_right = data & 0x3fff3fff;
 791         break;
 792     default:
 793         break;
 794     }
 795 }
 796
 797 static const MemoryRegionOps ati_mm_ops = {
 798     .read = ati_mm_read,
 799     .write = ati_mm_write,
 800     .endianness = DEVICE_LITTLE_ENDIAN,
 801 };
 802
 803 static void ati_vga_realize(PCIDevice *dev, Error **errp)
 804 {
 805     ATIVGAState *s = ATI_VGA(dev);
 806     VGACommonState *vga = &s->vga;
 807
 808     if (s->model) {
 809         int i;
 810         for (i = 0; i < ARRAY_SIZE(ati_model_aliases); i++) {
 811             if (!strcmp(s->model, ati_model_aliases[i].name)) {
 812                 s->dev_id = ati_model_aliases[i].dev_id;
 813                 break;
 814             }
 815         }
 816         if (i >= ARRAY_SIZE(ati_model_aliases)) {
 817             warn_report("Unknown ATI VGA model name, "
 818                         "using default rage128p");
 819         }
 820     }
 821     if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF &&
 822         s->dev_id != PCI_DEVICE_ID_ATI_RADEON_QY) {
 823         error_setg(errp, "Unknown ATI VGA device id, "
 824                    "only 0x5046 and 0x5159 are supported");
 825         return;
 826     }
 827     pci_set_word(dev->config + PCI_DEVICE_ID, s->dev_id);
 828
 829     if (s->dev_id == PCI_DEVICE_ID_ATI_RADEON_QY &&
 830         s->vga.vram_size_mb < 16) {
 831         warn_report("Too small video memory for device id");
 832         s->vga.vram_size_mb = 16;
 833     }
 834
 835     /* init vga bits */
 836     vga_common_init(vga, OBJECT(s));
 837     vga_init(vga, OBJECT(s), pci_address_space(dev),
 838              pci_address_space_io(dev), true);
 839     vga->con = graphic_console_init(DEVICE(s), 0, s->vga.hw_ops, &s->vga);
 840     if (s->cursor_guest_mode) {
 841         vga->cursor_invalidate = ati_cursor_invalidate;
 842         vga->cursor_draw_line = ati_cursor_draw_line;
 843     }
 844
 845     /* ddc, edid */
 846     I2CBus *i2cbus = i2c_init_bus(DEVICE(s), "ati-vga.ddc");
 847     s->bbi2c = bitbang_i2c_init(i2cbus);
 848     I2CSlave *i2cddc = I2C_SLAVE(qdev_create(BUS(i2cbus), TYPE_I2CDDC));
 849     i2c_set_slave_address(i2cddc, 0x50);
 850
 851     /* mmio register space */
 852     memory_region_init_io(&s->mm, OBJECT(s), &ati_mm_ops, s,
 853                           "ati.mmregs", 0x4000);
 854     /* io space is alias to beginning of mmregs */
 855     memory_region_init_alias(&s->io, OBJECT(s), "ati.io", &s->mm, 0, 0x100);
 856
 857     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram);
 858     pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
 859     pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mm);
 860 }
 861
 862 static void ati_vga_reset(DeviceState *dev)
 863 {
 864     ATIVGAState *s = ATI_VGA(dev);
 865
 866     /* reset vga */
 867     vga_common_reset(&s->vga);
 868     s->mode = VGA_MODE;
 869 }
 870
 871 static void ati_vga_exit(PCIDevice *dev)
 872 {
 873     ATIVGAState *s = ATI_VGA(dev);
 874
 875     graphic_console_close(s->vga.con);
 876     g_free(s->bbi2c);
 877 }
 878
 879 static Property ati_vga_properties[] = {
 880     DEFINE_PROP_UINT32("vgamem_mb", ATIVGAState, vga.vram_size_mb, 16),
 881     DEFINE_PROP_STRING("model", ATIVGAState, model),
 882     DEFINE_PROP_UINT16("x-device-id", ATIVGAState, dev_id,
 883                        PCI_DEVICE_ID_ATI_RAGE128_PF),
 884     DEFINE_PROP_BOOL("guest_hwcursor", ATIVGAState, cursor_guest_mode, false),
 885     DEFINE_PROP_END_OF_LIST()
 886 };
 887
 888 static void ati_vga_class_init(ObjectClass *klass, void *data)
 889 {
 890     DeviceClass *dc = DEVICE_CLASS(klass);
 891     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 892
 893     dc->reset = ati_vga_reset;
 894     dc->props = ati_vga_properties;
 895     dc->hotpluggable = false;
 896     set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
 897
 898     k->class_id = PCI_CLASS_DISPLAY_VGA;
 899     k->vendor_id = PCI_VENDOR_ID_ATI;
 900     k->device_id = PCI_DEVICE_ID_ATI_RAGE128_PF;
 901     k->romfile = "vgabios-stdvga.bin";
 902     k->realize = ati_vga_realize;
 903     k->exit = ati_vga_exit;
 904 }
 905
 906 static const TypeInfo ati_vga_info = {
 907     .name = TYPE_ATI_VGA,
 908     .parent = TYPE_PCI_DEVICE,
 909     .instance_size = sizeof(ATIVGAState),
 910     .class_init = ati_vga_class_init,
 911     .interfaces = (InterfaceInfo[]) {
 912           { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 913           { },
 914     },
 915 };
 916
 917 static void ati_vga_register_types(void)
 918 {
 919     type_register_static(&ati_vga_info);
 920 }
 921
 922 type_init(ati_vga_register_types)