2 * QEMU CG3 Frame buffer
4 * Copyright (c) 2012 Bob Breuer
5 * Copyright (c) 2013 Mark Cave-Ayland
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
27 #include "qemu-common.h"
28 #include "qapi/error.h"
29 #include "qemu/error-report.h"
30 #include "ui/console.h"
31 #include "hw/sysbus.h"
33 #include "hw/loader.h"
35 #include "qemu/module.h"
37 /* Change to 1 to enable debugging */
40 #define CG3_ROM_FILE "QEMU,cgthree.bin"
41 #define FCODE_MAX_ROM_SIZE 0x10000
43 #define CG3_REG_SIZE 0x20
45 #define CG3_REG_BT458_ADDR 0x0
46 #define CG3_REG_BT458_COLMAP 0x4
47 #define CG3_REG_FBC_CTRL 0x10
48 #define CG3_REG_FBC_STATUS 0x11
49 #define CG3_REG_FBC_CURSTART 0x12
50 #define CG3_REG_FBC_CUREND 0x13
51 #define CG3_REG_FBC_VCTRL 0x14
53 /* Control register flags */
54 #define CG3_CR_ENABLE_INTS 0x80
56 /* Status register flags */
57 #define CG3_SR_PENDING_INT 0x80
58 #define CG3_SR_1152_900_76_B 0x60
59 #define CG3_SR_ID_COLOR 0x01
61 #define CG3_VRAM_SIZE 0x100000
62 #define CG3_VRAM_OFFSET 0x800000
64 #define DPRINTF(fmt, ...) do { \
66 printf("CG3: " fmt , ## __VA_ARGS__); \
70 #define TYPE_CG3 "cgthree"
71 #define CG3(obj) OBJECT_CHECK(CG3State, (obj), TYPE_CG3)
73 typedef struct CG3State
{
74 SysBusDevice parent_obj
;
79 MemoryRegion vram_mem
;
85 uint8_t r
[256], g
[256], b
[256];
86 uint16_t width
, height
, depth
;
87 uint8_t dac_index
, dac_state
;
90 static void cg3_update_display(void *opaque
)
93 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
98 unsigned int width
, height
;
100 DirtyBitmapSnapshot
*snap
= NULL
;
102 if (surface_bits_per_pixel(surface
) != 32) {
109 pix
= memory_region_get_ram_ptr(&s
->vram_mem
);
110 data
= (uint32_t *)surface_data(surface
);
112 if (!s
->full_update
) {
113 snap
= memory_region_snapshot_and_clear_dirty(&s
->vram_mem
, 0x0,
114 memory_region_size(&s
->vram_mem
),
118 for (y
= 0; y
< height
; y
++) {
121 page
= (ram_addr_t
)y
* width
;
123 if (s
->full_update
) {
126 update
= memory_region_snapshot_get_dirty(&s
->vram_mem
, snap
, page
,
135 for (x
= 0; x
< width
; x
++) {
137 dval
= (s
->r
[dval
] << 16) | (s
->g
[dval
] << 8) | s
->b
[dval
];
142 dpy_gfx_update(s
->con
, 0, y_start
, width
, y
- y_start
);
151 dpy_gfx_update(s
->con
, 0, y_start
, width
, y
- y_start
);
153 /* vsync interrupt? */
154 if (s
->regs
[0] & CG3_CR_ENABLE_INTS
) {
155 s
->regs
[1] |= CG3_SR_PENDING_INT
;
156 qemu_irq_raise(s
->irq
);
161 static void cg3_invalidate_display(void *opaque
)
163 CG3State
*s
= opaque
;
165 memory_region_set_dirty(&s
->vram_mem
, 0, CG3_VRAM_SIZE
);
168 static uint64_t cg3_reg_read(void *opaque
, hwaddr addr
, unsigned size
)
170 CG3State
*s
= opaque
;
174 case CG3_REG_BT458_ADDR
:
175 case CG3_REG_BT458_COLMAP
:
178 case CG3_REG_FBC_CTRL
:
181 case CG3_REG_FBC_STATUS
:
182 /* monitor ID 6, board type = 1 (color) */
183 val
= s
->regs
[1] | CG3_SR_1152_900_76_B
| CG3_SR_ID_COLOR
;
185 case CG3_REG_FBC_CURSTART
... CG3_REG_SIZE
- 1:
186 val
= s
->regs
[addr
- 0x10];
189 qemu_log_mask(LOG_UNIMP
,
190 "cg3: Unimplemented register read "
191 "reg 0x%" HWADDR_PRIx
" size 0x%x\n",
196 DPRINTF("read %02x from reg %" HWADDR_PRIx
"\n", val
, addr
);
200 static void cg3_reg_write(void *opaque
, hwaddr addr
, uint64_t val
,
203 CG3State
*s
= opaque
;
207 DPRINTF("write %" PRIx64
" to reg %" HWADDR_PRIx
" size %d\n",
211 case CG3_REG_BT458_ADDR
:
215 case CG3_REG_BT458_COLMAP
:
216 /* This register can be written to as either a long word or a byte */
221 for (i
= 0; i
< size
; i
++) {
224 switch (s
->dac_state
) {
226 s
->r
[s
->dac_index
] = regval
;
230 s
->g
[s
->dac_index
] = regval
;
234 s
->b
[s
->dac_index
] = regval
;
235 /* Index autoincrement */
236 s
->dac_index
= (s
->dac_index
+ 1) & 0xff;
246 case CG3_REG_FBC_CTRL
:
249 case CG3_REG_FBC_STATUS
:
250 if (s
->regs
[1] & CG3_SR_PENDING_INT
) {
251 /* clear interrupt */
252 s
->regs
[1] &= ~CG3_SR_PENDING_INT
;
253 qemu_irq_lower(s
->irq
);
256 case CG3_REG_FBC_CURSTART
... CG3_REG_SIZE
- 1:
257 s
->regs
[addr
- 0x10] = val
;
260 qemu_log_mask(LOG_UNIMP
,
261 "cg3: Unimplemented register write "
262 "reg 0x%" HWADDR_PRIx
" size 0x%x value 0x%" PRIx64
"\n",
268 static const MemoryRegionOps cg3_reg_ops
= {
269 .read
= cg3_reg_read
,
270 .write
= cg3_reg_write
,
271 .endianness
= DEVICE_NATIVE_ENDIAN
,
273 .min_access_size
= 1,
274 .max_access_size
= 4,
278 static const GraphicHwOps cg3_ops
= {
279 .invalidate
= cg3_invalidate_display
,
280 .gfx_update
= cg3_update_display
,
283 static void cg3_initfn(Object
*obj
)
285 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
286 CG3State
*s
= CG3(obj
);
288 memory_region_init_ram_nomigrate(&s
->rom
, obj
, "cg3.prom", FCODE_MAX_ROM_SIZE
,
290 memory_region_set_readonly(&s
->rom
, true);
291 sysbus_init_mmio(sbd
, &s
->rom
);
293 memory_region_init_io(&s
->reg
, obj
, &cg3_reg_ops
, s
, "cg3.reg",
295 sysbus_init_mmio(sbd
, &s
->reg
);
298 static void cg3_realizefn(DeviceState
*dev
, Error
**errp
)
300 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
301 CG3State
*s
= CG3(dev
);
303 char *fcode_filename
;
306 vmstate_register_ram_global(&s
->rom
);
307 fcode_filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, CG3_ROM_FILE
);
308 if (fcode_filename
) {
309 ret
= load_image_mr(fcode_filename
, &s
->rom
);
310 g_free(fcode_filename
);
311 if (ret
< 0 || ret
> FCODE_MAX_ROM_SIZE
) {
312 warn_report("cg3: could not load prom '%s'", CG3_ROM_FILE
);
316 memory_region_init_ram(&s
->vram_mem
, NULL
, "cg3.vram", s
->vram_size
,
318 memory_region_set_log(&s
->vram_mem
, true, DIRTY_MEMORY_VGA
);
319 sysbus_init_mmio(sbd
, &s
->vram_mem
);
321 sysbus_init_irq(sbd
, &s
->irq
);
323 s
->con
= graphic_console_init(DEVICE(dev
), 0, &cg3_ops
, s
);
324 qemu_console_resize(s
->con
, s
->width
, s
->height
);
327 static int vmstate_cg3_post_load(void *opaque
, int version_id
)
329 CG3State
*s
= opaque
;
331 cg3_invalidate_display(s
);
336 static const VMStateDescription vmstate_cg3
= {
339 .minimum_version_id
= 1,
340 .post_load
= vmstate_cg3_post_load
,
341 .fields
= (VMStateField
[]) {
342 VMSTATE_UINT16(height
, CG3State
),
343 VMSTATE_UINT16(width
, CG3State
),
344 VMSTATE_UINT16(depth
, CG3State
),
345 VMSTATE_BUFFER(r
, CG3State
),
346 VMSTATE_BUFFER(g
, CG3State
),
347 VMSTATE_BUFFER(b
, CG3State
),
348 VMSTATE_UINT8(dac_index
, CG3State
),
349 VMSTATE_UINT8(dac_state
, CG3State
),
350 VMSTATE_END_OF_LIST()
354 static void cg3_reset(DeviceState
*d
)
356 CG3State
*s
= CG3(d
);
358 /* Initialize palette */
359 memset(s
->r
, 0, 256);
360 memset(s
->g
, 0, 256);
361 memset(s
->b
, 0, 256);
365 qemu_irq_lower(s
->irq
);
368 static Property cg3_properties
[] = {
369 DEFINE_PROP_UINT32("vram-size", CG3State
, vram_size
, -1),
370 DEFINE_PROP_UINT16("width", CG3State
, width
, -1),
371 DEFINE_PROP_UINT16("height", CG3State
, height
, -1),
372 DEFINE_PROP_UINT16("depth", CG3State
, depth
, -1),
373 DEFINE_PROP_END_OF_LIST(),
376 static void cg3_class_init(ObjectClass
*klass
, void *data
)
378 DeviceClass
*dc
= DEVICE_CLASS(klass
);
380 dc
->realize
= cg3_realizefn
;
381 dc
->reset
= cg3_reset
;
382 dc
->vmsd
= &vmstate_cg3
;
383 dc
->props
= cg3_properties
;
386 static const TypeInfo cg3_info
= {
388 .parent
= TYPE_SYS_BUS_DEVICE
,
389 .instance_size
= sizeof(CG3State
),
390 .instance_init
= cg3_initfn
,
391 .class_init
= cg3_class_init
,
394 static void cg3_register_types(void)
396 type_register_static(&cg3_info
);
399 type_init(cg3_register_types
)