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[mirror_qemu.git] / hw / display / cirrus_vga.c
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "trace.h"
32 #include "hw/hw.h"
33 #include "hw/pci/pci.h"
34 #include "ui/console.h"
35 #include "ui/pixel_ops.h"
36 #include "vga_int.h"
37 #include "hw/loader.h"
38
39 /*
40 * TODO:
41 * - destination write mask support not complete (bits 5..7)
42 * - optimize linear mappings
43 * - optimize bitblt functions
44 */
45
46 //#define DEBUG_CIRRUS
47 //#define DEBUG_BITBLT
48
49 /***************************************
50 *
51 * definitions
52 *
53 ***************************************/
54
55 // ID
56 #define CIRRUS_ID_CLGD5422 (0x23<<2)
57 #define CIRRUS_ID_CLGD5426 (0x24<<2)
58 #define CIRRUS_ID_CLGD5424 (0x25<<2)
59 #define CIRRUS_ID_CLGD5428 (0x26<<2)
60 #define CIRRUS_ID_CLGD5430 (0x28<<2)
61 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
62 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
63 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
64
65 // sequencer 0x07
66 #define CIRRUS_SR7_BPP_VGA 0x00
67 #define CIRRUS_SR7_BPP_SVGA 0x01
68 #define CIRRUS_SR7_BPP_MASK 0x0e
69 #define CIRRUS_SR7_BPP_8 0x00
70 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
71 #define CIRRUS_SR7_BPP_24 0x04
72 #define CIRRUS_SR7_BPP_16 0x06
73 #define CIRRUS_SR7_BPP_32 0x08
74 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
75
76 // sequencer 0x0f
77 #define CIRRUS_MEMSIZE_512k 0x08
78 #define CIRRUS_MEMSIZE_1M 0x10
79 #define CIRRUS_MEMSIZE_2M 0x18
80 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
81
82 // sequencer 0x12
83 #define CIRRUS_CURSOR_SHOW 0x01
84 #define CIRRUS_CURSOR_HIDDENPEL 0x02
85 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
86
87 // sequencer 0x17
88 #define CIRRUS_BUSTYPE_VLBFAST 0x10
89 #define CIRRUS_BUSTYPE_PCI 0x20
90 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
91 #define CIRRUS_BUSTYPE_ISA 0x38
92 #define CIRRUS_MMIO_ENABLE 0x04
93 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
94 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
95
96 // control 0x0b
97 #define CIRRUS_BANKING_DUAL 0x01
98 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
99
100 // control 0x30
101 #define CIRRUS_BLTMODE_BACKWARDS 0x01
102 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
103 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
104 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
105 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
106 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
107 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
108 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
109 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
110 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
111 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
112
113 // control 0x31
114 #define CIRRUS_BLT_BUSY 0x01
115 #define CIRRUS_BLT_START 0x02
116 #define CIRRUS_BLT_RESET 0x04
117 #define CIRRUS_BLT_FIFOUSED 0x10
118 #define CIRRUS_BLT_AUTOSTART 0x80
119
120 // control 0x32
121 #define CIRRUS_ROP_0 0x00
122 #define CIRRUS_ROP_SRC_AND_DST 0x05
123 #define CIRRUS_ROP_NOP 0x06
124 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
125 #define CIRRUS_ROP_NOTDST 0x0b
126 #define CIRRUS_ROP_SRC 0x0d
127 #define CIRRUS_ROP_1 0x0e
128 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
129 #define CIRRUS_ROP_SRC_XOR_DST 0x59
130 #define CIRRUS_ROP_SRC_OR_DST 0x6d
131 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
132 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
133 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
134 #define CIRRUS_ROP_NOTSRC 0xd0
135 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
136 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
137
138 #define CIRRUS_ROP_NOP_INDEX 2
139 #define CIRRUS_ROP_SRC_INDEX 5
140
141 // control 0x33
142 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
143 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
144 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
145
146 // memory-mapped IO
147 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
148 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
149 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
150 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
151 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
152 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
153 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
154 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
155 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
156 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
157 #define CIRRUS_MMIO_BLTROP 0x1a // byte
158 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
159 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
160 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
161 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
162 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
163 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
164 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
168 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
169 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
170 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
171 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
172 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
173 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
174 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
175 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
176
177 #define CIRRUS_PNPMMIO_SIZE 0x1000
178
179 struct CirrusVGAState;
180 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
181 uint8_t * dst, const uint8_t * src,
182 int dstpitch, int srcpitch,
183 int bltwidth, int bltheight);
184 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
185 uint8_t *dst, int dst_pitch, int width, int height);
186
187 typedef struct CirrusVGAState {
188 VGACommonState vga;
189
190 MemoryRegion cirrus_vga_io;
191 MemoryRegion cirrus_linear_io;
192 MemoryRegion cirrus_linear_bitblt_io;
193 MemoryRegion cirrus_mmio_io;
194 MemoryRegion pci_bar;
195 bool linear_vram; /* vga.vram mapped over cirrus_linear_io */
196 MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
197 MemoryRegion low_mem; /* always mapped, overridden by: */
198 MemoryRegion cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */
199 uint32_t cirrus_addr_mask;
200 uint32_t linear_mmio_mask;
201 uint8_t cirrus_shadow_gr0;
202 uint8_t cirrus_shadow_gr1;
203 uint8_t cirrus_hidden_dac_lockindex;
204 uint8_t cirrus_hidden_dac_data;
205 uint32_t cirrus_bank_base[2];
206 uint32_t cirrus_bank_limit[2];
207 uint8_t cirrus_hidden_palette[48];
208 int cirrus_blt_pixelwidth;
209 int cirrus_blt_width;
210 int cirrus_blt_height;
211 int cirrus_blt_dstpitch;
212 int cirrus_blt_srcpitch;
213 uint32_t cirrus_blt_fgcol;
214 uint32_t cirrus_blt_bgcol;
215 uint32_t cirrus_blt_dstaddr;
216 uint32_t cirrus_blt_srcaddr;
217 uint8_t cirrus_blt_mode;
218 uint8_t cirrus_blt_modeext;
219 cirrus_bitblt_rop_t cirrus_rop;
220 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
221 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
222 uint8_t *cirrus_srcptr;
223 uint8_t *cirrus_srcptr_end;
224 uint32_t cirrus_srccounter;
225 /* hwcursor display state */
226 int last_hw_cursor_size;
227 int last_hw_cursor_x;
228 int last_hw_cursor_y;
229 int last_hw_cursor_y_start;
230 int last_hw_cursor_y_end;
231 int real_vram_size; /* XXX: suppress that */
232 int device_id;
233 int bustype;
234 } CirrusVGAState;
235
236 typedef struct PCICirrusVGAState {
237 PCIDevice dev;
238 CirrusVGAState cirrus_vga;
239 } PCICirrusVGAState;
240
241 #define TYPE_PCI_CIRRUS_VGA "cirrus-vga"
242 #define PCI_CIRRUS_VGA(obj) \
243 OBJECT_CHECK(PCICirrusVGAState, (obj), TYPE_PCI_CIRRUS_VGA)
244
245 #define TYPE_ISA_CIRRUS_VGA "isa-cirrus-vga"
246 #define ISA_CIRRUS_VGA(obj) \
247 OBJECT_CHECK(ISACirrusVGAState, (obj), TYPE_ISA_CIRRUS_VGA)
248
249 typedef struct ISACirrusVGAState {
250 ISADevice parent_obj;
251
252 CirrusVGAState cirrus_vga;
253 } ISACirrusVGAState;
254
255 static uint8_t rop_to_index[256];
256
257 /***************************************
258 *
259 * prototypes.
260 *
261 ***************************************/
262
263
264 static void cirrus_bitblt_reset(CirrusVGAState *s);
265 static void cirrus_update_memory_access(CirrusVGAState *s);
266
267 /***************************************
268 *
269 * raster operations
270 *
271 ***************************************/
272
273 static bool blit_region_is_unsafe(struct CirrusVGAState *s,
274 int32_t pitch, int32_t addr)
275 {
276 if (!pitch) {
277 return true;
278 }
279 if (pitch < 0) {
280 int64_t min = addr
281 + ((int64_t)s->cirrus_blt_height - 1) * pitch
282 - s->cirrus_blt_width;
283 if (min < -1 || addr >= s->vga.vram_size) {
284 return true;
285 }
286 } else {
287 int64_t max = addr
288 + ((int64_t)s->cirrus_blt_height-1) * pitch
289 + s->cirrus_blt_width;
290 if (max > s->vga.vram_size) {
291 return true;
292 }
293 }
294 return false;
295 }
296
297 static bool blit_is_unsafe(struct CirrusVGAState *s, bool dst_only)
298 {
299 /* should be the case, see cirrus_bitblt_start */
300 assert(s->cirrus_blt_width > 0);
301 assert(s->cirrus_blt_height > 0);
302
303 if (s->cirrus_blt_width > CIRRUS_BLTBUFSIZE) {
304 return true;
305 }
306
307 if (blit_region_is_unsafe(s, s->cirrus_blt_dstpitch,
308 s->cirrus_blt_dstaddr)) {
309 return true;
310 }
311 if (dst_only) {
312 return false;
313 }
314 if (blit_region_is_unsafe(s, s->cirrus_blt_srcpitch,
315 s->cirrus_blt_srcaddr)) {
316 return true;
317 }
318
319 return false;
320 }
321
322 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
323 uint8_t *dst,const uint8_t *src,
324 int dstpitch,int srcpitch,
325 int bltwidth,int bltheight)
326 {
327 }
328
329 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
330 uint8_t *dst,
331 int dstpitch, int bltwidth,int bltheight)
332 {
333 }
334
335 #define ROP_NAME 0
336 #define ROP_FN(d, s) 0
337 #include "cirrus_vga_rop.h"
338
339 #define ROP_NAME src_and_dst
340 #define ROP_FN(d, s) (s) & (d)
341 #include "cirrus_vga_rop.h"
342
343 #define ROP_NAME src_and_notdst
344 #define ROP_FN(d, s) (s) & (~(d))
345 #include "cirrus_vga_rop.h"
346
347 #define ROP_NAME notdst
348 #define ROP_FN(d, s) ~(d)
349 #include "cirrus_vga_rop.h"
350
351 #define ROP_NAME src
352 #define ROP_FN(d, s) s
353 #include "cirrus_vga_rop.h"
354
355 #define ROP_NAME 1
356 #define ROP_FN(d, s) ~0
357 #include "cirrus_vga_rop.h"
358
359 #define ROP_NAME notsrc_and_dst
360 #define ROP_FN(d, s) (~(s)) & (d)
361 #include "cirrus_vga_rop.h"
362
363 #define ROP_NAME src_xor_dst
364 #define ROP_FN(d, s) (s) ^ (d)
365 #include "cirrus_vga_rop.h"
366
367 #define ROP_NAME src_or_dst
368 #define ROP_FN(d, s) (s) | (d)
369 #include "cirrus_vga_rop.h"
370
371 #define ROP_NAME notsrc_or_notdst
372 #define ROP_FN(d, s) (~(s)) | (~(d))
373 #include "cirrus_vga_rop.h"
374
375 #define ROP_NAME src_notxor_dst
376 #define ROP_FN(d, s) ~((s) ^ (d))
377 #include "cirrus_vga_rop.h"
378
379 #define ROP_NAME src_or_notdst
380 #define ROP_FN(d, s) (s) | (~(d))
381 #include "cirrus_vga_rop.h"
382
383 #define ROP_NAME notsrc
384 #define ROP_FN(d, s) (~(s))
385 #include "cirrus_vga_rop.h"
386
387 #define ROP_NAME notsrc_or_dst
388 #define ROP_FN(d, s) (~(s)) | (d)
389 #include "cirrus_vga_rop.h"
390
391 #define ROP_NAME notsrc_and_notdst
392 #define ROP_FN(d, s) (~(s)) & (~(d))
393 #include "cirrus_vga_rop.h"
394
395 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
396 cirrus_bitblt_rop_fwd_0,
397 cirrus_bitblt_rop_fwd_src_and_dst,
398 cirrus_bitblt_rop_nop,
399 cirrus_bitblt_rop_fwd_src_and_notdst,
400 cirrus_bitblt_rop_fwd_notdst,
401 cirrus_bitblt_rop_fwd_src,
402 cirrus_bitblt_rop_fwd_1,
403 cirrus_bitblt_rop_fwd_notsrc_and_dst,
404 cirrus_bitblt_rop_fwd_src_xor_dst,
405 cirrus_bitblt_rop_fwd_src_or_dst,
406 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
407 cirrus_bitblt_rop_fwd_src_notxor_dst,
408 cirrus_bitblt_rop_fwd_src_or_notdst,
409 cirrus_bitblt_rop_fwd_notsrc,
410 cirrus_bitblt_rop_fwd_notsrc_or_dst,
411 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
412 };
413
414 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
415 cirrus_bitblt_rop_bkwd_0,
416 cirrus_bitblt_rop_bkwd_src_and_dst,
417 cirrus_bitblt_rop_nop,
418 cirrus_bitblt_rop_bkwd_src_and_notdst,
419 cirrus_bitblt_rop_bkwd_notdst,
420 cirrus_bitblt_rop_bkwd_src,
421 cirrus_bitblt_rop_bkwd_1,
422 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
423 cirrus_bitblt_rop_bkwd_src_xor_dst,
424 cirrus_bitblt_rop_bkwd_src_or_dst,
425 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
426 cirrus_bitblt_rop_bkwd_src_notxor_dst,
427 cirrus_bitblt_rop_bkwd_src_or_notdst,
428 cirrus_bitblt_rop_bkwd_notsrc,
429 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
430 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
431 };
432
433 #define TRANSP_ROP(name) {\
434 name ## _8,\
435 name ## _16,\
436 }
437 #define TRANSP_NOP(func) {\
438 func,\
439 func,\
440 }
441
442 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
445 TRANSP_NOP(cirrus_bitblt_rop_nop),
446 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
447 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
448 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
449 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
450 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
451 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
452 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
453 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
454 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
455 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
456 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
457 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
458 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
459 };
460
461 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
464 TRANSP_NOP(cirrus_bitblt_rop_nop),
465 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
466 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
467 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
468 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
469 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
470 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
471 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
472 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
473 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
474 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
475 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
476 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
477 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
478 };
479
480 #define ROP2(name) {\
481 name ## _8,\
482 name ## _16,\
483 name ## _24,\
484 name ## _32,\
485 }
486
487 #define ROP_NOP2(func) {\
488 func,\
489 func,\
490 func,\
491 func,\
492 }
493
494 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
495 ROP2(cirrus_patternfill_0),
496 ROP2(cirrus_patternfill_src_and_dst),
497 ROP_NOP2(cirrus_bitblt_rop_nop),
498 ROP2(cirrus_patternfill_src_and_notdst),
499 ROP2(cirrus_patternfill_notdst),
500 ROP2(cirrus_patternfill_src),
501 ROP2(cirrus_patternfill_1),
502 ROP2(cirrus_patternfill_notsrc_and_dst),
503 ROP2(cirrus_patternfill_src_xor_dst),
504 ROP2(cirrus_patternfill_src_or_dst),
505 ROP2(cirrus_patternfill_notsrc_or_notdst),
506 ROP2(cirrus_patternfill_src_notxor_dst),
507 ROP2(cirrus_patternfill_src_or_notdst),
508 ROP2(cirrus_patternfill_notsrc),
509 ROP2(cirrus_patternfill_notsrc_or_dst),
510 ROP2(cirrus_patternfill_notsrc_and_notdst),
511 };
512
513 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
514 ROP2(cirrus_colorexpand_transp_0),
515 ROP2(cirrus_colorexpand_transp_src_and_dst),
516 ROP_NOP2(cirrus_bitblt_rop_nop),
517 ROP2(cirrus_colorexpand_transp_src_and_notdst),
518 ROP2(cirrus_colorexpand_transp_notdst),
519 ROP2(cirrus_colorexpand_transp_src),
520 ROP2(cirrus_colorexpand_transp_1),
521 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
522 ROP2(cirrus_colorexpand_transp_src_xor_dst),
523 ROP2(cirrus_colorexpand_transp_src_or_dst),
524 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
525 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
526 ROP2(cirrus_colorexpand_transp_src_or_notdst),
527 ROP2(cirrus_colorexpand_transp_notsrc),
528 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
529 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
530 };
531
532 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
533 ROP2(cirrus_colorexpand_0),
534 ROP2(cirrus_colorexpand_src_and_dst),
535 ROP_NOP2(cirrus_bitblt_rop_nop),
536 ROP2(cirrus_colorexpand_src_and_notdst),
537 ROP2(cirrus_colorexpand_notdst),
538 ROP2(cirrus_colorexpand_src),
539 ROP2(cirrus_colorexpand_1),
540 ROP2(cirrus_colorexpand_notsrc_and_dst),
541 ROP2(cirrus_colorexpand_src_xor_dst),
542 ROP2(cirrus_colorexpand_src_or_dst),
543 ROP2(cirrus_colorexpand_notsrc_or_notdst),
544 ROP2(cirrus_colorexpand_src_notxor_dst),
545 ROP2(cirrus_colorexpand_src_or_notdst),
546 ROP2(cirrus_colorexpand_notsrc),
547 ROP2(cirrus_colorexpand_notsrc_or_dst),
548 ROP2(cirrus_colorexpand_notsrc_and_notdst),
549 };
550
551 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
552 ROP2(cirrus_colorexpand_pattern_transp_0),
553 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
554 ROP_NOP2(cirrus_bitblt_rop_nop),
555 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
556 ROP2(cirrus_colorexpand_pattern_transp_notdst),
557 ROP2(cirrus_colorexpand_pattern_transp_src),
558 ROP2(cirrus_colorexpand_pattern_transp_1),
559 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
560 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
561 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
562 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
563 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
564 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
565 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
566 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
567 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
568 };
569
570 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
571 ROP2(cirrus_colorexpand_pattern_0),
572 ROP2(cirrus_colorexpand_pattern_src_and_dst),
573 ROP_NOP2(cirrus_bitblt_rop_nop),
574 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
575 ROP2(cirrus_colorexpand_pattern_notdst),
576 ROP2(cirrus_colorexpand_pattern_src),
577 ROP2(cirrus_colorexpand_pattern_1),
578 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
579 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
580 ROP2(cirrus_colorexpand_pattern_src_or_dst),
581 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
582 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
583 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
584 ROP2(cirrus_colorexpand_pattern_notsrc),
585 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
586 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
587 };
588
589 static const cirrus_fill_t cirrus_fill[16][4] = {
590 ROP2(cirrus_fill_0),
591 ROP2(cirrus_fill_src_and_dst),
592 ROP_NOP2(cirrus_bitblt_fill_nop),
593 ROP2(cirrus_fill_src_and_notdst),
594 ROP2(cirrus_fill_notdst),
595 ROP2(cirrus_fill_src),
596 ROP2(cirrus_fill_1),
597 ROP2(cirrus_fill_notsrc_and_dst),
598 ROP2(cirrus_fill_src_xor_dst),
599 ROP2(cirrus_fill_src_or_dst),
600 ROP2(cirrus_fill_notsrc_or_notdst),
601 ROP2(cirrus_fill_src_notxor_dst),
602 ROP2(cirrus_fill_src_or_notdst),
603 ROP2(cirrus_fill_notsrc),
604 ROP2(cirrus_fill_notsrc_or_dst),
605 ROP2(cirrus_fill_notsrc_and_notdst),
606 };
607
608 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
609 {
610 unsigned int color;
611 switch (s->cirrus_blt_pixelwidth) {
612 case 1:
613 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
614 break;
615 case 2:
616 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
617 s->cirrus_blt_fgcol = le16_to_cpu(color);
618 break;
619 case 3:
620 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
621 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
622 break;
623 default:
624 case 4:
625 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
626 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
627 s->cirrus_blt_fgcol = le32_to_cpu(color);
628 break;
629 }
630 }
631
632 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
633 {
634 unsigned int color;
635 switch (s->cirrus_blt_pixelwidth) {
636 case 1:
637 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
638 break;
639 case 2:
640 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
641 s->cirrus_blt_bgcol = le16_to_cpu(color);
642 break;
643 case 3:
644 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
645 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
646 break;
647 default:
648 case 4:
649 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
650 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
651 s->cirrus_blt_bgcol = le32_to_cpu(color);
652 break;
653 }
654 }
655
656 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
657 int off_pitch, int bytesperline,
658 int lines)
659 {
660 int y;
661 int off_cur;
662 int off_cur_end;
663
664 if (off_pitch < 0) {
665 off_begin -= bytesperline - 1;
666 }
667
668 for (y = 0; y < lines; y++) {
669 off_cur = off_begin;
670 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
671 assert(off_cur_end >= off_cur);
672 memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur);
673 off_begin += off_pitch;
674 }
675 }
676
677 static int cirrus_bitblt_common_patterncopy(CirrusVGAState *s, bool videosrc)
678 {
679 uint32_t patternsize;
680 uint8_t *dst;
681 uint8_t *src;
682
683 dst = s->vga.vram_ptr + s->cirrus_blt_dstaddr;
684
685 if (videosrc) {
686 switch (s->vga.get_bpp(&s->vga)) {
687 case 8:
688 patternsize = 64;
689 break;
690 case 15:
691 case 16:
692 patternsize = 128;
693 break;
694 case 24:
695 case 32:
696 default:
697 patternsize = 256;
698 break;
699 }
700 s->cirrus_blt_srcaddr &= ~(patternsize - 1);
701 if (s->cirrus_blt_srcaddr + patternsize > s->vga.vram_size) {
702 return 0;
703 }
704 src = s->vga.vram_ptr + s->cirrus_blt_srcaddr;
705 } else {
706 src = s->cirrus_bltbuf;
707 }
708
709 if (blit_is_unsafe(s, true)) {
710 return 0;
711 }
712
713 (*s->cirrus_rop) (s, dst, src,
714 s->cirrus_blt_dstpitch, 0,
715 s->cirrus_blt_width, s->cirrus_blt_height);
716 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
717 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
718 s->cirrus_blt_height);
719 return 1;
720 }
721
722 /* fill */
723
724 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
725 {
726 cirrus_fill_t rop_func;
727
728 if (blit_is_unsafe(s, true)) {
729 return 0;
730 }
731 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
732 rop_func(s, s->vga.vram_ptr + s->cirrus_blt_dstaddr,
733 s->cirrus_blt_dstpitch,
734 s->cirrus_blt_width, s->cirrus_blt_height);
735 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
736 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
737 s->cirrus_blt_height);
738 cirrus_bitblt_reset(s);
739 return 1;
740 }
741
742 /***************************************
743 *
744 * bitblt (video-to-video)
745 *
746 ***************************************/
747
748 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
749 {
750 return cirrus_bitblt_common_patterncopy(s, true);
751 }
752
753 static int cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
754 {
755 int sx = 0, sy = 0;
756 int dx = 0, dy = 0;
757 int depth = 0;
758 int notify = 0;
759
760 /* make sure to only copy if it's a plain copy ROP */
761 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
762 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
763
764 int width, height;
765
766 depth = s->vga.get_bpp(&s->vga) / 8;
767 if (!depth) {
768 return 0;
769 }
770 s->vga.get_resolution(&s->vga, &width, &height);
771
772 /* extra x, y */
773 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
774 sy = (src / ABS(s->cirrus_blt_srcpitch));
775 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
776 dy = (dst / ABS(s->cirrus_blt_dstpitch));
777
778 /* normalize width */
779 w /= depth;
780
781 /* if we're doing a backward copy, we have to adjust
782 our x/y to be the upper left corner (instead of the lower
783 right corner) */
784 if (s->cirrus_blt_dstpitch < 0) {
785 sx -= (s->cirrus_blt_width / depth) - 1;
786 dx -= (s->cirrus_blt_width / depth) - 1;
787 sy -= s->cirrus_blt_height - 1;
788 dy -= s->cirrus_blt_height - 1;
789 }
790
791 /* are we in the visible portion of memory? */
792 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
793 (sx + w) <= width && (sy + h) <= height &&
794 (dx + w) <= width && (dy + h) <= height) {
795 notify = 1;
796 }
797 }
798
799 (*s->cirrus_rop) (s, s->vga.vram_ptr + s->cirrus_blt_dstaddr,
800 s->vga.vram_ptr + s->cirrus_blt_srcaddr,
801 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
802 s->cirrus_blt_width, s->cirrus_blt_height);
803
804 if (notify) {
805 dpy_gfx_update(s->vga.con, dx, dy,
806 s->cirrus_blt_width / depth,
807 s->cirrus_blt_height);
808 }
809
810 /* we don't have to notify the display that this portion has
811 changed since qemu_console_copy implies this */
812
813 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
814 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
815 s->cirrus_blt_height);
816
817 return 1;
818 }
819
820 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
821 {
822 if (blit_is_unsafe(s, false))
823 return 0;
824
825 return cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
826 s->cirrus_blt_srcaddr - s->vga.start_addr,
827 s->cirrus_blt_width, s->cirrus_blt_height);
828 }
829
830 /***************************************
831 *
832 * bitblt (cpu-to-video)
833 *
834 ***************************************/
835
836 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
837 {
838 int copy_count;
839 uint8_t *end_ptr;
840
841 if (s->cirrus_srccounter > 0) {
842 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
843 cirrus_bitblt_common_patterncopy(s, false);
844 the_end:
845 s->cirrus_srccounter = 0;
846 cirrus_bitblt_reset(s);
847 } else {
848 /* at least one scan line */
849 do {
850 (*s->cirrus_rop)(s, s->vga.vram_ptr + s->cirrus_blt_dstaddr,
851 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
852 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
853 s->cirrus_blt_width, 1);
854 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
855 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
856 if (s->cirrus_srccounter <= 0)
857 goto the_end;
858 /* more bytes than needed can be transferred because of
859 word alignment, so we keep them for the next line */
860 /* XXX: keep alignment to speed up transfer */
861 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
862 copy_count = s->cirrus_srcptr_end - end_ptr;
863 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
864 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
865 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
866 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
867 }
868 }
869 }
870
871 /***************************************
872 *
873 * bitblt wrapper
874 *
875 ***************************************/
876
877 static void cirrus_bitblt_reset(CirrusVGAState * s)
878 {
879 int need_update;
880
881 s->vga.gr[0x31] &=
882 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
883 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
884 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
885 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
886 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
887 s->cirrus_srccounter = 0;
888 if (!need_update)
889 return;
890 cirrus_update_memory_access(s);
891 }
892
893 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
894 {
895 int w;
896
897 if (blit_is_unsafe(s, true)) {
898 return 0;
899 }
900
901 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
902 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
903 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
904
905 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
906 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
907 s->cirrus_blt_srcpitch = 8;
908 } else {
909 /* XXX: check for 24 bpp */
910 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
911 }
912 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
913 } else {
914 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
915 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
916 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
917 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
918 else
919 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
920 } else {
921 /* always align input size to 32 bits */
922 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
923 }
924 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
925 }
926
927 /* the blit_is_unsafe call above should catch this */
928 assert(s->cirrus_blt_srcpitch <= CIRRUS_BLTBUFSIZE);
929
930 s->cirrus_srcptr = s->cirrus_bltbuf;
931 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
932 cirrus_update_memory_access(s);
933 return 1;
934 }
935
936 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
937 {
938 /* XXX */
939 #ifdef DEBUG_BITBLT
940 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
941 #endif
942 return 0;
943 }
944
945 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
946 {
947 int ret;
948
949 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
950 ret = cirrus_bitblt_videotovideo_patterncopy(s);
951 } else {
952 ret = cirrus_bitblt_videotovideo_copy(s);
953 }
954 if (ret)
955 cirrus_bitblt_reset(s);
956 return ret;
957 }
958
959 static void cirrus_bitblt_start(CirrusVGAState * s)
960 {
961 uint8_t blt_rop;
962
963 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
964
965 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
966 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
967 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
968 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
969 s->cirrus_blt_dstaddr =
970 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
971 s->cirrus_blt_srcaddr =
972 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
973 s->cirrus_blt_mode = s->vga.gr[0x30];
974 s->cirrus_blt_modeext = s->vga.gr[0x33];
975 blt_rop = s->vga.gr[0x32];
976
977 s->cirrus_blt_dstaddr &= s->cirrus_addr_mask;
978 s->cirrus_blt_srcaddr &= s->cirrus_addr_mask;
979
980 #ifdef DEBUG_BITBLT
981 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
982 blt_rop,
983 s->cirrus_blt_mode,
984 s->cirrus_blt_modeext,
985 s->cirrus_blt_width,
986 s->cirrus_blt_height,
987 s->cirrus_blt_dstpitch,
988 s->cirrus_blt_srcpitch,
989 s->cirrus_blt_dstaddr,
990 s->cirrus_blt_srcaddr,
991 s->vga.gr[0x2f]);
992 #endif
993
994 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
995 case CIRRUS_BLTMODE_PIXELWIDTH8:
996 s->cirrus_blt_pixelwidth = 1;
997 break;
998 case CIRRUS_BLTMODE_PIXELWIDTH16:
999 s->cirrus_blt_pixelwidth = 2;
1000 break;
1001 case CIRRUS_BLTMODE_PIXELWIDTH24:
1002 s->cirrus_blt_pixelwidth = 3;
1003 break;
1004 case CIRRUS_BLTMODE_PIXELWIDTH32:
1005 s->cirrus_blt_pixelwidth = 4;
1006 break;
1007 default:
1008 #ifdef DEBUG_BITBLT
1009 printf("cirrus: bitblt - pixel width is unknown\n");
1010 #endif
1011 goto bitblt_ignore;
1012 }
1013 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
1014
1015 if ((s->
1016 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
1017 CIRRUS_BLTMODE_MEMSYSDEST))
1018 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
1019 #ifdef DEBUG_BITBLT
1020 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
1021 #endif
1022 goto bitblt_ignore;
1023 }
1024
1025 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
1026 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
1027 CIRRUS_BLTMODE_TRANSPARENTCOMP |
1028 CIRRUS_BLTMODE_PATTERNCOPY |
1029 CIRRUS_BLTMODE_COLOREXPAND)) ==
1030 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
1031 cirrus_bitblt_fgcol(s);
1032 cirrus_bitblt_solidfill(s, blt_rop);
1033 } else {
1034 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
1035 CIRRUS_BLTMODE_PATTERNCOPY)) ==
1036 CIRRUS_BLTMODE_COLOREXPAND) {
1037
1038 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1039 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1040 cirrus_bitblt_bgcol(s);
1041 else
1042 cirrus_bitblt_fgcol(s);
1043 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1044 } else {
1045 cirrus_bitblt_fgcol(s);
1046 cirrus_bitblt_bgcol(s);
1047 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1048 }
1049 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
1050 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1051 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1052 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1053 cirrus_bitblt_bgcol(s);
1054 else
1055 cirrus_bitblt_fgcol(s);
1056 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1057 } else {
1058 cirrus_bitblt_fgcol(s);
1059 cirrus_bitblt_bgcol(s);
1060 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1061 }
1062 } else {
1063 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1064 }
1065 } else {
1066 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1067 if (s->cirrus_blt_pixelwidth > 2) {
1068 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1069 goto bitblt_ignore;
1070 }
1071 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1072 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1073 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1074 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1075 } else {
1076 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1077 }
1078 } else {
1079 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1080 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1081 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1082 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1083 } else {
1084 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1085 }
1086 }
1087 }
1088 // setup bitblt engine.
1089 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1090 if (!cirrus_bitblt_cputovideo(s))
1091 goto bitblt_ignore;
1092 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1093 if (!cirrus_bitblt_videotocpu(s))
1094 goto bitblt_ignore;
1095 } else {
1096 if (!cirrus_bitblt_videotovideo(s))
1097 goto bitblt_ignore;
1098 }
1099 }
1100 return;
1101 bitblt_ignore:;
1102 cirrus_bitblt_reset(s);
1103 }
1104
1105 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1106 {
1107 unsigned old_value;
1108
1109 old_value = s->vga.gr[0x31];
1110 s->vga.gr[0x31] = reg_value;
1111
1112 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1113 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1114 cirrus_bitblt_reset(s);
1115 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1116 ((reg_value & CIRRUS_BLT_START) != 0)) {
1117 cirrus_bitblt_start(s);
1118 }
1119 }
1120
1121
1122 /***************************************
1123 *
1124 * basic parameters
1125 *
1126 ***************************************/
1127
1128 static void cirrus_get_offsets(VGACommonState *s1,
1129 uint32_t *pline_offset,
1130 uint32_t *pstart_addr,
1131 uint32_t *pline_compare)
1132 {
1133 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1134 uint32_t start_addr, line_offset, line_compare;
1135
1136 line_offset = s->vga.cr[0x13]
1137 | ((s->vga.cr[0x1b] & 0x10) << 4);
1138 line_offset <<= 3;
1139 *pline_offset = line_offset;
1140
1141 start_addr = (s->vga.cr[0x0c] << 8)
1142 | s->vga.cr[0x0d]
1143 | ((s->vga.cr[0x1b] & 0x01) << 16)
1144 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1145 | ((s->vga.cr[0x1d] & 0x80) << 12);
1146 *pstart_addr = start_addr;
1147
1148 line_compare = s->vga.cr[0x18] |
1149 ((s->vga.cr[0x07] & 0x10) << 4) |
1150 ((s->vga.cr[0x09] & 0x40) << 3);
1151 *pline_compare = line_compare;
1152 }
1153
1154 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1155 {
1156 uint32_t ret = 16;
1157
1158 switch (s->cirrus_hidden_dac_data & 0xf) {
1159 case 0:
1160 ret = 15;
1161 break; /* Sierra HiColor */
1162 case 1:
1163 ret = 16;
1164 break; /* XGA HiColor */
1165 default:
1166 #ifdef DEBUG_CIRRUS
1167 printf("cirrus: invalid DAC value %x in 16bpp\n",
1168 (s->cirrus_hidden_dac_data & 0xf));
1169 #endif
1170 ret = 15; /* XXX */
1171 break;
1172 }
1173 return ret;
1174 }
1175
1176 static int cirrus_get_bpp(VGACommonState *s1)
1177 {
1178 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1179 uint32_t ret = 8;
1180
1181 if ((s->vga.sr[0x07] & 0x01) != 0) {
1182 /* Cirrus SVGA */
1183 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1184 case CIRRUS_SR7_BPP_8:
1185 ret = 8;
1186 break;
1187 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1188 ret = cirrus_get_bpp16_depth(s);
1189 break;
1190 case CIRRUS_SR7_BPP_24:
1191 ret = 24;
1192 break;
1193 case CIRRUS_SR7_BPP_16:
1194 ret = cirrus_get_bpp16_depth(s);
1195 break;
1196 case CIRRUS_SR7_BPP_32:
1197 ret = 32;
1198 break;
1199 default:
1200 #ifdef DEBUG_CIRRUS
1201 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
1202 #endif
1203 ret = 8;
1204 break;
1205 }
1206 } else {
1207 /* VGA */
1208 ret = 0;
1209 }
1210
1211 return ret;
1212 }
1213
1214 static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1215 {
1216 int width, height;
1217
1218 width = (s->cr[0x01] + 1) * 8;
1219 height = s->cr[0x12] |
1220 ((s->cr[0x07] & 0x02) << 7) |
1221 ((s->cr[0x07] & 0x40) << 3);
1222 height = (height + 1);
1223 /* interlace support */
1224 if (s->cr[0x1a] & 0x01)
1225 height = height * 2;
1226 *pwidth = width;
1227 *pheight = height;
1228 }
1229
1230 /***************************************
1231 *
1232 * bank memory
1233 *
1234 ***************************************/
1235
1236 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1237 {
1238 unsigned offset;
1239 unsigned limit;
1240
1241 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1242 offset = s->vga.gr[0x09 + bank_index];
1243 else /* single bank */
1244 offset = s->vga.gr[0x09];
1245
1246 if ((s->vga.gr[0x0b] & 0x20) != 0)
1247 offset <<= 14;
1248 else
1249 offset <<= 12;
1250
1251 if (s->real_vram_size <= offset)
1252 limit = 0;
1253 else
1254 limit = s->real_vram_size - offset;
1255
1256 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1257 if (limit > 0x8000) {
1258 offset += 0x8000;
1259 limit -= 0x8000;
1260 } else {
1261 limit = 0;
1262 }
1263 }
1264
1265 if (limit > 0) {
1266 s->cirrus_bank_base[bank_index] = offset;
1267 s->cirrus_bank_limit[bank_index] = limit;
1268 } else {
1269 s->cirrus_bank_base[bank_index] = 0;
1270 s->cirrus_bank_limit[bank_index] = 0;
1271 }
1272 }
1273
1274 /***************************************
1275 *
1276 * I/O access between 0x3c4-0x3c5
1277 *
1278 ***************************************/
1279
1280 static int cirrus_vga_read_sr(CirrusVGAState * s)
1281 {
1282 switch (s->vga.sr_index) {
1283 case 0x00: // Standard VGA
1284 case 0x01: // Standard VGA
1285 case 0x02: // Standard VGA
1286 case 0x03: // Standard VGA
1287 case 0x04: // Standard VGA
1288 return s->vga.sr[s->vga.sr_index];
1289 case 0x06: // Unlock Cirrus extensions
1290 return s->vga.sr[s->vga.sr_index];
1291 case 0x10:
1292 case 0x30:
1293 case 0x50:
1294 case 0x70: // Graphics Cursor X
1295 case 0x90:
1296 case 0xb0:
1297 case 0xd0:
1298 case 0xf0: // Graphics Cursor X
1299 return s->vga.sr[0x10];
1300 case 0x11:
1301 case 0x31:
1302 case 0x51:
1303 case 0x71: // Graphics Cursor Y
1304 case 0x91:
1305 case 0xb1:
1306 case 0xd1:
1307 case 0xf1: // Graphics Cursor Y
1308 return s->vga.sr[0x11];
1309 case 0x05: // ???
1310 case 0x07: // Extended Sequencer Mode
1311 case 0x08: // EEPROM Control
1312 case 0x09: // Scratch Register 0
1313 case 0x0a: // Scratch Register 1
1314 case 0x0b: // VCLK 0
1315 case 0x0c: // VCLK 1
1316 case 0x0d: // VCLK 2
1317 case 0x0e: // VCLK 3
1318 case 0x0f: // DRAM Control
1319 case 0x12: // Graphics Cursor Attribute
1320 case 0x13: // Graphics Cursor Pattern Address
1321 case 0x14: // Scratch Register 2
1322 case 0x15: // Scratch Register 3
1323 case 0x16: // Performance Tuning Register
1324 case 0x17: // Configuration Readback and Extended Control
1325 case 0x18: // Signature Generator Control
1326 case 0x19: // Signal Generator Result
1327 case 0x1a: // Signal Generator Result
1328 case 0x1b: // VCLK 0 Denominator & Post
1329 case 0x1c: // VCLK 1 Denominator & Post
1330 case 0x1d: // VCLK 2 Denominator & Post
1331 case 0x1e: // VCLK 3 Denominator & Post
1332 case 0x1f: // BIOS Write Enable and MCLK select
1333 #ifdef DEBUG_CIRRUS
1334 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
1335 #endif
1336 return s->vga.sr[s->vga.sr_index];
1337 default:
1338 #ifdef DEBUG_CIRRUS
1339 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
1340 #endif
1341 return 0xff;
1342 break;
1343 }
1344 }
1345
1346 static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
1347 {
1348 switch (s->vga.sr_index) {
1349 case 0x00: // Standard VGA
1350 case 0x01: // Standard VGA
1351 case 0x02: // Standard VGA
1352 case 0x03: // Standard VGA
1353 case 0x04: // Standard VGA
1354 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1355 if (s->vga.sr_index == 1)
1356 s->vga.update_retrace_info(&s->vga);
1357 break;
1358 case 0x06: // Unlock Cirrus extensions
1359 val &= 0x17;
1360 if (val == 0x12) {
1361 s->vga.sr[s->vga.sr_index] = 0x12;
1362 } else {
1363 s->vga.sr[s->vga.sr_index] = 0x0f;
1364 }
1365 break;
1366 case 0x10:
1367 case 0x30:
1368 case 0x50:
1369 case 0x70: // Graphics Cursor X
1370 case 0x90:
1371 case 0xb0:
1372 case 0xd0:
1373 case 0xf0: // Graphics Cursor X
1374 s->vga.sr[0x10] = val;
1375 s->vga.hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
1376 break;
1377 case 0x11:
1378 case 0x31:
1379 case 0x51:
1380 case 0x71: // Graphics Cursor Y
1381 case 0x91:
1382 case 0xb1:
1383 case 0xd1:
1384 case 0xf1: // Graphics Cursor Y
1385 s->vga.sr[0x11] = val;
1386 s->vga.hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
1387 break;
1388 case 0x07: // Extended Sequencer Mode
1389 cirrus_update_memory_access(s);
1390 case 0x08: // EEPROM Control
1391 case 0x09: // Scratch Register 0
1392 case 0x0a: // Scratch Register 1
1393 case 0x0b: // VCLK 0
1394 case 0x0c: // VCLK 1
1395 case 0x0d: // VCLK 2
1396 case 0x0e: // VCLK 3
1397 case 0x0f: // DRAM Control
1398 case 0x13: // Graphics Cursor Pattern Address
1399 case 0x14: // Scratch Register 2
1400 case 0x15: // Scratch Register 3
1401 case 0x16: // Performance Tuning Register
1402 case 0x18: // Signature Generator Control
1403 case 0x19: // Signature Generator Result
1404 case 0x1a: // Signature Generator Result
1405 case 0x1b: // VCLK 0 Denominator & Post
1406 case 0x1c: // VCLK 1 Denominator & Post
1407 case 0x1d: // VCLK 2 Denominator & Post
1408 case 0x1e: // VCLK 3 Denominator & Post
1409 case 0x1f: // BIOS Write Enable and MCLK select
1410 s->vga.sr[s->vga.sr_index] = val;
1411 #ifdef DEBUG_CIRRUS
1412 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1413 s->vga.sr_index, val);
1414 #endif
1415 break;
1416 case 0x12: // Graphics Cursor Attribute
1417 s->vga.sr[0x12] = val;
1418 s->vga.force_shadow = !!(val & CIRRUS_CURSOR_SHOW);
1419 #ifdef DEBUG_CIRRUS
1420 printf("cirrus: cursor ctl SR12=%02x (force shadow: %d)\n",
1421 val, s->vga.force_shadow);
1422 #endif
1423 break;
1424 case 0x17: // Configuration Readback and Extended Control
1425 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1426 | (val & 0xc7);
1427 cirrus_update_memory_access(s);
1428 break;
1429 default:
1430 #ifdef DEBUG_CIRRUS
1431 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1432 s->vga.sr_index, val);
1433 #endif
1434 break;
1435 }
1436 }
1437
1438 /***************************************
1439 *
1440 * I/O access at 0x3c6
1441 *
1442 ***************************************/
1443
1444 static int cirrus_read_hidden_dac(CirrusVGAState * s)
1445 {
1446 if (++s->cirrus_hidden_dac_lockindex == 5) {
1447 s->cirrus_hidden_dac_lockindex = 0;
1448 return s->cirrus_hidden_dac_data;
1449 }
1450 return 0xff;
1451 }
1452
1453 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1454 {
1455 if (s->cirrus_hidden_dac_lockindex == 4) {
1456 s->cirrus_hidden_dac_data = reg_value;
1457 #if defined(DEBUG_CIRRUS)
1458 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1459 #endif
1460 }
1461 s->cirrus_hidden_dac_lockindex = 0;
1462 }
1463
1464 /***************************************
1465 *
1466 * I/O access at 0x3c9
1467 *
1468 ***************************************/
1469
1470 static int cirrus_vga_read_palette(CirrusVGAState * s)
1471 {
1472 int val;
1473
1474 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1475 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1476 s->vga.dac_sub_index];
1477 } else {
1478 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1479 }
1480 if (++s->vga.dac_sub_index == 3) {
1481 s->vga.dac_sub_index = 0;
1482 s->vga.dac_read_index++;
1483 }
1484 return val;
1485 }
1486
1487 static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
1488 {
1489 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1490 if (++s->vga.dac_sub_index == 3) {
1491 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1492 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1493 s->vga.dac_cache, 3);
1494 } else {
1495 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1496 }
1497 /* XXX update cursor */
1498 s->vga.dac_sub_index = 0;
1499 s->vga.dac_write_index++;
1500 }
1501 }
1502
1503 /***************************************
1504 *
1505 * I/O access between 0x3ce-0x3cf
1506 *
1507 ***************************************/
1508
1509 static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
1510 {
1511 switch (reg_index) {
1512 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1513 return s->cirrus_shadow_gr0;
1514 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1515 return s->cirrus_shadow_gr1;
1516 case 0x02: // Standard VGA
1517 case 0x03: // Standard VGA
1518 case 0x04: // Standard VGA
1519 case 0x06: // Standard VGA
1520 case 0x07: // Standard VGA
1521 case 0x08: // Standard VGA
1522 return s->vga.gr[s->vga.gr_index];
1523 case 0x05: // Standard VGA, Cirrus extended mode
1524 default:
1525 break;
1526 }
1527
1528 if (reg_index < 0x3a) {
1529 return s->vga.gr[reg_index];
1530 } else {
1531 #ifdef DEBUG_CIRRUS
1532 printf("cirrus: inport gr_index %02x\n", reg_index);
1533 #endif
1534 return 0xff;
1535 }
1536 }
1537
1538 static void
1539 cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1540 {
1541 #if defined(DEBUG_BITBLT) && 0
1542 printf("gr%02x: %02x\n", reg_index, reg_value);
1543 #endif
1544 switch (reg_index) {
1545 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1546 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1547 s->cirrus_shadow_gr0 = reg_value;
1548 break;
1549 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1550 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1551 s->cirrus_shadow_gr1 = reg_value;
1552 break;
1553 case 0x02: // Standard VGA
1554 case 0x03: // Standard VGA
1555 case 0x04: // Standard VGA
1556 case 0x06: // Standard VGA
1557 case 0x07: // Standard VGA
1558 case 0x08: // Standard VGA
1559 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1560 break;
1561 case 0x05: // Standard VGA, Cirrus extended mode
1562 s->vga.gr[reg_index] = reg_value & 0x7f;
1563 cirrus_update_memory_access(s);
1564 break;
1565 case 0x09: // bank offset #0
1566 case 0x0A: // bank offset #1
1567 s->vga.gr[reg_index] = reg_value;
1568 cirrus_update_bank_ptr(s, 0);
1569 cirrus_update_bank_ptr(s, 1);
1570 cirrus_update_memory_access(s);
1571 break;
1572 case 0x0B:
1573 s->vga.gr[reg_index] = reg_value;
1574 cirrus_update_bank_ptr(s, 0);
1575 cirrus_update_bank_ptr(s, 1);
1576 cirrus_update_memory_access(s);
1577 break;
1578 case 0x10: // BGCOLOR 0x0000ff00
1579 case 0x11: // FGCOLOR 0x0000ff00
1580 case 0x12: // BGCOLOR 0x00ff0000
1581 case 0x13: // FGCOLOR 0x00ff0000
1582 case 0x14: // BGCOLOR 0xff000000
1583 case 0x15: // FGCOLOR 0xff000000
1584 case 0x20: // BLT WIDTH 0x0000ff
1585 case 0x22: // BLT HEIGHT 0x0000ff
1586 case 0x24: // BLT DEST PITCH 0x0000ff
1587 case 0x26: // BLT SRC PITCH 0x0000ff
1588 case 0x28: // BLT DEST ADDR 0x0000ff
1589 case 0x29: // BLT DEST ADDR 0x00ff00
1590 case 0x2c: // BLT SRC ADDR 0x0000ff
1591 case 0x2d: // BLT SRC ADDR 0x00ff00
1592 case 0x2f: // BLT WRITEMASK
1593 case 0x30: // BLT MODE
1594 case 0x32: // RASTER OP
1595 case 0x33: // BLT MODEEXT
1596 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1597 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1598 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1599 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1600 s->vga.gr[reg_index] = reg_value;
1601 break;
1602 case 0x21: // BLT WIDTH 0x001f00
1603 case 0x23: // BLT HEIGHT 0x001f00
1604 case 0x25: // BLT DEST PITCH 0x001f00
1605 case 0x27: // BLT SRC PITCH 0x001f00
1606 s->vga.gr[reg_index] = reg_value & 0x1f;
1607 break;
1608 case 0x2a: // BLT DEST ADDR 0x3f0000
1609 s->vga.gr[reg_index] = reg_value & 0x3f;
1610 /* if auto start mode, starts bit blt now */
1611 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1612 cirrus_bitblt_start(s);
1613 }
1614 break;
1615 case 0x2e: // BLT SRC ADDR 0x3f0000
1616 s->vga.gr[reg_index] = reg_value & 0x3f;
1617 break;
1618 case 0x31: // BLT STATUS/START
1619 cirrus_write_bitblt(s, reg_value);
1620 break;
1621 default:
1622 #ifdef DEBUG_CIRRUS
1623 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1624 reg_value);
1625 #endif
1626 break;
1627 }
1628 }
1629
1630 /***************************************
1631 *
1632 * I/O access between 0x3d4-0x3d5
1633 *
1634 ***************************************/
1635
1636 static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
1637 {
1638 switch (reg_index) {
1639 case 0x00: // Standard VGA
1640 case 0x01: // Standard VGA
1641 case 0x02: // Standard VGA
1642 case 0x03: // Standard VGA
1643 case 0x04: // Standard VGA
1644 case 0x05: // Standard VGA
1645 case 0x06: // Standard VGA
1646 case 0x07: // Standard VGA
1647 case 0x08: // Standard VGA
1648 case 0x09: // Standard VGA
1649 case 0x0a: // Standard VGA
1650 case 0x0b: // Standard VGA
1651 case 0x0c: // Standard VGA
1652 case 0x0d: // Standard VGA
1653 case 0x0e: // Standard VGA
1654 case 0x0f: // Standard VGA
1655 case 0x10: // Standard VGA
1656 case 0x11: // Standard VGA
1657 case 0x12: // Standard VGA
1658 case 0x13: // Standard VGA
1659 case 0x14: // Standard VGA
1660 case 0x15: // Standard VGA
1661 case 0x16: // Standard VGA
1662 case 0x17: // Standard VGA
1663 case 0x18: // Standard VGA
1664 return s->vga.cr[s->vga.cr_index];
1665 case 0x24: // Attribute Controller Toggle Readback (R)
1666 return (s->vga.ar_flip_flop << 7);
1667 case 0x19: // Interlace End
1668 case 0x1a: // Miscellaneous Control
1669 case 0x1b: // Extended Display Control
1670 case 0x1c: // Sync Adjust and Genlock
1671 case 0x1d: // Overlay Extended Control
1672 case 0x22: // Graphics Data Latches Readback (R)
1673 case 0x25: // Part Status
1674 case 0x27: // Part ID (R)
1675 return s->vga.cr[s->vga.cr_index];
1676 case 0x26: // Attribute Controller Index Readback (R)
1677 return s->vga.ar_index & 0x3f;
1678 break;
1679 default:
1680 #ifdef DEBUG_CIRRUS
1681 printf("cirrus: inport cr_index %02x\n", reg_index);
1682 #endif
1683 return 0xff;
1684 }
1685 }
1686
1687 static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
1688 {
1689 switch (s->vga.cr_index) {
1690 case 0x00: // Standard VGA
1691 case 0x01: // Standard VGA
1692 case 0x02: // Standard VGA
1693 case 0x03: // Standard VGA
1694 case 0x04: // Standard VGA
1695 case 0x05: // Standard VGA
1696 case 0x06: // Standard VGA
1697 case 0x07: // Standard VGA
1698 case 0x08: // Standard VGA
1699 case 0x09: // Standard VGA
1700 case 0x0a: // Standard VGA
1701 case 0x0b: // Standard VGA
1702 case 0x0c: // Standard VGA
1703 case 0x0d: // Standard VGA
1704 case 0x0e: // Standard VGA
1705 case 0x0f: // Standard VGA
1706 case 0x10: // Standard VGA
1707 case 0x11: // Standard VGA
1708 case 0x12: // Standard VGA
1709 case 0x13: // Standard VGA
1710 case 0x14: // Standard VGA
1711 case 0x15: // Standard VGA
1712 case 0x16: // Standard VGA
1713 case 0x17: // Standard VGA
1714 case 0x18: // Standard VGA
1715 /* handle CR0-7 protection */
1716 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1717 /* can always write bit 4 of CR7 */
1718 if (s->vga.cr_index == 7)
1719 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1720 return;
1721 }
1722 s->vga.cr[s->vga.cr_index] = reg_value;
1723 switch(s->vga.cr_index) {
1724 case 0x00:
1725 case 0x04:
1726 case 0x05:
1727 case 0x06:
1728 case 0x07:
1729 case 0x11:
1730 case 0x17:
1731 s->vga.update_retrace_info(&s->vga);
1732 break;
1733 }
1734 break;
1735 case 0x19: // Interlace End
1736 case 0x1a: // Miscellaneous Control
1737 case 0x1b: // Extended Display Control
1738 case 0x1c: // Sync Adjust and Genlock
1739 case 0x1d: // Overlay Extended Control
1740 s->vga.cr[s->vga.cr_index] = reg_value;
1741 #ifdef DEBUG_CIRRUS
1742 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1743 s->vga.cr_index, reg_value);
1744 #endif
1745 break;
1746 case 0x22: // Graphics Data Latches Readback (R)
1747 case 0x24: // Attribute Controller Toggle Readback (R)
1748 case 0x26: // Attribute Controller Index Readback (R)
1749 case 0x27: // Part ID (R)
1750 break;
1751 case 0x25: // Part Status
1752 default:
1753 #ifdef DEBUG_CIRRUS
1754 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1755 s->vga.cr_index, reg_value);
1756 #endif
1757 break;
1758 }
1759 }
1760
1761 /***************************************
1762 *
1763 * memory-mapped I/O (bitblt)
1764 *
1765 ***************************************/
1766
1767 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1768 {
1769 int value = 0xff;
1770
1771 switch (address) {
1772 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1773 value = cirrus_vga_read_gr(s, 0x00);
1774 break;
1775 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1776 value = cirrus_vga_read_gr(s, 0x10);
1777 break;
1778 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1779 value = cirrus_vga_read_gr(s, 0x12);
1780 break;
1781 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1782 value = cirrus_vga_read_gr(s, 0x14);
1783 break;
1784 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1785 value = cirrus_vga_read_gr(s, 0x01);
1786 break;
1787 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1788 value = cirrus_vga_read_gr(s, 0x11);
1789 break;
1790 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1791 value = cirrus_vga_read_gr(s, 0x13);
1792 break;
1793 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1794 value = cirrus_vga_read_gr(s, 0x15);
1795 break;
1796 case (CIRRUS_MMIO_BLTWIDTH + 0):
1797 value = cirrus_vga_read_gr(s, 0x20);
1798 break;
1799 case (CIRRUS_MMIO_BLTWIDTH + 1):
1800 value = cirrus_vga_read_gr(s, 0x21);
1801 break;
1802 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1803 value = cirrus_vga_read_gr(s, 0x22);
1804 break;
1805 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1806 value = cirrus_vga_read_gr(s, 0x23);
1807 break;
1808 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1809 value = cirrus_vga_read_gr(s, 0x24);
1810 break;
1811 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1812 value = cirrus_vga_read_gr(s, 0x25);
1813 break;
1814 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1815 value = cirrus_vga_read_gr(s, 0x26);
1816 break;
1817 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1818 value = cirrus_vga_read_gr(s, 0x27);
1819 break;
1820 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1821 value = cirrus_vga_read_gr(s, 0x28);
1822 break;
1823 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1824 value = cirrus_vga_read_gr(s, 0x29);
1825 break;
1826 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1827 value = cirrus_vga_read_gr(s, 0x2a);
1828 break;
1829 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1830 value = cirrus_vga_read_gr(s, 0x2c);
1831 break;
1832 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1833 value = cirrus_vga_read_gr(s, 0x2d);
1834 break;
1835 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1836 value = cirrus_vga_read_gr(s, 0x2e);
1837 break;
1838 case CIRRUS_MMIO_BLTWRITEMASK:
1839 value = cirrus_vga_read_gr(s, 0x2f);
1840 break;
1841 case CIRRUS_MMIO_BLTMODE:
1842 value = cirrus_vga_read_gr(s, 0x30);
1843 break;
1844 case CIRRUS_MMIO_BLTROP:
1845 value = cirrus_vga_read_gr(s, 0x32);
1846 break;
1847 case CIRRUS_MMIO_BLTMODEEXT:
1848 value = cirrus_vga_read_gr(s, 0x33);
1849 break;
1850 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1851 value = cirrus_vga_read_gr(s, 0x34);
1852 break;
1853 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1854 value = cirrus_vga_read_gr(s, 0x35);
1855 break;
1856 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1857 value = cirrus_vga_read_gr(s, 0x38);
1858 break;
1859 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1860 value = cirrus_vga_read_gr(s, 0x39);
1861 break;
1862 case CIRRUS_MMIO_BLTSTATUS:
1863 value = cirrus_vga_read_gr(s, 0x31);
1864 break;
1865 default:
1866 #ifdef DEBUG_CIRRUS
1867 printf("cirrus: mmio read - address 0x%04x\n", address);
1868 #endif
1869 break;
1870 }
1871
1872 trace_vga_cirrus_write_blt(address, value);
1873 return (uint8_t) value;
1874 }
1875
1876 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1877 uint8_t value)
1878 {
1879 trace_vga_cirrus_write_blt(address, value);
1880 switch (address) {
1881 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1882 cirrus_vga_write_gr(s, 0x00, value);
1883 break;
1884 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1885 cirrus_vga_write_gr(s, 0x10, value);
1886 break;
1887 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1888 cirrus_vga_write_gr(s, 0x12, value);
1889 break;
1890 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1891 cirrus_vga_write_gr(s, 0x14, value);
1892 break;
1893 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1894 cirrus_vga_write_gr(s, 0x01, value);
1895 break;
1896 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1897 cirrus_vga_write_gr(s, 0x11, value);
1898 break;
1899 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1900 cirrus_vga_write_gr(s, 0x13, value);
1901 break;
1902 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1903 cirrus_vga_write_gr(s, 0x15, value);
1904 break;
1905 case (CIRRUS_MMIO_BLTWIDTH + 0):
1906 cirrus_vga_write_gr(s, 0x20, value);
1907 break;
1908 case (CIRRUS_MMIO_BLTWIDTH + 1):
1909 cirrus_vga_write_gr(s, 0x21, value);
1910 break;
1911 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1912 cirrus_vga_write_gr(s, 0x22, value);
1913 break;
1914 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1915 cirrus_vga_write_gr(s, 0x23, value);
1916 break;
1917 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1918 cirrus_vga_write_gr(s, 0x24, value);
1919 break;
1920 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1921 cirrus_vga_write_gr(s, 0x25, value);
1922 break;
1923 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1924 cirrus_vga_write_gr(s, 0x26, value);
1925 break;
1926 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1927 cirrus_vga_write_gr(s, 0x27, value);
1928 break;
1929 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1930 cirrus_vga_write_gr(s, 0x28, value);
1931 break;
1932 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1933 cirrus_vga_write_gr(s, 0x29, value);
1934 break;
1935 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1936 cirrus_vga_write_gr(s, 0x2a, value);
1937 break;
1938 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1939 /* ignored */
1940 break;
1941 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1942 cirrus_vga_write_gr(s, 0x2c, value);
1943 break;
1944 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1945 cirrus_vga_write_gr(s, 0x2d, value);
1946 break;
1947 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1948 cirrus_vga_write_gr(s, 0x2e, value);
1949 break;
1950 case CIRRUS_MMIO_BLTWRITEMASK:
1951 cirrus_vga_write_gr(s, 0x2f, value);
1952 break;
1953 case CIRRUS_MMIO_BLTMODE:
1954 cirrus_vga_write_gr(s, 0x30, value);
1955 break;
1956 case CIRRUS_MMIO_BLTROP:
1957 cirrus_vga_write_gr(s, 0x32, value);
1958 break;
1959 case CIRRUS_MMIO_BLTMODEEXT:
1960 cirrus_vga_write_gr(s, 0x33, value);
1961 break;
1962 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1963 cirrus_vga_write_gr(s, 0x34, value);
1964 break;
1965 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1966 cirrus_vga_write_gr(s, 0x35, value);
1967 break;
1968 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1969 cirrus_vga_write_gr(s, 0x38, value);
1970 break;
1971 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1972 cirrus_vga_write_gr(s, 0x39, value);
1973 break;
1974 case CIRRUS_MMIO_BLTSTATUS:
1975 cirrus_vga_write_gr(s, 0x31, value);
1976 break;
1977 default:
1978 #ifdef DEBUG_CIRRUS
1979 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1980 address, value);
1981 #endif
1982 break;
1983 }
1984 }
1985
1986 /***************************************
1987 *
1988 * write mode 4/5
1989 *
1990 ***************************************/
1991
1992 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1993 unsigned mode,
1994 unsigned offset,
1995 uint32_t mem_value)
1996 {
1997 int x;
1998 unsigned val = mem_value;
1999 uint8_t *dst;
2000
2001 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
2002 for (x = 0; x < 8; x++) {
2003 if (val & 0x80) {
2004 *dst = s->cirrus_shadow_gr1;
2005 } else if (mode == 5) {
2006 *dst = s->cirrus_shadow_gr0;
2007 }
2008 val <<= 1;
2009 dst++;
2010 }
2011 memory_region_set_dirty(&s->vga.vram, offset, 8);
2012 }
2013
2014 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
2015 unsigned mode,
2016 unsigned offset,
2017 uint32_t mem_value)
2018 {
2019 int x;
2020 unsigned val = mem_value;
2021 uint8_t *dst;
2022
2023 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
2024 for (x = 0; x < 8; x++) {
2025 if (val & 0x80) {
2026 *dst = s->cirrus_shadow_gr1;
2027 *(dst + 1) = s->vga.gr[0x11];
2028 } else if (mode == 5) {
2029 *dst = s->cirrus_shadow_gr0;
2030 *(dst + 1) = s->vga.gr[0x10];
2031 }
2032 val <<= 1;
2033 dst += 2;
2034 }
2035 memory_region_set_dirty(&s->vga.vram, offset, 16);
2036 }
2037
2038 /***************************************
2039 *
2040 * memory access between 0xa0000-0xbffff
2041 *
2042 ***************************************/
2043
2044 static uint64_t cirrus_vga_mem_read(void *opaque,
2045 hwaddr addr,
2046 uint32_t size)
2047 {
2048 CirrusVGAState *s = opaque;
2049 unsigned bank_index;
2050 unsigned bank_offset;
2051 uint32_t val;
2052
2053 if ((s->vga.sr[0x07] & 0x01) == 0) {
2054 return vga_mem_readb(&s->vga, addr);
2055 }
2056
2057 if (addr < 0x10000) {
2058 /* XXX handle bitblt */
2059 /* video memory */
2060 bank_index = addr >> 15;
2061 bank_offset = addr & 0x7fff;
2062 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2063 bank_offset += s->cirrus_bank_base[bank_index];
2064 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2065 bank_offset <<= 4;
2066 } else if (s->vga.gr[0x0B] & 0x02) {
2067 bank_offset <<= 3;
2068 }
2069 bank_offset &= s->cirrus_addr_mask;
2070 val = *(s->vga.vram_ptr + bank_offset);
2071 } else
2072 val = 0xff;
2073 } else if (addr >= 0x18000 && addr < 0x18100) {
2074 /* memory-mapped I/O */
2075 val = 0xff;
2076 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2077 val = cirrus_mmio_blt_read(s, addr & 0xff);
2078 }
2079 } else {
2080 val = 0xff;
2081 #ifdef DEBUG_CIRRUS
2082 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
2083 #endif
2084 }
2085 return val;
2086 }
2087
2088 static void cirrus_vga_mem_write(void *opaque,
2089 hwaddr addr,
2090 uint64_t mem_value,
2091 uint32_t size)
2092 {
2093 CirrusVGAState *s = opaque;
2094 unsigned bank_index;
2095 unsigned bank_offset;
2096 unsigned mode;
2097
2098 if ((s->vga.sr[0x07] & 0x01) == 0) {
2099 vga_mem_writeb(&s->vga, addr, mem_value);
2100 return;
2101 }
2102
2103 if (addr < 0x10000) {
2104 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2105 /* bitblt */
2106 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2107 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2108 cirrus_bitblt_cputovideo_next(s);
2109 }
2110 } else {
2111 /* video memory */
2112 bank_index = addr >> 15;
2113 bank_offset = addr & 0x7fff;
2114 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2115 bank_offset += s->cirrus_bank_base[bank_index];
2116 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2117 bank_offset <<= 4;
2118 } else if (s->vga.gr[0x0B] & 0x02) {
2119 bank_offset <<= 3;
2120 }
2121 bank_offset &= s->cirrus_addr_mask;
2122 mode = s->vga.gr[0x05] & 0x7;
2123 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2124 *(s->vga.vram_ptr + bank_offset) = mem_value;
2125 memory_region_set_dirty(&s->vga.vram, bank_offset,
2126 sizeof(mem_value));
2127 } else {
2128 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2129 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2130 bank_offset,
2131 mem_value);
2132 } else {
2133 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2134 bank_offset,
2135 mem_value);
2136 }
2137 }
2138 }
2139 }
2140 } else if (addr >= 0x18000 && addr < 0x18100) {
2141 /* memory-mapped I/O */
2142 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2143 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2144 }
2145 } else {
2146 #ifdef DEBUG_CIRRUS
2147 printf("cirrus: mem_writeb " TARGET_FMT_plx " value 0x%02" PRIu64 "\n", addr,
2148 mem_value);
2149 #endif
2150 }
2151 }
2152
2153 static const MemoryRegionOps cirrus_vga_mem_ops = {
2154 .read = cirrus_vga_mem_read,
2155 .write = cirrus_vga_mem_write,
2156 .endianness = DEVICE_LITTLE_ENDIAN,
2157 .impl = {
2158 .min_access_size = 1,
2159 .max_access_size = 1,
2160 },
2161 };
2162
2163 /***************************************
2164 *
2165 * hardware cursor
2166 *
2167 ***************************************/
2168
2169 static inline void invalidate_cursor1(CirrusVGAState *s)
2170 {
2171 if (s->last_hw_cursor_size) {
2172 vga_invalidate_scanlines(&s->vga,
2173 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2174 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2175 }
2176 }
2177
2178 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2179 {
2180 const uint8_t *src;
2181 uint32_t content;
2182 int y, y_min, y_max;
2183
2184 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2185 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2186 src += (s->vga.sr[0x13] & 0x3c) * 256;
2187 y_min = 64;
2188 y_max = -1;
2189 for(y = 0; y < 64; y++) {
2190 content = ((uint32_t *)src)[0] |
2191 ((uint32_t *)src)[1] |
2192 ((uint32_t *)src)[2] |
2193 ((uint32_t *)src)[3];
2194 if (content) {
2195 if (y < y_min)
2196 y_min = y;
2197 if (y > y_max)
2198 y_max = y;
2199 }
2200 src += 16;
2201 }
2202 } else {
2203 src += (s->vga.sr[0x13] & 0x3f) * 256;
2204 y_min = 32;
2205 y_max = -1;
2206 for(y = 0; y < 32; y++) {
2207 content = ((uint32_t *)src)[0] |
2208 ((uint32_t *)(src + 128))[0];
2209 if (content) {
2210 if (y < y_min)
2211 y_min = y;
2212 if (y > y_max)
2213 y_max = y;
2214 }
2215 src += 4;
2216 }
2217 }
2218 if (y_min > y_max) {
2219 s->last_hw_cursor_y_start = 0;
2220 s->last_hw_cursor_y_end = 0;
2221 } else {
2222 s->last_hw_cursor_y_start = y_min;
2223 s->last_hw_cursor_y_end = y_max + 1;
2224 }
2225 }
2226
2227 /* NOTE: we do not currently handle the cursor bitmap change, so we
2228 update the cursor only if it moves. */
2229 static void cirrus_cursor_invalidate(VGACommonState *s1)
2230 {
2231 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2232 int size;
2233
2234 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
2235 size = 0;
2236 } else {
2237 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
2238 size = 64;
2239 else
2240 size = 32;
2241 }
2242 /* invalidate last cursor and new cursor if any change */
2243 if (s->last_hw_cursor_size != size ||
2244 s->last_hw_cursor_x != s->vga.hw_cursor_x ||
2245 s->last_hw_cursor_y != s->vga.hw_cursor_y) {
2246
2247 invalidate_cursor1(s);
2248
2249 s->last_hw_cursor_size = size;
2250 s->last_hw_cursor_x = s->vga.hw_cursor_x;
2251 s->last_hw_cursor_y = s->vga.hw_cursor_y;
2252 /* compute the real cursor min and max y */
2253 cirrus_cursor_compute_yrange(s);
2254 invalidate_cursor1(s);
2255 }
2256 }
2257
2258 static void vga_draw_cursor_line(uint8_t *d1,
2259 const uint8_t *src1,
2260 int poffset, int w,
2261 unsigned int color0,
2262 unsigned int color1,
2263 unsigned int color_xor)
2264 {
2265 const uint8_t *plane0, *plane1;
2266 int x, b0, b1;
2267 uint8_t *d;
2268
2269 d = d1;
2270 plane0 = src1;
2271 plane1 = src1 + poffset;
2272 for (x = 0; x < w; x++) {
2273 b0 = (plane0[x >> 3] >> (7 - (x & 7))) & 1;
2274 b1 = (plane1[x >> 3] >> (7 - (x & 7))) & 1;
2275 switch (b0 | (b1 << 1)) {
2276 case 0:
2277 break;
2278 case 1:
2279 ((uint32_t *)d)[0] ^= color_xor;
2280 break;
2281 case 2:
2282 ((uint32_t *)d)[0] = color0;
2283 break;
2284 case 3:
2285 ((uint32_t *)d)[0] = color1;
2286 break;
2287 }
2288 d += 4;
2289 }
2290 }
2291
2292 static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
2293 {
2294 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2295 int w, h, x1, x2, poffset;
2296 unsigned int color0, color1;
2297 const uint8_t *palette, *src;
2298 uint32_t content;
2299
2300 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
2301 return;
2302 /* fast test to see if the cursor intersects with the scan line */
2303 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2304 h = 64;
2305 } else {
2306 h = 32;
2307 }
2308 if (scr_y < s->vga.hw_cursor_y ||
2309 scr_y >= (s->vga.hw_cursor_y + h)) {
2310 return;
2311 }
2312
2313 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2314 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2315 src += (s->vga.sr[0x13] & 0x3c) * 256;
2316 src += (scr_y - s->vga.hw_cursor_y) * 16;
2317 poffset = 8;
2318 content = ((uint32_t *)src)[0] |
2319 ((uint32_t *)src)[1] |
2320 ((uint32_t *)src)[2] |
2321 ((uint32_t *)src)[3];
2322 } else {
2323 src += (s->vga.sr[0x13] & 0x3f) * 256;
2324 src += (scr_y - s->vga.hw_cursor_y) * 4;
2325
2326
2327 poffset = 128;
2328 content = ((uint32_t *)src)[0] |
2329 ((uint32_t *)(src + 128))[0];
2330 }
2331 /* if nothing to draw, no need to continue */
2332 if (!content)
2333 return;
2334 w = h;
2335
2336 x1 = s->vga.hw_cursor_x;
2337 if (x1 >= s->vga.last_scr_width)
2338 return;
2339 x2 = s->vga.hw_cursor_x + w;
2340 if (x2 > s->vga.last_scr_width)
2341 x2 = s->vga.last_scr_width;
2342 w = x2 - x1;
2343 palette = s->cirrus_hidden_palette;
2344 color0 = rgb_to_pixel32(c6_to_8(palette[0x0 * 3]),
2345 c6_to_8(palette[0x0 * 3 + 1]),
2346 c6_to_8(palette[0x0 * 3 + 2]));
2347 color1 = rgb_to_pixel32(c6_to_8(palette[0xf * 3]),
2348 c6_to_8(palette[0xf * 3 + 1]),
2349 c6_to_8(palette[0xf * 3 + 2]));
2350 d1 += x1 * 4;
2351 vga_draw_cursor_line(d1, src, poffset, w, color0, color1, 0xffffff);
2352 }
2353
2354 /***************************************
2355 *
2356 * LFB memory access
2357 *
2358 ***************************************/
2359
2360 static uint64_t cirrus_linear_read(void *opaque, hwaddr addr,
2361 unsigned size)
2362 {
2363 CirrusVGAState *s = opaque;
2364 uint32_t ret;
2365
2366 addr &= s->cirrus_addr_mask;
2367
2368 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2369 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2370 /* memory-mapped I/O */
2371 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2372 } else if (0) {
2373 /* XXX handle bitblt */
2374 ret = 0xff;
2375 } else {
2376 /* video memory */
2377 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2378 addr <<= 4;
2379 } else if (s->vga.gr[0x0B] & 0x02) {
2380 addr <<= 3;
2381 }
2382 addr &= s->cirrus_addr_mask;
2383 ret = *(s->vga.vram_ptr + addr);
2384 }
2385
2386 return ret;
2387 }
2388
2389 static void cirrus_linear_write(void *opaque, hwaddr addr,
2390 uint64_t val, unsigned size)
2391 {
2392 CirrusVGAState *s = opaque;
2393 unsigned mode;
2394
2395 addr &= s->cirrus_addr_mask;
2396
2397 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2398 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2399 /* memory-mapped I/O */
2400 cirrus_mmio_blt_write(s, addr & 0xff, val);
2401 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2402 /* bitblt */
2403 *s->cirrus_srcptr++ = (uint8_t) val;
2404 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2405 cirrus_bitblt_cputovideo_next(s);
2406 }
2407 } else {
2408 /* video memory */
2409 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2410 addr <<= 4;
2411 } else if (s->vga.gr[0x0B] & 0x02) {
2412 addr <<= 3;
2413 }
2414 addr &= s->cirrus_addr_mask;
2415
2416 mode = s->vga.gr[0x05] & 0x7;
2417 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2418 *(s->vga.vram_ptr + addr) = (uint8_t) val;
2419 memory_region_set_dirty(&s->vga.vram, addr, 1);
2420 } else {
2421 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2422 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2423 } else {
2424 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2425 }
2426 }
2427 }
2428 }
2429
2430 /***************************************
2431 *
2432 * system to screen memory access
2433 *
2434 ***************************************/
2435
2436
2437 static uint64_t cirrus_linear_bitblt_read(void *opaque,
2438 hwaddr addr,
2439 unsigned size)
2440 {
2441 CirrusVGAState *s = opaque;
2442 uint32_t ret;
2443
2444 /* XXX handle bitblt */
2445 (void)s;
2446 ret = 0xff;
2447 return ret;
2448 }
2449
2450 static void cirrus_linear_bitblt_write(void *opaque,
2451 hwaddr addr,
2452 uint64_t val,
2453 unsigned size)
2454 {
2455 CirrusVGAState *s = opaque;
2456
2457 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2458 /* bitblt */
2459 *s->cirrus_srcptr++ = (uint8_t) val;
2460 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2461 cirrus_bitblt_cputovideo_next(s);
2462 }
2463 }
2464 }
2465
2466 static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
2467 .read = cirrus_linear_bitblt_read,
2468 .write = cirrus_linear_bitblt_write,
2469 .endianness = DEVICE_LITTLE_ENDIAN,
2470 .impl = {
2471 .min_access_size = 1,
2472 .max_access_size = 1,
2473 },
2474 };
2475
2476 static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank)
2477 {
2478 MemoryRegion *mr = &s->cirrus_bank[bank];
2479 bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end)
2480 && !((s->vga.sr[0x07] & 0x01) == 0)
2481 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2482 && !(s->vga.gr[0x0B] & 0x02);
2483
2484 memory_region_set_enabled(mr, enabled);
2485 memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]);
2486 }
2487
2488 static void map_linear_vram(CirrusVGAState *s)
2489 {
2490 if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) {
2491 s->linear_vram = true;
2492 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1);
2493 }
2494 map_linear_vram_bank(s, 0);
2495 map_linear_vram_bank(s, 1);
2496 }
2497
2498 static void unmap_linear_vram(CirrusVGAState *s)
2499 {
2500 if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) {
2501 s->linear_vram = false;
2502 memory_region_del_subregion(&s->pci_bar, &s->vga.vram);
2503 }
2504 memory_region_set_enabled(&s->cirrus_bank[0], false);
2505 memory_region_set_enabled(&s->cirrus_bank[1], false);
2506 }
2507
2508 /* Compute the memory access functions */
2509 static void cirrus_update_memory_access(CirrusVGAState *s)
2510 {
2511 unsigned mode;
2512
2513 memory_region_transaction_begin();
2514 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
2515 goto generic_io;
2516 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2517 goto generic_io;
2518 } else {
2519 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2520 goto generic_io;
2521 } else if (s->vga.gr[0x0B] & 0x02) {
2522 goto generic_io;
2523 }
2524
2525 mode = s->vga.gr[0x05] & 0x7;
2526 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2527 map_linear_vram(s);
2528 } else {
2529 generic_io:
2530 unmap_linear_vram(s);
2531 }
2532 }
2533 memory_region_transaction_commit();
2534 }
2535
2536
2537 /* I/O ports */
2538
2539 static uint64_t cirrus_vga_ioport_read(void *opaque, hwaddr addr,
2540 unsigned size)
2541 {
2542 CirrusVGAState *c = opaque;
2543 VGACommonState *s = &c->vga;
2544 int val, index;
2545
2546 addr += 0x3b0;
2547
2548 if (vga_ioport_invalid(s, addr)) {
2549 val = 0xff;
2550 } else {
2551 switch (addr) {
2552 case 0x3c0:
2553 if (s->ar_flip_flop == 0) {
2554 val = s->ar_index;
2555 } else {
2556 val = 0;
2557 }
2558 break;
2559 case 0x3c1:
2560 index = s->ar_index & 0x1f;
2561 if (index < 21)
2562 val = s->ar[index];
2563 else
2564 val = 0;
2565 break;
2566 case 0x3c2:
2567 val = s->st00;
2568 break;
2569 case 0x3c4:
2570 val = s->sr_index;
2571 break;
2572 case 0x3c5:
2573 val = cirrus_vga_read_sr(c);
2574 break;
2575 #ifdef DEBUG_VGA_REG
2576 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2577 #endif
2578 break;
2579 case 0x3c6:
2580 val = cirrus_read_hidden_dac(c);
2581 break;
2582 case 0x3c7:
2583 val = s->dac_state;
2584 break;
2585 case 0x3c8:
2586 val = s->dac_write_index;
2587 c->cirrus_hidden_dac_lockindex = 0;
2588 break;
2589 case 0x3c9:
2590 val = cirrus_vga_read_palette(c);
2591 break;
2592 case 0x3ca:
2593 val = s->fcr;
2594 break;
2595 case 0x3cc:
2596 val = s->msr;
2597 break;
2598 case 0x3ce:
2599 val = s->gr_index;
2600 break;
2601 case 0x3cf:
2602 val = cirrus_vga_read_gr(c, s->gr_index);
2603 #ifdef DEBUG_VGA_REG
2604 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2605 #endif
2606 break;
2607 case 0x3b4:
2608 case 0x3d4:
2609 val = s->cr_index;
2610 break;
2611 case 0x3b5:
2612 case 0x3d5:
2613 val = cirrus_vga_read_cr(c, s->cr_index);
2614 #ifdef DEBUG_VGA_REG
2615 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2616 #endif
2617 break;
2618 case 0x3ba:
2619 case 0x3da:
2620 /* just toggle to fool polling */
2621 val = s->st01 = s->retrace(s);
2622 s->ar_flip_flop = 0;
2623 break;
2624 default:
2625 val = 0x00;
2626 break;
2627 }
2628 }
2629 trace_vga_cirrus_read_io(addr, val);
2630 return val;
2631 }
2632
2633 static void cirrus_vga_ioport_write(void *opaque, hwaddr addr, uint64_t val,
2634 unsigned size)
2635 {
2636 CirrusVGAState *c = opaque;
2637 VGACommonState *s = &c->vga;
2638 int index;
2639
2640 addr += 0x3b0;
2641
2642 /* check port range access depending on color/monochrome mode */
2643 if (vga_ioport_invalid(s, addr)) {
2644 return;
2645 }
2646 trace_vga_cirrus_write_io(addr, val);
2647
2648 switch (addr) {
2649 case 0x3c0:
2650 if (s->ar_flip_flop == 0) {
2651 val &= 0x3f;
2652 s->ar_index = val;
2653 } else {
2654 index = s->ar_index & 0x1f;
2655 switch (index) {
2656 case 0x00 ... 0x0f:
2657 s->ar[index] = val & 0x3f;
2658 break;
2659 case 0x10:
2660 s->ar[index] = val & ~0x10;
2661 break;
2662 case 0x11:
2663 s->ar[index] = val;
2664 break;
2665 case 0x12:
2666 s->ar[index] = val & ~0xc0;
2667 break;
2668 case 0x13:
2669 s->ar[index] = val & ~0xf0;
2670 break;
2671 case 0x14:
2672 s->ar[index] = val & ~0xf0;
2673 break;
2674 default:
2675 break;
2676 }
2677 }
2678 s->ar_flip_flop ^= 1;
2679 break;
2680 case 0x3c2:
2681 s->msr = val & ~0x10;
2682 s->update_retrace_info(s);
2683 break;
2684 case 0x3c4:
2685 s->sr_index = val;
2686 break;
2687 case 0x3c5:
2688 #ifdef DEBUG_VGA_REG
2689 printf("vga: write SR%x = 0x%02" PRIu64 "\n", s->sr_index, val);
2690 #endif
2691 cirrus_vga_write_sr(c, val);
2692 break;
2693 case 0x3c6:
2694 cirrus_write_hidden_dac(c, val);
2695 break;
2696 case 0x3c7:
2697 s->dac_read_index = val;
2698 s->dac_sub_index = 0;
2699 s->dac_state = 3;
2700 break;
2701 case 0x3c8:
2702 s->dac_write_index = val;
2703 s->dac_sub_index = 0;
2704 s->dac_state = 0;
2705 break;
2706 case 0x3c9:
2707 cirrus_vga_write_palette(c, val);
2708 break;
2709 case 0x3ce:
2710 s->gr_index = val;
2711 break;
2712 case 0x3cf:
2713 #ifdef DEBUG_VGA_REG
2714 printf("vga: write GR%x = 0x%02" PRIu64 "\n", s->gr_index, val);
2715 #endif
2716 cirrus_vga_write_gr(c, s->gr_index, val);
2717 break;
2718 case 0x3b4:
2719 case 0x3d4:
2720 s->cr_index = val;
2721 break;
2722 case 0x3b5:
2723 case 0x3d5:
2724 #ifdef DEBUG_VGA_REG
2725 printf("vga: write CR%x = 0x%02"PRIu64"\n", s->cr_index, val);
2726 #endif
2727 cirrus_vga_write_cr(c, val);
2728 break;
2729 case 0x3ba:
2730 case 0x3da:
2731 s->fcr = val & 0x10;
2732 break;
2733 }
2734 }
2735
2736 /***************************************
2737 *
2738 * memory-mapped I/O access
2739 *
2740 ***************************************/
2741
2742 static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr,
2743 unsigned size)
2744 {
2745 CirrusVGAState *s = opaque;
2746
2747 if (addr >= 0x100) {
2748 return cirrus_mmio_blt_read(s, addr - 0x100);
2749 } else {
2750 return cirrus_vga_ioport_read(s, addr + 0x10, size);
2751 }
2752 }
2753
2754 static void cirrus_mmio_write(void *opaque, hwaddr addr,
2755 uint64_t val, unsigned size)
2756 {
2757 CirrusVGAState *s = opaque;
2758
2759 if (addr >= 0x100) {
2760 cirrus_mmio_blt_write(s, addr - 0x100, val);
2761 } else {
2762 cirrus_vga_ioport_write(s, addr + 0x10, val, size);
2763 }
2764 }
2765
2766 static const MemoryRegionOps cirrus_mmio_io_ops = {
2767 .read = cirrus_mmio_read,
2768 .write = cirrus_mmio_write,
2769 .endianness = DEVICE_LITTLE_ENDIAN,
2770 .impl = {
2771 .min_access_size = 1,
2772 .max_access_size = 1,
2773 },
2774 };
2775
2776 /* load/save state */
2777
2778 static int cirrus_post_load(void *opaque, int version_id)
2779 {
2780 CirrusVGAState *s = opaque;
2781
2782 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2783 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2784
2785 cirrus_update_memory_access(s);
2786 /* force refresh */
2787 s->vga.graphic_mode = -1;
2788 cirrus_update_bank_ptr(s, 0);
2789 cirrus_update_bank_ptr(s, 1);
2790 return 0;
2791 }
2792
2793 static const VMStateDescription vmstate_cirrus_vga = {
2794 .name = "cirrus_vga",
2795 .version_id = 2,
2796 .minimum_version_id = 1,
2797 .post_load = cirrus_post_load,
2798 .fields = (VMStateField[]) {
2799 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2800 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2801 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2802 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2803 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2804 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2805 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2806 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2807 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2808 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2809 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2810 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2811 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2812 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2813 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2814 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2815 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2816 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2817 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2818 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2819 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2820 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2821 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2822 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2823 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
2824 VMSTATE_UINT32(vga.hw_cursor_x, CirrusVGAState),
2825 VMSTATE_UINT32(vga.hw_cursor_y, CirrusVGAState),
2826 /* XXX: we do not save the bitblt state - we assume we do not save
2827 the state when the blitter is active */
2828 VMSTATE_END_OF_LIST()
2829 }
2830 };
2831
2832 static const VMStateDescription vmstate_pci_cirrus_vga = {
2833 .name = "cirrus_vga",
2834 .version_id = 2,
2835 .minimum_version_id = 2,
2836 .fields = (VMStateField[]) {
2837 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2838 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2839 vmstate_cirrus_vga, CirrusVGAState),
2840 VMSTATE_END_OF_LIST()
2841 }
2842 };
2843
2844 /***************************************
2845 *
2846 * initialize
2847 *
2848 ***************************************/
2849
2850 static void cirrus_reset(void *opaque)
2851 {
2852 CirrusVGAState *s = opaque;
2853
2854 vga_common_reset(&s->vga);
2855 unmap_linear_vram(s);
2856 s->vga.sr[0x06] = 0x0f;
2857 if (s->device_id == CIRRUS_ID_CLGD5446) {
2858 /* 4MB 64 bit memory config, always PCI */
2859 s->vga.sr[0x1F] = 0x2d; // MemClock
2860 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
2861 s->vga.sr[0x0f] = 0x98;
2862 s->vga.sr[0x17] = 0x20;
2863 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
2864 } else {
2865 s->vga.sr[0x1F] = 0x22; // MemClock
2866 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
2867 s->vga.sr[0x17] = s->bustype;
2868 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
2869 }
2870 s->vga.cr[0x27] = s->device_id;
2871
2872 s->cirrus_hidden_dac_lockindex = 5;
2873 s->cirrus_hidden_dac_data = 0;
2874 }
2875
2876 static const MemoryRegionOps cirrus_linear_io_ops = {
2877 .read = cirrus_linear_read,
2878 .write = cirrus_linear_write,
2879 .endianness = DEVICE_LITTLE_ENDIAN,
2880 .impl = {
2881 .min_access_size = 1,
2882 .max_access_size = 1,
2883 },
2884 };
2885
2886 static const MemoryRegionOps cirrus_vga_io_ops = {
2887 .read = cirrus_vga_ioport_read,
2888 .write = cirrus_vga_ioport_write,
2889 .endianness = DEVICE_LITTLE_ENDIAN,
2890 .impl = {
2891 .min_access_size = 1,
2892 .max_access_size = 1,
2893 },
2894 };
2895
2896 static void cirrus_init_common(CirrusVGAState *s, Object *owner,
2897 int device_id, int is_pci,
2898 MemoryRegion *system_memory,
2899 MemoryRegion *system_io)
2900 {
2901 int i;
2902 static int inited;
2903
2904 if (!inited) {
2905 inited = 1;
2906 for(i = 0;i < 256; i++)
2907 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2908 rop_to_index[CIRRUS_ROP_0] = 0;
2909 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2910 rop_to_index[CIRRUS_ROP_NOP] = 2;
2911 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2912 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2913 rop_to_index[CIRRUS_ROP_SRC] = 5;
2914 rop_to_index[CIRRUS_ROP_1] = 6;
2915 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2916 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2917 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2918 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2919 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2920 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2921 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2922 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2923 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2924 s->device_id = device_id;
2925 if (is_pci)
2926 s->bustype = CIRRUS_BUSTYPE_PCI;
2927 else
2928 s->bustype = CIRRUS_BUSTYPE_ISA;
2929 }
2930
2931 /* Register ioport 0x3b0 - 0x3df */
2932 memory_region_init_io(&s->cirrus_vga_io, owner, &cirrus_vga_io_ops, s,
2933 "cirrus-io", 0x30);
2934 memory_region_set_flush_coalesced(&s->cirrus_vga_io);
2935 memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io);
2936
2937 memory_region_init(&s->low_mem_container, owner,
2938 "cirrus-lowmem-container",
2939 0x20000);
2940
2941 memory_region_init_io(&s->low_mem, owner, &cirrus_vga_mem_ops, s,
2942 "cirrus-low-memory", 0x20000);
2943 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
2944 for (i = 0; i < 2; ++i) {
2945 static const char *names[] = { "vga.bank0", "vga.bank1" };
2946 MemoryRegion *bank = &s->cirrus_bank[i];
2947 memory_region_init_alias(bank, owner, names[i], &s->vga.vram,
2948 0, 0x8000);
2949 memory_region_set_enabled(bank, false);
2950 memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
2951 bank, 1);
2952 }
2953 memory_region_add_subregion_overlap(system_memory,
2954 0x000a0000,
2955 &s->low_mem_container,
2956 1);
2957 memory_region_set_coalescing(&s->low_mem);
2958
2959 /* I/O handler for LFB */
2960 memory_region_init_io(&s->cirrus_linear_io, owner, &cirrus_linear_io_ops, s,
2961 "cirrus-linear-io", s->vga.vram_size_mb
2962 * 1024 * 1024);
2963 memory_region_set_flush_coalesced(&s->cirrus_linear_io);
2964
2965 /* I/O handler for LFB */
2966 memory_region_init_io(&s->cirrus_linear_bitblt_io, owner,
2967 &cirrus_linear_bitblt_io_ops,
2968 s,
2969 "cirrus-bitblt-mmio",
2970 0x400000);
2971 memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io);
2972
2973 /* I/O handler for memory-mapped I/O */
2974 memory_region_init_io(&s->cirrus_mmio_io, owner, &cirrus_mmio_io_ops, s,
2975 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
2976 memory_region_set_flush_coalesced(&s->cirrus_mmio_io);
2977
2978 s->real_vram_size =
2979 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
2980
2981 /* XXX: s->vga.vram_size must be a power of two */
2982 s->cirrus_addr_mask = s->real_vram_size - 1;
2983 s->linear_mmio_mask = s->real_vram_size - 256;
2984
2985 s->vga.get_bpp = cirrus_get_bpp;
2986 s->vga.get_offsets = cirrus_get_offsets;
2987 s->vga.get_resolution = cirrus_get_resolution;
2988 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
2989 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
2990
2991 qemu_register_reset(cirrus_reset, s);
2992 }
2993
2994 /***************************************
2995 *
2996 * ISA bus support
2997 *
2998 ***************************************/
2999
3000 static void isa_cirrus_vga_realizefn(DeviceState *dev, Error **errp)
3001 {
3002 ISADevice *isadev = ISA_DEVICE(dev);
3003 ISACirrusVGAState *d = ISA_CIRRUS_VGA(dev);
3004 VGACommonState *s = &d->cirrus_vga.vga;
3005
3006 /* follow real hardware, cirrus card emulated has 4 MB video memory.
3007 Also accept 8 MB/16 MB for backward compatibility. */
3008 if (s->vram_size_mb != 4 && s->vram_size_mb != 8 &&
3009 s->vram_size_mb != 16) {
3010 error_setg(errp, "Invalid cirrus_vga ram size '%u'",
3011 s->vram_size_mb);
3012 return;
3013 }
3014 vga_common_init(s, OBJECT(dev), true);
3015 cirrus_init_common(&d->cirrus_vga, OBJECT(dev), CIRRUS_ID_CLGD5430, 0,
3016 isa_address_space(isadev),
3017 isa_address_space_io(isadev));
3018 s->con = graphic_console_init(dev, 0, s->hw_ops, s);
3019 rom_add_vga(VGABIOS_CIRRUS_FILENAME);
3020 /* XXX ISA-LFB support */
3021 /* FIXME not qdev yet */
3022 }
3023
3024 static Property isa_cirrus_vga_properties[] = {
3025 DEFINE_PROP_UINT32("vgamem_mb", struct ISACirrusVGAState,
3026 cirrus_vga.vga.vram_size_mb, 8),
3027 DEFINE_PROP_END_OF_LIST(),
3028 };
3029
3030 static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data)
3031 {
3032 DeviceClass *dc = DEVICE_CLASS(klass);
3033
3034 dc->vmsd = &vmstate_cirrus_vga;
3035 dc->realize = isa_cirrus_vga_realizefn;
3036 dc->props = isa_cirrus_vga_properties;
3037 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
3038 }
3039
3040 static const TypeInfo isa_cirrus_vga_info = {
3041 .name = TYPE_ISA_CIRRUS_VGA,
3042 .parent = TYPE_ISA_DEVICE,
3043 .instance_size = sizeof(ISACirrusVGAState),
3044 .class_init = isa_cirrus_vga_class_init,
3045 };
3046
3047 /***************************************
3048 *
3049 * PCI bus support
3050 *
3051 ***************************************/
3052
3053 static void pci_cirrus_vga_realize(PCIDevice *dev, Error **errp)
3054 {
3055 PCICirrusVGAState *d = PCI_CIRRUS_VGA(dev);
3056 CirrusVGAState *s = &d->cirrus_vga;
3057 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
3058 int16_t device_id = pc->device_id;
3059
3060 /* follow real hardware, cirrus card emulated has 4 MB video memory.
3061 Also accept 8 MB/16 MB for backward compatibility. */
3062 if (s->vga.vram_size_mb != 4 && s->vga.vram_size_mb != 8 &&
3063 s->vga.vram_size_mb != 16) {
3064 error_setg(errp, "Invalid cirrus_vga ram size '%u'",
3065 s->vga.vram_size_mb);
3066 return;
3067 }
3068 /* setup VGA */
3069 vga_common_init(&s->vga, OBJECT(dev), true);
3070 cirrus_init_common(s, OBJECT(dev), device_id, 1, pci_address_space(dev),
3071 pci_address_space_io(dev));
3072 s->vga.con = graphic_console_init(DEVICE(dev), 0, s->vga.hw_ops, &s->vga);
3073
3074 /* setup PCI */
3075
3076 memory_region_init(&s->pci_bar, OBJECT(dev), "cirrus-pci-bar0", 0x2000000);
3077
3078 /* XXX: add byte swapping apertures */
3079 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
3080 memory_region_add_subregion(&s->pci_bar, 0x1000000,
3081 &s->cirrus_linear_bitblt_io);
3082
3083 /* setup memory space */
3084 /* memory #0 LFB */
3085 /* memory #1 memory-mapped I/O */
3086 /* XXX: s->vga.vram_size must be a power of two */
3087 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
3088 if (device_id == CIRRUS_ID_CLGD5446) {
3089 pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
3090 }
3091 }
3092
3093 static Property pci_vga_cirrus_properties[] = {
3094 DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState,
3095 cirrus_vga.vga.vram_size_mb, 8),
3096 DEFINE_PROP_END_OF_LIST(),
3097 };
3098
3099 static void cirrus_vga_class_init(ObjectClass *klass, void *data)
3100 {
3101 DeviceClass *dc = DEVICE_CLASS(klass);
3102 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3103
3104 k->realize = pci_cirrus_vga_realize;
3105 k->romfile = VGABIOS_CIRRUS_FILENAME;
3106 k->vendor_id = PCI_VENDOR_ID_CIRRUS;
3107 k->device_id = CIRRUS_ID_CLGD5446;
3108 k->class_id = PCI_CLASS_DISPLAY_VGA;
3109 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
3110 dc->desc = "Cirrus CLGD 54xx VGA";
3111 dc->vmsd = &vmstate_pci_cirrus_vga;
3112 dc->props = pci_vga_cirrus_properties;
3113 dc->hotpluggable = false;
3114 }
3115
3116 static const TypeInfo cirrus_vga_info = {
3117 .name = TYPE_PCI_CIRRUS_VGA,
3118 .parent = TYPE_PCI_DEVICE,
3119 .instance_size = sizeof(PCICirrusVGAState),
3120 .class_init = cirrus_vga_class_init,
3121 };
3122
3123 static void cirrus_vga_register_types(void)
3124 {
3125 type_register_static(&isa_cirrus_vga_info);
3126 type_register_static(&cirrus_vga_info);
3127 }
3128
3129 type_init(cirrus_vga_register_types)
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