2 * QEMU Cirrus CLGD 54xx VGA Emulator.
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
33 #include "hw/pci/pci.h"
34 #include "ui/console.h"
35 #include "ui/pixel_ops.h"
37 #include "hw/loader.h"
41 * - destination write mask support not complete (bits 5..7)
42 * - optimize linear mappings
43 * - optimize bitblt functions
46 //#define DEBUG_CIRRUS
47 //#define DEBUG_BITBLT
49 /***************************************
53 ***************************************/
56 #define CIRRUS_ID_CLGD5422 (0x23<<2)
57 #define CIRRUS_ID_CLGD5426 (0x24<<2)
58 #define CIRRUS_ID_CLGD5424 (0x25<<2)
59 #define CIRRUS_ID_CLGD5428 (0x26<<2)
60 #define CIRRUS_ID_CLGD5430 (0x28<<2)
61 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
62 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
63 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
66 #define CIRRUS_SR7_BPP_VGA 0x00
67 #define CIRRUS_SR7_BPP_SVGA 0x01
68 #define CIRRUS_SR7_BPP_MASK 0x0e
69 #define CIRRUS_SR7_BPP_8 0x00
70 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
71 #define CIRRUS_SR7_BPP_24 0x04
72 #define CIRRUS_SR7_BPP_16 0x06
73 #define CIRRUS_SR7_BPP_32 0x08
74 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
77 #define CIRRUS_MEMSIZE_512k 0x08
78 #define CIRRUS_MEMSIZE_1M 0x10
79 #define CIRRUS_MEMSIZE_2M 0x18
80 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
83 #define CIRRUS_CURSOR_SHOW 0x01
84 #define CIRRUS_CURSOR_HIDDENPEL 0x02
85 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
88 #define CIRRUS_BUSTYPE_VLBFAST 0x10
89 #define CIRRUS_BUSTYPE_PCI 0x20
90 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
91 #define CIRRUS_BUSTYPE_ISA 0x38
92 #define CIRRUS_MMIO_ENABLE 0x04
93 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
94 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
97 #define CIRRUS_BANKING_DUAL 0x01
98 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
101 #define CIRRUS_BLTMODE_BACKWARDS 0x01
102 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
103 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
104 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
105 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
106 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
107 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
108 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
109 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
110 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
111 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
114 #define CIRRUS_BLT_BUSY 0x01
115 #define CIRRUS_BLT_START 0x02
116 #define CIRRUS_BLT_RESET 0x04
117 #define CIRRUS_BLT_FIFOUSED 0x10
118 #define CIRRUS_BLT_AUTOSTART 0x80
121 #define CIRRUS_ROP_0 0x00
122 #define CIRRUS_ROP_SRC_AND_DST 0x05
123 #define CIRRUS_ROP_NOP 0x06
124 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
125 #define CIRRUS_ROP_NOTDST 0x0b
126 #define CIRRUS_ROP_SRC 0x0d
127 #define CIRRUS_ROP_1 0x0e
128 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
129 #define CIRRUS_ROP_SRC_XOR_DST 0x59
130 #define CIRRUS_ROP_SRC_OR_DST 0x6d
131 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
132 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
133 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
134 #define CIRRUS_ROP_NOTSRC 0xd0
135 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
136 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
138 #define CIRRUS_ROP_NOP_INDEX 2
139 #define CIRRUS_ROP_SRC_INDEX 5
142 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
143 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
144 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
147 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
148 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
149 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
150 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
151 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
152 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
153 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
154 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
155 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
156 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
157 #define CIRRUS_MMIO_BLTROP 0x1a // byte
158 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
159 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
160 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
161 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
162 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
163 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
164 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
168 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
169 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
170 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
171 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
172 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
173 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
174 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
175 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
177 #define CIRRUS_PNPMMIO_SIZE 0x1000
179 struct CirrusVGAState
;
180 typedef void (*cirrus_bitblt_rop_t
) (struct CirrusVGAState
*s
,
181 uint8_t * dst
, const uint8_t * src
,
182 int dstpitch
, int srcpitch
,
183 int bltwidth
, int bltheight
);
184 typedef void (*cirrus_fill_t
)(struct CirrusVGAState
*s
,
185 uint8_t *dst
, int dst_pitch
, int width
, int height
);
187 typedef struct CirrusVGAState
{
190 MemoryRegion cirrus_vga_io
;
191 MemoryRegion cirrus_linear_io
;
192 MemoryRegion cirrus_linear_bitblt_io
;
193 MemoryRegion cirrus_mmio_io
;
194 MemoryRegion pci_bar
;
195 bool linear_vram
; /* vga.vram mapped over cirrus_linear_io */
196 MemoryRegion low_mem_container
; /* container for 0xa0000-0xc0000 */
197 MemoryRegion low_mem
; /* always mapped, overridden by: */
198 MemoryRegion cirrus_bank
[2]; /* aliases at 0xa0000-0xb0000 */
199 uint32_t cirrus_addr_mask
;
200 uint32_t linear_mmio_mask
;
201 uint8_t cirrus_shadow_gr0
;
202 uint8_t cirrus_shadow_gr1
;
203 uint8_t cirrus_hidden_dac_lockindex
;
204 uint8_t cirrus_hidden_dac_data
;
205 uint32_t cirrus_bank_base
[2];
206 uint32_t cirrus_bank_limit
[2];
207 uint8_t cirrus_hidden_palette
[48];
208 int cirrus_blt_pixelwidth
;
209 int cirrus_blt_width
;
210 int cirrus_blt_height
;
211 int cirrus_blt_dstpitch
;
212 int cirrus_blt_srcpitch
;
213 uint32_t cirrus_blt_fgcol
;
214 uint32_t cirrus_blt_bgcol
;
215 uint32_t cirrus_blt_dstaddr
;
216 uint32_t cirrus_blt_srcaddr
;
217 uint8_t cirrus_blt_mode
;
218 uint8_t cirrus_blt_modeext
;
219 cirrus_bitblt_rop_t cirrus_rop
;
220 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
221 uint8_t cirrus_bltbuf
[CIRRUS_BLTBUFSIZE
];
222 uint8_t *cirrus_srcptr
;
223 uint8_t *cirrus_srcptr_end
;
224 uint32_t cirrus_srccounter
;
225 /* hwcursor display state */
226 int last_hw_cursor_size
;
227 int last_hw_cursor_x
;
228 int last_hw_cursor_y
;
229 int last_hw_cursor_y_start
;
230 int last_hw_cursor_y_end
;
231 int real_vram_size
; /* XXX: suppress that */
236 typedef struct PCICirrusVGAState
{
238 CirrusVGAState cirrus_vga
;
241 #define TYPE_PCI_CIRRUS_VGA "cirrus-vga"
242 #define PCI_CIRRUS_VGA(obj) \
243 OBJECT_CHECK(PCICirrusVGAState, (obj), TYPE_PCI_CIRRUS_VGA)
245 #define TYPE_ISA_CIRRUS_VGA "isa-cirrus-vga"
246 #define ISA_CIRRUS_VGA(obj) \
247 OBJECT_CHECK(ISACirrusVGAState, (obj), TYPE_ISA_CIRRUS_VGA)
249 typedef struct ISACirrusVGAState
{
250 ISADevice parent_obj
;
252 CirrusVGAState cirrus_vga
;
255 static uint8_t rop_to_index
[256];
257 /***************************************
261 ***************************************/
264 static void cirrus_bitblt_reset(CirrusVGAState
*s
);
265 static void cirrus_update_memory_access(CirrusVGAState
*s
);
267 /***************************************
271 ***************************************/
273 static bool blit_region_is_unsafe(struct CirrusVGAState
*s
,
274 int32_t pitch
, int32_t addr
)
281 + ((int64_t)s
->cirrus_blt_height
- 1) * pitch
282 - s
->cirrus_blt_width
;
283 if (min
< -1 || addr
>= s
->vga
.vram_size
) {
288 + ((int64_t)s
->cirrus_blt_height
-1) * pitch
289 + s
->cirrus_blt_width
;
290 if (max
> s
->vga
.vram_size
) {
297 static bool blit_is_unsafe(struct CirrusVGAState
*s
, bool dst_only
)
299 /* should be the case, see cirrus_bitblt_start */
300 assert(s
->cirrus_blt_width
> 0);
301 assert(s
->cirrus_blt_height
> 0);
303 if (s
->cirrus_blt_width
> CIRRUS_BLTBUFSIZE
) {
307 if (blit_region_is_unsafe(s
, s
->cirrus_blt_dstpitch
,
308 s
->cirrus_blt_dstaddr
)) {
314 if (blit_region_is_unsafe(s
, s
->cirrus_blt_srcpitch
,
315 s
->cirrus_blt_srcaddr
)) {
322 static void cirrus_bitblt_rop_nop(CirrusVGAState
*s
,
323 uint8_t *dst
,const uint8_t *src
,
324 int dstpitch
,int srcpitch
,
325 int bltwidth
,int bltheight
)
329 static void cirrus_bitblt_fill_nop(CirrusVGAState
*s
,
331 int dstpitch
, int bltwidth
,int bltheight
)
336 #define ROP_FN(d, s) 0
337 #include "cirrus_vga_rop.h"
339 #define ROP_NAME src_and_dst
340 #define ROP_FN(d, s) (s) & (d)
341 #include "cirrus_vga_rop.h"
343 #define ROP_NAME src_and_notdst
344 #define ROP_FN(d, s) (s) & (~(d))
345 #include "cirrus_vga_rop.h"
347 #define ROP_NAME notdst
348 #define ROP_FN(d, s) ~(d)
349 #include "cirrus_vga_rop.h"
352 #define ROP_FN(d, s) s
353 #include "cirrus_vga_rop.h"
356 #define ROP_FN(d, s) ~0
357 #include "cirrus_vga_rop.h"
359 #define ROP_NAME notsrc_and_dst
360 #define ROP_FN(d, s) (~(s)) & (d)
361 #include "cirrus_vga_rop.h"
363 #define ROP_NAME src_xor_dst
364 #define ROP_FN(d, s) (s) ^ (d)
365 #include "cirrus_vga_rop.h"
367 #define ROP_NAME src_or_dst
368 #define ROP_FN(d, s) (s) | (d)
369 #include "cirrus_vga_rop.h"
371 #define ROP_NAME notsrc_or_notdst
372 #define ROP_FN(d, s) (~(s)) | (~(d))
373 #include "cirrus_vga_rop.h"
375 #define ROP_NAME src_notxor_dst
376 #define ROP_FN(d, s) ~((s) ^ (d))
377 #include "cirrus_vga_rop.h"
379 #define ROP_NAME src_or_notdst
380 #define ROP_FN(d, s) (s) | (~(d))
381 #include "cirrus_vga_rop.h"
383 #define ROP_NAME notsrc
384 #define ROP_FN(d, s) (~(s))
385 #include "cirrus_vga_rop.h"
387 #define ROP_NAME notsrc_or_dst
388 #define ROP_FN(d, s) (~(s)) | (d)
389 #include "cirrus_vga_rop.h"
391 #define ROP_NAME notsrc_and_notdst
392 #define ROP_FN(d, s) (~(s)) & (~(d))
393 #include "cirrus_vga_rop.h"
395 static const cirrus_bitblt_rop_t cirrus_fwd_rop
[16] = {
396 cirrus_bitblt_rop_fwd_0
,
397 cirrus_bitblt_rop_fwd_src_and_dst
,
398 cirrus_bitblt_rop_nop
,
399 cirrus_bitblt_rop_fwd_src_and_notdst
,
400 cirrus_bitblt_rop_fwd_notdst
,
401 cirrus_bitblt_rop_fwd_src
,
402 cirrus_bitblt_rop_fwd_1
,
403 cirrus_bitblt_rop_fwd_notsrc_and_dst
,
404 cirrus_bitblt_rop_fwd_src_xor_dst
,
405 cirrus_bitblt_rop_fwd_src_or_dst
,
406 cirrus_bitblt_rop_fwd_notsrc_or_notdst
,
407 cirrus_bitblt_rop_fwd_src_notxor_dst
,
408 cirrus_bitblt_rop_fwd_src_or_notdst
,
409 cirrus_bitblt_rop_fwd_notsrc
,
410 cirrus_bitblt_rop_fwd_notsrc_or_dst
,
411 cirrus_bitblt_rop_fwd_notsrc_and_notdst
,
414 static const cirrus_bitblt_rop_t cirrus_bkwd_rop
[16] = {
415 cirrus_bitblt_rop_bkwd_0
,
416 cirrus_bitblt_rop_bkwd_src_and_dst
,
417 cirrus_bitblt_rop_nop
,
418 cirrus_bitblt_rop_bkwd_src_and_notdst
,
419 cirrus_bitblt_rop_bkwd_notdst
,
420 cirrus_bitblt_rop_bkwd_src
,
421 cirrus_bitblt_rop_bkwd_1
,
422 cirrus_bitblt_rop_bkwd_notsrc_and_dst
,
423 cirrus_bitblt_rop_bkwd_src_xor_dst
,
424 cirrus_bitblt_rop_bkwd_src_or_dst
,
425 cirrus_bitblt_rop_bkwd_notsrc_or_notdst
,
426 cirrus_bitblt_rop_bkwd_src_notxor_dst
,
427 cirrus_bitblt_rop_bkwd_src_or_notdst
,
428 cirrus_bitblt_rop_bkwd_notsrc
,
429 cirrus_bitblt_rop_bkwd_notsrc_or_dst
,
430 cirrus_bitblt_rop_bkwd_notsrc_and_notdst
,
433 #define TRANSP_ROP(name) {\
437 #define TRANSP_NOP(func) {\
442 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop
[16][2] = {
443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0
),
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst
),
445 TRANSP_NOP(cirrus_bitblt_rop_nop
),
446 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst
),
447 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst
),
448 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src
),
449 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1
),
450 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst
),
451 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst
),
452 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst
),
453 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst
),
454 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst
),
455 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst
),
456 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc
),
457 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst
),
458 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst
),
461 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop
[16][2] = {
462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0
),
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst
),
464 TRANSP_NOP(cirrus_bitblt_rop_nop
),
465 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst
),
466 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst
),
467 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src
),
468 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1
),
469 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst
),
470 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst
),
471 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst
),
472 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst
),
473 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst
),
474 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst
),
475 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc
),
476 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst
),
477 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst
),
480 #define ROP2(name) {\
487 #define ROP_NOP2(func) {\
494 static const cirrus_bitblt_rop_t cirrus_patternfill
[16][4] = {
495 ROP2(cirrus_patternfill_0
),
496 ROP2(cirrus_patternfill_src_and_dst
),
497 ROP_NOP2(cirrus_bitblt_rop_nop
),
498 ROP2(cirrus_patternfill_src_and_notdst
),
499 ROP2(cirrus_patternfill_notdst
),
500 ROP2(cirrus_patternfill_src
),
501 ROP2(cirrus_patternfill_1
),
502 ROP2(cirrus_patternfill_notsrc_and_dst
),
503 ROP2(cirrus_patternfill_src_xor_dst
),
504 ROP2(cirrus_patternfill_src_or_dst
),
505 ROP2(cirrus_patternfill_notsrc_or_notdst
),
506 ROP2(cirrus_patternfill_src_notxor_dst
),
507 ROP2(cirrus_patternfill_src_or_notdst
),
508 ROP2(cirrus_patternfill_notsrc
),
509 ROP2(cirrus_patternfill_notsrc_or_dst
),
510 ROP2(cirrus_patternfill_notsrc_and_notdst
),
513 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp
[16][4] = {
514 ROP2(cirrus_colorexpand_transp_0
),
515 ROP2(cirrus_colorexpand_transp_src_and_dst
),
516 ROP_NOP2(cirrus_bitblt_rop_nop
),
517 ROP2(cirrus_colorexpand_transp_src_and_notdst
),
518 ROP2(cirrus_colorexpand_transp_notdst
),
519 ROP2(cirrus_colorexpand_transp_src
),
520 ROP2(cirrus_colorexpand_transp_1
),
521 ROP2(cirrus_colorexpand_transp_notsrc_and_dst
),
522 ROP2(cirrus_colorexpand_transp_src_xor_dst
),
523 ROP2(cirrus_colorexpand_transp_src_or_dst
),
524 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst
),
525 ROP2(cirrus_colorexpand_transp_src_notxor_dst
),
526 ROP2(cirrus_colorexpand_transp_src_or_notdst
),
527 ROP2(cirrus_colorexpand_transp_notsrc
),
528 ROP2(cirrus_colorexpand_transp_notsrc_or_dst
),
529 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst
),
532 static const cirrus_bitblt_rop_t cirrus_colorexpand
[16][4] = {
533 ROP2(cirrus_colorexpand_0
),
534 ROP2(cirrus_colorexpand_src_and_dst
),
535 ROP_NOP2(cirrus_bitblt_rop_nop
),
536 ROP2(cirrus_colorexpand_src_and_notdst
),
537 ROP2(cirrus_colorexpand_notdst
),
538 ROP2(cirrus_colorexpand_src
),
539 ROP2(cirrus_colorexpand_1
),
540 ROP2(cirrus_colorexpand_notsrc_and_dst
),
541 ROP2(cirrus_colorexpand_src_xor_dst
),
542 ROP2(cirrus_colorexpand_src_or_dst
),
543 ROP2(cirrus_colorexpand_notsrc_or_notdst
),
544 ROP2(cirrus_colorexpand_src_notxor_dst
),
545 ROP2(cirrus_colorexpand_src_or_notdst
),
546 ROP2(cirrus_colorexpand_notsrc
),
547 ROP2(cirrus_colorexpand_notsrc_or_dst
),
548 ROP2(cirrus_colorexpand_notsrc_and_notdst
),
551 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp
[16][4] = {
552 ROP2(cirrus_colorexpand_pattern_transp_0
),
553 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst
),
554 ROP_NOP2(cirrus_bitblt_rop_nop
),
555 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst
),
556 ROP2(cirrus_colorexpand_pattern_transp_notdst
),
557 ROP2(cirrus_colorexpand_pattern_transp_src
),
558 ROP2(cirrus_colorexpand_pattern_transp_1
),
559 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst
),
560 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst
),
561 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst
),
562 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst
),
563 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst
),
564 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst
),
565 ROP2(cirrus_colorexpand_pattern_transp_notsrc
),
566 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst
),
567 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst
),
570 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern
[16][4] = {
571 ROP2(cirrus_colorexpand_pattern_0
),
572 ROP2(cirrus_colorexpand_pattern_src_and_dst
),
573 ROP_NOP2(cirrus_bitblt_rop_nop
),
574 ROP2(cirrus_colorexpand_pattern_src_and_notdst
),
575 ROP2(cirrus_colorexpand_pattern_notdst
),
576 ROP2(cirrus_colorexpand_pattern_src
),
577 ROP2(cirrus_colorexpand_pattern_1
),
578 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst
),
579 ROP2(cirrus_colorexpand_pattern_src_xor_dst
),
580 ROP2(cirrus_colorexpand_pattern_src_or_dst
),
581 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst
),
582 ROP2(cirrus_colorexpand_pattern_src_notxor_dst
),
583 ROP2(cirrus_colorexpand_pattern_src_or_notdst
),
584 ROP2(cirrus_colorexpand_pattern_notsrc
),
585 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst
),
586 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst
),
589 static const cirrus_fill_t cirrus_fill
[16][4] = {
591 ROP2(cirrus_fill_src_and_dst
),
592 ROP_NOP2(cirrus_bitblt_fill_nop
),
593 ROP2(cirrus_fill_src_and_notdst
),
594 ROP2(cirrus_fill_notdst
),
595 ROP2(cirrus_fill_src
),
597 ROP2(cirrus_fill_notsrc_and_dst
),
598 ROP2(cirrus_fill_src_xor_dst
),
599 ROP2(cirrus_fill_src_or_dst
),
600 ROP2(cirrus_fill_notsrc_or_notdst
),
601 ROP2(cirrus_fill_src_notxor_dst
),
602 ROP2(cirrus_fill_src_or_notdst
),
603 ROP2(cirrus_fill_notsrc
),
604 ROP2(cirrus_fill_notsrc_or_dst
),
605 ROP2(cirrus_fill_notsrc_and_notdst
),
608 static inline void cirrus_bitblt_fgcol(CirrusVGAState
*s
)
611 switch (s
->cirrus_blt_pixelwidth
) {
613 s
->cirrus_blt_fgcol
= s
->cirrus_shadow_gr1
;
616 color
= s
->cirrus_shadow_gr1
| (s
->vga
.gr
[0x11] << 8);
617 s
->cirrus_blt_fgcol
= le16_to_cpu(color
);
620 s
->cirrus_blt_fgcol
= s
->cirrus_shadow_gr1
|
621 (s
->vga
.gr
[0x11] << 8) | (s
->vga
.gr
[0x13] << 16);
625 color
= s
->cirrus_shadow_gr1
| (s
->vga
.gr
[0x11] << 8) |
626 (s
->vga
.gr
[0x13] << 16) | (s
->vga
.gr
[0x15] << 24);
627 s
->cirrus_blt_fgcol
= le32_to_cpu(color
);
632 static inline void cirrus_bitblt_bgcol(CirrusVGAState
*s
)
635 switch (s
->cirrus_blt_pixelwidth
) {
637 s
->cirrus_blt_bgcol
= s
->cirrus_shadow_gr0
;
640 color
= s
->cirrus_shadow_gr0
| (s
->vga
.gr
[0x10] << 8);
641 s
->cirrus_blt_bgcol
= le16_to_cpu(color
);
644 s
->cirrus_blt_bgcol
= s
->cirrus_shadow_gr0
|
645 (s
->vga
.gr
[0x10] << 8) | (s
->vga
.gr
[0x12] << 16);
649 color
= s
->cirrus_shadow_gr0
| (s
->vga
.gr
[0x10] << 8) |
650 (s
->vga
.gr
[0x12] << 16) | (s
->vga
.gr
[0x14] << 24);
651 s
->cirrus_blt_bgcol
= le32_to_cpu(color
);
656 static void cirrus_invalidate_region(CirrusVGAState
* s
, int off_begin
,
657 int off_pitch
, int bytesperline
,
665 off_begin
-= bytesperline
- 1;
668 for (y
= 0; y
< lines
; y
++) {
670 off_cur_end
= (off_cur
+ bytesperline
) & s
->cirrus_addr_mask
;
671 assert(off_cur_end
>= off_cur
);
672 memory_region_set_dirty(&s
->vga
.vram
, off_cur
, off_cur_end
- off_cur
);
673 off_begin
+= off_pitch
;
677 static int cirrus_bitblt_common_patterncopy(CirrusVGAState
*s
, bool videosrc
)
679 uint32_t patternsize
;
683 dst
= s
->vga
.vram_ptr
+ s
->cirrus_blt_dstaddr
;
686 switch (s
->vga
.get_bpp(&s
->vga
)) {
700 s
->cirrus_blt_srcaddr
&= ~(patternsize
- 1);
701 if (s
->cirrus_blt_srcaddr
+ patternsize
> s
->vga
.vram_size
) {
704 src
= s
->vga
.vram_ptr
+ s
->cirrus_blt_srcaddr
;
706 src
= s
->cirrus_bltbuf
;
709 if (blit_is_unsafe(s
, true)) {
713 (*s
->cirrus_rop
) (s
, dst
, src
,
714 s
->cirrus_blt_dstpitch
, 0,
715 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
716 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
717 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
718 s
->cirrus_blt_height
);
724 static int cirrus_bitblt_solidfill(CirrusVGAState
*s
, int blt_rop
)
726 cirrus_fill_t rop_func
;
728 if (blit_is_unsafe(s
, true)) {
731 rop_func
= cirrus_fill
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
732 rop_func(s
, s
->vga
.vram_ptr
+ s
->cirrus_blt_dstaddr
,
733 s
->cirrus_blt_dstpitch
,
734 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
735 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
736 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
737 s
->cirrus_blt_height
);
738 cirrus_bitblt_reset(s
);
742 /***************************************
744 * bitblt (video-to-video)
746 ***************************************/
748 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState
* s
)
750 return cirrus_bitblt_common_patterncopy(s
, true);
753 static int cirrus_do_copy(CirrusVGAState
*s
, int dst
, int src
, int w
, int h
)
760 /* make sure to only copy if it's a plain copy ROP */
761 if (*s
->cirrus_rop
== cirrus_bitblt_rop_fwd_src
||
762 *s
->cirrus_rop
== cirrus_bitblt_rop_bkwd_src
) {
766 depth
= s
->vga
.get_bpp(&s
->vga
) / 8;
770 s
->vga
.get_resolution(&s
->vga
, &width
, &height
);
773 sx
= (src
% ABS(s
->cirrus_blt_srcpitch
)) / depth
;
774 sy
= (src
/ ABS(s
->cirrus_blt_srcpitch
));
775 dx
= (dst
% ABS(s
->cirrus_blt_dstpitch
)) / depth
;
776 dy
= (dst
/ ABS(s
->cirrus_blt_dstpitch
));
778 /* normalize width */
781 /* if we're doing a backward copy, we have to adjust
782 our x/y to be the upper left corner (instead of the lower
784 if (s
->cirrus_blt_dstpitch
< 0) {
785 sx
-= (s
->cirrus_blt_width
/ depth
) - 1;
786 dx
-= (s
->cirrus_blt_width
/ depth
) - 1;
787 sy
-= s
->cirrus_blt_height
- 1;
788 dy
-= s
->cirrus_blt_height
- 1;
791 /* are we in the visible portion of memory? */
792 if (sx
>= 0 && sy
>= 0 && dx
>= 0 && dy
>= 0 &&
793 (sx
+ w
) <= width
&& (sy
+ h
) <= height
&&
794 (dx
+ w
) <= width
&& (dy
+ h
) <= height
) {
799 /* we have to flush all pending changes so that the copy
800 is generated at the appropriate moment in time */
802 graphic_hw_update(s
->vga
.con
);
804 (*s
->cirrus_rop
) (s
, s
->vga
.vram_ptr
+ s
->cirrus_blt_dstaddr
,
805 s
->vga
.vram_ptr
+ s
->cirrus_blt_srcaddr
,
806 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_srcpitch
,
807 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
810 qemu_console_copy(s
->vga
.con
,
812 s
->cirrus_blt_width
/ depth
,
813 s
->cirrus_blt_height
);
816 /* we don't have to notify the display that this portion has
817 changed since qemu_console_copy implies this */
819 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
820 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
821 s
->cirrus_blt_height
);
826 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState
* s
)
828 if (blit_is_unsafe(s
, false))
831 return cirrus_do_copy(s
, s
->cirrus_blt_dstaddr
- s
->vga
.start_addr
,
832 s
->cirrus_blt_srcaddr
- s
->vga
.start_addr
,
833 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
836 /***************************************
838 * bitblt (cpu-to-video)
840 ***************************************/
842 static void cirrus_bitblt_cputovideo_next(CirrusVGAState
* s
)
847 if (s
->cirrus_srccounter
> 0) {
848 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
849 cirrus_bitblt_common_patterncopy(s
, false);
851 s
->cirrus_srccounter
= 0;
852 cirrus_bitblt_reset(s
);
854 /* at least one scan line */
856 (*s
->cirrus_rop
)(s
, s
->vga
.vram_ptr
+ s
->cirrus_blt_dstaddr
,
857 s
->cirrus_bltbuf
, 0, 0, s
->cirrus_blt_width
, 1);
858 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
, 0,
859 s
->cirrus_blt_width
, 1);
860 s
->cirrus_blt_dstaddr
+= s
->cirrus_blt_dstpitch
;
861 s
->cirrus_srccounter
-= s
->cirrus_blt_srcpitch
;
862 if (s
->cirrus_srccounter
<= 0)
864 /* more bytes than needed can be transferred because of
865 word alignment, so we keep them for the next line */
866 /* XXX: keep alignment to speed up transfer */
867 end_ptr
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
868 copy_count
= s
->cirrus_srcptr_end
- end_ptr
;
869 memmove(s
->cirrus_bltbuf
, end_ptr
, copy_count
);
870 s
->cirrus_srcptr
= s
->cirrus_bltbuf
+ copy_count
;
871 s
->cirrus_srcptr_end
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
872 } while (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
);
877 /***************************************
881 ***************************************/
883 static void cirrus_bitblt_reset(CirrusVGAState
* s
)
888 ~(CIRRUS_BLT_START
| CIRRUS_BLT_BUSY
| CIRRUS_BLT_FIFOUSED
);
889 need_update
= s
->cirrus_srcptr
!= &s
->cirrus_bltbuf
[0]
890 || s
->cirrus_srcptr_end
!= &s
->cirrus_bltbuf
[0];
891 s
->cirrus_srcptr
= &s
->cirrus_bltbuf
[0];
892 s
->cirrus_srcptr_end
= &s
->cirrus_bltbuf
[0];
893 s
->cirrus_srccounter
= 0;
896 cirrus_update_memory_access(s
);
899 static int cirrus_bitblt_cputovideo(CirrusVGAState
* s
)
903 if (blit_is_unsafe(s
, true)) {
907 s
->cirrus_blt_mode
&= ~CIRRUS_BLTMODE_MEMSYSSRC
;
908 s
->cirrus_srcptr
= &s
->cirrus_bltbuf
[0];
909 s
->cirrus_srcptr_end
= &s
->cirrus_bltbuf
[0];
911 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
912 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
913 s
->cirrus_blt_srcpitch
= 8;
915 /* XXX: check for 24 bpp */
916 s
->cirrus_blt_srcpitch
= 8 * 8 * s
->cirrus_blt_pixelwidth
;
918 s
->cirrus_srccounter
= s
->cirrus_blt_srcpitch
;
920 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
921 w
= s
->cirrus_blt_width
/ s
->cirrus_blt_pixelwidth
;
922 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_DWORDGRANULARITY
)
923 s
->cirrus_blt_srcpitch
= ((w
+ 31) >> 5);
925 s
->cirrus_blt_srcpitch
= ((w
+ 7) >> 3);
927 /* always align input size to 32 bits */
928 s
->cirrus_blt_srcpitch
= (s
->cirrus_blt_width
+ 3) & ~3;
930 s
->cirrus_srccounter
= s
->cirrus_blt_srcpitch
* s
->cirrus_blt_height
;
933 /* the blit_is_unsafe call above should catch this */
934 assert(s
->cirrus_blt_srcpitch
<= CIRRUS_BLTBUFSIZE
);
936 s
->cirrus_srcptr
= s
->cirrus_bltbuf
;
937 s
->cirrus_srcptr_end
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
938 cirrus_update_memory_access(s
);
942 static int cirrus_bitblt_videotocpu(CirrusVGAState
* s
)
946 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
951 static int cirrus_bitblt_videotovideo(CirrusVGAState
* s
)
955 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
956 ret
= cirrus_bitblt_videotovideo_patterncopy(s
);
958 ret
= cirrus_bitblt_videotovideo_copy(s
);
961 cirrus_bitblt_reset(s
);
965 static void cirrus_bitblt_start(CirrusVGAState
* s
)
969 s
->vga
.gr
[0x31] |= CIRRUS_BLT_BUSY
;
971 s
->cirrus_blt_width
= (s
->vga
.gr
[0x20] | (s
->vga
.gr
[0x21] << 8)) + 1;
972 s
->cirrus_blt_height
= (s
->vga
.gr
[0x22] | (s
->vga
.gr
[0x23] << 8)) + 1;
973 s
->cirrus_blt_dstpitch
= (s
->vga
.gr
[0x24] | (s
->vga
.gr
[0x25] << 8));
974 s
->cirrus_blt_srcpitch
= (s
->vga
.gr
[0x26] | (s
->vga
.gr
[0x27] << 8));
975 s
->cirrus_blt_dstaddr
=
976 (s
->vga
.gr
[0x28] | (s
->vga
.gr
[0x29] << 8) | (s
->vga
.gr
[0x2a] << 16));
977 s
->cirrus_blt_srcaddr
=
978 (s
->vga
.gr
[0x2c] | (s
->vga
.gr
[0x2d] << 8) | (s
->vga
.gr
[0x2e] << 16));
979 s
->cirrus_blt_mode
= s
->vga
.gr
[0x30];
980 s
->cirrus_blt_modeext
= s
->vga
.gr
[0x33];
981 blt_rop
= s
->vga
.gr
[0x32];
983 s
->cirrus_blt_dstaddr
&= s
->cirrus_addr_mask
;
984 s
->cirrus_blt_srcaddr
&= s
->cirrus_addr_mask
;
987 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
990 s
->cirrus_blt_modeext
,
992 s
->cirrus_blt_height
,
993 s
->cirrus_blt_dstpitch
,
994 s
->cirrus_blt_srcpitch
,
995 s
->cirrus_blt_dstaddr
,
996 s
->cirrus_blt_srcaddr
,
1000 switch (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PIXELWIDTHMASK
) {
1001 case CIRRUS_BLTMODE_PIXELWIDTH8
:
1002 s
->cirrus_blt_pixelwidth
= 1;
1004 case CIRRUS_BLTMODE_PIXELWIDTH16
:
1005 s
->cirrus_blt_pixelwidth
= 2;
1007 case CIRRUS_BLTMODE_PIXELWIDTH24
:
1008 s
->cirrus_blt_pixelwidth
= 3;
1010 case CIRRUS_BLTMODE_PIXELWIDTH32
:
1011 s
->cirrus_blt_pixelwidth
= 4;
1015 printf("cirrus: bitblt - pixel width is unknown\n");
1019 s
->cirrus_blt_mode
&= ~CIRRUS_BLTMODE_PIXELWIDTHMASK
;
1022 cirrus_blt_mode
& (CIRRUS_BLTMODE_MEMSYSSRC
|
1023 CIRRUS_BLTMODE_MEMSYSDEST
))
1024 == (CIRRUS_BLTMODE_MEMSYSSRC
| CIRRUS_BLTMODE_MEMSYSDEST
)) {
1026 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
1031 if ((s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_SOLIDFILL
) &&
1032 (s
->cirrus_blt_mode
& (CIRRUS_BLTMODE_MEMSYSDEST
|
1033 CIRRUS_BLTMODE_TRANSPARENTCOMP
|
1034 CIRRUS_BLTMODE_PATTERNCOPY
|
1035 CIRRUS_BLTMODE_COLOREXPAND
)) ==
1036 (CIRRUS_BLTMODE_PATTERNCOPY
| CIRRUS_BLTMODE_COLOREXPAND
)) {
1037 cirrus_bitblt_fgcol(s
);
1038 cirrus_bitblt_solidfill(s
, blt_rop
);
1040 if ((s
->cirrus_blt_mode
& (CIRRUS_BLTMODE_COLOREXPAND
|
1041 CIRRUS_BLTMODE_PATTERNCOPY
)) ==
1042 CIRRUS_BLTMODE_COLOREXPAND
) {
1044 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_TRANSPARENTCOMP
) {
1045 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_COLOREXPINV
)
1046 cirrus_bitblt_bgcol(s
);
1048 cirrus_bitblt_fgcol(s
);
1049 s
->cirrus_rop
= cirrus_colorexpand_transp
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1051 cirrus_bitblt_fgcol(s
);
1052 cirrus_bitblt_bgcol(s
);
1053 s
->cirrus_rop
= cirrus_colorexpand
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1055 } else if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
1056 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
1057 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_TRANSPARENTCOMP
) {
1058 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_COLOREXPINV
)
1059 cirrus_bitblt_bgcol(s
);
1061 cirrus_bitblt_fgcol(s
);
1062 s
->cirrus_rop
= cirrus_colorexpand_pattern_transp
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1064 cirrus_bitblt_fgcol(s
);
1065 cirrus_bitblt_bgcol(s
);
1066 s
->cirrus_rop
= cirrus_colorexpand_pattern
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1069 s
->cirrus_rop
= cirrus_patternfill
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1072 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_TRANSPARENTCOMP
) {
1073 if (s
->cirrus_blt_pixelwidth
> 2) {
1074 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1077 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_BACKWARDS
) {
1078 s
->cirrus_blt_dstpitch
= -s
->cirrus_blt_dstpitch
;
1079 s
->cirrus_blt_srcpitch
= -s
->cirrus_blt_srcpitch
;
1080 s
->cirrus_rop
= cirrus_bkwd_transp_rop
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1082 s
->cirrus_rop
= cirrus_fwd_transp_rop
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1085 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_BACKWARDS
) {
1086 s
->cirrus_blt_dstpitch
= -s
->cirrus_blt_dstpitch
;
1087 s
->cirrus_blt_srcpitch
= -s
->cirrus_blt_srcpitch
;
1088 s
->cirrus_rop
= cirrus_bkwd_rop
[rop_to_index
[blt_rop
]];
1090 s
->cirrus_rop
= cirrus_fwd_rop
[rop_to_index
[blt_rop
]];
1094 // setup bitblt engine.
1095 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_MEMSYSSRC
) {
1096 if (!cirrus_bitblt_cputovideo(s
))
1098 } else if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_MEMSYSDEST
) {
1099 if (!cirrus_bitblt_videotocpu(s
))
1102 if (!cirrus_bitblt_videotovideo(s
))
1108 cirrus_bitblt_reset(s
);
1111 static void cirrus_write_bitblt(CirrusVGAState
* s
, unsigned reg_value
)
1115 old_value
= s
->vga
.gr
[0x31];
1116 s
->vga
.gr
[0x31] = reg_value
;
1118 if (((old_value
& CIRRUS_BLT_RESET
) != 0) &&
1119 ((reg_value
& CIRRUS_BLT_RESET
) == 0)) {
1120 cirrus_bitblt_reset(s
);
1121 } else if (((old_value
& CIRRUS_BLT_START
) == 0) &&
1122 ((reg_value
& CIRRUS_BLT_START
) != 0)) {
1123 cirrus_bitblt_start(s
);
1128 /***************************************
1132 ***************************************/
1134 static void cirrus_get_offsets(VGACommonState
*s1
,
1135 uint32_t *pline_offset
,
1136 uint32_t *pstart_addr
,
1137 uint32_t *pline_compare
)
1139 CirrusVGAState
* s
= container_of(s1
, CirrusVGAState
, vga
);
1140 uint32_t start_addr
, line_offset
, line_compare
;
1142 line_offset
= s
->vga
.cr
[0x13]
1143 | ((s
->vga
.cr
[0x1b] & 0x10) << 4);
1145 *pline_offset
= line_offset
;
1147 start_addr
= (s
->vga
.cr
[0x0c] << 8)
1149 | ((s
->vga
.cr
[0x1b] & 0x01) << 16)
1150 | ((s
->vga
.cr
[0x1b] & 0x0c) << 15)
1151 | ((s
->vga
.cr
[0x1d] & 0x80) << 12);
1152 *pstart_addr
= start_addr
;
1154 line_compare
= s
->vga
.cr
[0x18] |
1155 ((s
->vga
.cr
[0x07] & 0x10) << 4) |
1156 ((s
->vga
.cr
[0x09] & 0x40) << 3);
1157 *pline_compare
= line_compare
;
1160 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState
* s
)
1164 switch (s
->cirrus_hidden_dac_data
& 0xf) {
1167 break; /* Sierra HiColor */
1170 break; /* XGA HiColor */
1173 printf("cirrus: invalid DAC value %x in 16bpp\n",
1174 (s
->cirrus_hidden_dac_data
& 0xf));
1182 static int cirrus_get_bpp(VGACommonState
*s1
)
1184 CirrusVGAState
* s
= container_of(s1
, CirrusVGAState
, vga
);
1187 if ((s
->vga
.sr
[0x07] & 0x01) != 0) {
1189 switch (s
->vga
.sr
[0x07] & CIRRUS_SR7_BPP_MASK
) {
1190 case CIRRUS_SR7_BPP_8
:
1193 case CIRRUS_SR7_BPP_16_DOUBLEVCLK
:
1194 ret
= cirrus_get_bpp16_depth(s
);
1196 case CIRRUS_SR7_BPP_24
:
1199 case CIRRUS_SR7_BPP_16
:
1200 ret
= cirrus_get_bpp16_depth(s
);
1202 case CIRRUS_SR7_BPP_32
:
1207 printf("cirrus: unknown bpp - sr7=%x\n", s
->vga
.sr
[0x7]);
1220 static void cirrus_get_resolution(VGACommonState
*s
, int *pwidth
, int *pheight
)
1224 width
= (s
->cr
[0x01] + 1) * 8;
1225 height
= s
->cr
[0x12] |
1226 ((s
->cr
[0x07] & 0x02) << 7) |
1227 ((s
->cr
[0x07] & 0x40) << 3);
1228 height
= (height
+ 1);
1229 /* interlace support */
1230 if (s
->cr
[0x1a] & 0x01)
1231 height
= height
* 2;
1236 /***************************************
1240 ***************************************/
1242 static void cirrus_update_bank_ptr(CirrusVGAState
* s
, unsigned bank_index
)
1247 if ((s
->vga
.gr
[0x0b] & 0x01) != 0) /* dual bank */
1248 offset
= s
->vga
.gr
[0x09 + bank_index
];
1249 else /* single bank */
1250 offset
= s
->vga
.gr
[0x09];
1252 if ((s
->vga
.gr
[0x0b] & 0x20) != 0)
1257 if (s
->real_vram_size
<= offset
)
1260 limit
= s
->real_vram_size
- offset
;
1262 if (((s
->vga
.gr
[0x0b] & 0x01) == 0) && (bank_index
!= 0)) {
1263 if (limit
> 0x8000) {
1272 s
->cirrus_bank_base
[bank_index
] = offset
;
1273 s
->cirrus_bank_limit
[bank_index
] = limit
;
1275 s
->cirrus_bank_base
[bank_index
] = 0;
1276 s
->cirrus_bank_limit
[bank_index
] = 0;
1280 /***************************************
1282 * I/O access between 0x3c4-0x3c5
1284 ***************************************/
1286 static int cirrus_vga_read_sr(CirrusVGAState
* s
)
1288 switch (s
->vga
.sr_index
) {
1289 case 0x00: // Standard VGA
1290 case 0x01: // Standard VGA
1291 case 0x02: // Standard VGA
1292 case 0x03: // Standard VGA
1293 case 0x04: // Standard VGA
1294 return s
->vga
.sr
[s
->vga
.sr_index
];
1295 case 0x06: // Unlock Cirrus extensions
1296 return s
->vga
.sr
[s
->vga
.sr_index
];
1300 case 0x70: // Graphics Cursor X
1304 case 0xf0: // Graphics Cursor X
1305 return s
->vga
.sr
[0x10];
1309 case 0x71: // Graphics Cursor Y
1313 case 0xf1: // Graphics Cursor Y
1314 return s
->vga
.sr
[0x11];
1316 case 0x07: // Extended Sequencer Mode
1317 case 0x08: // EEPROM Control
1318 case 0x09: // Scratch Register 0
1319 case 0x0a: // Scratch Register 1
1320 case 0x0b: // VCLK 0
1321 case 0x0c: // VCLK 1
1322 case 0x0d: // VCLK 2
1323 case 0x0e: // VCLK 3
1324 case 0x0f: // DRAM Control
1325 case 0x12: // Graphics Cursor Attribute
1326 case 0x13: // Graphics Cursor Pattern Address
1327 case 0x14: // Scratch Register 2
1328 case 0x15: // Scratch Register 3
1329 case 0x16: // Performance Tuning Register
1330 case 0x17: // Configuration Readback and Extended Control
1331 case 0x18: // Signature Generator Control
1332 case 0x19: // Signal Generator Result
1333 case 0x1a: // Signal Generator Result
1334 case 0x1b: // VCLK 0 Denominator & Post
1335 case 0x1c: // VCLK 1 Denominator & Post
1336 case 0x1d: // VCLK 2 Denominator & Post
1337 case 0x1e: // VCLK 3 Denominator & Post
1338 case 0x1f: // BIOS Write Enable and MCLK select
1340 printf("cirrus: handled inport sr_index %02x\n", s
->vga
.sr_index
);
1342 return s
->vga
.sr
[s
->vga
.sr_index
];
1345 printf("cirrus: inport sr_index %02x\n", s
->vga
.sr_index
);
1352 static void cirrus_vga_write_sr(CirrusVGAState
* s
, uint32_t val
)
1354 switch (s
->vga
.sr_index
) {
1355 case 0x00: // Standard VGA
1356 case 0x01: // Standard VGA
1357 case 0x02: // Standard VGA
1358 case 0x03: // Standard VGA
1359 case 0x04: // Standard VGA
1360 s
->vga
.sr
[s
->vga
.sr_index
] = val
& sr_mask
[s
->vga
.sr_index
];
1361 if (s
->vga
.sr_index
== 1)
1362 s
->vga
.update_retrace_info(&s
->vga
);
1364 case 0x06: // Unlock Cirrus extensions
1367 s
->vga
.sr
[s
->vga
.sr_index
] = 0x12;
1369 s
->vga
.sr
[s
->vga
.sr_index
] = 0x0f;
1375 case 0x70: // Graphics Cursor X
1379 case 0xf0: // Graphics Cursor X
1380 s
->vga
.sr
[0x10] = val
;
1381 s
->vga
.hw_cursor_x
= (val
<< 3) | (s
->vga
.sr_index
>> 5);
1386 case 0x71: // Graphics Cursor Y
1390 case 0xf1: // Graphics Cursor Y
1391 s
->vga
.sr
[0x11] = val
;
1392 s
->vga
.hw_cursor_y
= (val
<< 3) | (s
->vga
.sr_index
>> 5);
1394 case 0x07: // Extended Sequencer Mode
1395 cirrus_update_memory_access(s
);
1396 case 0x08: // EEPROM Control
1397 case 0x09: // Scratch Register 0
1398 case 0x0a: // Scratch Register 1
1399 case 0x0b: // VCLK 0
1400 case 0x0c: // VCLK 1
1401 case 0x0d: // VCLK 2
1402 case 0x0e: // VCLK 3
1403 case 0x0f: // DRAM Control
1404 case 0x13: // Graphics Cursor Pattern Address
1405 case 0x14: // Scratch Register 2
1406 case 0x15: // Scratch Register 3
1407 case 0x16: // Performance Tuning Register
1408 case 0x18: // Signature Generator Control
1409 case 0x19: // Signature Generator Result
1410 case 0x1a: // Signature Generator Result
1411 case 0x1b: // VCLK 0 Denominator & Post
1412 case 0x1c: // VCLK 1 Denominator & Post
1413 case 0x1d: // VCLK 2 Denominator & Post
1414 case 0x1e: // VCLK 3 Denominator & Post
1415 case 0x1f: // BIOS Write Enable and MCLK select
1416 s
->vga
.sr
[s
->vga
.sr_index
] = val
;
1418 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1419 s
->vga
.sr_index
, val
);
1422 case 0x12: // Graphics Cursor Attribute
1423 s
->vga
.sr
[0x12] = val
;
1424 s
->vga
.force_shadow
= !!(val
& CIRRUS_CURSOR_SHOW
);
1426 printf("cirrus: cursor ctl SR12=%02x (force shadow: %d)\n",
1427 val
, s
->vga
.force_shadow
);
1430 case 0x17: // Configuration Readback and Extended Control
1431 s
->vga
.sr
[s
->vga
.sr_index
] = (s
->vga
.sr
[s
->vga
.sr_index
] & 0x38)
1433 cirrus_update_memory_access(s
);
1437 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1438 s
->vga
.sr_index
, val
);
1444 /***************************************
1446 * I/O access at 0x3c6
1448 ***************************************/
1450 static int cirrus_read_hidden_dac(CirrusVGAState
* s
)
1452 if (++s
->cirrus_hidden_dac_lockindex
== 5) {
1453 s
->cirrus_hidden_dac_lockindex
= 0;
1454 return s
->cirrus_hidden_dac_data
;
1459 static void cirrus_write_hidden_dac(CirrusVGAState
* s
, int reg_value
)
1461 if (s
->cirrus_hidden_dac_lockindex
== 4) {
1462 s
->cirrus_hidden_dac_data
= reg_value
;
1463 #if defined(DEBUG_CIRRUS)
1464 printf("cirrus: outport hidden DAC, value %02x\n", reg_value
);
1467 s
->cirrus_hidden_dac_lockindex
= 0;
1470 /***************************************
1472 * I/O access at 0x3c9
1474 ***************************************/
1476 static int cirrus_vga_read_palette(CirrusVGAState
* s
)
1480 if ((s
->vga
.sr
[0x12] & CIRRUS_CURSOR_HIDDENPEL
)) {
1481 val
= s
->cirrus_hidden_palette
[(s
->vga
.dac_read_index
& 0x0f) * 3 +
1482 s
->vga
.dac_sub_index
];
1484 val
= s
->vga
.palette
[s
->vga
.dac_read_index
* 3 + s
->vga
.dac_sub_index
];
1486 if (++s
->vga
.dac_sub_index
== 3) {
1487 s
->vga
.dac_sub_index
= 0;
1488 s
->vga
.dac_read_index
++;
1493 static void cirrus_vga_write_palette(CirrusVGAState
* s
, int reg_value
)
1495 s
->vga
.dac_cache
[s
->vga
.dac_sub_index
] = reg_value
;
1496 if (++s
->vga
.dac_sub_index
== 3) {
1497 if ((s
->vga
.sr
[0x12] & CIRRUS_CURSOR_HIDDENPEL
)) {
1498 memcpy(&s
->cirrus_hidden_palette
[(s
->vga
.dac_write_index
& 0x0f) * 3],
1499 s
->vga
.dac_cache
, 3);
1501 memcpy(&s
->vga
.palette
[s
->vga
.dac_write_index
* 3], s
->vga
.dac_cache
, 3);
1503 /* XXX update cursor */
1504 s
->vga
.dac_sub_index
= 0;
1505 s
->vga
.dac_write_index
++;
1509 /***************************************
1511 * I/O access between 0x3ce-0x3cf
1513 ***************************************/
1515 static int cirrus_vga_read_gr(CirrusVGAState
* s
, unsigned reg_index
)
1517 switch (reg_index
) {
1518 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1519 return s
->cirrus_shadow_gr0
;
1520 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1521 return s
->cirrus_shadow_gr1
;
1522 case 0x02: // Standard VGA
1523 case 0x03: // Standard VGA
1524 case 0x04: // Standard VGA
1525 case 0x06: // Standard VGA
1526 case 0x07: // Standard VGA
1527 case 0x08: // Standard VGA
1528 return s
->vga
.gr
[s
->vga
.gr_index
];
1529 case 0x05: // Standard VGA, Cirrus extended mode
1534 if (reg_index
< 0x3a) {
1535 return s
->vga
.gr
[reg_index
];
1538 printf("cirrus: inport gr_index %02x\n", reg_index
);
1545 cirrus_vga_write_gr(CirrusVGAState
* s
, unsigned reg_index
, int reg_value
)
1547 #if defined(DEBUG_BITBLT) && 0
1548 printf("gr%02x: %02x\n", reg_index
, reg_value
);
1550 switch (reg_index
) {
1551 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1552 s
->vga
.gr
[reg_index
] = reg_value
& gr_mask
[reg_index
];
1553 s
->cirrus_shadow_gr0
= reg_value
;
1555 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1556 s
->vga
.gr
[reg_index
] = reg_value
& gr_mask
[reg_index
];
1557 s
->cirrus_shadow_gr1
= reg_value
;
1559 case 0x02: // Standard VGA
1560 case 0x03: // Standard VGA
1561 case 0x04: // Standard VGA
1562 case 0x06: // Standard VGA
1563 case 0x07: // Standard VGA
1564 case 0x08: // Standard VGA
1565 s
->vga
.gr
[reg_index
] = reg_value
& gr_mask
[reg_index
];
1567 case 0x05: // Standard VGA, Cirrus extended mode
1568 s
->vga
.gr
[reg_index
] = reg_value
& 0x7f;
1569 cirrus_update_memory_access(s
);
1571 case 0x09: // bank offset #0
1572 case 0x0A: // bank offset #1
1573 s
->vga
.gr
[reg_index
] = reg_value
;
1574 cirrus_update_bank_ptr(s
, 0);
1575 cirrus_update_bank_ptr(s
, 1);
1576 cirrus_update_memory_access(s
);
1579 s
->vga
.gr
[reg_index
] = reg_value
;
1580 cirrus_update_bank_ptr(s
, 0);
1581 cirrus_update_bank_ptr(s
, 1);
1582 cirrus_update_memory_access(s
);
1584 case 0x10: // BGCOLOR 0x0000ff00
1585 case 0x11: // FGCOLOR 0x0000ff00
1586 case 0x12: // BGCOLOR 0x00ff0000
1587 case 0x13: // FGCOLOR 0x00ff0000
1588 case 0x14: // BGCOLOR 0xff000000
1589 case 0x15: // FGCOLOR 0xff000000
1590 case 0x20: // BLT WIDTH 0x0000ff
1591 case 0x22: // BLT HEIGHT 0x0000ff
1592 case 0x24: // BLT DEST PITCH 0x0000ff
1593 case 0x26: // BLT SRC PITCH 0x0000ff
1594 case 0x28: // BLT DEST ADDR 0x0000ff
1595 case 0x29: // BLT DEST ADDR 0x00ff00
1596 case 0x2c: // BLT SRC ADDR 0x0000ff
1597 case 0x2d: // BLT SRC ADDR 0x00ff00
1598 case 0x2f: // BLT WRITEMASK
1599 case 0x30: // BLT MODE
1600 case 0x32: // RASTER OP
1601 case 0x33: // BLT MODEEXT
1602 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1603 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1604 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1605 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1606 s
->vga
.gr
[reg_index
] = reg_value
;
1608 case 0x21: // BLT WIDTH 0x001f00
1609 case 0x23: // BLT HEIGHT 0x001f00
1610 case 0x25: // BLT DEST PITCH 0x001f00
1611 case 0x27: // BLT SRC PITCH 0x001f00
1612 s
->vga
.gr
[reg_index
] = reg_value
& 0x1f;
1614 case 0x2a: // BLT DEST ADDR 0x3f0000
1615 s
->vga
.gr
[reg_index
] = reg_value
& 0x3f;
1616 /* if auto start mode, starts bit blt now */
1617 if (s
->vga
.gr
[0x31] & CIRRUS_BLT_AUTOSTART
) {
1618 cirrus_bitblt_start(s
);
1621 case 0x2e: // BLT SRC ADDR 0x3f0000
1622 s
->vga
.gr
[reg_index
] = reg_value
& 0x3f;
1624 case 0x31: // BLT STATUS/START
1625 cirrus_write_bitblt(s
, reg_value
);
1629 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index
,
1636 /***************************************
1638 * I/O access between 0x3d4-0x3d5
1640 ***************************************/
1642 static int cirrus_vga_read_cr(CirrusVGAState
* s
, unsigned reg_index
)
1644 switch (reg_index
) {
1645 case 0x00: // Standard VGA
1646 case 0x01: // Standard VGA
1647 case 0x02: // Standard VGA
1648 case 0x03: // Standard VGA
1649 case 0x04: // Standard VGA
1650 case 0x05: // Standard VGA
1651 case 0x06: // Standard VGA
1652 case 0x07: // Standard VGA
1653 case 0x08: // Standard VGA
1654 case 0x09: // Standard VGA
1655 case 0x0a: // Standard VGA
1656 case 0x0b: // Standard VGA
1657 case 0x0c: // Standard VGA
1658 case 0x0d: // Standard VGA
1659 case 0x0e: // Standard VGA
1660 case 0x0f: // Standard VGA
1661 case 0x10: // Standard VGA
1662 case 0x11: // Standard VGA
1663 case 0x12: // Standard VGA
1664 case 0x13: // Standard VGA
1665 case 0x14: // Standard VGA
1666 case 0x15: // Standard VGA
1667 case 0x16: // Standard VGA
1668 case 0x17: // Standard VGA
1669 case 0x18: // Standard VGA
1670 return s
->vga
.cr
[s
->vga
.cr_index
];
1671 case 0x24: // Attribute Controller Toggle Readback (R)
1672 return (s
->vga
.ar_flip_flop
<< 7);
1673 case 0x19: // Interlace End
1674 case 0x1a: // Miscellaneous Control
1675 case 0x1b: // Extended Display Control
1676 case 0x1c: // Sync Adjust and Genlock
1677 case 0x1d: // Overlay Extended Control
1678 case 0x22: // Graphics Data Latches Readback (R)
1679 case 0x25: // Part Status
1680 case 0x27: // Part ID (R)
1681 return s
->vga
.cr
[s
->vga
.cr_index
];
1682 case 0x26: // Attribute Controller Index Readback (R)
1683 return s
->vga
.ar_index
& 0x3f;
1687 printf("cirrus: inport cr_index %02x\n", reg_index
);
1693 static void cirrus_vga_write_cr(CirrusVGAState
* s
, int reg_value
)
1695 switch (s
->vga
.cr_index
) {
1696 case 0x00: // Standard VGA
1697 case 0x01: // Standard VGA
1698 case 0x02: // Standard VGA
1699 case 0x03: // Standard VGA
1700 case 0x04: // Standard VGA
1701 case 0x05: // Standard VGA
1702 case 0x06: // Standard VGA
1703 case 0x07: // Standard VGA
1704 case 0x08: // Standard VGA
1705 case 0x09: // Standard VGA
1706 case 0x0a: // Standard VGA
1707 case 0x0b: // Standard VGA
1708 case 0x0c: // Standard VGA
1709 case 0x0d: // Standard VGA
1710 case 0x0e: // Standard VGA
1711 case 0x0f: // Standard VGA
1712 case 0x10: // Standard VGA
1713 case 0x11: // Standard VGA
1714 case 0x12: // Standard VGA
1715 case 0x13: // Standard VGA
1716 case 0x14: // Standard VGA
1717 case 0x15: // Standard VGA
1718 case 0x16: // Standard VGA
1719 case 0x17: // Standard VGA
1720 case 0x18: // Standard VGA
1721 /* handle CR0-7 protection */
1722 if ((s
->vga
.cr
[0x11] & 0x80) && s
->vga
.cr_index
<= 7) {
1723 /* can always write bit 4 of CR7 */
1724 if (s
->vga
.cr_index
== 7)
1725 s
->vga
.cr
[7] = (s
->vga
.cr
[7] & ~0x10) | (reg_value
& 0x10);
1728 s
->vga
.cr
[s
->vga
.cr_index
] = reg_value
;
1729 switch(s
->vga
.cr_index
) {
1737 s
->vga
.update_retrace_info(&s
->vga
);
1741 case 0x19: // Interlace End
1742 case 0x1a: // Miscellaneous Control
1743 case 0x1b: // Extended Display Control
1744 case 0x1c: // Sync Adjust and Genlock
1745 case 0x1d: // Overlay Extended Control
1746 s
->vga
.cr
[s
->vga
.cr_index
] = reg_value
;
1748 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1749 s
->vga
.cr_index
, reg_value
);
1752 case 0x22: // Graphics Data Latches Readback (R)
1753 case 0x24: // Attribute Controller Toggle Readback (R)
1754 case 0x26: // Attribute Controller Index Readback (R)
1755 case 0x27: // Part ID (R)
1757 case 0x25: // Part Status
1760 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1761 s
->vga
.cr_index
, reg_value
);
1767 /***************************************
1769 * memory-mapped I/O (bitblt)
1771 ***************************************/
1773 static uint8_t cirrus_mmio_blt_read(CirrusVGAState
* s
, unsigned address
)
1778 case (CIRRUS_MMIO_BLTBGCOLOR
+ 0):
1779 value
= cirrus_vga_read_gr(s
, 0x00);
1781 case (CIRRUS_MMIO_BLTBGCOLOR
+ 1):
1782 value
= cirrus_vga_read_gr(s
, 0x10);
1784 case (CIRRUS_MMIO_BLTBGCOLOR
+ 2):
1785 value
= cirrus_vga_read_gr(s
, 0x12);
1787 case (CIRRUS_MMIO_BLTBGCOLOR
+ 3):
1788 value
= cirrus_vga_read_gr(s
, 0x14);
1790 case (CIRRUS_MMIO_BLTFGCOLOR
+ 0):
1791 value
= cirrus_vga_read_gr(s
, 0x01);
1793 case (CIRRUS_MMIO_BLTFGCOLOR
+ 1):
1794 value
= cirrus_vga_read_gr(s
, 0x11);
1796 case (CIRRUS_MMIO_BLTFGCOLOR
+ 2):
1797 value
= cirrus_vga_read_gr(s
, 0x13);
1799 case (CIRRUS_MMIO_BLTFGCOLOR
+ 3):
1800 value
= cirrus_vga_read_gr(s
, 0x15);
1802 case (CIRRUS_MMIO_BLTWIDTH
+ 0):
1803 value
= cirrus_vga_read_gr(s
, 0x20);
1805 case (CIRRUS_MMIO_BLTWIDTH
+ 1):
1806 value
= cirrus_vga_read_gr(s
, 0x21);
1808 case (CIRRUS_MMIO_BLTHEIGHT
+ 0):
1809 value
= cirrus_vga_read_gr(s
, 0x22);
1811 case (CIRRUS_MMIO_BLTHEIGHT
+ 1):
1812 value
= cirrus_vga_read_gr(s
, 0x23);
1814 case (CIRRUS_MMIO_BLTDESTPITCH
+ 0):
1815 value
= cirrus_vga_read_gr(s
, 0x24);
1817 case (CIRRUS_MMIO_BLTDESTPITCH
+ 1):
1818 value
= cirrus_vga_read_gr(s
, 0x25);
1820 case (CIRRUS_MMIO_BLTSRCPITCH
+ 0):
1821 value
= cirrus_vga_read_gr(s
, 0x26);
1823 case (CIRRUS_MMIO_BLTSRCPITCH
+ 1):
1824 value
= cirrus_vga_read_gr(s
, 0x27);
1826 case (CIRRUS_MMIO_BLTDESTADDR
+ 0):
1827 value
= cirrus_vga_read_gr(s
, 0x28);
1829 case (CIRRUS_MMIO_BLTDESTADDR
+ 1):
1830 value
= cirrus_vga_read_gr(s
, 0x29);
1832 case (CIRRUS_MMIO_BLTDESTADDR
+ 2):
1833 value
= cirrus_vga_read_gr(s
, 0x2a);
1835 case (CIRRUS_MMIO_BLTSRCADDR
+ 0):
1836 value
= cirrus_vga_read_gr(s
, 0x2c);
1838 case (CIRRUS_MMIO_BLTSRCADDR
+ 1):
1839 value
= cirrus_vga_read_gr(s
, 0x2d);
1841 case (CIRRUS_MMIO_BLTSRCADDR
+ 2):
1842 value
= cirrus_vga_read_gr(s
, 0x2e);
1844 case CIRRUS_MMIO_BLTWRITEMASK
:
1845 value
= cirrus_vga_read_gr(s
, 0x2f);
1847 case CIRRUS_MMIO_BLTMODE
:
1848 value
= cirrus_vga_read_gr(s
, 0x30);
1850 case CIRRUS_MMIO_BLTROP
:
1851 value
= cirrus_vga_read_gr(s
, 0x32);
1853 case CIRRUS_MMIO_BLTMODEEXT
:
1854 value
= cirrus_vga_read_gr(s
, 0x33);
1856 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 0):
1857 value
= cirrus_vga_read_gr(s
, 0x34);
1859 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 1):
1860 value
= cirrus_vga_read_gr(s
, 0x35);
1862 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 0):
1863 value
= cirrus_vga_read_gr(s
, 0x38);
1865 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 1):
1866 value
= cirrus_vga_read_gr(s
, 0x39);
1868 case CIRRUS_MMIO_BLTSTATUS
:
1869 value
= cirrus_vga_read_gr(s
, 0x31);
1873 printf("cirrus: mmio read - address 0x%04x\n", address
);
1878 trace_vga_cirrus_write_blt(address
, value
);
1879 return (uint8_t) value
;
1882 static void cirrus_mmio_blt_write(CirrusVGAState
* s
, unsigned address
,
1885 trace_vga_cirrus_write_blt(address
, value
);
1887 case (CIRRUS_MMIO_BLTBGCOLOR
+ 0):
1888 cirrus_vga_write_gr(s
, 0x00, value
);
1890 case (CIRRUS_MMIO_BLTBGCOLOR
+ 1):
1891 cirrus_vga_write_gr(s
, 0x10, value
);
1893 case (CIRRUS_MMIO_BLTBGCOLOR
+ 2):
1894 cirrus_vga_write_gr(s
, 0x12, value
);
1896 case (CIRRUS_MMIO_BLTBGCOLOR
+ 3):
1897 cirrus_vga_write_gr(s
, 0x14, value
);
1899 case (CIRRUS_MMIO_BLTFGCOLOR
+ 0):
1900 cirrus_vga_write_gr(s
, 0x01, value
);
1902 case (CIRRUS_MMIO_BLTFGCOLOR
+ 1):
1903 cirrus_vga_write_gr(s
, 0x11, value
);
1905 case (CIRRUS_MMIO_BLTFGCOLOR
+ 2):
1906 cirrus_vga_write_gr(s
, 0x13, value
);
1908 case (CIRRUS_MMIO_BLTFGCOLOR
+ 3):
1909 cirrus_vga_write_gr(s
, 0x15, value
);
1911 case (CIRRUS_MMIO_BLTWIDTH
+ 0):
1912 cirrus_vga_write_gr(s
, 0x20, value
);
1914 case (CIRRUS_MMIO_BLTWIDTH
+ 1):
1915 cirrus_vga_write_gr(s
, 0x21, value
);
1917 case (CIRRUS_MMIO_BLTHEIGHT
+ 0):
1918 cirrus_vga_write_gr(s
, 0x22, value
);
1920 case (CIRRUS_MMIO_BLTHEIGHT
+ 1):
1921 cirrus_vga_write_gr(s
, 0x23, value
);
1923 case (CIRRUS_MMIO_BLTDESTPITCH
+ 0):
1924 cirrus_vga_write_gr(s
, 0x24, value
);
1926 case (CIRRUS_MMIO_BLTDESTPITCH
+ 1):
1927 cirrus_vga_write_gr(s
, 0x25, value
);
1929 case (CIRRUS_MMIO_BLTSRCPITCH
+ 0):
1930 cirrus_vga_write_gr(s
, 0x26, value
);
1932 case (CIRRUS_MMIO_BLTSRCPITCH
+ 1):
1933 cirrus_vga_write_gr(s
, 0x27, value
);
1935 case (CIRRUS_MMIO_BLTDESTADDR
+ 0):
1936 cirrus_vga_write_gr(s
, 0x28, value
);
1938 case (CIRRUS_MMIO_BLTDESTADDR
+ 1):
1939 cirrus_vga_write_gr(s
, 0x29, value
);
1941 case (CIRRUS_MMIO_BLTDESTADDR
+ 2):
1942 cirrus_vga_write_gr(s
, 0x2a, value
);
1944 case (CIRRUS_MMIO_BLTDESTADDR
+ 3):
1947 case (CIRRUS_MMIO_BLTSRCADDR
+ 0):
1948 cirrus_vga_write_gr(s
, 0x2c, value
);
1950 case (CIRRUS_MMIO_BLTSRCADDR
+ 1):
1951 cirrus_vga_write_gr(s
, 0x2d, value
);
1953 case (CIRRUS_MMIO_BLTSRCADDR
+ 2):
1954 cirrus_vga_write_gr(s
, 0x2e, value
);
1956 case CIRRUS_MMIO_BLTWRITEMASK
:
1957 cirrus_vga_write_gr(s
, 0x2f, value
);
1959 case CIRRUS_MMIO_BLTMODE
:
1960 cirrus_vga_write_gr(s
, 0x30, value
);
1962 case CIRRUS_MMIO_BLTROP
:
1963 cirrus_vga_write_gr(s
, 0x32, value
);
1965 case CIRRUS_MMIO_BLTMODEEXT
:
1966 cirrus_vga_write_gr(s
, 0x33, value
);
1968 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 0):
1969 cirrus_vga_write_gr(s
, 0x34, value
);
1971 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 1):
1972 cirrus_vga_write_gr(s
, 0x35, value
);
1974 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 0):
1975 cirrus_vga_write_gr(s
, 0x38, value
);
1977 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 1):
1978 cirrus_vga_write_gr(s
, 0x39, value
);
1980 case CIRRUS_MMIO_BLTSTATUS
:
1981 cirrus_vga_write_gr(s
, 0x31, value
);
1985 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1992 /***************************************
1996 ***************************************/
1998 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState
* s
,
2004 unsigned val
= mem_value
;
2007 dst
= s
->vga
.vram_ptr
+ (offset
&= s
->cirrus_addr_mask
);
2008 for (x
= 0; x
< 8; x
++) {
2010 *dst
= s
->cirrus_shadow_gr1
;
2011 } else if (mode
== 5) {
2012 *dst
= s
->cirrus_shadow_gr0
;
2017 memory_region_set_dirty(&s
->vga
.vram
, offset
, 8);
2020 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState
* s
,
2026 unsigned val
= mem_value
;
2029 dst
= s
->vga
.vram_ptr
+ (offset
&= s
->cirrus_addr_mask
);
2030 for (x
= 0; x
< 8; x
++) {
2032 *dst
= s
->cirrus_shadow_gr1
;
2033 *(dst
+ 1) = s
->vga
.gr
[0x11];
2034 } else if (mode
== 5) {
2035 *dst
= s
->cirrus_shadow_gr0
;
2036 *(dst
+ 1) = s
->vga
.gr
[0x10];
2041 memory_region_set_dirty(&s
->vga
.vram
, offset
, 16);
2044 /***************************************
2046 * memory access between 0xa0000-0xbffff
2048 ***************************************/
2050 static uint64_t cirrus_vga_mem_read(void *opaque
,
2054 CirrusVGAState
*s
= opaque
;
2055 unsigned bank_index
;
2056 unsigned bank_offset
;
2059 if ((s
->vga
.sr
[0x07] & 0x01) == 0) {
2060 return vga_mem_readb(&s
->vga
, addr
);
2063 if (addr
< 0x10000) {
2064 /* XXX handle bitblt */
2066 bank_index
= addr
>> 15;
2067 bank_offset
= addr
& 0x7fff;
2068 if (bank_offset
< s
->cirrus_bank_limit
[bank_index
]) {
2069 bank_offset
+= s
->cirrus_bank_base
[bank_index
];
2070 if ((s
->vga
.gr
[0x0B] & 0x14) == 0x14) {
2072 } else if (s
->vga
.gr
[0x0B] & 0x02) {
2075 bank_offset
&= s
->cirrus_addr_mask
;
2076 val
= *(s
->vga
.vram_ptr
+ bank_offset
);
2079 } else if (addr
>= 0x18000 && addr
< 0x18100) {
2080 /* memory-mapped I/O */
2082 if ((s
->vga
.sr
[0x17] & 0x44) == 0x04) {
2083 val
= cirrus_mmio_blt_read(s
, addr
& 0xff);
2088 printf("cirrus: mem_readb " TARGET_FMT_plx
"\n", addr
);
2094 static void cirrus_vga_mem_write(void *opaque
,
2099 CirrusVGAState
*s
= opaque
;
2100 unsigned bank_index
;
2101 unsigned bank_offset
;
2104 if ((s
->vga
.sr
[0x07] & 0x01) == 0) {
2105 vga_mem_writeb(&s
->vga
, addr
, mem_value
);
2109 if (addr
< 0x10000) {
2110 if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2112 *s
->cirrus_srcptr
++ = (uint8_t) mem_value
;
2113 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
2114 cirrus_bitblt_cputovideo_next(s
);
2118 bank_index
= addr
>> 15;
2119 bank_offset
= addr
& 0x7fff;
2120 if (bank_offset
< s
->cirrus_bank_limit
[bank_index
]) {
2121 bank_offset
+= s
->cirrus_bank_base
[bank_index
];
2122 if ((s
->vga
.gr
[0x0B] & 0x14) == 0x14) {
2124 } else if (s
->vga
.gr
[0x0B] & 0x02) {
2127 bank_offset
&= s
->cirrus_addr_mask
;
2128 mode
= s
->vga
.gr
[0x05] & 0x7;
2129 if (mode
< 4 || mode
> 5 || ((s
->vga
.gr
[0x0B] & 0x4) == 0)) {
2130 *(s
->vga
.vram_ptr
+ bank_offset
) = mem_value
;
2131 memory_region_set_dirty(&s
->vga
.vram
, bank_offset
,
2134 if ((s
->vga
.gr
[0x0B] & 0x14) != 0x14) {
2135 cirrus_mem_writeb_mode4and5_8bpp(s
, mode
,
2139 cirrus_mem_writeb_mode4and5_16bpp(s
, mode
,
2146 } else if (addr
>= 0x18000 && addr
< 0x18100) {
2147 /* memory-mapped I/O */
2148 if ((s
->vga
.sr
[0x17] & 0x44) == 0x04) {
2149 cirrus_mmio_blt_write(s
, addr
& 0xff, mem_value
);
2153 printf("cirrus: mem_writeb " TARGET_FMT_plx
" value 0x%02" PRIu64
"\n", addr
,
2159 static const MemoryRegionOps cirrus_vga_mem_ops
= {
2160 .read
= cirrus_vga_mem_read
,
2161 .write
= cirrus_vga_mem_write
,
2162 .endianness
= DEVICE_LITTLE_ENDIAN
,
2164 .min_access_size
= 1,
2165 .max_access_size
= 1,
2169 /***************************************
2173 ***************************************/
2175 static inline void invalidate_cursor1(CirrusVGAState
*s
)
2177 if (s
->last_hw_cursor_size
) {
2178 vga_invalidate_scanlines(&s
->vga
,
2179 s
->last_hw_cursor_y
+ s
->last_hw_cursor_y_start
,
2180 s
->last_hw_cursor_y
+ s
->last_hw_cursor_y_end
);
2184 static inline void cirrus_cursor_compute_yrange(CirrusVGAState
*s
)
2188 int y
, y_min
, y_max
;
2190 src
= s
->vga
.vram_ptr
+ s
->real_vram_size
- 16 * 1024;
2191 if (s
->vga
.sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2192 src
+= (s
->vga
.sr
[0x13] & 0x3c) * 256;
2195 for(y
= 0; y
< 64; y
++) {
2196 content
= ((uint32_t *)src
)[0] |
2197 ((uint32_t *)src
)[1] |
2198 ((uint32_t *)src
)[2] |
2199 ((uint32_t *)src
)[3];
2209 src
+= (s
->vga
.sr
[0x13] & 0x3f) * 256;
2212 for(y
= 0; y
< 32; y
++) {
2213 content
= ((uint32_t *)src
)[0] |
2214 ((uint32_t *)(src
+ 128))[0];
2224 if (y_min
> y_max
) {
2225 s
->last_hw_cursor_y_start
= 0;
2226 s
->last_hw_cursor_y_end
= 0;
2228 s
->last_hw_cursor_y_start
= y_min
;
2229 s
->last_hw_cursor_y_end
= y_max
+ 1;
2233 /* NOTE: we do not currently handle the cursor bitmap change, so we
2234 update the cursor only if it moves. */
2235 static void cirrus_cursor_invalidate(VGACommonState
*s1
)
2237 CirrusVGAState
*s
= container_of(s1
, CirrusVGAState
, vga
);
2240 if (!(s
->vga
.sr
[0x12] & CIRRUS_CURSOR_SHOW
)) {
2243 if (s
->vga
.sr
[0x12] & CIRRUS_CURSOR_LARGE
)
2248 /* invalidate last cursor and new cursor if any change */
2249 if (s
->last_hw_cursor_size
!= size
||
2250 s
->last_hw_cursor_x
!= s
->vga
.hw_cursor_x
||
2251 s
->last_hw_cursor_y
!= s
->vga
.hw_cursor_y
) {
2253 invalidate_cursor1(s
);
2255 s
->last_hw_cursor_size
= size
;
2256 s
->last_hw_cursor_x
= s
->vga
.hw_cursor_x
;
2257 s
->last_hw_cursor_y
= s
->vga
.hw_cursor_y
;
2258 /* compute the real cursor min and max y */
2259 cirrus_cursor_compute_yrange(s
);
2260 invalidate_cursor1(s
);
2264 static void vga_draw_cursor_line(uint8_t *d1
,
2265 const uint8_t *src1
,
2267 unsigned int color0
,
2268 unsigned int color1
,
2269 unsigned int color_xor
)
2271 const uint8_t *plane0
, *plane1
;
2277 plane1
= src1
+ poffset
;
2278 for (x
= 0; x
< w
; x
++) {
2279 b0
= (plane0
[x
>> 3] >> (7 - (x
& 7))) & 1;
2280 b1
= (plane1
[x
>> 3] >> (7 - (x
& 7))) & 1;
2281 switch (b0
| (b1
<< 1)) {
2285 ((uint32_t *)d
)[0] ^= color_xor
;
2288 ((uint32_t *)d
)[0] = color0
;
2291 ((uint32_t *)d
)[0] = color1
;
2298 static void cirrus_cursor_draw_line(VGACommonState
*s1
, uint8_t *d1
, int scr_y
)
2300 CirrusVGAState
*s
= container_of(s1
, CirrusVGAState
, vga
);
2301 int w
, h
, x1
, x2
, poffset
;
2302 unsigned int color0
, color1
;
2303 const uint8_t *palette
, *src
;
2306 if (!(s
->vga
.sr
[0x12] & CIRRUS_CURSOR_SHOW
))
2308 /* fast test to see if the cursor intersects with the scan line */
2309 if (s
->vga
.sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2314 if (scr_y
< s
->vga
.hw_cursor_y
||
2315 scr_y
>= (s
->vga
.hw_cursor_y
+ h
)) {
2319 src
= s
->vga
.vram_ptr
+ s
->real_vram_size
- 16 * 1024;
2320 if (s
->vga
.sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2321 src
+= (s
->vga
.sr
[0x13] & 0x3c) * 256;
2322 src
+= (scr_y
- s
->vga
.hw_cursor_y
) * 16;
2324 content
= ((uint32_t *)src
)[0] |
2325 ((uint32_t *)src
)[1] |
2326 ((uint32_t *)src
)[2] |
2327 ((uint32_t *)src
)[3];
2329 src
+= (s
->vga
.sr
[0x13] & 0x3f) * 256;
2330 src
+= (scr_y
- s
->vga
.hw_cursor_y
) * 4;
2334 content
= ((uint32_t *)src
)[0] |
2335 ((uint32_t *)(src
+ 128))[0];
2337 /* if nothing to draw, no need to continue */
2342 x1
= s
->vga
.hw_cursor_x
;
2343 if (x1
>= s
->vga
.last_scr_width
)
2345 x2
= s
->vga
.hw_cursor_x
+ w
;
2346 if (x2
> s
->vga
.last_scr_width
)
2347 x2
= s
->vga
.last_scr_width
;
2349 palette
= s
->cirrus_hidden_palette
;
2350 color0
= rgb_to_pixel32(c6_to_8(palette
[0x0 * 3]),
2351 c6_to_8(palette
[0x0 * 3 + 1]),
2352 c6_to_8(palette
[0x0 * 3 + 2]));
2353 color1
= rgb_to_pixel32(c6_to_8(palette
[0xf * 3]),
2354 c6_to_8(palette
[0xf * 3 + 1]),
2355 c6_to_8(palette
[0xf * 3 + 2]));
2357 vga_draw_cursor_line(d1
, src
, poffset
, w
, color0
, color1
, 0xffffff);
2360 /***************************************
2364 ***************************************/
2366 static uint64_t cirrus_linear_read(void *opaque
, hwaddr addr
,
2369 CirrusVGAState
*s
= opaque
;
2372 addr
&= s
->cirrus_addr_mask
;
2374 if (((s
->vga
.sr
[0x17] & 0x44) == 0x44) &&
2375 ((addr
& s
->linear_mmio_mask
) == s
->linear_mmio_mask
)) {
2376 /* memory-mapped I/O */
2377 ret
= cirrus_mmio_blt_read(s
, addr
& 0xff);
2379 /* XXX handle bitblt */
2383 if ((s
->vga
.gr
[0x0B] & 0x14) == 0x14) {
2385 } else if (s
->vga
.gr
[0x0B] & 0x02) {
2388 addr
&= s
->cirrus_addr_mask
;
2389 ret
= *(s
->vga
.vram_ptr
+ addr
);
2395 static void cirrus_linear_write(void *opaque
, hwaddr addr
,
2396 uint64_t val
, unsigned size
)
2398 CirrusVGAState
*s
= opaque
;
2401 addr
&= s
->cirrus_addr_mask
;
2403 if (((s
->vga
.sr
[0x17] & 0x44) == 0x44) &&
2404 ((addr
& s
->linear_mmio_mask
) == s
->linear_mmio_mask
)) {
2405 /* memory-mapped I/O */
2406 cirrus_mmio_blt_write(s
, addr
& 0xff, val
);
2407 } else if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2409 *s
->cirrus_srcptr
++ = (uint8_t) val
;
2410 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
2411 cirrus_bitblt_cputovideo_next(s
);
2415 if ((s
->vga
.gr
[0x0B] & 0x14) == 0x14) {
2417 } else if (s
->vga
.gr
[0x0B] & 0x02) {
2420 addr
&= s
->cirrus_addr_mask
;
2422 mode
= s
->vga
.gr
[0x05] & 0x7;
2423 if (mode
< 4 || mode
> 5 || ((s
->vga
.gr
[0x0B] & 0x4) == 0)) {
2424 *(s
->vga
.vram_ptr
+ addr
) = (uint8_t) val
;
2425 memory_region_set_dirty(&s
->vga
.vram
, addr
, 1);
2427 if ((s
->vga
.gr
[0x0B] & 0x14) != 0x14) {
2428 cirrus_mem_writeb_mode4and5_8bpp(s
, mode
, addr
, val
);
2430 cirrus_mem_writeb_mode4and5_16bpp(s
, mode
, addr
, val
);
2436 /***************************************
2438 * system to screen memory access
2440 ***************************************/
2443 static uint64_t cirrus_linear_bitblt_read(void *opaque
,
2447 CirrusVGAState
*s
= opaque
;
2450 /* XXX handle bitblt */
2456 static void cirrus_linear_bitblt_write(void *opaque
,
2461 CirrusVGAState
*s
= opaque
;
2463 if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2465 *s
->cirrus_srcptr
++ = (uint8_t) val
;
2466 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
2467 cirrus_bitblt_cputovideo_next(s
);
2472 static const MemoryRegionOps cirrus_linear_bitblt_io_ops
= {
2473 .read
= cirrus_linear_bitblt_read
,
2474 .write
= cirrus_linear_bitblt_write
,
2475 .endianness
= DEVICE_LITTLE_ENDIAN
,
2477 .min_access_size
= 1,
2478 .max_access_size
= 1,
2482 static void map_linear_vram_bank(CirrusVGAState
*s
, unsigned bank
)
2484 MemoryRegion
*mr
= &s
->cirrus_bank
[bank
];
2485 bool enabled
= !(s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
)
2486 && !((s
->vga
.sr
[0x07] & 0x01) == 0)
2487 && !((s
->vga
.gr
[0x0B] & 0x14) == 0x14)
2488 && !(s
->vga
.gr
[0x0B] & 0x02);
2490 memory_region_set_enabled(mr
, enabled
);
2491 memory_region_set_alias_offset(mr
, s
->cirrus_bank_base
[bank
]);
2494 static void map_linear_vram(CirrusVGAState
*s
)
2496 if (s
->bustype
== CIRRUS_BUSTYPE_PCI
&& !s
->linear_vram
) {
2497 s
->linear_vram
= true;
2498 memory_region_add_subregion_overlap(&s
->pci_bar
, 0, &s
->vga
.vram
, 1);
2500 map_linear_vram_bank(s
, 0);
2501 map_linear_vram_bank(s
, 1);
2504 static void unmap_linear_vram(CirrusVGAState
*s
)
2506 if (s
->bustype
== CIRRUS_BUSTYPE_PCI
&& s
->linear_vram
) {
2507 s
->linear_vram
= false;
2508 memory_region_del_subregion(&s
->pci_bar
, &s
->vga
.vram
);
2510 memory_region_set_enabled(&s
->cirrus_bank
[0], false);
2511 memory_region_set_enabled(&s
->cirrus_bank
[1], false);
2514 /* Compute the memory access functions */
2515 static void cirrus_update_memory_access(CirrusVGAState
*s
)
2519 memory_region_transaction_begin();
2520 if ((s
->vga
.sr
[0x17] & 0x44) == 0x44) {
2522 } else if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2525 if ((s
->vga
.gr
[0x0B] & 0x14) == 0x14) {
2527 } else if (s
->vga
.gr
[0x0B] & 0x02) {
2531 mode
= s
->vga
.gr
[0x05] & 0x7;
2532 if (mode
< 4 || mode
> 5 || ((s
->vga
.gr
[0x0B] & 0x4) == 0)) {
2536 unmap_linear_vram(s
);
2539 memory_region_transaction_commit();
2545 static uint64_t cirrus_vga_ioport_read(void *opaque
, hwaddr addr
,
2548 CirrusVGAState
*c
= opaque
;
2549 VGACommonState
*s
= &c
->vga
;
2554 if (vga_ioport_invalid(s
, addr
)) {
2559 if (s
->ar_flip_flop
== 0) {
2566 index
= s
->ar_index
& 0x1f;
2579 val
= cirrus_vga_read_sr(c
);
2581 #ifdef DEBUG_VGA_REG
2582 printf("vga: read SR%x = 0x%02x\n", s
->sr_index
, val
);
2586 val
= cirrus_read_hidden_dac(c
);
2592 val
= s
->dac_write_index
;
2593 c
->cirrus_hidden_dac_lockindex
= 0;
2596 val
= cirrus_vga_read_palette(c
);
2608 val
= cirrus_vga_read_gr(c
, s
->gr_index
);
2609 #ifdef DEBUG_VGA_REG
2610 printf("vga: read GR%x = 0x%02x\n", s
->gr_index
, val
);
2619 val
= cirrus_vga_read_cr(c
, s
->cr_index
);
2620 #ifdef DEBUG_VGA_REG
2621 printf("vga: read CR%x = 0x%02x\n", s
->cr_index
, val
);
2626 /* just toggle to fool polling */
2627 val
= s
->st01
= s
->retrace(s
);
2628 s
->ar_flip_flop
= 0;
2635 trace_vga_cirrus_read_io(addr
, val
);
2639 static void cirrus_vga_ioport_write(void *opaque
, hwaddr addr
, uint64_t val
,
2642 CirrusVGAState
*c
= opaque
;
2643 VGACommonState
*s
= &c
->vga
;
2648 /* check port range access depending on color/monochrome mode */
2649 if (vga_ioport_invalid(s
, addr
)) {
2652 trace_vga_cirrus_write_io(addr
, val
);
2656 if (s
->ar_flip_flop
== 0) {
2660 index
= s
->ar_index
& 0x1f;
2663 s
->ar
[index
] = val
& 0x3f;
2666 s
->ar
[index
] = val
& ~0x10;
2672 s
->ar
[index
] = val
& ~0xc0;
2675 s
->ar
[index
] = val
& ~0xf0;
2678 s
->ar
[index
] = val
& ~0xf0;
2684 s
->ar_flip_flop
^= 1;
2687 s
->msr
= val
& ~0x10;
2688 s
->update_retrace_info(s
);
2694 #ifdef DEBUG_VGA_REG
2695 printf("vga: write SR%x = 0x%02" PRIu64
"\n", s
->sr_index
, val
);
2697 cirrus_vga_write_sr(c
, val
);
2700 cirrus_write_hidden_dac(c
, val
);
2703 s
->dac_read_index
= val
;
2704 s
->dac_sub_index
= 0;
2708 s
->dac_write_index
= val
;
2709 s
->dac_sub_index
= 0;
2713 cirrus_vga_write_palette(c
, val
);
2719 #ifdef DEBUG_VGA_REG
2720 printf("vga: write GR%x = 0x%02" PRIu64
"\n", s
->gr_index
, val
);
2722 cirrus_vga_write_gr(c
, s
->gr_index
, val
);
2730 #ifdef DEBUG_VGA_REG
2731 printf("vga: write CR%x = 0x%02"PRIu64
"\n", s
->cr_index
, val
);
2733 cirrus_vga_write_cr(c
, val
);
2737 s
->fcr
= val
& 0x10;
2742 /***************************************
2744 * memory-mapped I/O access
2746 ***************************************/
2748 static uint64_t cirrus_mmio_read(void *opaque
, hwaddr addr
,
2751 CirrusVGAState
*s
= opaque
;
2753 if (addr
>= 0x100) {
2754 return cirrus_mmio_blt_read(s
, addr
- 0x100);
2756 return cirrus_vga_ioport_read(s
, addr
+ 0x10, size
);
2760 static void cirrus_mmio_write(void *opaque
, hwaddr addr
,
2761 uint64_t val
, unsigned size
)
2763 CirrusVGAState
*s
= opaque
;
2765 if (addr
>= 0x100) {
2766 cirrus_mmio_blt_write(s
, addr
- 0x100, val
);
2768 cirrus_vga_ioport_write(s
, addr
+ 0x10, val
, size
);
2772 static const MemoryRegionOps cirrus_mmio_io_ops
= {
2773 .read
= cirrus_mmio_read
,
2774 .write
= cirrus_mmio_write
,
2775 .endianness
= DEVICE_LITTLE_ENDIAN
,
2777 .min_access_size
= 1,
2778 .max_access_size
= 1,
2782 /* load/save state */
2784 static int cirrus_post_load(void *opaque
, int version_id
)
2786 CirrusVGAState
*s
= opaque
;
2788 s
->vga
.gr
[0x00] = s
->cirrus_shadow_gr0
& 0x0f;
2789 s
->vga
.gr
[0x01] = s
->cirrus_shadow_gr1
& 0x0f;
2791 cirrus_update_memory_access(s
);
2793 s
->vga
.graphic_mode
= -1;
2794 cirrus_update_bank_ptr(s
, 0);
2795 cirrus_update_bank_ptr(s
, 1);
2799 static const VMStateDescription vmstate_cirrus_vga
= {
2800 .name
= "cirrus_vga",
2802 .minimum_version_id
= 1,
2803 .post_load
= cirrus_post_load
,
2804 .fields
= (VMStateField
[]) {
2805 VMSTATE_UINT32(vga
.latch
, CirrusVGAState
),
2806 VMSTATE_UINT8(vga
.sr_index
, CirrusVGAState
),
2807 VMSTATE_BUFFER(vga
.sr
, CirrusVGAState
),
2808 VMSTATE_UINT8(vga
.gr_index
, CirrusVGAState
),
2809 VMSTATE_UINT8(cirrus_shadow_gr0
, CirrusVGAState
),
2810 VMSTATE_UINT8(cirrus_shadow_gr1
, CirrusVGAState
),
2811 VMSTATE_BUFFER_START_MIDDLE(vga
.gr
, CirrusVGAState
, 2),
2812 VMSTATE_UINT8(vga
.ar_index
, CirrusVGAState
),
2813 VMSTATE_BUFFER(vga
.ar
, CirrusVGAState
),
2814 VMSTATE_INT32(vga
.ar_flip_flop
, CirrusVGAState
),
2815 VMSTATE_UINT8(vga
.cr_index
, CirrusVGAState
),
2816 VMSTATE_BUFFER(vga
.cr
, CirrusVGAState
),
2817 VMSTATE_UINT8(vga
.msr
, CirrusVGAState
),
2818 VMSTATE_UINT8(vga
.fcr
, CirrusVGAState
),
2819 VMSTATE_UINT8(vga
.st00
, CirrusVGAState
),
2820 VMSTATE_UINT8(vga
.st01
, CirrusVGAState
),
2821 VMSTATE_UINT8(vga
.dac_state
, CirrusVGAState
),
2822 VMSTATE_UINT8(vga
.dac_sub_index
, CirrusVGAState
),
2823 VMSTATE_UINT8(vga
.dac_read_index
, CirrusVGAState
),
2824 VMSTATE_UINT8(vga
.dac_write_index
, CirrusVGAState
),
2825 VMSTATE_BUFFER(vga
.dac_cache
, CirrusVGAState
),
2826 VMSTATE_BUFFER(vga
.palette
, CirrusVGAState
),
2827 VMSTATE_INT32(vga
.bank_offset
, CirrusVGAState
),
2828 VMSTATE_UINT8(cirrus_hidden_dac_lockindex
, CirrusVGAState
),
2829 VMSTATE_UINT8(cirrus_hidden_dac_data
, CirrusVGAState
),
2830 VMSTATE_UINT32(vga
.hw_cursor_x
, CirrusVGAState
),
2831 VMSTATE_UINT32(vga
.hw_cursor_y
, CirrusVGAState
),
2832 /* XXX: we do not save the bitblt state - we assume we do not save
2833 the state when the blitter is active */
2834 VMSTATE_END_OF_LIST()
2838 static const VMStateDescription vmstate_pci_cirrus_vga
= {
2839 .name
= "cirrus_vga",
2841 .minimum_version_id
= 2,
2842 .fields
= (VMStateField
[]) {
2843 VMSTATE_PCI_DEVICE(dev
, PCICirrusVGAState
),
2844 VMSTATE_STRUCT(cirrus_vga
, PCICirrusVGAState
, 0,
2845 vmstate_cirrus_vga
, CirrusVGAState
),
2846 VMSTATE_END_OF_LIST()
2850 /***************************************
2854 ***************************************/
2856 static void cirrus_reset(void *opaque
)
2858 CirrusVGAState
*s
= opaque
;
2860 vga_common_reset(&s
->vga
);
2861 unmap_linear_vram(s
);
2862 s
->vga
.sr
[0x06] = 0x0f;
2863 if (s
->device_id
== CIRRUS_ID_CLGD5446
) {
2864 /* 4MB 64 bit memory config, always PCI */
2865 s
->vga
.sr
[0x1F] = 0x2d; // MemClock
2866 s
->vga
.gr
[0x18] = 0x0f; // fastest memory configuration
2867 s
->vga
.sr
[0x0f] = 0x98;
2868 s
->vga
.sr
[0x17] = 0x20;
2869 s
->vga
.sr
[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
2871 s
->vga
.sr
[0x1F] = 0x22; // MemClock
2872 s
->vga
.sr
[0x0F] = CIRRUS_MEMSIZE_2M
;
2873 s
->vga
.sr
[0x17] = s
->bustype
;
2874 s
->vga
.sr
[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
2876 s
->vga
.cr
[0x27] = s
->device_id
;
2878 s
->cirrus_hidden_dac_lockindex
= 5;
2879 s
->cirrus_hidden_dac_data
= 0;
2882 static const MemoryRegionOps cirrus_linear_io_ops
= {
2883 .read
= cirrus_linear_read
,
2884 .write
= cirrus_linear_write
,
2885 .endianness
= DEVICE_LITTLE_ENDIAN
,
2887 .min_access_size
= 1,
2888 .max_access_size
= 1,
2892 static const MemoryRegionOps cirrus_vga_io_ops
= {
2893 .read
= cirrus_vga_ioport_read
,
2894 .write
= cirrus_vga_ioport_write
,
2895 .endianness
= DEVICE_LITTLE_ENDIAN
,
2897 .min_access_size
= 1,
2898 .max_access_size
= 1,
2902 static void cirrus_init_common(CirrusVGAState
*s
, Object
*owner
,
2903 int device_id
, int is_pci
,
2904 MemoryRegion
*system_memory
,
2905 MemoryRegion
*system_io
)
2912 for(i
= 0;i
< 256; i
++)
2913 rop_to_index
[i
] = CIRRUS_ROP_NOP_INDEX
; /* nop rop */
2914 rop_to_index
[CIRRUS_ROP_0
] = 0;
2915 rop_to_index
[CIRRUS_ROP_SRC_AND_DST
] = 1;
2916 rop_to_index
[CIRRUS_ROP_NOP
] = 2;
2917 rop_to_index
[CIRRUS_ROP_SRC_AND_NOTDST
] = 3;
2918 rop_to_index
[CIRRUS_ROP_NOTDST
] = 4;
2919 rop_to_index
[CIRRUS_ROP_SRC
] = 5;
2920 rop_to_index
[CIRRUS_ROP_1
] = 6;
2921 rop_to_index
[CIRRUS_ROP_NOTSRC_AND_DST
] = 7;
2922 rop_to_index
[CIRRUS_ROP_SRC_XOR_DST
] = 8;
2923 rop_to_index
[CIRRUS_ROP_SRC_OR_DST
] = 9;
2924 rop_to_index
[CIRRUS_ROP_NOTSRC_OR_NOTDST
] = 10;
2925 rop_to_index
[CIRRUS_ROP_SRC_NOTXOR_DST
] = 11;
2926 rop_to_index
[CIRRUS_ROP_SRC_OR_NOTDST
] = 12;
2927 rop_to_index
[CIRRUS_ROP_NOTSRC
] = 13;
2928 rop_to_index
[CIRRUS_ROP_NOTSRC_OR_DST
] = 14;
2929 rop_to_index
[CIRRUS_ROP_NOTSRC_AND_NOTDST
] = 15;
2930 s
->device_id
= device_id
;
2932 s
->bustype
= CIRRUS_BUSTYPE_PCI
;
2934 s
->bustype
= CIRRUS_BUSTYPE_ISA
;
2937 /* Register ioport 0x3b0 - 0x3df */
2938 memory_region_init_io(&s
->cirrus_vga_io
, owner
, &cirrus_vga_io_ops
, s
,
2940 memory_region_set_flush_coalesced(&s
->cirrus_vga_io
);
2941 memory_region_add_subregion(system_io
, 0x3b0, &s
->cirrus_vga_io
);
2943 memory_region_init(&s
->low_mem_container
, owner
,
2944 "cirrus-lowmem-container",
2947 memory_region_init_io(&s
->low_mem
, owner
, &cirrus_vga_mem_ops
, s
,
2948 "cirrus-low-memory", 0x20000);
2949 memory_region_add_subregion(&s
->low_mem_container
, 0, &s
->low_mem
);
2950 for (i
= 0; i
< 2; ++i
) {
2951 static const char *names
[] = { "vga.bank0", "vga.bank1" };
2952 MemoryRegion
*bank
= &s
->cirrus_bank
[i
];
2953 memory_region_init_alias(bank
, owner
, names
[i
], &s
->vga
.vram
,
2955 memory_region_set_enabled(bank
, false);
2956 memory_region_add_subregion_overlap(&s
->low_mem_container
, i
* 0x8000,
2959 memory_region_add_subregion_overlap(system_memory
,
2961 &s
->low_mem_container
,
2963 memory_region_set_coalescing(&s
->low_mem
);
2965 /* I/O handler for LFB */
2966 memory_region_init_io(&s
->cirrus_linear_io
, owner
, &cirrus_linear_io_ops
, s
,
2967 "cirrus-linear-io", s
->vga
.vram_size_mb
2969 memory_region_set_flush_coalesced(&s
->cirrus_linear_io
);
2971 /* I/O handler for LFB */
2972 memory_region_init_io(&s
->cirrus_linear_bitblt_io
, owner
,
2973 &cirrus_linear_bitblt_io_ops
,
2975 "cirrus-bitblt-mmio",
2977 memory_region_set_flush_coalesced(&s
->cirrus_linear_bitblt_io
);
2979 /* I/O handler for memory-mapped I/O */
2980 memory_region_init_io(&s
->cirrus_mmio_io
, owner
, &cirrus_mmio_io_ops
, s
,
2981 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE
);
2982 memory_region_set_flush_coalesced(&s
->cirrus_mmio_io
);
2985 (s
->device_id
== CIRRUS_ID_CLGD5446
) ? 4096 * 1024 : 2048 * 1024;
2987 /* XXX: s->vga.vram_size must be a power of two */
2988 s
->cirrus_addr_mask
= s
->real_vram_size
- 1;
2989 s
->linear_mmio_mask
= s
->real_vram_size
- 256;
2991 s
->vga
.get_bpp
= cirrus_get_bpp
;
2992 s
->vga
.get_offsets
= cirrus_get_offsets
;
2993 s
->vga
.get_resolution
= cirrus_get_resolution
;
2994 s
->vga
.cursor_invalidate
= cirrus_cursor_invalidate
;
2995 s
->vga
.cursor_draw_line
= cirrus_cursor_draw_line
;
2997 qemu_register_reset(cirrus_reset
, s
);
3000 /***************************************
3004 ***************************************/
3006 static void isa_cirrus_vga_realizefn(DeviceState
*dev
, Error
**errp
)
3008 ISADevice
*isadev
= ISA_DEVICE(dev
);
3009 ISACirrusVGAState
*d
= ISA_CIRRUS_VGA(dev
);
3010 VGACommonState
*s
= &d
->cirrus_vga
.vga
;
3012 /* follow real hardware, cirrus card emulated has 4 MB video memory.
3013 Also accept 8 MB/16 MB for backward compatibility. */
3014 if (s
->vram_size_mb
!= 4 && s
->vram_size_mb
!= 8 &&
3015 s
->vram_size_mb
!= 16) {
3016 error_setg(errp
, "Invalid cirrus_vga ram size '%u'",
3020 vga_common_init(s
, OBJECT(dev
), true);
3021 cirrus_init_common(&d
->cirrus_vga
, OBJECT(dev
), CIRRUS_ID_CLGD5430
, 0,
3022 isa_address_space(isadev
),
3023 isa_address_space_io(isadev
));
3024 s
->con
= graphic_console_init(dev
, 0, s
->hw_ops
, s
);
3025 rom_add_vga(VGABIOS_CIRRUS_FILENAME
);
3026 /* XXX ISA-LFB support */
3027 /* FIXME not qdev yet */
3030 static Property isa_cirrus_vga_properties
[] = {
3031 DEFINE_PROP_UINT32("vgamem_mb", struct ISACirrusVGAState
,
3032 cirrus_vga
.vga
.vram_size_mb
, 8),
3033 DEFINE_PROP_END_OF_LIST(),
3036 static void isa_cirrus_vga_class_init(ObjectClass
*klass
, void *data
)
3038 DeviceClass
*dc
= DEVICE_CLASS(klass
);
3040 dc
->vmsd
= &vmstate_cirrus_vga
;
3041 dc
->realize
= isa_cirrus_vga_realizefn
;
3042 dc
->props
= isa_cirrus_vga_properties
;
3043 set_bit(DEVICE_CATEGORY_DISPLAY
, dc
->categories
);
3046 static const TypeInfo isa_cirrus_vga_info
= {
3047 .name
= TYPE_ISA_CIRRUS_VGA
,
3048 .parent
= TYPE_ISA_DEVICE
,
3049 .instance_size
= sizeof(ISACirrusVGAState
),
3050 .class_init
= isa_cirrus_vga_class_init
,
3053 /***************************************
3057 ***************************************/
3059 static void pci_cirrus_vga_realize(PCIDevice
*dev
, Error
**errp
)
3061 PCICirrusVGAState
*d
= PCI_CIRRUS_VGA(dev
);
3062 CirrusVGAState
*s
= &d
->cirrus_vga
;
3063 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
3064 int16_t device_id
= pc
->device_id
;
3066 /* follow real hardware, cirrus card emulated has 4 MB video memory.
3067 Also accept 8 MB/16 MB for backward compatibility. */
3068 if (s
->vga
.vram_size_mb
!= 4 && s
->vga
.vram_size_mb
!= 8 &&
3069 s
->vga
.vram_size_mb
!= 16) {
3070 error_setg(errp
, "Invalid cirrus_vga ram size '%u'",
3071 s
->vga
.vram_size_mb
);
3075 vga_common_init(&s
->vga
, OBJECT(dev
), true);
3076 cirrus_init_common(s
, OBJECT(dev
), device_id
, 1, pci_address_space(dev
),
3077 pci_address_space_io(dev
));
3078 s
->vga
.con
= graphic_console_init(DEVICE(dev
), 0, s
->vga
.hw_ops
, &s
->vga
);
3082 memory_region_init(&s
->pci_bar
, OBJECT(dev
), "cirrus-pci-bar0", 0x2000000);
3084 /* XXX: add byte swapping apertures */
3085 memory_region_add_subregion(&s
->pci_bar
, 0, &s
->cirrus_linear_io
);
3086 memory_region_add_subregion(&s
->pci_bar
, 0x1000000,
3087 &s
->cirrus_linear_bitblt_io
);
3089 /* setup memory space */
3091 /* memory #1 memory-mapped I/O */
3092 /* XXX: s->vga.vram_size must be a power of two */
3093 pci_register_bar(&d
->dev
, 0, PCI_BASE_ADDRESS_MEM_PREFETCH
, &s
->pci_bar
);
3094 if (device_id
== CIRRUS_ID_CLGD5446
) {
3095 pci_register_bar(&d
->dev
, 1, 0, &s
->cirrus_mmio_io
);
3099 static Property pci_vga_cirrus_properties
[] = {
3100 DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState
,
3101 cirrus_vga
.vga
.vram_size_mb
, 8),
3102 DEFINE_PROP_END_OF_LIST(),
3105 static void cirrus_vga_class_init(ObjectClass
*klass
, void *data
)
3107 DeviceClass
*dc
= DEVICE_CLASS(klass
);
3108 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
3110 k
->realize
= pci_cirrus_vga_realize
;
3111 k
->romfile
= VGABIOS_CIRRUS_FILENAME
;
3112 k
->vendor_id
= PCI_VENDOR_ID_CIRRUS
;
3113 k
->device_id
= CIRRUS_ID_CLGD5446
;
3114 k
->class_id
= PCI_CLASS_DISPLAY_VGA
;
3115 set_bit(DEVICE_CATEGORY_DISPLAY
, dc
->categories
);
3116 dc
->desc
= "Cirrus CLGD 54xx VGA";
3117 dc
->vmsd
= &vmstate_pci_cirrus_vga
;
3118 dc
->props
= pci_vga_cirrus_properties
;
3119 dc
->hotpluggable
= false;
3122 static const TypeInfo cirrus_vga_info
= {
3123 .name
= TYPE_PCI_CIRRUS_VGA
,
3124 .parent
= TYPE_PCI_DEVICE
,
3125 .instance_size
= sizeof(PCICirrusVGAState
),
3126 .class_init
= cirrus_vga_class_init
,
3129 static void cirrus_vga_register_types(void)
3131 type_register_static(&isa_cirrus_vga_info
);
3132 type_register_static(&cirrus_vga_info
);
3135 type_init(cirrus_vga_register_types
)