2 * QEMU Cirrus CLGD 54xx VGA Emulator.
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * Reference: Finn Thogersons' VGADOC4b:
28 * http://web.archive.org/web/20021019054927/http://home.worldonline.dk/finth/
30 * VGADOC4b.ZIP content available at:
32 * https://pdos.csail.mit.edu/6.828/2005/readings/hardware/vgadoc
35 #include "qemu/osdep.h"
36 #include "qemu/module.h"
37 #include "qemu/units.h"
39 #include "sysemu/reset.h"
40 #include "qapi/error.h"
42 #include "hw/pci/pci.h"
43 #include "hw/qdev-properties.h"
44 #include "migration/vmstate.h"
45 #include "ui/pixel_ops.h"
46 #include "cirrus_vga_internal.h"
47 #include "qom/object.h"
51 * - destination write mask support not complete (bits 5..7)
52 * - optimize linear mappings
53 * - optimize bitblt functions
56 //#define DEBUG_CIRRUS
58 /***************************************
62 ***************************************/
65 #define CIRRUS_SR7_BPP_VGA 0x00
66 #define CIRRUS_SR7_BPP_SVGA 0x01
67 #define CIRRUS_SR7_BPP_MASK 0x0e
68 #define CIRRUS_SR7_BPP_8 0x00
69 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
70 #define CIRRUS_SR7_BPP_24 0x04
71 #define CIRRUS_SR7_BPP_16 0x06
72 #define CIRRUS_SR7_BPP_32 0x08
73 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
76 #define CIRRUS_MEMSIZE_512k 0x08
77 #define CIRRUS_MEMSIZE_1M 0x10
78 #define CIRRUS_MEMSIZE_2M 0x18
79 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
82 #define CIRRUS_CURSOR_SHOW 0x01
83 #define CIRRUS_CURSOR_HIDDENPEL 0x02
84 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
87 #define CIRRUS_BUSTYPE_VLBFAST 0x10
88 #define CIRRUS_BUSTYPE_PCI 0x20
89 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
90 #define CIRRUS_BUSTYPE_ISA 0x38
91 #define CIRRUS_MMIO_ENABLE 0x04
92 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
93 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
96 #define CIRRUS_BANKING_DUAL 0x01
97 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
100 #define CIRRUS_BLTMODE_BACKWARDS 0x01
101 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
102 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
103 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
104 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
105 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
106 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
107 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
108 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
109 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
110 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
113 #define CIRRUS_BLT_BUSY 0x01
114 #define CIRRUS_BLT_START 0x02
115 #define CIRRUS_BLT_RESET 0x04
116 #define CIRRUS_BLT_FIFOUSED 0x10
117 #define CIRRUS_BLT_AUTOSTART 0x80
120 #define CIRRUS_ROP_0 0x00
121 #define CIRRUS_ROP_SRC_AND_DST 0x05
122 #define CIRRUS_ROP_NOP 0x06
123 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
124 #define CIRRUS_ROP_NOTDST 0x0b
125 #define CIRRUS_ROP_SRC 0x0d
126 #define CIRRUS_ROP_1 0x0e
127 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
128 #define CIRRUS_ROP_SRC_XOR_DST 0x59
129 #define CIRRUS_ROP_SRC_OR_DST 0x6d
130 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
131 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
132 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
133 #define CIRRUS_ROP_NOTSRC 0xd0
134 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
135 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
137 #define CIRRUS_ROP_NOP_INDEX 2
138 #define CIRRUS_ROP_SRC_INDEX 5
141 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
142 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
143 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
146 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
147 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
148 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
149 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
150 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
151 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
152 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
153 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
154 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
155 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
156 #define CIRRUS_MMIO_BLTROP 0x1a // byte
157 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
158 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
159 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
160 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
161 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
162 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
163 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
164 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
168 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
169 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
170 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
171 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
172 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
173 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
174 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
176 #define CIRRUS_PNPMMIO_SIZE 0x1000
178 typedef void (*cirrus_fill_t
)(struct CirrusVGAState
*s
,
179 uint32_t dstaddr
, int dst_pitch
,
180 int width
, int height
);
182 struct PCICirrusVGAState
{
184 CirrusVGAState cirrus_vga
;
186 typedef struct PCICirrusVGAState PCICirrusVGAState
;
188 #define TYPE_PCI_CIRRUS_VGA "cirrus-vga"
189 DECLARE_INSTANCE_CHECKER(PCICirrusVGAState
, PCI_CIRRUS_VGA
,
192 static uint8_t rop_to_index
[256];
194 /***************************************
198 ***************************************/
201 static void cirrus_bitblt_reset(CirrusVGAState
*s
);
202 static void cirrus_update_memory_access(CirrusVGAState
*s
);
204 /***************************************
208 ***************************************/
210 static bool blit_region_is_unsafe(struct CirrusVGAState
*s
,
211 int32_t pitch
, int32_t addr
)
218 + ((int64_t)s
->cirrus_blt_height
- 1) * pitch
219 - s
->cirrus_blt_width
;
220 if (min
< -1 || addr
>= s
->vga
.vram_size
) {
225 + ((int64_t)s
->cirrus_blt_height
-1) * pitch
226 + s
->cirrus_blt_width
;
227 if (max
> s
->vga
.vram_size
) {
234 static bool blit_is_unsafe(struct CirrusVGAState
*s
, bool dst_only
)
236 /* should be the case, see cirrus_bitblt_start */
237 assert(s
->cirrus_blt_width
> 0);
238 assert(s
->cirrus_blt_height
> 0);
240 if (s
->cirrus_blt_width
> CIRRUS_BLTBUFSIZE
) {
244 if (blit_region_is_unsafe(s
, s
->cirrus_blt_dstpitch
,
245 s
->cirrus_blt_dstaddr
)) {
251 if (blit_region_is_unsafe(s
, s
->cirrus_blt_srcpitch
,
252 s
->cirrus_blt_srcaddr
)) {
259 static void cirrus_bitblt_rop_nop(CirrusVGAState
*s
,
260 uint32_t dstaddr
, uint32_t srcaddr
,
261 int dstpitch
,int srcpitch
,
262 int bltwidth
,int bltheight
)
266 static void cirrus_bitblt_fill_nop(CirrusVGAState
*s
,
268 int dstpitch
, int bltwidth
,int bltheight
)
272 static inline uint8_t cirrus_src(CirrusVGAState
*s
, uint32_t srcaddr
)
274 if (s
->cirrus_srccounter
) {
276 return s
->cirrus_bltbuf
[srcaddr
& (CIRRUS_BLTBUFSIZE
- 1)];
279 return s
->vga
.vram_ptr
[srcaddr
& s
->cirrus_addr_mask
];
283 static inline uint16_t cirrus_src16(CirrusVGAState
*s
, uint32_t srcaddr
)
287 if (s
->cirrus_srccounter
) {
289 src
= (void *)&s
->cirrus_bltbuf
[srcaddr
& (CIRRUS_BLTBUFSIZE
- 1) & ~1];
292 src
= (void *)&s
->vga
.vram_ptr
[srcaddr
& s
->cirrus_addr_mask
& ~1];
297 static inline uint32_t cirrus_src32(CirrusVGAState
*s
, uint32_t srcaddr
)
301 if (s
->cirrus_srccounter
) {
303 src
= (void *)&s
->cirrus_bltbuf
[srcaddr
& (CIRRUS_BLTBUFSIZE
- 1) & ~3];
306 src
= (void *)&s
->vga
.vram_ptr
[srcaddr
& s
->cirrus_addr_mask
& ~3];
312 #define ROP_FN(d, s) 0
313 #include "cirrus_vga_rop.h"
315 #define ROP_NAME src_and_dst
316 #define ROP_FN(d, s) (s) & (d)
317 #include "cirrus_vga_rop.h"
319 #define ROP_NAME src_and_notdst
320 #define ROP_FN(d, s) (s) & (~(d))
321 #include "cirrus_vga_rop.h"
323 #define ROP_NAME notdst
324 #define ROP_FN(d, s) ~(d)
325 #include "cirrus_vga_rop.h"
328 #define ROP_FN(d, s) s
329 #include "cirrus_vga_rop.h"
332 #define ROP_FN(d, s) ~0
333 #include "cirrus_vga_rop.h"
335 #define ROP_NAME notsrc_and_dst
336 #define ROP_FN(d, s) (~(s)) & (d)
337 #include "cirrus_vga_rop.h"
339 #define ROP_NAME src_xor_dst
340 #define ROP_FN(d, s) (s) ^ (d)
341 #include "cirrus_vga_rop.h"
343 #define ROP_NAME src_or_dst
344 #define ROP_FN(d, s) (s) | (d)
345 #include "cirrus_vga_rop.h"
347 #define ROP_NAME notsrc_or_notdst
348 #define ROP_FN(d, s) (~(s)) | (~(d))
349 #include "cirrus_vga_rop.h"
351 #define ROP_NAME src_notxor_dst
352 #define ROP_FN(d, s) ~((s) ^ (d))
353 #include "cirrus_vga_rop.h"
355 #define ROP_NAME src_or_notdst
356 #define ROP_FN(d, s) (s) | (~(d))
357 #include "cirrus_vga_rop.h"
359 #define ROP_NAME notsrc
360 #define ROP_FN(d, s) (~(s))
361 #include "cirrus_vga_rop.h"
363 #define ROP_NAME notsrc_or_dst
364 #define ROP_FN(d, s) (~(s)) | (d)
365 #include "cirrus_vga_rop.h"
367 #define ROP_NAME notsrc_and_notdst
368 #define ROP_FN(d, s) (~(s)) & (~(d))
369 #include "cirrus_vga_rop.h"
371 static const cirrus_bitblt_rop_t cirrus_fwd_rop
[16] = {
372 cirrus_bitblt_rop_fwd_0
,
373 cirrus_bitblt_rop_fwd_src_and_dst
,
374 cirrus_bitblt_rop_nop
,
375 cirrus_bitblt_rop_fwd_src_and_notdst
,
376 cirrus_bitblt_rop_fwd_notdst
,
377 cirrus_bitblt_rop_fwd_src
,
378 cirrus_bitblt_rop_fwd_1
,
379 cirrus_bitblt_rop_fwd_notsrc_and_dst
,
380 cirrus_bitblt_rop_fwd_src_xor_dst
,
381 cirrus_bitblt_rop_fwd_src_or_dst
,
382 cirrus_bitblt_rop_fwd_notsrc_or_notdst
,
383 cirrus_bitblt_rop_fwd_src_notxor_dst
,
384 cirrus_bitblt_rop_fwd_src_or_notdst
,
385 cirrus_bitblt_rop_fwd_notsrc
,
386 cirrus_bitblt_rop_fwd_notsrc_or_dst
,
387 cirrus_bitblt_rop_fwd_notsrc_and_notdst
,
390 static const cirrus_bitblt_rop_t cirrus_bkwd_rop
[16] = {
391 cirrus_bitblt_rop_bkwd_0
,
392 cirrus_bitblt_rop_bkwd_src_and_dst
,
393 cirrus_bitblt_rop_nop
,
394 cirrus_bitblt_rop_bkwd_src_and_notdst
,
395 cirrus_bitblt_rop_bkwd_notdst
,
396 cirrus_bitblt_rop_bkwd_src
,
397 cirrus_bitblt_rop_bkwd_1
,
398 cirrus_bitblt_rop_bkwd_notsrc_and_dst
,
399 cirrus_bitblt_rop_bkwd_src_xor_dst
,
400 cirrus_bitblt_rop_bkwd_src_or_dst
,
401 cirrus_bitblt_rop_bkwd_notsrc_or_notdst
,
402 cirrus_bitblt_rop_bkwd_src_notxor_dst
,
403 cirrus_bitblt_rop_bkwd_src_or_notdst
,
404 cirrus_bitblt_rop_bkwd_notsrc
,
405 cirrus_bitblt_rop_bkwd_notsrc_or_dst
,
406 cirrus_bitblt_rop_bkwd_notsrc_and_notdst
,
409 #define TRANSP_ROP(name) {\
413 #define TRANSP_NOP(func) {\
418 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop
[16][2] = {
419 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0
),
420 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst
),
421 TRANSP_NOP(cirrus_bitblt_rop_nop
),
422 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst
),
423 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst
),
424 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src
),
425 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1
),
426 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst
),
427 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst
),
428 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst
),
429 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst
),
430 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst
),
431 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst
),
432 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc
),
433 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst
),
434 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst
),
437 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop
[16][2] = {
438 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0
),
439 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst
),
440 TRANSP_NOP(cirrus_bitblt_rop_nop
),
441 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst
),
442 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst
),
443 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src
),
444 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1
),
445 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst
),
446 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst
),
447 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst
),
448 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst
),
449 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst
),
450 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst
),
451 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc
),
452 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst
),
453 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst
),
456 #define ROP2(name) {\
463 #define ROP_NOP2(func) {\
470 static const cirrus_bitblt_rop_t cirrus_patternfill
[16][4] = {
471 ROP2(cirrus_patternfill_0
),
472 ROP2(cirrus_patternfill_src_and_dst
),
473 ROP_NOP2(cirrus_bitblt_rop_nop
),
474 ROP2(cirrus_patternfill_src_and_notdst
),
475 ROP2(cirrus_patternfill_notdst
),
476 ROP2(cirrus_patternfill_src
),
477 ROP2(cirrus_patternfill_1
),
478 ROP2(cirrus_patternfill_notsrc_and_dst
),
479 ROP2(cirrus_patternfill_src_xor_dst
),
480 ROP2(cirrus_patternfill_src_or_dst
),
481 ROP2(cirrus_patternfill_notsrc_or_notdst
),
482 ROP2(cirrus_patternfill_src_notxor_dst
),
483 ROP2(cirrus_patternfill_src_or_notdst
),
484 ROP2(cirrus_patternfill_notsrc
),
485 ROP2(cirrus_patternfill_notsrc_or_dst
),
486 ROP2(cirrus_patternfill_notsrc_and_notdst
),
489 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp
[16][4] = {
490 ROP2(cirrus_colorexpand_transp_0
),
491 ROP2(cirrus_colorexpand_transp_src_and_dst
),
492 ROP_NOP2(cirrus_bitblt_rop_nop
),
493 ROP2(cirrus_colorexpand_transp_src_and_notdst
),
494 ROP2(cirrus_colorexpand_transp_notdst
),
495 ROP2(cirrus_colorexpand_transp_src
),
496 ROP2(cirrus_colorexpand_transp_1
),
497 ROP2(cirrus_colorexpand_transp_notsrc_and_dst
),
498 ROP2(cirrus_colorexpand_transp_src_xor_dst
),
499 ROP2(cirrus_colorexpand_transp_src_or_dst
),
500 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst
),
501 ROP2(cirrus_colorexpand_transp_src_notxor_dst
),
502 ROP2(cirrus_colorexpand_transp_src_or_notdst
),
503 ROP2(cirrus_colorexpand_transp_notsrc
),
504 ROP2(cirrus_colorexpand_transp_notsrc_or_dst
),
505 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst
),
508 static const cirrus_bitblt_rop_t cirrus_colorexpand
[16][4] = {
509 ROP2(cirrus_colorexpand_0
),
510 ROP2(cirrus_colorexpand_src_and_dst
),
511 ROP_NOP2(cirrus_bitblt_rop_nop
),
512 ROP2(cirrus_colorexpand_src_and_notdst
),
513 ROP2(cirrus_colorexpand_notdst
),
514 ROP2(cirrus_colorexpand_src
),
515 ROP2(cirrus_colorexpand_1
),
516 ROP2(cirrus_colorexpand_notsrc_and_dst
),
517 ROP2(cirrus_colorexpand_src_xor_dst
),
518 ROP2(cirrus_colorexpand_src_or_dst
),
519 ROP2(cirrus_colorexpand_notsrc_or_notdst
),
520 ROP2(cirrus_colorexpand_src_notxor_dst
),
521 ROP2(cirrus_colorexpand_src_or_notdst
),
522 ROP2(cirrus_colorexpand_notsrc
),
523 ROP2(cirrus_colorexpand_notsrc_or_dst
),
524 ROP2(cirrus_colorexpand_notsrc_and_notdst
),
527 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp
[16][4] = {
528 ROP2(cirrus_colorexpand_pattern_transp_0
),
529 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst
),
530 ROP_NOP2(cirrus_bitblt_rop_nop
),
531 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst
),
532 ROP2(cirrus_colorexpand_pattern_transp_notdst
),
533 ROP2(cirrus_colorexpand_pattern_transp_src
),
534 ROP2(cirrus_colorexpand_pattern_transp_1
),
535 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst
),
536 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst
),
537 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst
),
538 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst
),
539 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst
),
540 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst
),
541 ROP2(cirrus_colorexpand_pattern_transp_notsrc
),
542 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst
),
543 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst
),
546 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern
[16][4] = {
547 ROP2(cirrus_colorexpand_pattern_0
),
548 ROP2(cirrus_colorexpand_pattern_src_and_dst
),
549 ROP_NOP2(cirrus_bitblt_rop_nop
),
550 ROP2(cirrus_colorexpand_pattern_src_and_notdst
),
551 ROP2(cirrus_colorexpand_pattern_notdst
),
552 ROP2(cirrus_colorexpand_pattern_src
),
553 ROP2(cirrus_colorexpand_pattern_1
),
554 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst
),
555 ROP2(cirrus_colorexpand_pattern_src_xor_dst
),
556 ROP2(cirrus_colorexpand_pattern_src_or_dst
),
557 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst
),
558 ROP2(cirrus_colorexpand_pattern_src_notxor_dst
),
559 ROP2(cirrus_colorexpand_pattern_src_or_notdst
),
560 ROP2(cirrus_colorexpand_pattern_notsrc
),
561 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst
),
562 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst
),
565 static const cirrus_fill_t cirrus_fill
[16][4] = {
567 ROP2(cirrus_fill_src_and_dst
),
568 ROP_NOP2(cirrus_bitblt_fill_nop
),
569 ROP2(cirrus_fill_src_and_notdst
),
570 ROP2(cirrus_fill_notdst
),
571 ROP2(cirrus_fill_src
),
573 ROP2(cirrus_fill_notsrc_and_dst
),
574 ROP2(cirrus_fill_src_xor_dst
),
575 ROP2(cirrus_fill_src_or_dst
),
576 ROP2(cirrus_fill_notsrc_or_notdst
),
577 ROP2(cirrus_fill_src_notxor_dst
),
578 ROP2(cirrus_fill_src_or_notdst
),
579 ROP2(cirrus_fill_notsrc
),
580 ROP2(cirrus_fill_notsrc_or_dst
),
581 ROP2(cirrus_fill_notsrc_and_notdst
),
584 static inline void cirrus_bitblt_fgcol(CirrusVGAState
*s
)
587 switch (s
->cirrus_blt_pixelwidth
) {
589 s
->cirrus_blt_fgcol
= s
->cirrus_shadow_gr1
;
592 color
= s
->cirrus_shadow_gr1
| (s
->vga
.gr
[0x11] << 8);
593 s
->cirrus_blt_fgcol
= le16_to_cpu(color
);
596 s
->cirrus_blt_fgcol
= s
->cirrus_shadow_gr1
|
597 (s
->vga
.gr
[0x11] << 8) | (s
->vga
.gr
[0x13] << 16);
601 color
= s
->cirrus_shadow_gr1
| (s
->vga
.gr
[0x11] << 8) |
602 (s
->vga
.gr
[0x13] << 16) | (s
->vga
.gr
[0x15] << 24);
603 s
->cirrus_blt_fgcol
= le32_to_cpu(color
);
608 static inline void cirrus_bitblt_bgcol(CirrusVGAState
*s
)
611 switch (s
->cirrus_blt_pixelwidth
) {
613 s
->cirrus_blt_bgcol
= s
->cirrus_shadow_gr0
;
616 color
= s
->cirrus_shadow_gr0
| (s
->vga
.gr
[0x10] << 8);
617 s
->cirrus_blt_bgcol
= le16_to_cpu(color
);
620 s
->cirrus_blt_bgcol
= s
->cirrus_shadow_gr0
|
621 (s
->vga
.gr
[0x10] << 8) | (s
->vga
.gr
[0x12] << 16);
625 color
= s
->cirrus_shadow_gr0
| (s
->vga
.gr
[0x10] << 8) |
626 (s
->vga
.gr
[0x12] << 16) | (s
->vga
.gr
[0x14] << 24);
627 s
->cirrus_blt_bgcol
= le32_to_cpu(color
);
632 static void cirrus_invalidate_region(CirrusVGAState
* s
, int off_begin
,
633 int off_pitch
, int bytesperline
,
641 off_begin
-= bytesperline
- 1;
644 for (y
= 0; y
< lines
; y
++) {
645 off_cur
= off_begin
& s
->cirrus_addr_mask
;
646 off_cur_end
= ((off_cur
+ bytesperline
- 1) & s
->cirrus_addr_mask
) + 1;
647 if (off_cur_end
>= off_cur
) {
648 memory_region_set_dirty(&s
->vga
.vram
, off_cur
, off_cur_end
- off_cur
);
651 memory_region_set_dirty(&s
->vga
.vram
, off_cur
,
652 s
->cirrus_addr_mask
+ 1 - off_cur
);
653 memory_region_set_dirty(&s
->vga
.vram
, 0, off_cur_end
);
655 off_begin
+= off_pitch
;
659 static int cirrus_bitblt_common_patterncopy(CirrusVGAState
*s
)
661 uint32_t patternsize
;
662 bool videosrc
= !s
->cirrus_srccounter
;
665 switch (s
->vga
.get_bpp(&s
->vga
)) {
679 s
->cirrus_blt_srcaddr
&= ~(patternsize
- 1);
680 if (s
->cirrus_blt_srcaddr
+ patternsize
> s
->vga
.vram_size
) {
685 if (blit_is_unsafe(s
, true)) {
689 (*s
->cirrus_rop
) (s
, s
->cirrus_blt_dstaddr
,
690 videosrc
? s
->cirrus_blt_srcaddr
: 0,
691 s
->cirrus_blt_dstpitch
, 0,
692 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
693 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
694 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
695 s
->cirrus_blt_height
);
701 static int cirrus_bitblt_solidfill(CirrusVGAState
*s
, int blt_rop
)
703 cirrus_fill_t rop_func
;
705 if (blit_is_unsafe(s
, true)) {
708 rop_func
= cirrus_fill
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
709 rop_func(s
, s
->cirrus_blt_dstaddr
,
710 s
->cirrus_blt_dstpitch
,
711 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
712 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
713 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
714 s
->cirrus_blt_height
);
715 cirrus_bitblt_reset(s
);
719 /***************************************
721 * bitblt (video-to-video)
723 ***************************************/
725 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState
* s
)
727 return cirrus_bitblt_common_patterncopy(s
);
730 static int cirrus_do_copy(CirrusVGAState
*s
, int dst
, int src
, int w
, int h
)
737 /* make sure to only copy if it's a plain copy ROP */
738 if (*s
->cirrus_rop
== cirrus_bitblt_rop_fwd_src
||
739 *s
->cirrus_rop
== cirrus_bitblt_rop_bkwd_src
) {
743 depth
= s
->vga
.get_bpp(&s
->vga
) / 8;
747 s
->vga
.get_resolution(&s
->vga
, &width
, &height
);
750 sx
= (src
% ABS(s
->cirrus_blt_srcpitch
)) / depth
;
751 sy
= (src
/ ABS(s
->cirrus_blt_srcpitch
));
752 dx
= (dst
% ABS(s
->cirrus_blt_dstpitch
)) / depth
;
753 dy
= (dst
/ ABS(s
->cirrus_blt_dstpitch
));
755 /* normalize width */
758 /* if we're doing a backward copy, we have to adjust
759 our x/y to be the upper left corner (instead of the lower
761 if (s
->cirrus_blt_dstpitch
< 0) {
762 sx
-= (s
->cirrus_blt_width
/ depth
) - 1;
763 dx
-= (s
->cirrus_blt_width
/ depth
) - 1;
764 sy
-= s
->cirrus_blt_height
- 1;
765 dy
-= s
->cirrus_blt_height
- 1;
768 /* are we in the visible portion of memory? */
769 if (sx
>= 0 && sy
>= 0 && dx
>= 0 && dy
>= 0 &&
770 (sx
+ w
) <= width
&& (sy
+ h
) <= height
&&
771 (dx
+ w
) <= width
&& (dy
+ h
) <= height
) {
776 (*s
->cirrus_rop
) (s
, s
->cirrus_blt_dstaddr
,
777 s
->cirrus_blt_srcaddr
,
778 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_srcpitch
,
779 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
782 dpy_gfx_update(s
->vga
.con
, dx
, dy
,
783 s
->cirrus_blt_width
/ depth
,
784 s
->cirrus_blt_height
);
787 /* we don't have to notify the display that this portion has
788 changed since qemu_console_copy implies this */
790 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
791 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
792 s
->cirrus_blt_height
);
797 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState
* s
)
799 if (blit_is_unsafe(s
, false))
802 return cirrus_do_copy(s
, s
->cirrus_blt_dstaddr
- s
->vga
.start_addr
,
803 s
->cirrus_blt_srcaddr
- s
->vga
.start_addr
,
804 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
807 /***************************************
809 * bitblt (cpu-to-video)
811 ***************************************/
813 static void cirrus_bitblt_cputovideo_next(CirrusVGAState
* s
)
818 if (s
->cirrus_srccounter
> 0) {
819 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
820 cirrus_bitblt_common_patterncopy(s
);
822 s
->cirrus_srccounter
= 0;
823 cirrus_bitblt_reset(s
);
825 /* at least one scan line */
827 (*s
->cirrus_rop
)(s
, s
->cirrus_blt_dstaddr
,
828 0, 0, 0, s
->cirrus_blt_width
, 1);
829 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
, 0,
830 s
->cirrus_blt_width
, 1);
831 s
->cirrus_blt_dstaddr
+= s
->cirrus_blt_dstpitch
;
832 s
->cirrus_srccounter
-= s
->cirrus_blt_srcpitch
;
833 if (s
->cirrus_srccounter
<= 0)
835 /* more bytes than needed can be transferred because of
836 word alignment, so we keep them for the next line */
837 /* XXX: keep alignment to speed up transfer */
838 end_ptr
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
839 copy_count
= s
->cirrus_srcptr_end
- end_ptr
;
840 memmove(s
->cirrus_bltbuf
, end_ptr
, copy_count
);
841 s
->cirrus_srcptr
= s
->cirrus_bltbuf
+ copy_count
;
842 s
->cirrus_srcptr_end
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
843 } while (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
);
848 /***************************************
852 ***************************************/
854 static void cirrus_bitblt_reset(CirrusVGAState
* s
)
859 ~(CIRRUS_BLT_START
| CIRRUS_BLT_BUSY
| CIRRUS_BLT_FIFOUSED
);
860 need_update
= s
->cirrus_srcptr
!= &s
->cirrus_bltbuf
[0]
861 || s
->cirrus_srcptr_end
!= &s
->cirrus_bltbuf
[0];
862 s
->cirrus_srcptr
= &s
->cirrus_bltbuf
[0];
863 s
->cirrus_srcptr_end
= &s
->cirrus_bltbuf
[0];
864 s
->cirrus_srccounter
= 0;
867 cirrus_update_memory_access(s
);
870 static int cirrus_bitblt_cputovideo(CirrusVGAState
* s
)
874 if (blit_is_unsafe(s
, true)) {
878 s
->cirrus_blt_mode
&= ~CIRRUS_BLTMODE_MEMSYSSRC
;
879 s
->cirrus_srcptr
= &s
->cirrus_bltbuf
[0];
880 s
->cirrus_srcptr_end
= &s
->cirrus_bltbuf
[0];
882 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
883 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
884 s
->cirrus_blt_srcpitch
= 8;
886 /* XXX: check for 24 bpp */
887 s
->cirrus_blt_srcpitch
= 8 * 8 * s
->cirrus_blt_pixelwidth
;
889 s
->cirrus_srccounter
= s
->cirrus_blt_srcpitch
;
891 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
892 w
= s
->cirrus_blt_width
/ s
->cirrus_blt_pixelwidth
;
893 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_DWORDGRANULARITY
)
894 s
->cirrus_blt_srcpitch
= ((w
+ 31) >> 5);
896 s
->cirrus_blt_srcpitch
= ((w
+ 7) >> 3);
898 /* always align input size to 32 bits */
899 s
->cirrus_blt_srcpitch
= (s
->cirrus_blt_width
+ 3) & ~3;
901 s
->cirrus_srccounter
= s
->cirrus_blt_srcpitch
* s
->cirrus_blt_height
;
904 /* the blit_is_unsafe call above should catch this */
905 assert(s
->cirrus_blt_srcpitch
<= CIRRUS_BLTBUFSIZE
);
907 s
->cirrus_srcptr
= s
->cirrus_bltbuf
;
908 s
->cirrus_srcptr_end
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
909 cirrus_update_memory_access(s
);
913 static int cirrus_bitblt_videotocpu(CirrusVGAState
* s
)
916 qemu_log_mask(LOG_UNIMP
,
917 "cirrus: bitblt (video to cpu) is not implemented\n");
921 static int cirrus_bitblt_videotovideo(CirrusVGAState
* s
)
925 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
926 ret
= cirrus_bitblt_videotovideo_patterncopy(s
);
928 ret
= cirrus_bitblt_videotovideo_copy(s
);
931 cirrus_bitblt_reset(s
);
935 static void cirrus_bitblt_start(CirrusVGAState
* s
)
939 if (!s
->enable_blitter
) {
943 s
->vga
.gr
[0x31] |= CIRRUS_BLT_BUSY
;
945 s
->cirrus_blt_width
= (s
->vga
.gr
[0x20] | (s
->vga
.gr
[0x21] << 8)) + 1;
946 s
->cirrus_blt_height
= (s
->vga
.gr
[0x22] | (s
->vga
.gr
[0x23] << 8)) + 1;
947 s
->cirrus_blt_dstpitch
= (s
->vga
.gr
[0x24] | (s
->vga
.gr
[0x25] << 8));
948 s
->cirrus_blt_srcpitch
= (s
->vga
.gr
[0x26] | (s
->vga
.gr
[0x27] << 8));
949 s
->cirrus_blt_dstaddr
=
950 (s
->vga
.gr
[0x28] | (s
->vga
.gr
[0x29] << 8) | (s
->vga
.gr
[0x2a] << 16));
951 s
->cirrus_blt_srcaddr
=
952 (s
->vga
.gr
[0x2c] | (s
->vga
.gr
[0x2d] << 8) | (s
->vga
.gr
[0x2e] << 16));
953 s
->cirrus_blt_mode
= s
->vga
.gr
[0x30];
954 s
->cirrus_blt_modeext
= s
->vga
.gr
[0x33];
955 blt_rop
= s
->vga
.gr
[0x32];
957 s
->cirrus_blt_dstaddr
&= s
->cirrus_addr_mask
;
958 s
->cirrus_blt_srcaddr
&= s
->cirrus_addr_mask
;
960 trace_vga_cirrus_bitblt_start(blt_rop
,
962 s
->cirrus_blt_modeext
,
964 s
->cirrus_blt_height
,
965 s
->cirrus_blt_dstpitch
,
966 s
->cirrus_blt_srcpitch
,
967 s
->cirrus_blt_dstaddr
,
968 s
->cirrus_blt_srcaddr
,
971 switch (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PIXELWIDTHMASK
) {
972 case CIRRUS_BLTMODE_PIXELWIDTH8
:
973 s
->cirrus_blt_pixelwidth
= 1;
975 case CIRRUS_BLTMODE_PIXELWIDTH16
:
976 s
->cirrus_blt_pixelwidth
= 2;
978 case CIRRUS_BLTMODE_PIXELWIDTH24
:
979 s
->cirrus_blt_pixelwidth
= 3;
981 case CIRRUS_BLTMODE_PIXELWIDTH32
:
982 s
->cirrus_blt_pixelwidth
= 4;
985 qemu_log_mask(LOG_GUEST_ERROR
,
986 "cirrus: bitblt - pixel width is unknown\n");
989 s
->cirrus_blt_mode
&= ~CIRRUS_BLTMODE_PIXELWIDTHMASK
;
992 cirrus_blt_mode
& (CIRRUS_BLTMODE_MEMSYSSRC
|
993 CIRRUS_BLTMODE_MEMSYSDEST
))
994 == (CIRRUS_BLTMODE_MEMSYSSRC
| CIRRUS_BLTMODE_MEMSYSDEST
)) {
995 qemu_log_mask(LOG_UNIMP
,
996 "cirrus: bitblt - memory-to-memory copy requested\n");
1000 if ((s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_SOLIDFILL
) &&
1001 (s
->cirrus_blt_mode
& (CIRRUS_BLTMODE_MEMSYSDEST
|
1002 CIRRUS_BLTMODE_TRANSPARENTCOMP
|
1003 CIRRUS_BLTMODE_PATTERNCOPY
|
1004 CIRRUS_BLTMODE_COLOREXPAND
)) ==
1005 (CIRRUS_BLTMODE_PATTERNCOPY
| CIRRUS_BLTMODE_COLOREXPAND
)) {
1006 cirrus_bitblt_fgcol(s
);
1007 cirrus_bitblt_solidfill(s
, blt_rop
);
1009 if ((s
->cirrus_blt_mode
& (CIRRUS_BLTMODE_COLOREXPAND
|
1010 CIRRUS_BLTMODE_PATTERNCOPY
)) ==
1011 CIRRUS_BLTMODE_COLOREXPAND
) {
1013 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_TRANSPARENTCOMP
) {
1014 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_COLOREXPINV
)
1015 cirrus_bitblt_bgcol(s
);
1017 cirrus_bitblt_fgcol(s
);
1018 s
->cirrus_rop
= cirrus_colorexpand_transp
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1020 cirrus_bitblt_fgcol(s
);
1021 cirrus_bitblt_bgcol(s
);
1022 s
->cirrus_rop
= cirrus_colorexpand
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1024 } else if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
1025 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
1026 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_TRANSPARENTCOMP
) {
1027 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_COLOREXPINV
)
1028 cirrus_bitblt_bgcol(s
);
1030 cirrus_bitblt_fgcol(s
);
1031 s
->cirrus_rop
= cirrus_colorexpand_pattern_transp
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1033 cirrus_bitblt_fgcol(s
);
1034 cirrus_bitblt_bgcol(s
);
1035 s
->cirrus_rop
= cirrus_colorexpand_pattern
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1038 s
->cirrus_rop
= cirrus_patternfill
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1041 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_TRANSPARENTCOMP
) {
1042 if (s
->cirrus_blt_pixelwidth
> 2) {
1043 qemu_log_mask(LOG_GUEST_ERROR
,
1044 "cirrus: src transparent without colorexpand "
1045 "must be 8bpp or 16bpp\n");
1048 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_BACKWARDS
) {
1049 s
->cirrus_blt_dstpitch
= -s
->cirrus_blt_dstpitch
;
1050 s
->cirrus_blt_srcpitch
= -s
->cirrus_blt_srcpitch
;
1051 s
->cirrus_rop
= cirrus_bkwd_transp_rop
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1053 s
->cirrus_rop
= cirrus_fwd_transp_rop
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1056 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_BACKWARDS
) {
1057 s
->cirrus_blt_dstpitch
= -s
->cirrus_blt_dstpitch
;
1058 s
->cirrus_blt_srcpitch
= -s
->cirrus_blt_srcpitch
;
1059 s
->cirrus_rop
= cirrus_bkwd_rop
[rop_to_index
[blt_rop
]];
1061 s
->cirrus_rop
= cirrus_fwd_rop
[rop_to_index
[blt_rop
]];
1065 // setup bitblt engine.
1066 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_MEMSYSSRC
) {
1067 if (!cirrus_bitblt_cputovideo(s
))
1069 } else if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_MEMSYSDEST
) {
1070 if (!cirrus_bitblt_videotocpu(s
))
1073 if (!cirrus_bitblt_videotovideo(s
))
1079 cirrus_bitblt_reset(s
);
1082 static void cirrus_write_bitblt(CirrusVGAState
* s
, unsigned reg_value
)
1086 old_value
= s
->vga
.gr
[0x31];
1087 s
->vga
.gr
[0x31] = reg_value
;
1089 if (((old_value
& CIRRUS_BLT_RESET
) != 0) &&
1090 ((reg_value
& CIRRUS_BLT_RESET
) == 0)) {
1091 cirrus_bitblt_reset(s
);
1092 } else if (((old_value
& CIRRUS_BLT_START
) == 0) &&
1093 ((reg_value
& CIRRUS_BLT_START
) != 0)) {
1094 cirrus_bitblt_start(s
);
1099 /***************************************
1103 ***************************************/
1105 static void cirrus_get_offsets(VGACommonState
*s1
,
1106 uint32_t *pline_offset
,
1107 uint32_t *pstart_addr
,
1108 uint32_t *pline_compare
)
1110 CirrusVGAState
* s
= container_of(s1
, CirrusVGAState
, vga
);
1111 uint32_t start_addr
, line_offset
, line_compare
;
1113 line_offset
= s
->vga
.cr
[0x13]
1114 | ((s
->vga
.cr
[0x1b] & 0x10) << 4);
1116 *pline_offset
= line_offset
;
1118 start_addr
= (s
->vga
.cr
[0x0c] << 8)
1120 | ((s
->vga
.cr
[0x1b] & 0x01) << 16)
1121 | ((s
->vga
.cr
[0x1b] & 0x0c) << 15)
1122 | ((s
->vga
.cr
[0x1d] & 0x80) << 12);
1123 *pstart_addr
= start_addr
;
1125 line_compare
= s
->vga
.cr
[0x18] |
1126 ((s
->vga
.cr
[0x07] & 0x10) << 4) |
1127 ((s
->vga
.cr
[0x09] & 0x40) << 3);
1128 *pline_compare
= line_compare
;
1131 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState
* s
)
1135 switch (s
->cirrus_hidden_dac_data
& 0xf) {
1138 break; /* Sierra HiColor */
1141 break; /* XGA HiColor */
1143 qemu_log_mask(LOG_GUEST_ERROR
,
1144 "cirrus: invalid DAC value 0x%x in 16bpp\n",
1145 (s
->cirrus_hidden_dac_data
& 0xf));
1152 static int cirrus_get_bpp(VGACommonState
*s1
)
1154 CirrusVGAState
* s
= container_of(s1
, CirrusVGAState
, vga
);
1157 if ((s
->vga
.sr
[0x07] & 0x01) != 0) {
1159 switch (s
->vga
.sr
[0x07] & CIRRUS_SR7_BPP_MASK
) {
1160 case CIRRUS_SR7_BPP_8
:
1163 case CIRRUS_SR7_BPP_16_DOUBLEVCLK
:
1164 ret
= cirrus_get_bpp16_depth(s
);
1166 case CIRRUS_SR7_BPP_24
:
1169 case CIRRUS_SR7_BPP_16
:
1170 ret
= cirrus_get_bpp16_depth(s
);
1172 case CIRRUS_SR7_BPP_32
:
1177 printf("cirrus: unknown bpp - sr7=%x\n", s
->vga
.sr
[0x7]);
1190 static void cirrus_get_resolution(VGACommonState
*s
, int *pwidth
, int *pheight
)
1194 width
= (s
->cr
[0x01] + 1) * 8;
1195 height
= s
->cr
[0x12] |
1196 ((s
->cr
[0x07] & 0x02) << 7) |
1197 ((s
->cr
[0x07] & 0x40) << 3);
1198 height
= (height
+ 1);
1199 /* interlace support */
1200 if (s
->cr
[0x1a] & 0x01)
1201 height
= height
* 2;
1206 /***************************************
1210 ***************************************/
1212 static void cirrus_update_bank_ptr(CirrusVGAState
* s
, unsigned bank_index
)
1217 if ((s
->vga
.gr
[0x0b] & 0x01) != 0) /* dual bank */
1218 offset
= s
->vga
.gr
[0x09 + bank_index
];
1219 else /* single bank */
1220 offset
= s
->vga
.gr
[0x09];
1222 if ((s
->vga
.gr
[0x0b] & 0x20) != 0)
1227 if (s
->real_vram_size
<= offset
)
1230 limit
= s
->real_vram_size
- offset
;
1232 if (((s
->vga
.gr
[0x0b] & 0x01) == 0) && (bank_index
!= 0)) {
1233 if (limit
> 0x8000) {
1242 s
->cirrus_bank_base
[bank_index
] = offset
;
1243 s
->cirrus_bank_limit
[bank_index
] = limit
;
1245 s
->cirrus_bank_base
[bank_index
] = 0;
1246 s
->cirrus_bank_limit
[bank_index
] = 0;
1250 /***************************************
1252 * I/O access between 0x3c4-0x3c5
1254 ***************************************/
1256 static int cirrus_vga_read_sr(CirrusVGAState
* s
)
1258 switch (s
->vga
.sr_index
) {
1259 case 0x00: // Standard VGA
1260 case 0x01: // Standard VGA
1261 case 0x02: // Standard VGA
1262 case 0x03: // Standard VGA
1263 case 0x04: // Standard VGA
1264 return s
->vga
.sr
[s
->vga
.sr_index
];
1265 case 0x06: // Unlock Cirrus extensions
1266 return s
->vga
.sr
[s
->vga
.sr_index
];
1270 case 0x70: // Graphics Cursor X
1274 case 0xf0: // Graphics Cursor X
1275 return s
->vga
.sr
[0x10];
1279 case 0x71: // Graphics Cursor Y
1283 case 0xf1: // Graphics Cursor Y
1284 return s
->vga
.sr
[0x11];
1286 case 0x07: // Extended Sequencer Mode
1287 case 0x08: // EEPROM Control
1288 case 0x09: // Scratch Register 0
1289 case 0x0a: // Scratch Register 1
1290 case 0x0b: // VCLK 0
1291 case 0x0c: // VCLK 1
1292 case 0x0d: // VCLK 2
1293 case 0x0e: // VCLK 3
1294 case 0x0f: // DRAM Control
1295 case 0x12: // Graphics Cursor Attribute
1296 case 0x13: // Graphics Cursor Pattern Address
1297 case 0x14: // Scratch Register 2
1298 case 0x15: // Scratch Register 3
1299 case 0x16: // Performance Tuning Register
1300 case 0x17: // Configuration Readback and Extended Control
1301 case 0x18: // Signature Generator Control
1302 case 0x19: // Signal Generator Result
1303 case 0x1a: // Signal Generator Result
1304 case 0x1b: // VCLK 0 Denominator & Post
1305 case 0x1c: // VCLK 1 Denominator & Post
1306 case 0x1d: // VCLK 2 Denominator & Post
1307 case 0x1e: // VCLK 3 Denominator & Post
1308 case 0x1f: // BIOS Write Enable and MCLK select
1310 printf("cirrus: handled inport sr_index %02x\n", s
->vga
.sr_index
);
1312 return s
->vga
.sr
[s
->vga
.sr_index
];
1314 qemu_log_mask(LOG_GUEST_ERROR
,
1315 "cirrus: inport sr_index 0x%02x\n", s
->vga
.sr_index
);
1320 static void cirrus_vga_write_sr(CirrusVGAState
* s
, uint32_t val
)
1322 switch (s
->vga
.sr_index
) {
1323 case 0x00: // Standard VGA
1324 case 0x01: // Standard VGA
1325 case 0x02: // Standard VGA
1326 case 0x03: // Standard VGA
1327 case 0x04: // Standard VGA
1328 s
->vga
.sr
[s
->vga
.sr_index
] = val
& sr_mask
[s
->vga
.sr_index
];
1329 if (s
->vga
.sr_index
== 1)
1330 s
->vga
.update_retrace_info(&s
->vga
);
1332 case 0x06: // Unlock Cirrus extensions
1335 s
->vga
.sr
[s
->vga
.sr_index
] = 0x12;
1337 s
->vga
.sr
[s
->vga
.sr_index
] = 0x0f;
1343 case 0x70: // Graphics Cursor X
1347 case 0xf0: // Graphics Cursor X
1348 s
->vga
.sr
[0x10] = val
;
1349 s
->vga
.hw_cursor_x
= (val
<< 3) | (s
->vga
.sr_index
>> 5);
1354 case 0x71: // Graphics Cursor Y
1358 case 0xf1: // Graphics Cursor Y
1359 s
->vga
.sr
[0x11] = val
;
1360 s
->vga
.hw_cursor_y
= (val
<< 3) | (s
->vga
.sr_index
>> 5);
1362 case 0x07: // Extended Sequencer Mode
1363 cirrus_update_memory_access(s
);
1365 case 0x08: // EEPROM Control
1366 case 0x09: // Scratch Register 0
1367 case 0x0a: // Scratch Register 1
1368 case 0x0b: // VCLK 0
1369 case 0x0c: // VCLK 1
1370 case 0x0d: // VCLK 2
1371 case 0x0e: // VCLK 3
1372 case 0x0f: // DRAM Control
1373 case 0x13: // Graphics Cursor Pattern Address
1374 case 0x14: // Scratch Register 2
1375 case 0x15: // Scratch Register 3
1376 case 0x16: // Performance Tuning Register
1377 case 0x18: // Signature Generator Control
1378 case 0x19: // Signature Generator Result
1379 case 0x1a: // Signature Generator Result
1380 case 0x1b: // VCLK 0 Denominator & Post
1381 case 0x1c: // VCLK 1 Denominator & Post
1382 case 0x1d: // VCLK 2 Denominator & Post
1383 case 0x1e: // VCLK 3 Denominator & Post
1384 case 0x1f: // BIOS Write Enable and MCLK select
1385 s
->vga
.sr
[s
->vga
.sr_index
] = val
;
1387 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1388 s
->vga
.sr_index
, val
);
1391 case 0x12: // Graphics Cursor Attribute
1392 s
->vga
.sr
[0x12] = val
;
1393 s
->vga
.force_shadow
= !!(val
& CIRRUS_CURSOR_SHOW
);
1395 printf("cirrus: cursor ctl SR12=%02x (force shadow: %d)\n",
1396 val
, s
->vga
.force_shadow
);
1399 case 0x17: // Configuration Readback and Extended Control
1400 s
->vga
.sr
[s
->vga
.sr_index
] = (s
->vga
.sr
[s
->vga
.sr_index
] & 0x38)
1402 cirrus_update_memory_access(s
);
1405 qemu_log_mask(LOG_GUEST_ERROR
,
1406 "cirrus: outport sr_index 0x%02x, sr_value 0x%02x\n",
1407 s
->vga
.sr_index
, val
);
1412 /***************************************
1414 * I/O access at 0x3c6
1416 ***************************************/
1418 static int cirrus_read_hidden_dac(CirrusVGAState
* s
)
1420 if (++s
->cirrus_hidden_dac_lockindex
== 5) {
1421 s
->cirrus_hidden_dac_lockindex
= 0;
1422 return s
->cirrus_hidden_dac_data
;
1427 static void cirrus_write_hidden_dac(CirrusVGAState
* s
, int reg_value
)
1429 if (s
->cirrus_hidden_dac_lockindex
== 4) {
1430 s
->cirrus_hidden_dac_data
= reg_value
;
1431 #if defined(DEBUG_CIRRUS)
1432 printf("cirrus: outport hidden DAC, value %02x\n", reg_value
);
1435 s
->cirrus_hidden_dac_lockindex
= 0;
1438 /***************************************
1440 * I/O access at 0x3c9
1442 ***************************************/
1444 static int cirrus_vga_read_palette(CirrusVGAState
* s
)
1448 if ((s
->vga
.sr
[0x12] & CIRRUS_CURSOR_HIDDENPEL
)) {
1449 val
= s
->cirrus_hidden_palette
[(s
->vga
.dac_read_index
& 0x0f) * 3 +
1450 s
->vga
.dac_sub_index
];
1452 val
= s
->vga
.palette
[s
->vga
.dac_read_index
* 3 + s
->vga
.dac_sub_index
];
1454 if (++s
->vga
.dac_sub_index
== 3) {
1455 s
->vga
.dac_sub_index
= 0;
1456 s
->vga
.dac_read_index
++;
1461 static void cirrus_vga_write_palette(CirrusVGAState
* s
, int reg_value
)
1463 s
->vga
.dac_cache
[s
->vga
.dac_sub_index
] = reg_value
;
1464 if (++s
->vga
.dac_sub_index
== 3) {
1465 if ((s
->vga
.sr
[0x12] & CIRRUS_CURSOR_HIDDENPEL
)) {
1466 memcpy(&s
->cirrus_hidden_palette
[(s
->vga
.dac_write_index
& 0x0f) * 3],
1467 s
->vga
.dac_cache
, 3);
1469 memcpy(&s
->vga
.palette
[s
->vga
.dac_write_index
* 3], s
->vga
.dac_cache
, 3);
1471 /* XXX update cursor */
1472 s
->vga
.dac_sub_index
= 0;
1473 s
->vga
.dac_write_index
++;
1477 /***************************************
1479 * I/O access between 0x3ce-0x3cf
1481 ***************************************/
1483 static int cirrus_vga_read_gr(CirrusVGAState
* s
, unsigned reg_index
)
1485 switch (reg_index
) {
1486 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1487 return s
->cirrus_shadow_gr0
;
1488 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1489 return s
->cirrus_shadow_gr1
;
1490 case 0x02: // Standard VGA
1491 case 0x03: // Standard VGA
1492 case 0x04: // Standard VGA
1493 case 0x06: // Standard VGA
1494 case 0x07: // Standard VGA
1495 case 0x08: // Standard VGA
1496 return s
->vga
.gr
[s
->vga
.gr_index
];
1497 case 0x05: // Standard VGA, Cirrus extended mode
1502 if (reg_index
< 0x3a) {
1503 return s
->vga
.gr
[reg_index
];
1505 qemu_log_mask(LOG_GUEST_ERROR
,
1506 "cirrus: inport gr_index 0x%02x\n", reg_index
);
1512 cirrus_vga_write_gr(CirrusVGAState
* s
, unsigned reg_index
, int reg_value
)
1514 trace_vga_cirrus_write_gr(reg_index
, reg_value
);
1515 switch (reg_index
) {
1516 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1517 s
->vga
.gr
[reg_index
] = reg_value
& gr_mask
[reg_index
];
1518 s
->cirrus_shadow_gr0
= reg_value
;
1520 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1521 s
->vga
.gr
[reg_index
] = reg_value
& gr_mask
[reg_index
];
1522 s
->cirrus_shadow_gr1
= reg_value
;
1524 case 0x02: // Standard VGA
1525 case 0x03: // Standard VGA
1526 case 0x04: // Standard VGA
1527 case 0x06: // Standard VGA
1528 case 0x07: // Standard VGA
1529 case 0x08: // Standard VGA
1530 s
->vga
.gr
[reg_index
] = reg_value
& gr_mask
[reg_index
];
1532 case 0x05: // Standard VGA, Cirrus extended mode
1533 s
->vga
.gr
[reg_index
] = reg_value
& 0x7f;
1534 cirrus_update_memory_access(s
);
1536 case 0x09: // bank offset #0
1537 case 0x0A: // bank offset #1
1538 s
->vga
.gr
[reg_index
] = reg_value
;
1539 cirrus_update_bank_ptr(s
, 0);
1540 cirrus_update_bank_ptr(s
, 1);
1541 cirrus_update_memory_access(s
);
1544 s
->vga
.gr
[reg_index
] = reg_value
;
1545 cirrus_update_bank_ptr(s
, 0);
1546 cirrus_update_bank_ptr(s
, 1);
1547 cirrus_update_memory_access(s
);
1549 case 0x10: // BGCOLOR 0x0000ff00
1550 case 0x11: // FGCOLOR 0x0000ff00
1551 case 0x12: // BGCOLOR 0x00ff0000
1552 case 0x13: // FGCOLOR 0x00ff0000
1553 case 0x14: // BGCOLOR 0xff000000
1554 case 0x15: // FGCOLOR 0xff000000
1555 case 0x20: // BLT WIDTH 0x0000ff
1556 case 0x22: // BLT HEIGHT 0x0000ff
1557 case 0x24: // BLT DEST PITCH 0x0000ff
1558 case 0x26: // BLT SRC PITCH 0x0000ff
1559 case 0x28: // BLT DEST ADDR 0x0000ff
1560 case 0x29: // BLT DEST ADDR 0x00ff00
1561 case 0x2c: // BLT SRC ADDR 0x0000ff
1562 case 0x2d: // BLT SRC ADDR 0x00ff00
1563 case 0x2f: // BLT WRITEMASK
1564 case 0x30: // BLT MODE
1565 case 0x32: // RASTER OP
1566 case 0x33: // BLT MODEEXT
1567 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1568 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1569 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1570 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1571 s
->vga
.gr
[reg_index
] = reg_value
;
1573 case 0x21: // BLT WIDTH 0x001f00
1574 case 0x23: // BLT HEIGHT 0x001f00
1575 case 0x25: // BLT DEST PITCH 0x001f00
1576 case 0x27: // BLT SRC PITCH 0x001f00
1577 s
->vga
.gr
[reg_index
] = reg_value
& 0x1f;
1579 case 0x2a: // BLT DEST ADDR 0x3f0000
1580 s
->vga
.gr
[reg_index
] = reg_value
& 0x3f;
1581 /* if auto start mode, starts bit blt now */
1582 if (s
->vga
.gr
[0x31] & CIRRUS_BLT_AUTOSTART
) {
1583 cirrus_bitblt_start(s
);
1586 case 0x2e: // BLT SRC ADDR 0x3f0000
1587 s
->vga
.gr
[reg_index
] = reg_value
& 0x3f;
1589 case 0x31: // BLT STATUS/START
1590 cirrus_write_bitblt(s
, reg_value
);
1593 qemu_log_mask(LOG_GUEST_ERROR
,
1594 "cirrus: outport gr_index 0x%02x, gr_value 0x%02x\n",
1595 reg_index
, reg_value
);
1600 /***************************************
1602 * I/O access between 0x3d4-0x3d5
1604 ***************************************/
1606 static int cirrus_vga_read_cr(CirrusVGAState
* s
, unsigned reg_index
)
1608 switch (reg_index
) {
1609 case 0x00: // Standard VGA
1610 case 0x01: // Standard VGA
1611 case 0x02: // Standard VGA
1612 case 0x03: // Standard VGA
1613 case 0x04: // Standard VGA
1614 case 0x05: // Standard VGA
1615 case 0x06: // Standard VGA
1616 case 0x07: // Standard VGA
1617 case 0x08: // Standard VGA
1618 case 0x09: // Standard VGA
1619 case 0x0a: // Standard VGA
1620 case 0x0b: // Standard VGA
1621 case 0x0c: // Standard VGA
1622 case 0x0d: // Standard VGA
1623 case 0x0e: // Standard VGA
1624 case 0x0f: // Standard VGA
1625 case 0x10: // Standard VGA
1626 case 0x11: // Standard VGA
1627 case 0x12: // Standard VGA
1628 case 0x13: // Standard VGA
1629 case 0x14: // Standard VGA
1630 case 0x15: // Standard VGA
1631 case 0x16: // Standard VGA
1632 case 0x17: // Standard VGA
1633 case 0x18: // Standard VGA
1634 return s
->vga
.cr
[s
->vga
.cr_index
];
1635 case 0x24: // Attribute Controller Toggle Readback (R)
1636 return (s
->vga
.ar_flip_flop
<< 7);
1637 case 0x19: // Interlace End
1638 case 0x1a: // Miscellaneous Control
1639 case 0x1b: // Extended Display Control
1640 case 0x1c: // Sync Adjust and Genlock
1641 case 0x1d: // Overlay Extended Control
1642 case 0x22: // Graphics Data Latches Readback (R)
1643 case 0x25: // Part Status
1644 case 0x27: // Part ID (R)
1645 return s
->vga
.cr
[s
->vga
.cr_index
];
1646 case 0x26: // Attribute Controller Index Readback (R)
1647 return s
->vga
.ar_index
& 0x3f;
1649 qemu_log_mask(LOG_GUEST_ERROR
,
1650 "cirrus: inport cr_index 0x%02x\n", reg_index
);
1655 static void cirrus_vga_write_cr(CirrusVGAState
* s
, int reg_value
)
1657 switch (s
->vga
.cr_index
) {
1658 case 0x00: // Standard VGA
1659 case 0x01: // Standard VGA
1660 case 0x02: // Standard VGA
1661 case 0x03: // Standard VGA
1662 case 0x04: // Standard VGA
1663 case 0x05: // Standard VGA
1664 case 0x06: // Standard VGA
1665 case 0x07: // Standard VGA
1666 case 0x08: // Standard VGA
1667 case 0x09: // Standard VGA
1668 case 0x0a: // Standard VGA
1669 case 0x0b: // Standard VGA
1670 case 0x0c: // Standard VGA
1671 case 0x0d: // Standard VGA
1672 case 0x0e: // Standard VGA
1673 case 0x0f: // Standard VGA
1674 case 0x10: // Standard VGA
1675 case 0x11: // Standard VGA
1676 case 0x12: // Standard VGA
1677 case 0x13: // Standard VGA
1678 case 0x14: // Standard VGA
1679 case 0x15: // Standard VGA
1680 case 0x16: // Standard VGA
1681 case 0x17: // Standard VGA
1682 case 0x18: // Standard VGA
1683 /* handle CR0-7 protection */
1684 if ((s
->vga
.cr
[0x11] & 0x80) && s
->vga
.cr_index
<= 7) {
1685 /* can always write bit 4 of CR7 */
1686 if (s
->vga
.cr_index
== 7)
1687 s
->vga
.cr
[7] = (s
->vga
.cr
[7] & ~0x10) | (reg_value
& 0x10);
1690 s
->vga
.cr
[s
->vga
.cr_index
] = reg_value
;
1691 switch(s
->vga
.cr_index
) {
1699 s
->vga
.update_retrace_info(&s
->vga
);
1703 case 0x19: // Interlace End
1704 case 0x1a: // Miscellaneous Control
1705 case 0x1b: // Extended Display Control
1706 case 0x1c: // Sync Adjust and Genlock
1707 case 0x1d: // Overlay Extended Control
1708 s
->vga
.cr
[s
->vga
.cr_index
] = reg_value
;
1710 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1711 s
->vga
.cr_index
, reg_value
);
1714 case 0x22: // Graphics Data Latches Readback (R)
1715 case 0x24: // Attribute Controller Toggle Readback (R)
1716 case 0x26: // Attribute Controller Index Readback (R)
1717 case 0x27: // Part ID (R)
1719 case 0x25: // Part Status
1721 qemu_log_mask(LOG_GUEST_ERROR
,
1722 "cirrus: outport cr_index 0x%02x, cr_value 0x%02x\n",
1723 s
->vga
.cr_index
, reg_value
);
1728 /***************************************
1730 * memory-mapped I/O (bitblt)
1732 ***************************************/
1734 static uint8_t cirrus_mmio_blt_read(CirrusVGAState
* s
, unsigned address
)
1739 case (CIRRUS_MMIO_BLTBGCOLOR
+ 0):
1740 value
= cirrus_vga_read_gr(s
, 0x00);
1742 case (CIRRUS_MMIO_BLTBGCOLOR
+ 1):
1743 value
= cirrus_vga_read_gr(s
, 0x10);
1745 case (CIRRUS_MMIO_BLTBGCOLOR
+ 2):
1746 value
= cirrus_vga_read_gr(s
, 0x12);
1748 case (CIRRUS_MMIO_BLTBGCOLOR
+ 3):
1749 value
= cirrus_vga_read_gr(s
, 0x14);
1751 case (CIRRUS_MMIO_BLTFGCOLOR
+ 0):
1752 value
= cirrus_vga_read_gr(s
, 0x01);
1754 case (CIRRUS_MMIO_BLTFGCOLOR
+ 1):
1755 value
= cirrus_vga_read_gr(s
, 0x11);
1757 case (CIRRUS_MMIO_BLTFGCOLOR
+ 2):
1758 value
= cirrus_vga_read_gr(s
, 0x13);
1760 case (CIRRUS_MMIO_BLTFGCOLOR
+ 3):
1761 value
= cirrus_vga_read_gr(s
, 0x15);
1763 case (CIRRUS_MMIO_BLTWIDTH
+ 0):
1764 value
= cirrus_vga_read_gr(s
, 0x20);
1766 case (CIRRUS_MMIO_BLTWIDTH
+ 1):
1767 value
= cirrus_vga_read_gr(s
, 0x21);
1769 case (CIRRUS_MMIO_BLTHEIGHT
+ 0):
1770 value
= cirrus_vga_read_gr(s
, 0x22);
1772 case (CIRRUS_MMIO_BLTHEIGHT
+ 1):
1773 value
= cirrus_vga_read_gr(s
, 0x23);
1775 case (CIRRUS_MMIO_BLTDESTPITCH
+ 0):
1776 value
= cirrus_vga_read_gr(s
, 0x24);
1778 case (CIRRUS_MMIO_BLTDESTPITCH
+ 1):
1779 value
= cirrus_vga_read_gr(s
, 0x25);
1781 case (CIRRUS_MMIO_BLTSRCPITCH
+ 0):
1782 value
= cirrus_vga_read_gr(s
, 0x26);
1784 case (CIRRUS_MMIO_BLTSRCPITCH
+ 1):
1785 value
= cirrus_vga_read_gr(s
, 0x27);
1787 case (CIRRUS_MMIO_BLTDESTADDR
+ 0):
1788 value
= cirrus_vga_read_gr(s
, 0x28);
1790 case (CIRRUS_MMIO_BLTDESTADDR
+ 1):
1791 value
= cirrus_vga_read_gr(s
, 0x29);
1793 case (CIRRUS_MMIO_BLTDESTADDR
+ 2):
1794 value
= cirrus_vga_read_gr(s
, 0x2a);
1796 case (CIRRUS_MMIO_BLTSRCADDR
+ 0):
1797 value
= cirrus_vga_read_gr(s
, 0x2c);
1799 case (CIRRUS_MMIO_BLTSRCADDR
+ 1):
1800 value
= cirrus_vga_read_gr(s
, 0x2d);
1802 case (CIRRUS_MMIO_BLTSRCADDR
+ 2):
1803 value
= cirrus_vga_read_gr(s
, 0x2e);
1805 case CIRRUS_MMIO_BLTWRITEMASK
:
1806 value
= cirrus_vga_read_gr(s
, 0x2f);
1808 case CIRRUS_MMIO_BLTMODE
:
1809 value
= cirrus_vga_read_gr(s
, 0x30);
1811 case CIRRUS_MMIO_BLTROP
:
1812 value
= cirrus_vga_read_gr(s
, 0x32);
1814 case CIRRUS_MMIO_BLTMODEEXT
:
1815 value
= cirrus_vga_read_gr(s
, 0x33);
1817 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 0):
1818 value
= cirrus_vga_read_gr(s
, 0x34);
1820 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 1):
1821 value
= cirrus_vga_read_gr(s
, 0x35);
1823 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 0):
1824 value
= cirrus_vga_read_gr(s
, 0x38);
1826 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 1):
1827 value
= cirrus_vga_read_gr(s
, 0x39);
1829 case CIRRUS_MMIO_BLTSTATUS
:
1830 value
= cirrus_vga_read_gr(s
, 0x31);
1833 qemu_log_mask(LOG_GUEST_ERROR
,
1834 "cirrus: mmio read - address 0x%04x\n", address
);
1838 trace_vga_cirrus_write_blt(address
, value
);
1839 return (uint8_t) value
;
1842 static void cirrus_mmio_blt_write(CirrusVGAState
* s
, unsigned address
,
1845 trace_vga_cirrus_write_blt(address
, value
);
1847 case (CIRRUS_MMIO_BLTBGCOLOR
+ 0):
1848 cirrus_vga_write_gr(s
, 0x00, value
);
1850 case (CIRRUS_MMIO_BLTBGCOLOR
+ 1):
1851 cirrus_vga_write_gr(s
, 0x10, value
);
1853 case (CIRRUS_MMIO_BLTBGCOLOR
+ 2):
1854 cirrus_vga_write_gr(s
, 0x12, value
);
1856 case (CIRRUS_MMIO_BLTBGCOLOR
+ 3):
1857 cirrus_vga_write_gr(s
, 0x14, value
);
1859 case (CIRRUS_MMIO_BLTFGCOLOR
+ 0):
1860 cirrus_vga_write_gr(s
, 0x01, value
);
1862 case (CIRRUS_MMIO_BLTFGCOLOR
+ 1):
1863 cirrus_vga_write_gr(s
, 0x11, value
);
1865 case (CIRRUS_MMIO_BLTFGCOLOR
+ 2):
1866 cirrus_vga_write_gr(s
, 0x13, value
);
1868 case (CIRRUS_MMIO_BLTFGCOLOR
+ 3):
1869 cirrus_vga_write_gr(s
, 0x15, value
);
1871 case (CIRRUS_MMIO_BLTWIDTH
+ 0):
1872 cirrus_vga_write_gr(s
, 0x20, value
);
1874 case (CIRRUS_MMIO_BLTWIDTH
+ 1):
1875 cirrus_vga_write_gr(s
, 0x21, value
);
1877 case (CIRRUS_MMIO_BLTHEIGHT
+ 0):
1878 cirrus_vga_write_gr(s
, 0x22, value
);
1880 case (CIRRUS_MMIO_BLTHEIGHT
+ 1):
1881 cirrus_vga_write_gr(s
, 0x23, value
);
1883 case (CIRRUS_MMIO_BLTDESTPITCH
+ 0):
1884 cirrus_vga_write_gr(s
, 0x24, value
);
1886 case (CIRRUS_MMIO_BLTDESTPITCH
+ 1):
1887 cirrus_vga_write_gr(s
, 0x25, value
);
1889 case (CIRRUS_MMIO_BLTSRCPITCH
+ 0):
1890 cirrus_vga_write_gr(s
, 0x26, value
);
1892 case (CIRRUS_MMIO_BLTSRCPITCH
+ 1):
1893 cirrus_vga_write_gr(s
, 0x27, value
);
1895 case (CIRRUS_MMIO_BLTDESTADDR
+ 0):
1896 cirrus_vga_write_gr(s
, 0x28, value
);
1898 case (CIRRUS_MMIO_BLTDESTADDR
+ 1):
1899 cirrus_vga_write_gr(s
, 0x29, value
);
1901 case (CIRRUS_MMIO_BLTDESTADDR
+ 2):
1902 cirrus_vga_write_gr(s
, 0x2a, value
);
1904 case (CIRRUS_MMIO_BLTDESTADDR
+ 3):
1907 case (CIRRUS_MMIO_BLTSRCADDR
+ 0):
1908 cirrus_vga_write_gr(s
, 0x2c, value
);
1910 case (CIRRUS_MMIO_BLTSRCADDR
+ 1):
1911 cirrus_vga_write_gr(s
, 0x2d, value
);
1913 case (CIRRUS_MMIO_BLTSRCADDR
+ 2):
1914 cirrus_vga_write_gr(s
, 0x2e, value
);
1916 case CIRRUS_MMIO_BLTWRITEMASK
:
1917 cirrus_vga_write_gr(s
, 0x2f, value
);
1919 case CIRRUS_MMIO_BLTMODE
:
1920 cirrus_vga_write_gr(s
, 0x30, value
);
1922 case CIRRUS_MMIO_BLTROP
:
1923 cirrus_vga_write_gr(s
, 0x32, value
);
1925 case CIRRUS_MMIO_BLTMODEEXT
:
1926 cirrus_vga_write_gr(s
, 0x33, value
);
1928 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 0):
1929 cirrus_vga_write_gr(s
, 0x34, value
);
1931 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 1):
1932 cirrus_vga_write_gr(s
, 0x35, value
);
1934 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 0):
1935 cirrus_vga_write_gr(s
, 0x38, value
);
1937 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 1):
1938 cirrus_vga_write_gr(s
, 0x39, value
);
1940 case CIRRUS_MMIO_BLTSTATUS
:
1941 cirrus_vga_write_gr(s
, 0x31, value
);
1944 qemu_log_mask(LOG_GUEST_ERROR
,
1945 "cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1951 /***************************************
1955 ***************************************/
1957 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState
* s
,
1963 unsigned val
= mem_value
;
1966 for (x
= 0; x
< 8; x
++) {
1967 dst
= s
->vga
.vram_ptr
+ ((offset
+ x
) & s
->cirrus_addr_mask
);
1969 *dst
= s
->cirrus_shadow_gr1
;
1970 } else if (mode
== 5) {
1971 *dst
= s
->cirrus_shadow_gr0
;
1975 memory_region_set_dirty(&s
->vga
.vram
, offset
, 8);
1978 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState
* s
,
1984 unsigned val
= mem_value
;
1987 for (x
= 0; x
< 8; x
++) {
1988 dst
= s
->vga
.vram_ptr
+ ((offset
+ 2 * x
) & s
->cirrus_addr_mask
& ~1);
1990 *dst
= s
->cirrus_shadow_gr1
;
1991 *(dst
+ 1) = s
->vga
.gr
[0x11];
1992 } else if (mode
== 5) {
1993 *dst
= s
->cirrus_shadow_gr0
;
1994 *(dst
+ 1) = s
->vga
.gr
[0x10];
1998 memory_region_set_dirty(&s
->vga
.vram
, offset
, 16);
2001 /***************************************
2003 * memory access between 0xa0000-0xbffff
2005 ***************************************/
2007 static uint64_t cirrus_vga_mem_read(void *opaque
,
2011 CirrusVGAState
*s
= opaque
;
2012 unsigned bank_index
;
2013 unsigned bank_offset
;
2016 if ((s
->vga
.sr
[0x07] & 0x01) == 0) {
2017 return vga_mem_readb(&s
->vga
, addr
);
2020 if (addr
< 0x10000) {
2021 /* XXX handle bitblt */
2023 bank_index
= addr
>> 15;
2024 bank_offset
= addr
& 0x7fff;
2025 if (bank_offset
< s
->cirrus_bank_limit
[bank_index
]) {
2026 bank_offset
+= s
->cirrus_bank_base
[bank_index
];
2027 if ((s
->vga
.gr
[0x0B] & 0x14) == 0x14) {
2029 } else if (s
->vga
.gr
[0x0B] & 0x02) {
2032 bank_offset
&= s
->cirrus_addr_mask
;
2033 val
= *(s
->vga
.vram_ptr
+ bank_offset
);
2036 } else if (addr
>= 0x18000 && addr
< 0x18100) {
2037 /* memory-mapped I/O */
2039 if ((s
->vga
.sr
[0x17] & 0x44) == 0x04) {
2040 val
= cirrus_mmio_blt_read(s
, addr
& 0xff);
2044 qemu_log_mask(LOG_GUEST_ERROR
,
2045 "cirrus: mem_readb 0x" TARGET_FMT_plx
"\n", addr
);
2050 static void cirrus_vga_mem_write(void *opaque
,
2055 CirrusVGAState
*s
= opaque
;
2056 unsigned bank_index
;
2057 unsigned bank_offset
;
2060 if ((s
->vga
.sr
[0x07] & 0x01) == 0) {
2061 vga_mem_writeb(&s
->vga
, addr
, mem_value
);
2065 if (addr
< 0x10000) {
2066 if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2068 *s
->cirrus_srcptr
++ = (uint8_t) mem_value
;
2069 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
2070 cirrus_bitblt_cputovideo_next(s
);
2074 bank_index
= addr
>> 15;
2075 bank_offset
= addr
& 0x7fff;
2076 if (bank_offset
< s
->cirrus_bank_limit
[bank_index
]) {
2077 bank_offset
+= s
->cirrus_bank_base
[bank_index
];
2078 if ((s
->vga
.gr
[0x0B] & 0x14) == 0x14) {
2080 } else if (s
->vga
.gr
[0x0B] & 0x02) {
2083 bank_offset
&= s
->cirrus_addr_mask
;
2084 mode
= s
->vga
.gr
[0x05] & 0x7;
2085 if (mode
< 4 || mode
> 5 || ((s
->vga
.gr
[0x0B] & 0x4) == 0)) {
2086 *(s
->vga
.vram_ptr
+ bank_offset
) = mem_value
;
2087 memory_region_set_dirty(&s
->vga
.vram
, bank_offset
,
2090 if ((s
->vga
.gr
[0x0B] & 0x14) != 0x14) {
2091 cirrus_mem_writeb_mode4and5_8bpp(s
, mode
,
2095 cirrus_mem_writeb_mode4and5_16bpp(s
, mode
,
2102 } else if (addr
>= 0x18000 && addr
< 0x18100) {
2103 /* memory-mapped I/O */
2104 if ((s
->vga
.sr
[0x17] & 0x44) == 0x04) {
2105 cirrus_mmio_blt_write(s
, addr
& 0xff, mem_value
);
2108 qemu_log_mask(LOG_GUEST_ERROR
,
2109 "cirrus: mem_writeb 0x" TARGET_FMT_plx
" "
2110 "value 0x%02" PRIu64
"\n", addr
, mem_value
);
2114 static const MemoryRegionOps cirrus_vga_mem_ops
= {
2115 .read
= cirrus_vga_mem_read
,
2116 .write
= cirrus_vga_mem_write
,
2117 .endianness
= DEVICE_LITTLE_ENDIAN
,
2119 .min_access_size
= 1,
2120 .max_access_size
= 1,
2124 /***************************************
2128 ***************************************/
2130 static inline void invalidate_cursor1(CirrusVGAState
*s
)
2132 if (s
->last_hw_cursor_size
) {
2133 vga_invalidate_scanlines(&s
->vga
,
2134 s
->last_hw_cursor_y
+ s
->last_hw_cursor_y_start
,
2135 s
->last_hw_cursor_y
+ s
->last_hw_cursor_y_end
);
2139 static inline void cirrus_cursor_compute_yrange(CirrusVGAState
*s
)
2143 int y
, y_min
, y_max
;
2145 src
= s
->vga
.vram_ptr
+ s
->real_vram_size
- 16 * KiB
;
2146 if (s
->vga
.sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2147 src
+= (s
->vga
.sr
[0x13] & 0x3c) * 256;
2150 for(y
= 0; y
< 64; y
++) {
2151 content
= ((uint32_t *)src
)[0] |
2152 ((uint32_t *)src
)[1] |
2153 ((uint32_t *)src
)[2] |
2154 ((uint32_t *)src
)[3];
2164 src
+= (s
->vga
.sr
[0x13] & 0x3f) * 256;
2167 for(y
= 0; y
< 32; y
++) {
2168 content
= ((uint32_t *)src
)[0] |
2169 ((uint32_t *)(src
+ 128))[0];
2179 if (y_min
> y_max
) {
2180 s
->last_hw_cursor_y_start
= 0;
2181 s
->last_hw_cursor_y_end
= 0;
2183 s
->last_hw_cursor_y_start
= y_min
;
2184 s
->last_hw_cursor_y_end
= y_max
+ 1;
2188 /* NOTE: we do not currently handle the cursor bitmap change, so we
2189 update the cursor only if it moves. */
2190 static void cirrus_cursor_invalidate(VGACommonState
*s1
)
2192 CirrusVGAState
*s
= container_of(s1
, CirrusVGAState
, vga
);
2195 if (!(s
->vga
.sr
[0x12] & CIRRUS_CURSOR_SHOW
)) {
2198 if (s
->vga
.sr
[0x12] & CIRRUS_CURSOR_LARGE
)
2203 /* invalidate last cursor and new cursor if any change */
2204 if (s
->last_hw_cursor_size
!= size
||
2205 s
->last_hw_cursor_x
!= s
->vga
.hw_cursor_x
||
2206 s
->last_hw_cursor_y
!= s
->vga
.hw_cursor_y
) {
2208 invalidate_cursor1(s
);
2210 s
->last_hw_cursor_size
= size
;
2211 s
->last_hw_cursor_x
= s
->vga
.hw_cursor_x
;
2212 s
->last_hw_cursor_y
= s
->vga
.hw_cursor_y
;
2213 /* compute the real cursor min and max y */
2214 cirrus_cursor_compute_yrange(s
);
2215 invalidate_cursor1(s
);
2219 static void vga_draw_cursor_line(uint8_t *d1
,
2220 const uint8_t *src1
,
2222 unsigned int color0
,
2223 unsigned int color1
,
2224 unsigned int color_xor
)
2226 const uint8_t *plane0
, *plane1
;
2232 plane1
= src1
+ poffset
;
2233 for (x
= 0; x
< w
; x
++) {
2234 b0
= (plane0
[x
>> 3] >> (7 - (x
& 7))) & 1;
2235 b1
= (plane1
[x
>> 3] >> (7 - (x
& 7))) & 1;
2236 switch (b0
| (b1
<< 1)) {
2240 ((uint32_t *)d
)[0] ^= color_xor
;
2243 ((uint32_t *)d
)[0] = color0
;
2246 ((uint32_t *)d
)[0] = color1
;
2253 static void cirrus_cursor_draw_line(VGACommonState
*s1
, uint8_t *d1
, int scr_y
)
2255 CirrusVGAState
*s
= container_of(s1
, CirrusVGAState
, vga
);
2256 int w
, h
, x1
, x2
, poffset
;
2257 unsigned int color0
, color1
;
2258 const uint8_t *palette
, *src
;
2261 if (!(s
->vga
.sr
[0x12] & CIRRUS_CURSOR_SHOW
))
2263 /* fast test to see if the cursor intersects with the scan line */
2264 if (s
->vga
.sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2269 if (scr_y
< s
->vga
.hw_cursor_y
||
2270 scr_y
>= (s
->vga
.hw_cursor_y
+ h
)) {
2274 src
= s
->vga
.vram_ptr
+ s
->real_vram_size
- 16 * KiB
;
2275 if (s
->vga
.sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2276 src
+= (s
->vga
.sr
[0x13] & 0x3c) * 256;
2277 src
+= (scr_y
- s
->vga
.hw_cursor_y
) * 16;
2279 content
= ((uint32_t *)src
)[0] |
2280 ((uint32_t *)src
)[1] |
2281 ((uint32_t *)src
)[2] |
2282 ((uint32_t *)src
)[3];
2284 src
+= (s
->vga
.sr
[0x13] & 0x3f) * 256;
2285 src
+= (scr_y
- s
->vga
.hw_cursor_y
) * 4;
2289 content
= ((uint32_t *)src
)[0] |
2290 ((uint32_t *)(src
+ 128))[0];
2292 /* if nothing to draw, no need to continue */
2297 x1
= s
->vga
.hw_cursor_x
;
2298 if (x1
>= s
->vga
.last_scr_width
)
2300 x2
= s
->vga
.hw_cursor_x
+ w
;
2301 if (x2
> s
->vga
.last_scr_width
)
2302 x2
= s
->vga
.last_scr_width
;
2304 palette
= s
->cirrus_hidden_palette
;
2305 color0
= rgb_to_pixel32(c6_to_8(palette
[0x0 * 3]),
2306 c6_to_8(palette
[0x0 * 3 + 1]),
2307 c6_to_8(palette
[0x0 * 3 + 2]));
2308 color1
= rgb_to_pixel32(c6_to_8(palette
[0xf * 3]),
2309 c6_to_8(palette
[0xf * 3 + 1]),
2310 c6_to_8(palette
[0xf * 3 + 2]));
2312 vga_draw_cursor_line(d1
, src
, poffset
, w
, color0
, color1
, 0xffffff);
2315 /***************************************
2319 ***************************************/
2321 static uint64_t cirrus_linear_read(void *opaque
, hwaddr addr
,
2324 CirrusVGAState
*s
= opaque
;
2327 addr
&= s
->cirrus_addr_mask
;
2329 if (((s
->vga
.sr
[0x17] & 0x44) == 0x44) &&
2330 ((addr
& s
->linear_mmio_mask
) == s
->linear_mmio_mask
)) {
2331 /* memory-mapped I/O */
2332 ret
= cirrus_mmio_blt_read(s
, addr
& 0xff);
2334 /* XXX handle bitblt */
2338 if ((s
->vga
.gr
[0x0B] & 0x14) == 0x14) {
2340 } else if (s
->vga
.gr
[0x0B] & 0x02) {
2343 addr
&= s
->cirrus_addr_mask
;
2344 ret
= *(s
->vga
.vram_ptr
+ addr
);
2350 static void cirrus_linear_write(void *opaque
, hwaddr addr
,
2351 uint64_t val
, unsigned size
)
2353 CirrusVGAState
*s
= opaque
;
2356 addr
&= s
->cirrus_addr_mask
;
2358 if (((s
->vga
.sr
[0x17] & 0x44) == 0x44) &&
2359 ((addr
& s
->linear_mmio_mask
) == s
->linear_mmio_mask
)) {
2360 /* memory-mapped I/O */
2361 cirrus_mmio_blt_write(s
, addr
& 0xff, val
);
2362 } else if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2364 *s
->cirrus_srcptr
++ = (uint8_t) val
;
2365 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
2366 cirrus_bitblt_cputovideo_next(s
);
2370 if ((s
->vga
.gr
[0x0B] & 0x14) == 0x14) {
2372 } else if (s
->vga
.gr
[0x0B] & 0x02) {
2375 addr
&= s
->cirrus_addr_mask
;
2377 mode
= s
->vga
.gr
[0x05] & 0x7;
2378 if (mode
< 4 || mode
> 5 || ((s
->vga
.gr
[0x0B] & 0x4) == 0)) {
2379 *(s
->vga
.vram_ptr
+ addr
) = (uint8_t) val
;
2380 memory_region_set_dirty(&s
->vga
.vram
, addr
, 1);
2382 if ((s
->vga
.gr
[0x0B] & 0x14) != 0x14) {
2383 cirrus_mem_writeb_mode4and5_8bpp(s
, mode
, addr
, val
);
2385 cirrus_mem_writeb_mode4and5_16bpp(s
, mode
, addr
, val
);
2391 /***************************************
2393 * system to screen memory access
2395 ***************************************/
2398 static uint64_t cirrus_linear_bitblt_read(void *opaque
,
2402 CirrusVGAState
*s
= opaque
;
2404 /* XXX handle bitblt */
2406 qemu_log_mask(LOG_UNIMP
,
2407 "cirrus: linear bitblt is not implemented\n");
2412 static void cirrus_linear_bitblt_write(void *opaque
,
2417 CirrusVGAState
*s
= opaque
;
2419 if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2421 *s
->cirrus_srcptr
++ = (uint8_t) val
;
2422 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
2423 cirrus_bitblt_cputovideo_next(s
);
2428 static const MemoryRegionOps cirrus_linear_bitblt_io_ops
= {
2429 .read
= cirrus_linear_bitblt_read
,
2430 .write
= cirrus_linear_bitblt_write
,
2431 .endianness
= DEVICE_LITTLE_ENDIAN
,
2433 .min_access_size
= 1,
2434 .max_access_size
= 1,
2438 static void map_linear_vram_bank(CirrusVGAState
*s
, unsigned bank
)
2440 MemoryRegion
*mr
= &s
->cirrus_bank
[bank
];
2441 bool enabled
= !(s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
)
2442 && !((s
->vga
.sr
[0x07] & 0x01) == 0)
2443 && !((s
->vga
.gr
[0x0B] & 0x14) == 0x14)
2444 && !(s
->vga
.gr
[0x0B] & 0x02);
2446 memory_region_set_enabled(mr
, enabled
);
2447 memory_region_set_alias_offset(mr
, s
->cirrus_bank_base
[bank
]);
2450 static void map_linear_vram(CirrusVGAState
*s
)
2452 if (s
->bustype
== CIRRUS_BUSTYPE_PCI
&& !s
->linear_vram
) {
2453 s
->linear_vram
= true;
2454 memory_region_add_subregion_overlap(&s
->pci_bar
, 0, &s
->vga
.vram
, 1);
2456 map_linear_vram_bank(s
, 0);
2457 map_linear_vram_bank(s
, 1);
2460 static void unmap_linear_vram(CirrusVGAState
*s
)
2462 if (s
->bustype
== CIRRUS_BUSTYPE_PCI
&& s
->linear_vram
) {
2463 s
->linear_vram
= false;
2464 memory_region_del_subregion(&s
->pci_bar
, &s
->vga
.vram
);
2466 memory_region_set_enabled(&s
->cirrus_bank
[0], false);
2467 memory_region_set_enabled(&s
->cirrus_bank
[1], false);
2470 /* Compute the memory access functions */
2471 static void cirrus_update_memory_access(CirrusVGAState
*s
)
2475 memory_region_transaction_begin();
2476 if ((s
->vga
.sr
[0x17] & 0x44) == 0x44) {
2478 } else if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2481 if ((s
->vga
.gr
[0x0B] & 0x14) == 0x14) {
2483 } else if (s
->vga
.gr
[0x0B] & 0x02) {
2487 mode
= s
->vga
.gr
[0x05] & 0x7;
2488 if (mode
< 4 || mode
> 5 || ((s
->vga
.gr
[0x0B] & 0x4) == 0)) {
2492 unmap_linear_vram(s
);
2495 memory_region_transaction_commit();
2501 static uint64_t cirrus_vga_ioport_read(void *opaque
, hwaddr addr
,
2504 CirrusVGAState
*c
= opaque
;
2505 VGACommonState
*s
= &c
->vga
;
2510 if (vga_ioport_invalid(s
, addr
)) {
2515 if (s
->ar_flip_flop
== 0) {
2522 index
= s
->ar_index
& 0x1f;
2535 val
= cirrus_vga_read_sr(c
);
2537 #ifdef DEBUG_VGA_REG
2538 printf("vga: read SR%x = 0x%02x\n", s
->sr_index
, val
);
2542 val
= cirrus_read_hidden_dac(c
);
2548 val
= s
->dac_write_index
;
2549 c
->cirrus_hidden_dac_lockindex
= 0;
2552 val
= cirrus_vga_read_palette(c
);
2564 val
= cirrus_vga_read_gr(c
, s
->gr_index
);
2565 #ifdef DEBUG_VGA_REG
2566 printf("vga: read GR%x = 0x%02x\n", s
->gr_index
, val
);
2575 val
= cirrus_vga_read_cr(c
, s
->cr_index
);
2576 #ifdef DEBUG_VGA_REG
2577 printf("vga: read CR%x = 0x%02x\n", s
->cr_index
, val
);
2582 /* just toggle to fool polling */
2583 val
= s
->st01
= s
->retrace(s
);
2584 s
->ar_flip_flop
= 0;
2591 trace_vga_cirrus_read_io(addr
, val
);
2595 static void cirrus_vga_ioport_write(void *opaque
, hwaddr addr
, uint64_t val
,
2598 CirrusVGAState
*c
= opaque
;
2599 VGACommonState
*s
= &c
->vga
;
2604 /* check port range access depending on color/monochrome mode */
2605 if (vga_ioport_invalid(s
, addr
)) {
2608 trace_vga_cirrus_write_io(addr
, val
);
2612 if (s
->ar_flip_flop
== 0) {
2616 index
= s
->ar_index
& 0x1f;
2619 s
->ar
[index
] = val
& 0x3f;
2622 s
->ar
[index
] = val
& ~0x10;
2628 s
->ar
[index
] = val
& ~0xc0;
2631 s
->ar
[index
] = val
& ~0xf0;
2634 s
->ar
[index
] = val
& ~0xf0;
2640 s
->ar_flip_flop
^= 1;
2643 s
->msr
= val
& ~0x10;
2644 s
->update_retrace_info(s
);
2650 #ifdef DEBUG_VGA_REG
2651 printf("vga: write SR%x = 0x%02" PRIu64
"\n", s
->sr_index
, val
);
2653 cirrus_vga_write_sr(c
, val
);
2656 cirrus_write_hidden_dac(c
, val
);
2659 s
->dac_read_index
= val
;
2660 s
->dac_sub_index
= 0;
2664 s
->dac_write_index
= val
;
2665 s
->dac_sub_index
= 0;
2669 cirrus_vga_write_palette(c
, val
);
2675 #ifdef DEBUG_VGA_REG
2676 printf("vga: write GR%x = 0x%02" PRIu64
"\n", s
->gr_index
, val
);
2678 cirrus_vga_write_gr(c
, s
->gr_index
, val
);
2686 #ifdef DEBUG_VGA_REG
2687 printf("vga: write CR%x = 0x%02"PRIu64
"\n", s
->cr_index
, val
);
2689 cirrus_vga_write_cr(c
, val
);
2693 s
->fcr
= val
& 0x10;
2698 /***************************************
2700 * memory-mapped I/O access
2702 ***************************************/
2704 static uint64_t cirrus_mmio_read(void *opaque
, hwaddr addr
,
2707 CirrusVGAState
*s
= opaque
;
2709 if (addr
>= 0x100) {
2710 return cirrus_mmio_blt_read(s
, addr
- 0x100);
2712 return cirrus_vga_ioport_read(s
, addr
+ 0x10, size
);
2716 static void cirrus_mmio_write(void *opaque
, hwaddr addr
,
2717 uint64_t val
, unsigned size
)
2719 CirrusVGAState
*s
= opaque
;
2721 if (addr
>= 0x100) {
2722 cirrus_mmio_blt_write(s
, addr
- 0x100, val
);
2724 cirrus_vga_ioport_write(s
, addr
+ 0x10, val
, size
);
2728 static const MemoryRegionOps cirrus_mmio_io_ops
= {
2729 .read
= cirrus_mmio_read
,
2730 .write
= cirrus_mmio_write
,
2731 .endianness
= DEVICE_LITTLE_ENDIAN
,
2733 .min_access_size
= 1,
2734 .max_access_size
= 1,
2738 /* load/save state */
2740 static int cirrus_post_load(void *opaque
, int version_id
)
2742 CirrusVGAState
*s
= opaque
;
2744 s
->vga
.gr
[0x00] = s
->cirrus_shadow_gr0
& 0x0f;
2745 s
->vga
.gr
[0x01] = s
->cirrus_shadow_gr1
& 0x0f;
2747 cirrus_update_bank_ptr(s
, 0);
2748 cirrus_update_bank_ptr(s
, 1);
2749 cirrus_update_memory_access(s
);
2751 s
->vga
.graphic_mode
= -1;
2756 const VMStateDescription vmstate_cirrus_vga
= {
2757 .name
= "cirrus_vga",
2759 .minimum_version_id
= 1,
2760 .post_load
= cirrus_post_load
,
2761 .fields
= (VMStateField
[]) {
2762 VMSTATE_UINT32(vga
.latch
, CirrusVGAState
),
2763 VMSTATE_UINT8(vga
.sr_index
, CirrusVGAState
),
2764 VMSTATE_BUFFER(vga
.sr
, CirrusVGAState
),
2765 VMSTATE_UINT8(vga
.gr_index
, CirrusVGAState
),
2766 VMSTATE_UINT8(cirrus_shadow_gr0
, CirrusVGAState
),
2767 VMSTATE_UINT8(cirrus_shadow_gr1
, CirrusVGAState
),
2768 VMSTATE_BUFFER_START_MIDDLE(vga
.gr
, CirrusVGAState
, 2),
2769 VMSTATE_UINT8(vga
.ar_index
, CirrusVGAState
),
2770 VMSTATE_BUFFER(vga
.ar
, CirrusVGAState
),
2771 VMSTATE_INT32(vga
.ar_flip_flop
, CirrusVGAState
),
2772 VMSTATE_UINT8(vga
.cr_index
, CirrusVGAState
),
2773 VMSTATE_BUFFER(vga
.cr
, CirrusVGAState
),
2774 VMSTATE_UINT8(vga
.msr
, CirrusVGAState
),
2775 VMSTATE_UINT8(vga
.fcr
, CirrusVGAState
),
2776 VMSTATE_UINT8(vga
.st00
, CirrusVGAState
),
2777 VMSTATE_UINT8(vga
.st01
, CirrusVGAState
),
2778 VMSTATE_UINT8(vga
.dac_state
, CirrusVGAState
),
2779 VMSTATE_UINT8(vga
.dac_sub_index
, CirrusVGAState
),
2780 VMSTATE_UINT8(vga
.dac_read_index
, CirrusVGAState
),
2781 VMSTATE_UINT8(vga
.dac_write_index
, CirrusVGAState
),
2782 VMSTATE_BUFFER(vga
.dac_cache
, CirrusVGAState
),
2783 VMSTATE_BUFFER(vga
.palette
, CirrusVGAState
),
2784 VMSTATE_INT32(vga
.bank_offset
, CirrusVGAState
),
2785 VMSTATE_UINT8(cirrus_hidden_dac_lockindex
, CirrusVGAState
),
2786 VMSTATE_UINT8(cirrus_hidden_dac_data
, CirrusVGAState
),
2787 VMSTATE_UINT32(vga
.hw_cursor_x
, CirrusVGAState
),
2788 VMSTATE_UINT32(vga
.hw_cursor_y
, CirrusVGAState
),
2789 /* XXX: we do not save the bitblt state - we assume we do not save
2790 the state when the blitter is active */
2791 VMSTATE_END_OF_LIST()
2795 static const VMStateDescription vmstate_pci_cirrus_vga
= {
2796 .name
= "cirrus_vga",
2798 .minimum_version_id
= 2,
2799 .fields
= (VMStateField
[]) {
2800 VMSTATE_PCI_DEVICE(dev
, PCICirrusVGAState
),
2801 VMSTATE_STRUCT(cirrus_vga
, PCICirrusVGAState
, 0,
2802 vmstate_cirrus_vga
, CirrusVGAState
),
2803 VMSTATE_END_OF_LIST()
2807 /***************************************
2811 ***************************************/
2813 static void cirrus_reset(void *opaque
)
2815 CirrusVGAState
*s
= opaque
;
2817 vga_common_reset(&s
->vga
);
2818 unmap_linear_vram(s
);
2819 s
->vga
.sr
[0x06] = 0x0f;
2820 if (s
->device_id
== CIRRUS_ID_CLGD5446
) {
2821 /* 4MB 64 bit memory config, always PCI */
2822 s
->vga
.sr
[0x1F] = 0x2d; // MemClock
2823 s
->vga
.gr
[0x18] = 0x0f; // fastest memory configuration
2824 s
->vga
.sr
[0x0f] = 0x98;
2825 s
->vga
.sr
[0x17] = 0x20;
2826 s
->vga
.sr
[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
2828 s
->vga
.sr
[0x1F] = 0x22; // MemClock
2829 s
->vga
.sr
[0x0F] = CIRRUS_MEMSIZE_2M
;
2830 s
->vga
.sr
[0x17] = s
->bustype
;
2831 s
->vga
.sr
[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
2833 s
->vga
.cr
[0x27] = s
->device_id
;
2835 s
->cirrus_hidden_dac_lockindex
= 5;
2836 s
->cirrus_hidden_dac_data
= 0;
2839 static const MemoryRegionOps cirrus_linear_io_ops
= {
2840 .read
= cirrus_linear_read
,
2841 .write
= cirrus_linear_write
,
2842 .endianness
= DEVICE_LITTLE_ENDIAN
,
2844 .min_access_size
= 1,
2845 .max_access_size
= 1,
2849 static const MemoryRegionOps cirrus_vga_io_ops
= {
2850 .read
= cirrus_vga_ioport_read
,
2851 .write
= cirrus_vga_ioport_write
,
2852 .endianness
= DEVICE_LITTLE_ENDIAN
,
2854 .min_access_size
= 1,
2855 .max_access_size
= 1,
2859 void cirrus_init_common(CirrusVGAState
*s
, Object
*owner
,
2860 int device_id
, int is_pci
,
2861 MemoryRegion
*system_memory
, MemoryRegion
*system_io
)
2868 for(i
= 0;i
< 256; i
++)
2869 rop_to_index
[i
] = CIRRUS_ROP_NOP_INDEX
; /* nop rop */
2870 rop_to_index
[CIRRUS_ROP_0
] = 0;
2871 rop_to_index
[CIRRUS_ROP_SRC_AND_DST
] = 1;
2872 rop_to_index
[CIRRUS_ROP_NOP
] = 2;
2873 rop_to_index
[CIRRUS_ROP_SRC_AND_NOTDST
] = 3;
2874 rop_to_index
[CIRRUS_ROP_NOTDST
] = 4;
2875 rop_to_index
[CIRRUS_ROP_SRC
] = 5;
2876 rop_to_index
[CIRRUS_ROP_1
] = 6;
2877 rop_to_index
[CIRRUS_ROP_NOTSRC_AND_DST
] = 7;
2878 rop_to_index
[CIRRUS_ROP_SRC_XOR_DST
] = 8;
2879 rop_to_index
[CIRRUS_ROP_SRC_OR_DST
] = 9;
2880 rop_to_index
[CIRRUS_ROP_NOTSRC_OR_NOTDST
] = 10;
2881 rop_to_index
[CIRRUS_ROP_SRC_NOTXOR_DST
] = 11;
2882 rop_to_index
[CIRRUS_ROP_SRC_OR_NOTDST
] = 12;
2883 rop_to_index
[CIRRUS_ROP_NOTSRC
] = 13;
2884 rop_to_index
[CIRRUS_ROP_NOTSRC_OR_DST
] = 14;
2885 rop_to_index
[CIRRUS_ROP_NOTSRC_AND_NOTDST
] = 15;
2886 s
->device_id
= device_id
;
2888 s
->bustype
= CIRRUS_BUSTYPE_PCI
;
2890 s
->bustype
= CIRRUS_BUSTYPE_ISA
;
2893 /* Register ioport 0x3b0 - 0x3df */
2894 memory_region_init_io(&s
->cirrus_vga_io
, owner
, &cirrus_vga_io_ops
, s
,
2896 memory_region_set_flush_coalesced(&s
->cirrus_vga_io
);
2897 memory_region_add_subregion(system_io
, 0x3b0, &s
->cirrus_vga_io
);
2899 memory_region_init(&s
->low_mem_container
, owner
,
2900 "cirrus-lowmem-container",
2903 memory_region_init_io(&s
->low_mem
, owner
, &cirrus_vga_mem_ops
, s
,
2904 "cirrus-low-memory", 0x20000);
2905 memory_region_add_subregion(&s
->low_mem_container
, 0, &s
->low_mem
);
2906 for (i
= 0; i
< 2; ++i
) {
2907 static const char *names
[] = { "vga.bank0", "vga.bank1" };
2908 MemoryRegion
*bank
= &s
->cirrus_bank
[i
];
2909 memory_region_init_alias(bank
, owner
, names
[i
], &s
->vga
.vram
,
2911 memory_region_set_enabled(bank
, false);
2912 memory_region_add_subregion_overlap(&s
->low_mem_container
, i
* 0x8000,
2915 memory_region_add_subregion_overlap(system_memory
,
2917 &s
->low_mem_container
,
2919 memory_region_set_coalescing(&s
->low_mem
);
2921 /* I/O handler for LFB */
2922 memory_region_init_io(&s
->cirrus_linear_io
, owner
, &cirrus_linear_io_ops
, s
,
2923 "cirrus-linear-io", s
->vga
.vram_size_mb
* MiB
);
2924 memory_region_set_flush_coalesced(&s
->cirrus_linear_io
);
2926 /* I/O handler for LFB */
2927 memory_region_init_io(&s
->cirrus_linear_bitblt_io
, owner
,
2928 &cirrus_linear_bitblt_io_ops
,
2930 "cirrus-bitblt-mmio",
2932 memory_region_set_flush_coalesced(&s
->cirrus_linear_bitblt_io
);
2934 /* I/O handler for memory-mapped I/O */
2935 memory_region_init_io(&s
->cirrus_mmio_io
, owner
, &cirrus_mmio_io_ops
, s
,
2936 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE
);
2937 memory_region_set_flush_coalesced(&s
->cirrus_mmio_io
);
2940 (s
->device_id
== CIRRUS_ID_CLGD5446
) ? 4 * MiB
: 2 * MiB
;
2942 /* XXX: s->vga.vram_size must be a power of two */
2943 s
->cirrus_addr_mask
= s
->real_vram_size
- 1;
2944 s
->linear_mmio_mask
= s
->real_vram_size
- 256;
2946 s
->vga
.get_bpp
= cirrus_get_bpp
;
2947 s
->vga
.get_offsets
= cirrus_get_offsets
;
2948 s
->vga
.get_resolution
= cirrus_get_resolution
;
2949 s
->vga
.cursor_invalidate
= cirrus_cursor_invalidate
;
2950 s
->vga
.cursor_draw_line
= cirrus_cursor_draw_line
;
2952 qemu_register_reset(cirrus_reset
, s
);
2955 /***************************************
2959 ***************************************/
2961 static void pci_cirrus_vga_realize(PCIDevice
*dev
, Error
**errp
)
2963 PCICirrusVGAState
*d
= PCI_CIRRUS_VGA(dev
);
2964 CirrusVGAState
*s
= &d
->cirrus_vga
;
2965 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
2966 int16_t device_id
= pc
->device_id
;
2968 /* follow real hardware, cirrus card emulated has 4 MB video memory.
2969 Also accept 8 MB/16 MB for backward compatibility. */
2970 if (s
->vga
.vram_size_mb
!= 4 && s
->vga
.vram_size_mb
!= 8 &&
2971 s
->vga
.vram_size_mb
!= 16) {
2972 error_setg(errp
, "Invalid cirrus_vga ram size '%u'",
2973 s
->vga
.vram_size_mb
);
2977 vga_common_init(&s
->vga
, OBJECT(dev
));
2978 cirrus_init_common(s
, OBJECT(dev
), device_id
, 1, pci_address_space(dev
),
2979 pci_address_space_io(dev
));
2980 s
->vga
.con
= graphic_console_init(DEVICE(dev
), 0, s
->vga
.hw_ops
, &s
->vga
);
2984 memory_region_init(&s
->pci_bar
, OBJECT(dev
), "cirrus-pci-bar0", 0x2000000);
2986 /* XXX: add byte swapping apertures */
2987 memory_region_add_subregion(&s
->pci_bar
, 0, &s
->cirrus_linear_io
);
2988 memory_region_add_subregion(&s
->pci_bar
, 0x1000000,
2989 &s
->cirrus_linear_bitblt_io
);
2991 /* setup memory space */
2993 /* memory #1 memory-mapped I/O */
2994 /* XXX: s->vga.vram_size must be a power of two */
2995 pci_register_bar(&d
->dev
, 0, PCI_BASE_ADDRESS_MEM_PREFETCH
, &s
->pci_bar
);
2996 if (device_id
== CIRRUS_ID_CLGD5446
) {
2997 pci_register_bar(&d
->dev
, 1, 0, &s
->cirrus_mmio_io
);
3001 static Property pci_vga_cirrus_properties
[] = {
3002 DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState
,
3003 cirrus_vga
.vga
.vram_size_mb
, 4),
3004 DEFINE_PROP_BOOL("blitter", struct PCICirrusVGAState
,
3005 cirrus_vga
.enable_blitter
, true),
3006 DEFINE_PROP_BOOL("global-vmstate", struct PCICirrusVGAState
,
3007 cirrus_vga
.vga
.global_vmstate
, false),
3008 DEFINE_PROP_END_OF_LIST(),
3011 static void cirrus_vga_class_init(ObjectClass
*klass
, void *data
)
3013 DeviceClass
*dc
= DEVICE_CLASS(klass
);
3014 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
3016 k
->realize
= pci_cirrus_vga_realize
;
3017 k
->romfile
= VGABIOS_CIRRUS_FILENAME
;
3018 k
->vendor_id
= PCI_VENDOR_ID_CIRRUS
;
3019 k
->device_id
= CIRRUS_ID_CLGD5446
;
3020 k
->class_id
= PCI_CLASS_DISPLAY_VGA
;
3021 set_bit(DEVICE_CATEGORY_DISPLAY
, dc
->categories
);
3022 dc
->desc
= "Cirrus CLGD 54xx VGA";
3023 dc
->vmsd
= &vmstate_pci_cirrus_vga
;
3024 device_class_set_props(dc
, pci_vga_cirrus_properties
);
3025 dc
->hotpluggable
= false;
3028 static const TypeInfo cirrus_vga_info
= {
3029 .name
= TYPE_PCI_CIRRUS_VGA
,
3030 .parent
= TYPE_PCI_DEVICE
,
3031 .instance_size
= sizeof(PCICirrusVGAState
),
3032 .class_init
= cirrus_vga_class_init
,
3033 .interfaces
= (InterfaceInfo
[]) {
3034 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
3039 static void cirrus_vga_register_types(void)
3041 type_register_static(&cirrus_vga_info
);
3044 type_init(cirrus_vga_register_types
)