hw/display/pl110.c

   1 /*
   2  * Arm PrimeCell PL110 Color LCD Controller
   3  *
   4  * Copyright (c) 2005-2009 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GNU LGPL
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/sysbus.h"
  12 #include "ui/console.h"
  13 #include "framebuffer.h"
  14 #include "ui/pixel_ops.h"
  15 #include "qemu/timer.h"
  16 #include "qemu/log.h"
  17 #include "qemu/module.h"
  18
  19 #define PL110_CR_EN   0x001
  20 #define PL110_CR_BGR  0x100
  21 #define PL110_CR_BEBO 0x200
  22 #define PL110_CR_BEPO 0x400
  23 #define PL110_CR_PWR  0x800
  24 #define PL110_IE_NB   0x004
  25 #define PL110_IE_VC   0x008
  26
  27 enum pl110_bppmode
  28 {
  29     BPP_1,
  30     BPP_2,
  31     BPP_4,
  32     BPP_8,
  33     BPP_16,
  34     BPP_32,
  35     BPP_16_565, /* PL111 only */
  36     BPP_12      /* PL111 only */
  37 };
  38
  39
  40 /* The Versatile/PB uses a slightly modified PL110 controller.  */
  41 enum pl110_version
  42 {
  43     PL110,
  44     PL110_VERSATILE,
  45     PL111
  46 };
  47
  48 #define TYPE_PL110 "pl110"
  49 #define PL110(obj) OBJECT_CHECK(PL110State, (obj), TYPE_PL110)
  50
  51 typedef struct PL110State {
  52     SysBusDevice parent_obj;
  53
  54     MemoryRegion iomem;
  55     MemoryRegionSection fbsection;
  56     QemuConsole *con;
  57     QEMUTimer *vblank_timer;
  58
  59     int version;
  60     uint32_t timing[4];
  61     uint32_t cr;
  62     uint32_t upbase;
  63     uint32_t lpbase;
  64     uint32_t int_status;
  65     uint32_t int_mask;
  66     int cols;
  67     int rows;
  68     enum pl110_bppmode bpp;
  69     int invalidate;
  70     uint32_t mux_ctrl;
  71     uint32_t palette[256];
  72     uint32_t raw_palette[128];
  73     qemu_irq irq;
  74 } PL110State;
  75
  76 static int vmstate_pl110_post_load(void *opaque, int version_id);
  77
  78 static const VMStateDescription vmstate_pl110 = {
  79     .name = "pl110",
  80     .version_id = 2,
  81     .minimum_version_id = 1,
  82     .post_load = vmstate_pl110_post_load,
  83     .fields = (VMStateField[]) {
  84         VMSTATE_INT32(version, PL110State),
  85         VMSTATE_UINT32_ARRAY(timing, PL110State, 4),
  86         VMSTATE_UINT32(cr, PL110State),
  87         VMSTATE_UINT32(upbase, PL110State),
  88         VMSTATE_UINT32(lpbase, PL110State),
  89         VMSTATE_UINT32(int_status, PL110State),
  90         VMSTATE_UINT32(int_mask, PL110State),
  91         VMSTATE_INT32(cols, PL110State),
  92         VMSTATE_INT32(rows, PL110State),
  93         VMSTATE_UINT32(bpp, PL110State),
  94         VMSTATE_INT32(invalidate, PL110State),
  95         VMSTATE_UINT32_ARRAY(palette, PL110State, 256),
  96         VMSTATE_UINT32_ARRAY(raw_palette, PL110State, 128),
  97         VMSTATE_UINT32_V(mux_ctrl, PL110State, 2),
  98         VMSTATE_END_OF_LIST()
  99     }
 100 };
 101
 102 static const unsigned char pl110_id[] =
 103 { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
 104
 105 static const unsigned char pl111_id[] = {
 106     0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1
 107 };
 108
 109
 110 /* Indexed by pl110_version */
 111 static const unsigned char *idregs[] = {
 112     pl110_id,
 113     /* The ARM documentation (DDI0224C) says the CLCDC on the Versatile board
 114      * has a different ID (0x93, 0x10, 0x04, 0x00, ...). However the hardware
 115      * itself has the same ID values as a stock PL110, and guests (in
 116      * particular Linux) rely on this. We emulate what the hardware does,
 117      * rather than what the docs claim it ought to do.
 118      */
 119     pl110_id,
 120     pl111_id
 121 };
 122
 123 #define BITS 8
 124 #include "pl110_template.h"
 125 #define BITS 15
 126 #include "pl110_template.h"
 127 #define BITS 16
 128 #include "pl110_template.h"
 129 #define BITS 24
 130 #include "pl110_template.h"
 131 #define BITS 32
 132 #include "pl110_template.h"
 133
 134 static int pl110_enabled(PL110State *s)
 135 {
 136   return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
 137 }
 138
 139 static void pl110_update_display(void *opaque)
 140 {
 141     PL110State *s = (PL110State *)opaque;
 142     SysBusDevice *sbd;
 143     DisplaySurface *surface = qemu_console_surface(s->con);
 144     drawfn* fntable;
 145     drawfn fn;
 146     int dest_width;
 147     int src_width;
 148     int bpp_offset;
 149     int first;
 150     int last;
 151
 152     if (!pl110_enabled(s)) {
 153         return;
 154     }
 155
 156     sbd = SYS_BUS_DEVICE(s);
 157
 158     switch (surface_bits_per_pixel(surface)) {
 159     case 0:
 160         return;
 161     case 8:
 162         fntable = pl110_draw_fn_8;
 163         dest_width = 1;
 164         break;
 165     case 15:
 166         fntable = pl110_draw_fn_15;
 167         dest_width = 2;
 168         break;
 169     case 16:
 170         fntable = pl110_draw_fn_16;
 171         dest_width = 2;
 172         break;
 173     case 24:
 174         fntable = pl110_draw_fn_24;
 175         dest_width = 3;
 176         break;
 177     case 32:
 178         fntable = pl110_draw_fn_32;
 179         dest_width = 4;
 180         break;
 181     default:
 182         fprintf(stderr, "pl110: Bad color depth\n");
 183         exit(1);
 184     }
 185     if (s->cr & PL110_CR_BGR)
 186         bpp_offset = 0;
 187     else
 188         bpp_offset = 24;
 189
 190     if ((s->version != PL111) && (s->bpp == BPP_16)) {
 191         /* The PL110's native 16 bit mode is 5551; however
 192          * most boards with a PL110 implement an external
 193          * mux which allows bits to be reshuffled to give
 194          * 565 format. The mux is typically controlled by
 195          * an external system register.
 196          * This is controlled by a GPIO input pin
 197          * so boards can wire it up to their register.
 198          *
 199          * The PL111 straightforwardly implements both
 200          * 5551 and 565 under control of the bpp field
 201          * in the LCDControl register.
 202          */
 203         switch (s->mux_ctrl) {
 204         case 3: /* 565 BGR */
 205             bpp_offset = (BPP_16_565 - BPP_16);
 206             break;
 207         case 1: /* 5551 */
 208             break;
 209         case 0: /* 888; also if we have loaded vmstate from an old version */
 210         case 2: /* 565 RGB */
 211         default:
 212             /* treat as 565 but honour BGR bit */
 213             bpp_offset += (BPP_16_565 - BPP_16);
 214             break;
 215         }
 216     }
 217
 218     if (s->cr & PL110_CR_BEBO)
 219         fn = fntable[s->bpp + 8 + bpp_offset];
 220     else if (s->cr & PL110_CR_BEPO)
 221         fn = fntable[s->bpp + 16 + bpp_offset];
 222     else
 223         fn = fntable[s->bpp + bpp_offset];
 224
 225     src_width = s->cols;
 226     switch (s->bpp) {
 227     case BPP_1:
 228         src_width >>= 3;
 229         break;
 230     case BPP_2:
 231         src_width >>= 2;
 232         break;
 233     case BPP_4:
 234         src_width >>= 1;
 235         break;
 236     case BPP_8:
 237         break;
 238     case BPP_16:
 239     case BPP_16_565:
 240     case BPP_12:
 241         src_width <<= 1;
 242         break;
 243     case BPP_32:
 244         src_width <<= 2;
 245         break;
 246     }
 247     dest_width *= s->cols;
 248     first = 0;
 249     if (s->invalidate) {
 250         framebuffer_update_memory_section(&s->fbsection,
 251                                           sysbus_address_space(sbd),
 252                                           s->upbase,
 253                                           s->rows, src_width);
 254     }
 255
 256     framebuffer_update_display(surface, &s->fbsection,
 257                                s->cols, s->rows,
 258                                src_width, dest_width, 0,
 259                                s->invalidate,
 260                                fn, s->palette,
 261                                &first, &last);
 262
 263     if (first >= 0) {
 264         dpy_gfx_update(s->con, 0, first, s->cols, last - first + 1);
 265     }
 266     s->invalidate = 0;
 267 }
 268
 269 static void pl110_invalidate_display(void * opaque)
 270 {
 271     PL110State *s = (PL110State *)opaque;
 272     s->invalidate = 1;
 273     if (pl110_enabled(s)) {
 274         qemu_console_resize(s->con, s->cols, s->rows);
 275     }
 276 }
 277
 278 static void pl110_update_palette(PL110State *s, int n)
 279 {
 280     DisplaySurface *surface = qemu_console_surface(s->con);
 281     int i;
 282     uint32_t raw;
 283     unsigned int r, g, b;
 284
 285     raw = s->raw_palette[n];
 286     n <<= 1;
 287     for (i = 0; i < 2; i++) {
 288         r = (raw & 0x1f) << 3;
 289         raw >>= 5;
 290         g = (raw & 0x1f) << 3;
 291         raw >>= 5;
 292         b = (raw & 0x1f) << 3;
 293         /* The I bit is ignored.  */
 294         raw >>= 6;
 295         switch (surface_bits_per_pixel(surface)) {
 296         case 8:
 297             s->palette[n] = rgb_to_pixel8(r, g, b);
 298             break;
 299         case 15:
 300             s->palette[n] = rgb_to_pixel15(r, g, b);
 301             break;
 302         case 16:
 303             s->palette[n] = rgb_to_pixel16(r, g, b);
 304             break;
 305         case 24:
 306         case 32:
 307             s->palette[n] = rgb_to_pixel32(r, g, b);
 308             break;
 309         }
 310         n++;
 311     }
 312 }
 313
 314 static void pl110_resize(PL110State *s, int width, int height)
 315 {
 316     if (width != s->cols || height != s->rows) {
 317         if (pl110_enabled(s)) {
 318             qemu_console_resize(s->con, width, height);
 319         }
 320     }
 321     s->cols = width;
 322     s->rows = height;
 323 }
 324
 325 /* Update interrupts.  */
 326 static void pl110_update(PL110State *s)
 327 {
 328     /* Raise IRQ if enabled and any status bit is 1 */
 329     if (s->int_status & s->int_mask) {
 330         qemu_irq_raise(s->irq);
 331     } else {
 332         qemu_irq_lower(s->irq);
 333     }
 334 }
 335
 336 static void pl110_vblank_interrupt(void *opaque)
 337 {
 338     PL110State *s = opaque;
 339
 340     /* Fire the vertical compare and next base IRQs and re-arm */
 341     s->int_status |= (PL110_IE_NB | PL110_IE_VC);
 342     timer_mod(s->vblank_timer,
 343               qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 344                                 NANOSECONDS_PER_SECOND / 60);
 345     pl110_update(s);
 346 }
 347
 348 static uint64_t pl110_read(void *opaque, hwaddr offset,
 349                            unsigned size)
 350 {
 351     PL110State *s = (PL110State *)opaque;
 352
 353     if (offset >= 0xfe0 && offset < 0x1000) {
 354         return idregs[s->version][(offset - 0xfe0) >> 2];
 355     }
 356     if (offset >= 0x200 && offset < 0x400) {
 357         return s->raw_palette[(offset - 0x200) >> 2];
 358     }
 359     switch (offset >> 2) {
 360     case 0: /* LCDTiming0 */
 361         return s->timing[0];
 362     case 1: /* LCDTiming1 */
 363         return s->timing[1];
 364     case 2: /* LCDTiming2 */
 365         return s->timing[2];
 366     case 3: /* LCDTiming3 */
 367         return s->timing[3];
 368     case 4: /* LCDUPBASE */
 369         return s->upbase;
 370     case 5: /* LCDLPBASE */
 371         return s->lpbase;
 372     case 6: /* LCDIMSC */
 373         if (s->version != PL110) {
 374             return s->cr;
 375         }
 376         return s->int_mask;
 377     case 7: /* LCDControl */
 378         if (s->version != PL110) {
 379             return s->int_mask;
 380         }
 381         return s->cr;
 382     case 8: /* LCDRIS */
 383         return s->int_status;
 384     case 9: /* LCDMIS */
 385         return s->int_status & s->int_mask;
 386     case 11: /* LCDUPCURR */
 387         /* TODO: Implement vertical refresh.  */
 388         return s->upbase;
 389     case 12: /* LCDLPCURR */
 390         return s->lpbase;
 391     default:
 392         qemu_log_mask(LOG_GUEST_ERROR,
 393                       "pl110_read: Bad offset %x\n", (int)offset);
 394         return 0;
 395     }
 396 }
 397
 398 static void pl110_write(void *opaque, hwaddr offset,
 399                         uint64_t val, unsigned size)
 400 {
 401     PL110State *s = (PL110State *)opaque;
 402     int n;
 403
 404     /* For simplicity invalidate the display whenever a control register
 405        is written to.  */
 406     s->invalidate = 1;
 407     if (offset >= 0x200 && offset < 0x400) {
 408         /* Palette.  */
 409         n = (offset - 0x200) >> 2;
 410         s->raw_palette[(offset - 0x200) >> 2] = val;
 411         pl110_update_palette(s, n);
 412         return;
 413     }
 414     switch (offset >> 2) {
 415     case 0: /* LCDTiming0 */
 416         s->timing[0] = val;
 417         n = ((val & 0xfc) + 4) * 4;
 418         pl110_resize(s, n, s->rows);
 419         break;
 420     case 1: /* LCDTiming1 */
 421         s->timing[1] = val;
 422         n = (val & 0x3ff) + 1;
 423         pl110_resize(s, s->cols, n);
 424         break;
 425     case 2: /* LCDTiming2 */
 426         s->timing[2] = val;
 427         break;
 428     case 3: /* LCDTiming3 */
 429         s->timing[3] = val;
 430         break;
 431     case 4: /* LCDUPBASE */
 432         s->upbase = val;
 433         break;
 434     case 5: /* LCDLPBASE */
 435         s->lpbase = val;
 436         break;
 437     case 6: /* LCDIMSC */
 438         if (s->version != PL110) {
 439             goto control;
 440         }
 441     imsc:
 442         s->int_mask = val;
 443         pl110_update(s);
 444         break;
 445     case 7: /* LCDControl */
 446         if (s->version != PL110) {
 447             goto imsc;
 448         }
 449     control:
 450         s->cr = val;
 451         s->bpp = (val >> 1) & 7;
 452         if (pl110_enabled(s)) {
 453             qemu_console_resize(s->con, s->cols, s->rows);
 454             timer_mod(s->vblank_timer,
 455                       qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 456                                         NANOSECONDS_PER_SECOND / 60);
 457         } else {
 458             timer_del(s->vblank_timer);
 459         }
 460         break;
 461     case 10: /* LCDICR */
 462         s->int_status &= ~val;
 463         pl110_update(s);
 464         break;
 465     default:
 466         qemu_log_mask(LOG_GUEST_ERROR,
 467                       "pl110_write: Bad offset %x\n", (int)offset);
 468     }
 469 }
 470
 471 static const MemoryRegionOps pl110_ops = {
 472     .read = pl110_read,
 473     .write = pl110_write,
 474     .endianness = DEVICE_NATIVE_ENDIAN,
 475 };
 476
 477 static void pl110_mux_ctrl_set(void *opaque, int line, int level)
 478 {
 479     PL110State *s = (PL110State *)opaque;
 480     s->mux_ctrl = level;
 481 }
 482
 483 static int vmstate_pl110_post_load(void *opaque, int version_id)
 484 {
 485     PL110State *s = opaque;
 486     /* Make sure we redraw, and at the right size */
 487     pl110_invalidate_display(s);
 488     return 0;
 489 }
 490
 491 static const GraphicHwOps pl110_gfx_ops = {
 492     .invalidate  = pl110_invalidate_display,
 493     .gfx_update  = pl110_update_display,
 494 };
 495
 496 static void pl110_realize(DeviceState *dev, Error **errp)
 497 {
 498     PL110State *s = PL110(dev);
 499     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 500
 501     memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x1000);
 502     sysbus_init_mmio(sbd, &s->iomem);
 503     sysbus_init_irq(sbd, &s->irq);
 504     s->vblank_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 505                                    pl110_vblank_interrupt, s);
 506     qdev_init_gpio_in(dev, pl110_mux_ctrl_set, 1);
 507     s->con = graphic_console_init(dev, 0, &pl110_gfx_ops, s);
 508 }
 509
 510 static void pl110_init(Object *obj)
 511 {
 512     PL110State *s = PL110(obj);
 513
 514     s->version = PL110;
 515 }
 516
 517 static void pl110_versatile_init(Object *obj)
 518 {
 519     PL110State *s = PL110(obj);
 520
 521     s->version = PL110_VERSATILE;
 522 }
 523
 524 static void pl111_init(Object *obj)
 525 {
 526     PL110State *s = PL110(obj);
 527
 528     s->version = PL111;
 529 }
 530
 531 static void pl110_class_init(ObjectClass *klass, void *data)
 532 {
 533     DeviceClass *dc = DEVICE_CLASS(klass);
 534
 535     set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
 536     dc->vmsd = &vmstate_pl110;
 537     dc->realize = pl110_realize;
 538 }
 539
 540 static const TypeInfo pl110_info = {
 541     .name          = TYPE_PL110,
 542     .parent        = TYPE_SYS_BUS_DEVICE,
 543     .instance_size = sizeof(PL110State),
 544     .instance_init = pl110_init,
 545     .class_init    = pl110_class_init,
 546 };
 547
 548 static const TypeInfo pl110_versatile_info = {
 549     .name          = "pl110_versatile",
 550     .parent        = TYPE_PL110,
 551     .instance_init = pl110_versatile_init,
 552 };
 553
 554 static const TypeInfo pl111_info = {
 555     .name          = "pl111",
 556     .parent        = TYPE_PL110,
 557     .instance_init = pl111_init,
 558 };
 559
 560 static void pl110_register_types(void)
 561 {
 562     type_register_static(&pl110_info);
 563     type_register_static(&pl110_versatile_info);
 564     type_register_static(&pl111_info);
 565 }
 566
 567 type_init(pl110_register_types)