hw/display/pl110.c

   1 /*
   2  * Arm PrimeCell PL110 Color LCD Controller
   3  *
   4  * Copyright (c) 2005-2009 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GNU LGPL
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/irq.h"
  12 #include "hw/sysbus.h"
  13 #include "migration/vmstate.h"
  14 #include "ui/console.h"
  15 #include "framebuffer.h"
  16 #include "ui/pixel_ops.h"
  17 #include "qemu/timer.h"
  18 #include "qemu/log.h"
  19 #include "qemu/module.h"
  20 #include "qom/object.h"
  21
  22 #define PL110_CR_EN   0x001
  23 #define PL110_CR_BGR  0x100
  24 #define PL110_CR_BEBO 0x200
  25 #define PL110_CR_BEPO 0x400
  26 #define PL110_CR_PWR  0x800
  27 #define PL110_IE_NB   0x004
  28 #define PL110_IE_VC   0x008
  29
  30 enum pl110_bppmode
  31 {
  32     BPP_1,
  33     BPP_2,
  34     BPP_4,
  35     BPP_8,
  36     BPP_16,
  37     BPP_32,
  38     BPP_16_565, /* PL111 only */
  39     BPP_12      /* PL111 only */
  40 };
  41
  42
  43 /* The Versatile/PB uses a slightly modified PL110 controller.  */
  44 enum pl110_version
  45 {
  46     VERSION_PL110,
  47     VERSION_PL110_VERSATILE,
  48     VERSION_PL111
  49 };
  50
  51 #define TYPE_PL110 "pl110"
  52 typedef struct PL110State PL110State;
  53 #define PL110(obj) OBJECT_CHECK(PL110State, (obj), TYPE_PL110)
  54
  55 struct PL110State {
  56     SysBusDevice parent_obj;
  57
  58     MemoryRegion iomem;
  59     MemoryRegionSection fbsection;
  60     QemuConsole *con;
  61     QEMUTimer *vblank_timer;
  62
  63     int version;
  64     uint32_t timing[4];
  65     uint32_t cr;
  66     uint32_t upbase;
  67     uint32_t lpbase;
  68     uint32_t int_status;
  69     uint32_t int_mask;
  70     int cols;
  71     int rows;
  72     enum pl110_bppmode bpp;
  73     int invalidate;
  74     uint32_t mux_ctrl;
  75     uint32_t palette[256];
  76     uint32_t raw_palette[128];
  77     qemu_irq irq;
  78 };
  79
  80 static int vmstate_pl110_post_load(void *opaque, int version_id);
  81
  82 static const VMStateDescription vmstate_pl110 = {
  83     .name = "pl110",
  84     .version_id = 2,
  85     .minimum_version_id = 1,
  86     .post_load = vmstate_pl110_post_load,
  87     .fields = (VMStateField[]) {
  88         VMSTATE_INT32(version, PL110State),
  89         VMSTATE_UINT32_ARRAY(timing, PL110State, 4),
  90         VMSTATE_UINT32(cr, PL110State),
  91         VMSTATE_UINT32(upbase, PL110State),
  92         VMSTATE_UINT32(lpbase, PL110State),
  93         VMSTATE_UINT32(int_status, PL110State),
  94         VMSTATE_UINT32(int_mask, PL110State),
  95         VMSTATE_INT32(cols, PL110State),
  96         VMSTATE_INT32(rows, PL110State),
  97         VMSTATE_UINT32(bpp, PL110State),
  98         VMSTATE_INT32(invalidate, PL110State),
  99         VMSTATE_UINT32_ARRAY(palette, PL110State, 256),
 100         VMSTATE_UINT32_ARRAY(raw_palette, PL110State, 128),
 101         VMSTATE_UINT32_V(mux_ctrl, PL110State, 2),
 102         VMSTATE_END_OF_LIST()
 103     }
 104 };
 105
 106 static const unsigned char pl110_id[] =
 107 { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
 108
 109 static const unsigned char pl111_id[] = {
 110     0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1
 111 };
 112
 113
 114 /* Indexed by pl110_version */
 115 static const unsigned char *idregs[] = {
 116     pl110_id,
 117     /* The ARM documentation (DDI0224C) says the CLCDC on the Versatile board
 118      * has a different ID (0x93, 0x10, 0x04, 0x00, ...). However the hardware
 119      * itself has the same ID values as a stock PL110, and guests (in
 120      * particular Linux) rely on this. We emulate what the hardware does,
 121      * rather than what the docs claim it ought to do.
 122      */
 123     pl110_id,
 124     pl111_id
 125 };
 126
 127 #define BITS 8
 128 #include "pl110_template.h"
 129 #define BITS 15
 130 #include "pl110_template.h"
 131 #define BITS 16
 132 #include "pl110_template.h"
 133 #define BITS 24
 134 #include "pl110_template.h"
 135 #define BITS 32
 136 #include "pl110_template.h"
 137
 138 static int pl110_enabled(PL110State *s)
 139 {
 140   return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
 141 }
 142
 143 static void pl110_update_display(void *opaque)
 144 {
 145     PL110State *s = (PL110State *)opaque;
 146     SysBusDevice *sbd;
 147     DisplaySurface *surface = qemu_console_surface(s->con);
 148     drawfn* fntable;
 149     drawfn fn;
 150     int dest_width;
 151     int src_width;
 152     int bpp_offset;
 153     int first;
 154     int last;
 155
 156     if (!pl110_enabled(s)) {
 157         return;
 158     }
 159
 160     sbd = SYS_BUS_DEVICE(s);
 161
 162     switch (surface_bits_per_pixel(surface)) {
 163     case 0:
 164         return;
 165     case 8:
 166         fntable = pl110_draw_fn_8;
 167         dest_width = 1;
 168         break;
 169     case 15:
 170         fntable = pl110_draw_fn_15;
 171         dest_width = 2;
 172         break;
 173     case 16:
 174         fntable = pl110_draw_fn_16;
 175         dest_width = 2;
 176         break;
 177     case 24:
 178         fntable = pl110_draw_fn_24;
 179         dest_width = 3;
 180         break;
 181     case 32:
 182         fntable = pl110_draw_fn_32;
 183         dest_width = 4;
 184         break;
 185     default:
 186         fprintf(stderr, "pl110: Bad color depth\n");
 187         exit(1);
 188     }
 189     if (s->cr & PL110_CR_BGR)
 190         bpp_offset = 0;
 191     else
 192         bpp_offset = 24;
 193
 194     if ((s->version != VERSION_PL111) && (s->bpp == BPP_16)) {
 195         /* The PL110's native 16 bit mode is 5551; however
 196          * most boards with a PL110 implement an external
 197          * mux which allows bits to be reshuffled to give
 198          * 565 format. The mux is typically controlled by
 199          * an external system register.
 200          * This is controlled by a GPIO input pin
 201          * so boards can wire it up to their register.
 202          *
 203          * The PL111 straightforwardly implements both
 204          * 5551 and 565 under control of the bpp field
 205          * in the LCDControl register.
 206          */
 207         switch (s->mux_ctrl) {
 208         case 3: /* 565 BGR */
 209             bpp_offset = (BPP_16_565 - BPP_16);
 210             break;
 211         case 1: /* 5551 */
 212             break;
 213         case 0: /* 888; also if we have loaded vmstate from an old version */
 214         case 2: /* 565 RGB */
 215         default:
 216             /* treat as 565 but honour BGR bit */
 217             bpp_offset += (BPP_16_565 - BPP_16);
 218             break;
 219         }
 220     }
 221
 222     if (s->cr & PL110_CR_BEBO)
 223         fn = fntable[s->bpp + 8 + bpp_offset];
 224     else if (s->cr & PL110_CR_BEPO)
 225         fn = fntable[s->bpp + 16 + bpp_offset];
 226     else
 227         fn = fntable[s->bpp + bpp_offset];
 228
 229     src_width = s->cols;
 230     switch (s->bpp) {
 231     case BPP_1:
 232         src_width >>= 3;
 233         break;
 234     case BPP_2:
 235         src_width >>= 2;
 236         break;
 237     case BPP_4:
 238         src_width >>= 1;
 239         break;
 240     case BPP_8:
 241         break;
 242     case BPP_16:
 243     case BPP_16_565:
 244     case BPP_12:
 245         src_width <<= 1;
 246         break;
 247     case BPP_32:
 248         src_width <<= 2;
 249         break;
 250     }
 251     dest_width *= s->cols;
 252     first = 0;
 253     if (s->invalidate) {
 254         framebuffer_update_memory_section(&s->fbsection,
 255                                           sysbus_address_space(sbd),
 256                                           s->upbase,
 257                                           s->rows, src_width);
 258     }
 259
 260     framebuffer_update_display(surface, &s->fbsection,
 261                                s->cols, s->rows,
 262                                src_width, dest_width, 0,
 263                                s->invalidate,
 264                                fn, s->palette,
 265                                &first, &last);
 266
 267     if (first >= 0) {
 268         dpy_gfx_update(s->con, 0, first, s->cols, last - first + 1);
 269     }
 270     s->invalidate = 0;
 271 }
 272
 273 static void pl110_invalidate_display(void * opaque)
 274 {
 275     PL110State *s = (PL110State *)opaque;
 276     s->invalidate = 1;
 277     if (pl110_enabled(s)) {
 278         qemu_console_resize(s->con, s->cols, s->rows);
 279     }
 280 }
 281
 282 static void pl110_update_palette(PL110State *s, int n)
 283 {
 284     DisplaySurface *surface = qemu_console_surface(s->con);
 285     int i;
 286     uint32_t raw;
 287     unsigned int r, g, b;
 288
 289     raw = s->raw_palette[n];
 290     n <<= 1;
 291     for (i = 0; i < 2; i++) {
 292         r = (raw & 0x1f) << 3;
 293         raw >>= 5;
 294         g = (raw & 0x1f) << 3;
 295         raw >>= 5;
 296         b = (raw & 0x1f) << 3;
 297         /* The I bit is ignored.  */
 298         raw >>= 6;
 299         switch (surface_bits_per_pixel(surface)) {
 300         case 8:
 301             s->palette[n] = rgb_to_pixel8(r, g, b);
 302             break;
 303         case 15:
 304             s->palette[n] = rgb_to_pixel15(r, g, b);
 305             break;
 306         case 16:
 307             s->palette[n] = rgb_to_pixel16(r, g, b);
 308             break;
 309         case 24:
 310         case 32:
 311             s->palette[n] = rgb_to_pixel32(r, g, b);
 312             break;
 313         }
 314         n++;
 315     }
 316 }
 317
 318 static void pl110_resize(PL110State *s, int width, int height)
 319 {
 320     if (width != s->cols || height != s->rows) {
 321         if (pl110_enabled(s)) {
 322             qemu_console_resize(s->con, width, height);
 323         }
 324     }
 325     s->cols = width;
 326     s->rows = height;
 327 }
 328
 329 /* Update interrupts.  */
 330 static void pl110_update(PL110State *s)
 331 {
 332     /* Raise IRQ if enabled and any status bit is 1 */
 333     if (s->int_status & s->int_mask) {
 334         qemu_irq_raise(s->irq);
 335     } else {
 336         qemu_irq_lower(s->irq);
 337     }
 338 }
 339
 340 static void pl110_vblank_interrupt(void *opaque)
 341 {
 342     PL110State *s = opaque;
 343
 344     /* Fire the vertical compare and next base IRQs and re-arm */
 345     s->int_status |= (PL110_IE_NB | PL110_IE_VC);
 346     timer_mod(s->vblank_timer,
 347               qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 348                                 NANOSECONDS_PER_SECOND / 60);
 349     pl110_update(s);
 350 }
 351
 352 static uint64_t pl110_read(void *opaque, hwaddr offset,
 353                            unsigned size)
 354 {
 355     PL110State *s = (PL110State *)opaque;
 356
 357     if (offset >= 0xfe0 && offset < 0x1000) {
 358         return idregs[s->version][(offset - 0xfe0) >> 2];
 359     }
 360     if (offset >= 0x200 && offset < 0x400) {
 361         return s->raw_palette[(offset - 0x200) >> 2];
 362     }
 363     switch (offset >> 2) {
 364     case 0: /* LCDTiming0 */
 365         return s->timing[0];
 366     case 1: /* LCDTiming1 */
 367         return s->timing[1];
 368     case 2: /* LCDTiming2 */
 369         return s->timing[2];
 370     case 3: /* LCDTiming3 */
 371         return s->timing[3];
 372     case 4: /* LCDUPBASE */
 373         return s->upbase;
 374     case 5: /* LCDLPBASE */
 375         return s->lpbase;
 376     case 6: /* LCDIMSC */
 377         if (s->version != VERSION_PL110) {
 378             return s->cr;
 379         }
 380         return s->int_mask;
 381     case 7: /* LCDControl */
 382         if (s->version != VERSION_PL110) {
 383             return s->int_mask;
 384         }
 385         return s->cr;
 386     case 8: /* LCDRIS */
 387         return s->int_status;
 388     case 9: /* LCDMIS */
 389         return s->int_status & s->int_mask;
 390     case 11: /* LCDUPCURR */
 391         /* TODO: Implement vertical refresh.  */
 392         return s->upbase;
 393     case 12: /* LCDLPCURR */
 394         return s->lpbase;
 395     default:
 396         qemu_log_mask(LOG_GUEST_ERROR,
 397                       "pl110_read: Bad offset %x\n", (int)offset);
 398         return 0;
 399     }
 400 }
 401
 402 static void pl110_write(void *opaque, hwaddr offset,
 403                         uint64_t val, unsigned size)
 404 {
 405     PL110State *s = (PL110State *)opaque;
 406     int n;
 407
 408     /* For simplicity invalidate the display whenever a control register
 409        is written to.  */
 410     s->invalidate = 1;
 411     if (offset >= 0x200 && offset < 0x400) {
 412         /* Palette.  */
 413         n = (offset - 0x200) >> 2;
 414         s->raw_palette[(offset - 0x200) >> 2] = val;
 415         pl110_update_palette(s, n);
 416         return;
 417     }
 418     switch (offset >> 2) {
 419     case 0: /* LCDTiming0 */
 420         s->timing[0] = val;
 421         n = ((val & 0xfc) + 4) * 4;
 422         pl110_resize(s, n, s->rows);
 423         break;
 424     case 1: /* LCDTiming1 */
 425         s->timing[1] = val;
 426         n = (val & 0x3ff) + 1;
 427         pl110_resize(s, s->cols, n);
 428         break;
 429     case 2: /* LCDTiming2 */
 430         s->timing[2] = val;
 431         break;
 432     case 3: /* LCDTiming3 */
 433         s->timing[3] = val;
 434         break;
 435     case 4: /* LCDUPBASE */
 436         s->upbase = val;
 437         break;
 438     case 5: /* LCDLPBASE */
 439         s->lpbase = val;
 440         break;
 441     case 6: /* LCDIMSC */
 442         if (s->version != VERSION_PL110) {
 443             goto control;
 444         }
 445     imsc:
 446         s->int_mask = val;
 447         pl110_update(s);
 448         break;
 449     case 7: /* LCDControl */
 450         if (s->version != VERSION_PL110) {
 451             goto imsc;
 452         }
 453     control:
 454         s->cr = val;
 455         s->bpp = (val >> 1) & 7;
 456         if (pl110_enabled(s)) {
 457             qemu_console_resize(s->con, s->cols, s->rows);
 458             timer_mod(s->vblank_timer,
 459                       qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 460                                         NANOSECONDS_PER_SECOND / 60);
 461         } else {
 462             timer_del(s->vblank_timer);
 463         }
 464         break;
 465     case 10: /* LCDICR */
 466         s->int_status &= ~val;
 467         pl110_update(s);
 468         break;
 469     default:
 470         qemu_log_mask(LOG_GUEST_ERROR,
 471                       "pl110_write: Bad offset %x\n", (int)offset);
 472     }
 473 }
 474
 475 static const MemoryRegionOps pl110_ops = {
 476     .read = pl110_read,
 477     .write = pl110_write,
 478     .endianness = DEVICE_NATIVE_ENDIAN,
 479 };
 480
 481 static void pl110_mux_ctrl_set(void *opaque, int line, int level)
 482 {
 483     PL110State *s = (PL110State *)opaque;
 484     s->mux_ctrl = level;
 485 }
 486
 487 static int vmstate_pl110_post_load(void *opaque, int version_id)
 488 {
 489     PL110State *s = opaque;
 490     /* Make sure we redraw, and at the right size */
 491     pl110_invalidate_display(s);
 492     return 0;
 493 }
 494
 495 static const GraphicHwOps pl110_gfx_ops = {
 496     .invalidate  = pl110_invalidate_display,
 497     .gfx_update  = pl110_update_display,
 498 };
 499
 500 static void pl110_realize(DeviceState *dev, Error **errp)
 501 {
 502     PL110State *s = PL110(dev);
 503     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 504
 505     memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x1000);
 506     sysbus_init_mmio(sbd, &s->iomem);
 507     sysbus_init_irq(sbd, &s->irq);
 508     s->vblank_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 509                                    pl110_vblank_interrupt, s);
 510     qdev_init_gpio_in(dev, pl110_mux_ctrl_set, 1);
 511     s->con = graphic_console_init(dev, 0, &pl110_gfx_ops, s);
 512 }
 513
 514 static void pl110_init(Object *obj)
 515 {
 516     PL110State *s = PL110(obj);
 517
 518     s->version = VERSION_PL110;
 519 }
 520
 521 static void pl110_versatile_init(Object *obj)
 522 {
 523     PL110State *s = PL110(obj);
 524
 525     s->version = VERSION_PL110_VERSATILE;
 526 }
 527
 528 static void pl111_init(Object *obj)
 529 {
 530     PL110State *s = PL110(obj);
 531
 532     s->version = VERSION_PL111;
 533 }
 534
 535 static void pl110_class_init(ObjectClass *klass, void *data)
 536 {
 537     DeviceClass *dc = DEVICE_CLASS(klass);
 538
 539     set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
 540     dc->vmsd = &vmstate_pl110;
 541     dc->realize = pl110_realize;
 542 }
 543
 544 static const TypeInfo pl110_info = {
 545     .name          = TYPE_PL110,
 546     .parent        = TYPE_SYS_BUS_DEVICE,
 547     .instance_size = sizeof(PL110State),
 548     .instance_init = pl110_init,
 549     .class_init    = pl110_class_init,
 550 };
 551
 552 static const TypeInfo pl110_versatile_info = {
 553     .name          = "pl110_versatile",
 554     .parent        = TYPE_PL110,
 555     .instance_init = pl110_versatile_init,
 556 };
 557
 558 static const TypeInfo pl111_info = {
 559     .name          = "pl111",
 560     .parent        = TYPE_PL110,
 561     .instance_init = pl111_init,
 562 };
 563
 564 static void pl110_register_types(void)
 565 {
 566     type_register_static(&pl110_info);
 567     type_register_static(&pl110_versatile_info);
 568     type_register_static(&pl111_info);
 569 }
 570
 571 type_init(pl110_register_types)