2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
24 #include "qemu-common.h"
25 #include "qemu/timer.h"
26 #include "qemu/queue.h"
27 #include "qemu/atomic.h"
28 #include "sysemu/sysemu.h"
29 #include "migration/blocker.h"
35 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
36 * such can be changed by the guest, so to avoid a guest trigerrable
37 * abort we just qxl_set_guest_bug and set the return to NULL. Still
38 * it may happen as a result of emulator bug as well.
40 #undef SPICE_RING_PROD_ITEM
41 #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
42 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
43 if (prod >= ARRAY_SIZE((r)->items)) { \
44 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
45 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \
48 ret = &(r)->items[prod].el; \
52 #undef SPICE_RING_CONS_ITEM
53 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
54 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
55 if (cons >= ARRAY_SIZE((r)->items)) { \
56 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
57 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
60 ret = &(r)->items[cons].el; \
65 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
67 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
69 #define QXL_MODE(_x, _y, _b, _o) \
73 .stride = (_x) * (_b) / 8, \
74 .x_mili = PIXEL_SIZE * (_x), \
75 .y_mili = PIXEL_SIZE * (_y), \
79 #define QXL_MODE_16_32(x_res, y_res, orientation) \
80 QXL_MODE(x_res, y_res, 16, orientation), \
81 QXL_MODE(x_res, y_res, 32, orientation)
83 #define QXL_MODE_EX(x_res, y_res) \
84 QXL_MODE_16_32(x_res, y_res, 0), \
85 QXL_MODE_16_32(x_res, y_res, 1)
87 static QXLMode qxl_modes
[] = {
88 QXL_MODE_EX(640, 480),
89 QXL_MODE_EX(800, 480),
90 QXL_MODE_EX(800, 600),
91 QXL_MODE_EX(832, 624),
92 QXL_MODE_EX(960, 640),
93 QXL_MODE_EX(1024, 600),
94 QXL_MODE_EX(1024, 768),
95 QXL_MODE_EX(1152, 864),
96 QXL_MODE_EX(1152, 870),
97 QXL_MODE_EX(1280, 720),
98 QXL_MODE_EX(1280, 760),
99 QXL_MODE_EX(1280, 768),
100 QXL_MODE_EX(1280, 800),
101 QXL_MODE_EX(1280, 960),
102 QXL_MODE_EX(1280, 1024),
103 QXL_MODE_EX(1360, 768),
104 QXL_MODE_EX(1366, 768),
105 QXL_MODE_EX(1400, 1050),
106 QXL_MODE_EX(1440, 900),
107 QXL_MODE_EX(1600, 900),
108 QXL_MODE_EX(1600, 1200),
109 QXL_MODE_EX(1680, 1050),
110 QXL_MODE_EX(1920, 1080),
111 /* these modes need more than 8 MB video memory */
112 QXL_MODE_EX(1920, 1200),
113 QXL_MODE_EX(1920, 1440),
114 QXL_MODE_EX(2000, 2000),
115 QXL_MODE_EX(2048, 1536),
116 QXL_MODE_EX(2048, 2048),
117 QXL_MODE_EX(2560, 1440),
118 QXL_MODE_EX(2560, 1600),
119 /* these modes need more than 16 MB video memory */
120 QXL_MODE_EX(2560, 2048),
121 QXL_MODE_EX(2800, 2100),
122 QXL_MODE_EX(3200, 2400),
123 /* these modes need more than 32 MB video memory */
124 QXL_MODE_EX(3840, 2160), /* 4k mainstream */
125 QXL_MODE_EX(4096, 2160), /* 4k */
126 /* these modes need more than 64 MB video memory */
127 QXL_MODE_EX(7680, 4320), /* 8k mainstream */
128 /* these modes need more than 128 MB video memory */
129 QXL_MODE_EX(8192, 4320), /* 8k */
132 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
);
133 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
);
134 static void qxl_reset_memslots(PCIQXLDevice
*d
);
135 static void qxl_reset_surfaces(PCIQXLDevice
*d
);
136 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
);
138 static void qxl_hw_update(void *opaque
);
140 void qxl_set_guest_bug(PCIQXLDevice
*qxl
, const char *msg
, ...)
142 trace_qxl_set_guest_bug(qxl
->id
);
143 qxl_send_events(qxl
, QXL_INTERRUPT_ERROR
);
145 if (qxl
->guestdebug
) {
148 fprintf(stderr
, "qxl-%d: guest bug: ", qxl
->id
);
149 vfprintf(stderr
, msg
, ap
);
150 fprintf(stderr
, "\n");
155 static void qxl_clear_guest_bug(PCIQXLDevice
*qxl
)
160 void qxl_spice_update_area(PCIQXLDevice
*qxl
, uint32_t surface_id
,
161 struct QXLRect
*area
, struct QXLRect
*dirty_rects
,
162 uint32_t num_dirty_rects
,
163 uint32_t clear_dirty_region
,
164 qxl_async_io async
, struct QXLCookie
*cookie
)
166 trace_qxl_spice_update_area(qxl
->id
, surface_id
, area
->left
, area
->right
,
167 area
->top
, area
->bottom
);
168 trace_qxl_spice_update_area_rest(qxl
->id
, num_dirty_rects
,
170 if (async
== QXL_SYNC
) {
171 spice_qxl_update_area(&qxl
->ssd
.qxl
, surface_id
, area
,
172 dirty_rects
, num_dirty_rects
, clear_dirty_region
);
174 assert(cookie
!= NULL
);
175 spice_qxl_update_area_async(&qxl
->ssd
.qxl
, surface_id
, area
,
176 clear_dirty_region
, (uintptr_t)cookie
);
180 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice
*qxl
,
183 trace_qxl_spice_destroy_surface_wait_complete(qxl
->id
, id
);
184 qemu_mutex_lock(&qxl
->track_lock
);
185 qxl
->guest_surfaces
.cmds
[id
] = 0;
186 qxl
->guest_surfaces
.count
--;
187 qemu_mutex_unlock(&qxl
->track_lock
);
190 static void qxl_spice_destroy_surface_wait(PCIQXLDevice
*qxl
, uint32_t id
,
195 trace_qxl_spice_destroy_surface_wait(qxl
->id
, id
, async
);
197 cookie
= qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
198 QXL_IO_DESTROY_SURFACE_ASYNC
);
199 cookie
->u
.surface_id
= id
;
200 spice_qxl_destroy_surface_async(&qxl
->ssd
.qxl
, id
, (uintptr_t)cookie
);
202 spice_qxl_destroy_surface_wait(&qxl
->ssd
.qxl
, id
);
203 qxl_spice_destroy_surface_wait_complete(qxl
, id
);
207 static void qxl_spice_flush_surfaces_async(PCIQXLDevice
*qxl
)
209 trace_qxl_spice_flush_surfaces_async(qxl
->id
, qxl
->guest_surfaces
.count
,
211 spice_qxl_flush_surfaces_async(&qxl
->ssd
.qxl
,
212 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
213 QXL_IO_FLUSH_SURFACES_ASYNC
));
216 void qxl_spice_loadvm_commands(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
,
219 trace_qxl_spice_loadvm_commands(qxl
->id
, ext
, count
);
220 spice_qxl_loadvm_commands(&qxl
->ssd
.qxl
, ext
, count
);
223 void qxl_spice_oom(PCIQXLDevice
*qxl
)
225 trace_qxl_spice_oom(qxl
->id
);
226 spice_qxl_oom(&qxl
->ssd
.qxl
);
229 void qxl_spice_reset_memslots(PCIQXLDevice
*qxl
)
231 trace_qxl_spice_reset_memslots(qxl
->id
);
232 spice_qxl_reset_memslots(&qxl
->ssd
.qxl
);
235 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice
*qxl
)
237 trace_qxl_spice_destroy_surfaces_complete(qxl
->id
);
238 qemu_mutex_lock(&qxl
->track_lock
);
239 memset(qxl
->guest_surfaces
.cmds
, 0,
240 sizeof(qxl
->guest_surfaces
.cmds
[0]) * qxl
->ssd
.num_surfaces
);
241 qxl
->guest_surfaces
.count
= 0;
242 qemu_mutex_unlock(&qxl
->track_lock
);
245 static void qxl_spice_destroy_surfaces(PCIQXLDevice
*qxl
, qxl_async_io async
)
247 trace_qxl_spice_destroy_surfaces(qxl
->id
, async
);
249 spice_qxl_destroy_surfaces_async(&qxl
->ssd
.qxl
,
250 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
251 QXL_IO_DESTROY_ALL_SURFACES_ASYNC
));
253 spice_qxl_destroy_surfaces(&qxl
->ssd
.qxl
);
254 qxl_spice_destroy_surfaces_complete(qxl
);
258 static void qxl_spice_monitors_config_async(PCIQXLDevice
*qxl
, int replay
)
260 trace_qxl_spice_monitors_config(qxl
->id
);
263 * don't use QXL_COOKIE_TYPE_IO:
264 * - we are not running yet (post_load), we will assert
266 * - this is not a guest io, but a reply, so async_io isn't set.
268 spice_qxl_monitors_config_async(&qxl
->ssd
.qxl
,
269 qxl
->guest_monitors_config
,
271 (uintptr_t)qxl_cookie_new(
272 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG
,
275 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
276 if (qxl
->max_outputs
) {
277 spice_qxl_set_max_monitors(&qxl
->ssd
.qxl
, qxl
->max_outputs
);
280 qxl
->guest_monitors_config
= qxl
->ram
->monitors_config
;
281 spice_qxl_monitors_config_async(&qxl
->ssd
.qxl
,
282 qxl
->ram
->monitors_config
,
284 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
285 QXL_IO_MONITORS_CONFIG_ASYNC
));
289 void qxl_spice_reset_image_cache(PCIQXLDevice
*qxl
)
291 trace_qxl_spice_reset_image_cache(qxl
->id
);
292 spice_qxl_reset_image_cache(&qxl
->ssd
.qxl
);
295 void qxl_spice_reset_cursor(PCIQXLDevice
*qxl
)
297 trace_qxl_spice_reset_cursor(qxl
->id
);
298 spice_qxl_reset_cursor(&qxl
->ssd
.qxl
);
299 qemu_mutex_lock(&qxl
->track_lock
);
300 qxl
->guest_cursor
= 0;
301 qemu_mutex_unlock(&qxl
->track_lock
);
302 if (qxl
->ssd
.cursor
) {
303 cursor_put(qxl
->ssd
.cursor
);
305 qxl
->ssd
.cursor
= cursor_builtin_hidden();
308 static uint32_t qxl_crc32(const uint8_t *p
, unsigned len
)
311 * zlib xors the seed with 0xffffffff, and xors the result
312 * again with 0xffffffff; Both are not done with linux's crc32,
313 * which we want to be compatible with, so undo that.
315 return crc32(0xffffffff, p
, len
) ^ 0xffffffff;
318 static ram_addr_t
qxl_rom_size(void)
320 #define QXL_REQUIRED_SZ (sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes))
321 #define QXL_ROM_SZ 8192
323 QEMU_BUILD_BUG_ON(QXL_REQUIRED_SZ
> QXL_ROM_SZ
);
327 static void init_qxl_rom(PCIQXLDevice
*d
)
329 QXLRom
*rom
= memory_region_get_ram_ptr(&d
->rom_bar
);
330 QXLModes
*modes
= (QXLModes
*)(rom
+ 1);
331 uint32_t ram_header_size
;
332 uint32_t surface0_area_size
;
337 memset(rom
, 0, d
->rom_size
);
339 rom
->magic
= cpu_to_le32(QXL_ROM_MAGIC
);
340 rom
->id
= cpu_to_le32(d
->id
);
341 rom
->log_level
= cpu_to_le32(d
->guestdebug
);
342 rom
->modes_offset
= cpu_to_le32(sizeof(QXLRom
));
344 rom
->slot_gen_bits
= MEMSLOT_GENERATION_BITS
;
345 rom
->slot_id_bits
= MEMSLOT_SLOT_BITS
;
346 rom
->slots_start
= 1;
347 rom
->slots_end
= NUM_MEMSLOTS
- 1;
348 rom
->n_surfaces
= cpu_to_le32(d
->ssd
.num_surfaces
);
350 for (i
= 0, n
= 0; i
< ARRAY_SIZE(qxl_modes
); i
++) {
351 fb
= qxl_modes
[i
].y_res
* qxl_modes
[i
].stride
;
352 if (fb
> d
->vgamem_size
) {
355 modes
->modes
[n
].id
= cpu_to_le32(i
);
356 modes
->modes
[n
].x_res
= cpu_to_le32(qxl_modes
[i
].x_res
);
357 modes
->modes
[n
].y_res
= cpu_to_le32(qxl_modes
[i
].y_res
);
358 modes
->modes
[n
].bits
= cpu_to_le32(qxl_modes
[i
].bits
);
359 modes
->modes
[n
].stride
= cpu_to_le32(qxl_modes
[i
].stride
);
360 modes
->modes
[n
].x_mili
= cpu_to_le32(qxl_modes
[i
].x_mili
);
361 modes
->modes
[n
].y_mili
= cpu_to_le32(qxl_modes
[i
].y_mili
);
362 modes
->modes
[n
].orientation
= cpu_to_le32(qxl_modes
[i
].orientation
);
365 modes
->n_modes
= cpu_to_le32(n
);
367 ram_header_size
= ALIGN(sizeof(QXLRam
), 4096);
368 surface0_area_size
= ALIGN(d
->vgamem_size
, 4096);
369 num_pages
= d
->vga
.vram_size
;
370 num_pages
-= ram_header_size
;
371 num_pages
-= surface0_area_size
;
372 num_pages
= num_pages
/ QXL_PAGE_SIZE
;
374 assert(ram_header_size
+ surface0_area_size
<= d
->vga
.vram_size
);
376 rom
->draw_area_offset
= cpu_to_le32(0);
377 rom
->surface0_area_size
= cpu_to_le32(surface0_area_size
);
378 rom
->pages_offset
= cpu_to_le32(surface0_area_size
);
379 rom
->num_pages
= cpu_to_le32(num_pages
);
380 rom
->ram_header_offset
= cpu_to_le32(d
->vga
.vram_size
- ram_header_size
);
382 if (d
->xres
&& d
->yres
) {
383 /* needs linux kernel 4.12+ to work */
384 rom
->client_monitors_config
.count
= 1;
385 rom
->client_monitors_config
.heads
[0].left
= 0;
386 rom
->client_monitors_config
.heads
[0].top
= 0;
387 rom
->client_monitors_config
.heads
[0].right
= cpu_to_le32(d
->xres
);
388 rom
->client_monitors_config
.heads
[0].bottom
= cpu_to_le32(d
->yres
);
389 rom
->client_monitors_config_crc
= qxl_crc32(
390 (const uint8_t *)&rom
->client_monitors_config
,
391 sizeof(rom
->client_monitors_config
));
394 d
->shadow_rom
= *rom
;
399 static void init_qxl_ram(PCIQXLDevice
*d
)
404 buf
= d
->vga
.vram_ptr
;
405 d
->ram
= (QXLRam
*)(buf
+ le32_to_cpu(d
->shadow_rom
.ram_header_offset
));
406 d
->ram
->magic
= cpu_to_le32(QXL_RAM_MAGIC
);
407 d
->ram
->int_pending
= cpu_to_le32(0);
408 d
->ram
->int_mask
= cpu_to_le32(0);
409 d
->ram
->update_surface
= 0;
410 d
->ram
->monitors_config
= 0;
411 SPICE_RING_INIT(&d
->ram
->cmd_ring
);
412 SPICE_RING_INIT(&d
->ram
->cursor_ring
);
413 SPICE_RING_INIT(&d
->ram
->release_ring
);
414 SPICE_RING_PROD_ITEM(d
, &d
->ram
->release_ring
, item
);
417 qxl_ring_set_dirty(d
);
420 /* can be called from spice server thread context */
421 static void qxl_set_dirty(MemoryRegion
*mr
, ram_addr_t addr
, ram_addr_t end
)
423 memory_region_set_dirty(mr
, addr
, end
- addr
);
426 static void qxl_rom_set_dirty(PCIQXLDevice
*qxl
)
428 qxl_set_dirty(&qxl
->rom_bar
, 0, qxl
->rom_size
);
431 /* called from spice server thread context only */
432 static void qxl_ram_set_dirty(PCIQXLDevice
*qxl
, void *ptr
)
434 void *base
= qxl
->vga
.vram_ptr
;
438 assert(offset
< qxl
->vga
.vram_size
);
439 qxl_set_dirty(&qxl
->vga
.vram
, offset
, offset
+ 3);
442 /* can be called from spice server thread context */
443 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
)
445 ram_addr_t addr
= qxl
->shadow_rom
.ram_header_offset
;
446 ram_addr_t end
= qxl
->vga
.vram_size
;
447 qxl_set_dirty(&qxl
->vga
.vram
, addr
, end
);
451 * keep track of some command state, for savevm/loadvm.
452 * called from spice server thread context only
454 static int qxl_track_command(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
)
456 switch (le32_to_cpu(ext
->cmd
.type
)) {
457 case QXL_CMD_SURFACE
:
459 QXLSurfaceCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
464 uint32_t id
= le32_to_cpu(cmd
->surface_id
);
466 if (id
>= qxl
->ssd
.num_surfaces
) {
467 qxl_set_guest_bug(qxl
, "QXL_CMD_SURFACE id %d >= %d", id
,
468 qxl
->ssd
.num_surfaces
);
471 if (cmd
->type
== QXL_SURFACE_CMD_CREATE
&&
472 (cmd
->u
.surface_create
.stride
& 0x03) != 0) {
473 qxl_set_guest_bug(qxl
, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
474 cmd
->u
.surface_create
.stride
);
477 qemu_mutex_lock(&qxl
->track_lock
);
478 if (cmd
->type
== QXL_SURFACE_CMD_CREATE
) {
479 qxl
->guest_surfaces
.cmds
[id
] = ext
->cmd
.data
;
480 qxl
->guest_surfaces
.count
++;
481 if (qxl
->guest_surfaces
.max
< qxl
->guest_surfaces
.count
)
482 qxl
->guest_surfaces
.max
= qxl
->guest_surfaces
.count
;
484 if (cmd
->type
== QXL_SURFACE_CMD_DESTROY
) {
485 qxl
->guest_surfaces
.cmds
[id
] = 0;
486 qxl
->guest_surfaces
.count
--;
488 qemu_mutex_unlock(&qxl
->track_lock
);
493 QXLCursorCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
498 if (cmd
->type
== QXL_CURSOR_SET
) {
499 qemu_mutex_lock(&qxl
->track_lock
);
500 qxl
->guest_cursor
= ext
->cmd
.data
;
501 qemu_mutex_unlock(&qxl
->track_lock
);
503 if (cmd
->type
== QXL_CURSOR_HIDE
) {
504 qemu_mutex_lock(&qxl
->track_lock
);
505 qxl
->guest_cursor
= 0;
506 qemu_mutex_unlock(&qxl
->track_lock
);
514 /* spice display interface callbacks */
516 static void interface_attach_worker(QXLInstance
*sin
, QXLWorker
*qxl_worker
)
518 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
520 trace_qxl_interface_attach_worker(qxl
->id
);
521 qxl
->ssd
.worker
= qxl_worker
;
524 static void interface_set_compression_level(QXLInstance
*sin
, int level
)
526 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
528 trace_qxl_interface_set_compression_level(qxl
->id
, level
);
529 qxl
->shadow_rom
.compression_level
= cpu_to_le32(level
);
530 qxl
->rom
->compression_level
= cpu_to_le32(level
);
531 qxl_rom_set_dirty(qxl
);
534 #if SPICE_NEEDS_SET_MM_TIME
535 static void interface_set_mm_time(QXLInstance
*sin
, uint32_t mm_time
)
537 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
539 if (!qemu_spice_display_is_running(&qxl
->ssd
)) {
543 trace_qxl_interface_set_mm_time(qxl
->id
, mm_time
);
544 qxl
->shadow_rom
.mm_clock
= cpu_to_le32(mm_time
);
545 qxl
->rom
->mm_clock
= cpu_to_le32(mm_time
);
546 qxl_rom_set_dirty(qxl
);
550 static void interface_get_init_info(QXLInstance
*sin
, QXLDevInitInfo
*info
)
552 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
554 trace_qxl_interface_get_init_info(qxl
->id
);
555 info
->memslot_gen_bits
= MEMSLOT_GENERATION_BITS
;
556 info
->memslot_id_bits
= MEMSLOT_SLOT_BITS
;
557 info
->num_memslots
= NUM_MEMSLOTS
;
558 info
->num_memslots_groups
= NUM_MEMSLOTS_GROUPS
;
559 info
->internal_groupslot_id
= 0;
561 le32_to_cpu(qxl
->shadow_rom
.num_pages
) << QXL_PAGE_BITS
;
562 info
->n_surfaces
= qxl
->ssd
.num_surfaces
;
565 static const char *qxl_mode_to_string(int mode
)
568 case QXL_MODE_COMPAT
:
570 case QXL_MODE_NATIVE
:
572 case QXL_MODE_UNDEFINED
:
580 static const char *io_port_to_string(uint32_t io_port
)
582 if (io_port
>= QXL_IO_RANGE_SIZE
) {
583 return "out of range";
585 static const char *io_port_to_string
[QXL_IO_RANGE_SIZE
+ 1] = {
586 [QXL_IO_NOTIFY_CMD
] = "QXL_IO_NOTIFY_CMD",
587 [QXL_IO_NOTIFY_CURSOR
] = "QXL_IO_NOTIFY_CURSOR",
588 [QXL_IO_UPDATE_AREA
] = "QXL_IO_UPDATE_AREA",
589 [QXL_IO_UPDATE_IRQ
] = "QXL_IO_UPDATE_IRQ",
590 [QXL_IO_NOTIFY_OOM
] = "QXL_IO_NOTIFY_OOM",
591 [QXL_IO_RESET
] = "QXL_IO_RESET",
592 [QXL_IO_SET_MODE
] = "QXL_IO_SET_MODE",
593 [QXL_IO_LOG
] = "QXL_IO_LOG",
594 [QXL_IO_MEMSLOT_ADD
] = "QXL_IO_MEMSLOT_ADD",
595 [QXL_IO_MEMSLOT_DEL
] = "QXL_IO_MEMSLOT_DEL",
596 [QXL_IO_DETACH_PRIMARY
] = "QXL_IO_DETACH_PRIMARY",
597 [QXL_IO_ATTACH_PRIMARY
] = "QXL_IO_ATTACH_PRIMARY",
598 [QXL_IO_CREATE_PRIMARY
] = "QXL_IO_CREATE_PRIMARY",
599 [QXL_IO_DESTROY_PRIMARY
] = "QXL_IO_DESTROY_PRIMARY",
600 [QXL_IO_DESTROY_SURFACE_WAIT
] = "QXL_IO_DESTROY_SURFACE_WAIT",
601 [QXL_IO_DESTROY_ALL_SURFACES
] = "QXL_IO_DESTROY_ALL_SURFACES",
602 [QXL_IO_UPDATE_AREA_ASYNC
] = "QXL_IO_UPDATE_AREA_ASYNC",
603 [QXL_IO_MEMSLOT_ADD_ASYNC
] = "QXL_IO_MEMSLOT_ADD_ASYNC",
604 [QXL_IO_CREATE_PRIMARY_ASYNC
] = "QXL_IO_CREATE_PRIMARY_ASYNC",
605 [QXL_IO_DESTROY_PRIMARY_ASYNC
] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
606 [QXL_IO_DESTROY_SURFACE_ASYNC
] = "QXL_IO_DESTROY_SURFACE_ASYNC",
607 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC
]
608 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
609 [QXL_IO_FLUSH_SURFACES_ASYNC
] = "QXL_IO_FLUSH_SURFACES_ASYNC",
610 [QXL_IO_FLUSH_RELEASE
] = "QXL_IO_FLUSH_RELEASE",
611 [QXL_IO_MONITORS_CONFIG_ASYNC
] = "QXL_IO_MONITORS_CONFIG_ASYNC",
613 return io_port_to_string
[io_port
];
616 /* called from spice server thread context only */
617 static int interface_get_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
619 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
620 SimpleSpiceUpdate
*update
;
621 QXLCommandRing
*ring
;
625 trace_qxl_ring_command_check(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
630 qemu_mutex_lock(&qxl
->ssd
.lock
);
631 update
= QTAILQ_FIRST(&qxl
->ssd
.updates
);
632 if (update
!= NULL
) {
633 QTAILQ_REMOVE(&qxl
->ssd
.updates
, update
, next
);
637 qemu_mutex_unlock(&qxl
->ssd
.lock
);
639 trace_qxl_ring_command_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
640 qxl_log_command(qxl
, "vga", ext
);
643 case QXL_MODE_COMPAT
:
644 case QXL_MODE_NATIVE
:
645 case QXL_MODE_UNDEFINED
:
646 ring
= &qxl
->ram
->cmd_ring
;
647 if (qxl
->guest_bug
|| SPICE_RING_IS_EMPTY(ring
)) {
650 SPICE_RING_CONS_ITEM(qxl
, ring
, cmd
);
655 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
656 ext
->flags
= qxl
->cmdflags
;
657 SPICE_RING_POP(ring
, notify
);
658 qxl_ring_set_dirty(qxl
);
660 qxl_send_events(qxl
, QXL_INTERRUPT_DISPLAY
);
662 qxl
->guest_primary
.commands
++;
663 qxl_track_command(qxl
, ext
);
664 qxl_log_command(qxl
, "cmd", ext
);
667 * Windows 8 drivers place qxl commands in the vram
668 * (instead of the ram) bar. We can't live migrate such a
669 * guest, so add a migration blocker in case we detect
670 * this, to avoid triggering the assert in pre_save().
672 * https://cgit.freedesktop.org/spice/win32/qxl-wddm-dod/commit/?id=f6e099db39e7d0787f294d5fd0dce328b5210faa
674 void *msg
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
676 msg
< (void *)qxl
->vga
.vram_ptr
||
677 msg
> ((void *)qxl
->vga
.vram_ptr
+ qxl
->vga
.vram_size
))) {
678 if (!qxl
->migration_blocker
) {
679 Error
*local_err
= NULL
;
680 error_setg(&qxl
->migration_blocker
,
681 "qxl: guest bug: command not in ram bar");
682 migrate_add_blocker(qxl
->migration_blocker
, &local_err
);
684 error_report_err(local_err
);
689 trace_qxl_ring_command_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
696 /* called from spice server thread context only */
697 static int interface_req_cmd_notification(QXLInstance
*sin
)
699 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
702 trace_qxl_ring_command_req_notification(qxl
->id
);
704 case QXL_MODE_COMPAT
:
705 case QXL_MODE_NATIVE
:
706 case QXL_MODE_UNDEFINED
:
707 SPICE_RING_CONS_WAIT(&qxl
->ram
->cmd_ring
, wait
);
708 qxl_ring_set_dirty(qxl
);
717 /* called from spice server thread context only */
718 static inline void qxl_push_free_res(PCIQXLDevice
*d
, int flush
)
720 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
724 #define QXL_FREE_BUNCH_SIZE 32
726 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
727 /* ring full -- can't push */
730 if (!flush
&& d
->oom_running
) {
731 /* collect everything from oom handler before pushing */
734 if (!flush
&& d
->num_free_res
< QXL_FREE_BUNCH_SIZE
) {
735 /* collect a bit more before pushing */
739 SPICE_RING_PUSH(ring
, notify
);
740 trace_qxl_ring_res_push(d
->id
, qxl_mode_to_string(d
->mode
),
741 d
->guest_surfaces
.count
, d
->num_free_res
,
742 d
->last_release
, notify
? "yes" : "no");
743 trace_qxl_ring_res_push_rest(d
->id
, ring
->prod
- ring
->cons
,
744 ring
->num_items
, ring
->prod
, ring
->cons
);
746 qxl_send_events(d
, QXL_INTERRUPT_DISPLAY
);
748 SPICE_RING_PROD_ITEM(d
, ring
, item
);
754 d
->last_release
= NULL
;
755 qxl_ring_set_dirty(d
);
758 /* called from spice server thread context only */
759 static void interface_release_resource(QXLInstance
*sin
,
760 QXLReleaseInfoExt ext
)
762 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
763 QXLReleaseRing
*ring
;
766 if (ext
.group_id
== MEMSLOT_GROUP_HOST
) {
767 /* host group -> vga mode update request */
768 QXLCommandExt
*cmdext
= (void *)(intptr_t)(ext
.info
->id
);
769 SimpleSpiceUpdate
*update
;
770 g_assert(cmdext
->cmd
.type
== QXL_CMD_DRAW
);
771 update
= container_of(cmdext
, SimpleSpiceUpdate
, ext
);
772 qemu_spice_destroy_update(&qxl
->ssd
, update
);
777 * ext->info points into guest-visible memory
778 * pci bar 0, $command.release_info
780 ring
= &qxl
->ram
->release_ring
;
781 SPICE_RING_PROD_ITEM(qxl
, ring
, item
);
786 /* stick head into the ring */
789 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
791 qxl_ring_set_dirty(qxl
);
793 /* append item to the list */
794 qxl
->last_release
->next
= ext
.info
->id
;
795 qxl_ram_set_dirty(qxl
, &qxl
->last_release
->next
);
797 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
799 qxl
->last_release
= ext
.info
;
801 trace_qxl_ring_res_put(qxl
->id
, qxl
->num_free_res
);
802 qxl_push_free_res(qxl
, 0);
805 /* called from spice server thread context only */
806 static int interface_get_cursor_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
808 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
813 trace_qxl_ring_cursor_check(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
816 case QXL_MODE_COMPAT
:
817 case QXL_MODE_NATIVE
:
818 case QXL_MODE_UNDEFINED
:
819 ring
= &qxl
->ram
->cursor_ring
;
820 if (SPICE_RING_IS_EMPTY(ring
)) {
823 SPICE_RING_CONS_ITEM(qxl
, ring
, cmd
);
828 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
829 ext
->flags
= qxl
->cmdflags
;
830 SPICE_RING_POP(ring
, notify
);
831 qxl_ring_set_dirty(qxl
);
833 qxl_send_events(qxl
, QXL_INTERRUPT_CURSOR
);
835 qxl
->guest_primary
.commands
++;
836 qxl_track_command(qxl
, ext
);
837 qxl_log_command(qxl
, "csr", ext
);
839 qxl_render_cursor(qxl
, ext
);
841 trace_qxl_ring_cursor_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
848 /* called from spice server thread context only */
849 static int interface_req_cursor_notification(QXLInstance
*sin
)
851 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
854 trace_qxl_ring_cursor_req_notification(qxl
->id
);
856 case QXL_MODE_COMPAT
:
857 case QXL_MODE_NATIVE
:
858 case QXL_MODE_UNDEFINED
:
859 SPICE_RING_CONS_WAIT(&qxl
->ram
->cursor_ring
, wait
);
860 qxl_ring_set_dirty(qxl
);
869 /* called from spice server thread context */
870 static void interface_notify_update(QXLInstance
*sin
, uint32_t update_id
)
873 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
874 * use by xf86-video-qxl and is defined out in the qxl windows driver.
875 * Probably was at some earlier version that is prior to git start (2009),
876 * and is still guest trigerrable.
878 fprintf(stderr
, "%s: deprecated\n", __func__
);
881 /* called from spice server thread context only */
882 static int interface_flush_resources(QXLInstance
*sin
)
884 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
887 ret
= qxl
->num_free_res
;
889 qxl_push_free_res(qxl
, 1);
894 static void qxl_create_guest_primary_complete(PCIQXLDevice
*d
);
896 /* called from spice server thread context only */
897 static void interface_async_complete_io(PCIQXLDevice
*qxl
, QXLCookie
*cookie
)
899 uint32_t current_async
;
901 qemu_mutex_lock(&qxl
->async_lock
);
902 current_async
= qxl
->current_async
;
903 qxl
->current_async
= QXL_UNDEFINED_IO
;
904 qemu_mutex_unlock(&qxl
->async_lock
);
906 trace_qxl_interface_async_complete_io(qxl
->id
, current_async
, cookie
);
908 fprintf(stderr
, "qxl: %s: error, cookie is NULL\n", __func__
);
911 if (cookie
&& current_async
!= cookie
->io
) {
913 "qxl: %s: error: current_async = %d != %"
914 PRId64
" = cookie->io\n", __func__
, current_async
, cookie
->io
);
916 switch (current_async
) {
917 case QXL_IO_MEMSLOT_ADD_ASYNC
:
918 case QXL_IO_DESTROY_PRIMARY_ASYNC
:
919 case QXL_IO_UPDATE_AREA_ASYNC
:
920 case QXL_IO_FLUSH_SURFACES_ASYNC
:
921 case QXL_IO_MONITORS_CONFIG_ASYNC
:
923 case QXL_IO_CREATE_PRIMARY_ASYNC
:
924 qxl_create_guest_primary_complete(qxl
);
926 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
927 qxl_spice_destroy_surfaces_complete(qxl
);
929 case QXL_IO_DESTROY_SURFACE_ASYNC
:
930 qxl_spice_destroy_surface_wait_complete(qxl
, cookie
->u
.surface_id
);
933 fprintf(stderr
, "qxl: %s: unexpected current_async %d\n", __func__
,
936 qxl_send_events(qxl
, QXL_INTERRUPT_IO_CMD
);
939 /* called from spice server thread context only */
940 static void interface_update_area_complete(QXLInstance
*sin
,
942 QXLRect
*dirty
, uint32_t num_updated_rects
)
944 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
948 qemu_mutex_lock(&qxl
->ssd
.lock
);
949 if (surface_id
!= 0 || !num_updated_rects
||
950 !qxl
->render_update_cookie_num
) {
951 qemu_mutex_unlock(&qxl
->ssd
.lock
);
954 trace_qxl_interface_update_area_complete(qxl
->id
, surface_id
, dirty
->left
,
955 dirty
->right
, dirty
->top
, dirty
->bottom
);
956 trace_qxl_interface_update_area_complete_rest(qxl
->id
, num_updated_rects
);
957 if (qxl
->num_dirty_rects
+ num_updated_rects
> QXL_NUM_DIRTY_RECTS
) {
959 * overflow - treat this as a full update. Not expected to be common.
961 trace_qxl_interface_update_area_complete_overflow(qxl
->id
,
962 QXL_NUM_DIRTY_RECTS
);
963 qxl
->guest_primary
.resized
= 1;
965 if (qxl
->guest_primary
.resized
) {
967 * Don't bother copying or scheduling the bh since we will flip
968 * the whole area anyway on completion of the update_area async call
970 qemu_mutex_unlock(&qxl
->ssd
.lock
);
973 qxl_i
= qxl
->num_dirty_rects
;
974 for (i
= 0; i
< num_updated_rects
; i
++) {
975 qxl
->dirty
[qxl_i
++] = dirty
[i
];
977 qxl
->num_dirty_rects
+= num_updated_rects
;
978 trace_qxl_interface_update_area_complete_schedule_bh(qxl
->id
,
979 qxl
->num_dirty_rects
);
980 qemu_bh_schedule(qxl
->update_area_bh
);
981 qemu_mutex_unlock(&qxl
->ssd
.lock
);
984 /* called from spice server thread context only */
985 static void interface_async_complete(QXLInstance
*sin
, uint64_t cookie_token
)
987 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
988 QXLCookie
*cookie
= (QXLCookie
*)(uintptr_t)cookie_token
;
990 switch (cookie
->type
) {
991 case QXL_COOKIE_TYPE_IO
:
992 interface_async_complete_io(qxl
, cookie
);
995 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA
:
996 qxl_render_update_area_done(qxl
, cookie
);
998 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG
:
1001 fprintf(stderr
, "qxl: %s: unexpected cookie type %d\n",
1002 __func__
, cookie
->type
);
1007 /* called from spice server thread context only */
1008 static void interface_set_client_capabilities(QXLInstance
*sin
,
1009 uint8_t client_present
,
1012 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
1014 if (qxl
->revision
< 4) {
1015 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl
->id
,
1020 if (runstate_check(RUN_STATE_INMIGRATE
) ||
1021 runstate_check(RUN_STATE_POSTMIGRATE
)) {
1025 qxl
->shadow_rom
.client_present
= client_present
;
1026 memcpy(qxl
->shadow_rom
.client_capabilities
, caps
,
1027 sizeof(qxl
->shadow_rom
.client_capabilities
));
1028 qxl
->rom
->client_present
= client_present
;
1029 memcpy(qxl
->rom
->client_capabilities
, caps
,
1030 sizeof(qxl
->rom
->client_capabilities
));
1031 qxl_rom_set_dirty(qxl
);
1033 qxl_send_events(qxl
, QXL_INTERRUPT_CLIENT
);
1036 static bool qxl_rom_monitors_config_changed(QXLRom
*rom
,
1037 VDAgentMonitorsConfig
*monitors_config
,
1038 unsigned int max_outputs
)
1041 unsigned int monitors_count
;
1043 monitors_count
= MIN(monitors_config
->num_of_monitors
, max_outputs
);
1045 if (rom
->client_monitors_config
.count
!= monitors_count
) {
1049 for (i
= 0 ; i
< rom
->client_monitors_config
.count
; ++i
) {
1050 VDAgentMonConfig
*monitor
= &monitors_config
->monitors
[i
];
1051 QXLURect
*rect
= &rom
->client_monitors_config
.heads
[i
];
1052 /* monitor->depth ignored */
1053 if ((rect
->left
!= monitor
->x
) ||
1054 (rect
->top
!= monitor
->y
) ||
1055 (rect
->right
!= monitor
->x
+ monitor
->width
) ||
1056 (rect
->bottom
!= monitor
->y
+ monitor
->height
)) {
1064 /* called from main context only */
1065 static int interface_client_monitors_config(QXLInstance
*sin
,
1066 VDAgentMonitorsConfig
*monitors_config
)
1068 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
1069 QXLRom
*rom
= memory_region_get_ram_ptr(&qxl
->rom_bar
);
1071 unsigned max_outputs
= ARRAY_SIZE(rom
->client_monitors_config
.heads
);
1072 bool config_changed
= false;
1074 if (qxl
->revision
< 4) {
1075 trace_qxl_client_monitors_config_unsupported_by_device(qxl
->id
,
1080 * Older windows drivers set int_mask to 0 when their ISR is called,
1081 * then later set it to ~0. So it doesn't relate to the actual interrupts
1082 * handled. However, they are old, so clearly they don't support this
1085 if (qxl
->ram
->int_mask
== 0 || qxl
->ram
->int_mask
== ~0 ||
1086 !(qxl
->ram
->int_mask
& QXL_INTERRUPT_CLIENT_MONITORS_CONFIG
)) {
1087 trace_qxl_client_monitors_config_unsupported_by_guest(qxl
->id
,
1092 if (!monitors_config
) {
1096 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
1097 /* limit number of outputs based on setting limit */
1098 if (qxl
->max_outputs
&& qxl
->max_outputs
<= max_outputs
) {
1099 max_outputs
= qxl
->max_outputs
;
1103 config_changed
= qxl_rom_monitors_config_changed(rom
,
1107 memset(&rom
->client_monitors_config
, 0,
1108 sizeof(rom
->client_monitors_config
));
1109 rom
->client_monitors_config
.count
= monitors_config
->num_of_monitors
;
1110 /* monitors_config->flags ignored */
1111 if (rom
->client_monitors_config
.count
>= max_outputs
) {
1112 trace_qxl_client_monitors_config_capped(qxl
->id
,
1113 monitors_config
->num_of_monitors
,
1115 rom
->client_monitors_config
.count
= max_outputs
;
1117 for (i
= 0 ; i
< rom
->client_monitors_config
.count
; ++i
) {
1118 VDAgentMonConfig
*monitor
= &monitors_config
->monitors
[i
];
1119 QXLURect
*rect
= &rom
->client_monitors_config
.heads
[i
];
1120 /* monitor->depth ignored */
1121 rect
->left
= monitor
->x
;
1122 rect
->top
= monitor
->y
;
1123 rect
->right
= monitor
->x
+ monitor
->width
;
1124 rect
->bottom
= monitor
->y
+ monitor
->height
;
1126 rom
->client_monitors_config_crc
= qxl_crc32(
1127 (const uint8_t *)&rom
->client_monitors_config
,
1128 sizeof(rom
->client_monitors_config
));
1129 trace_qxl_client_monitors_config_crc(qxl
->id
,
1130 sizeof(rom
->client_monitors_config
),
1131 rom
->client_monitors_config_crc
);
1133 trace_qxl_interrupt_client_monitors_config(qxl
->id
,
1134 rom
->client_monitors_config
.count
,
1135 rom
->client_monitors_config
.heads
);
1136 if (config_changed
) {
1137 qxl_send_events(qxl
, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG
);
1142 static const QXLInterface qxl_interface
= {
1143 .base
.type
= SPICE_INTERFACE_QXL
,
1144 .base
.description
= "qxl gpu",
1145 .base
.major_version
= SPICE_INTERFACE_QXL_MAJOR
,
1146 .base
.minor_version
= SPICE_INTERFACE_QXL_MINOR
,
1148 .attache_worker
= interface_attach_worker
,
1149 .set_compression_level
= interface_set_compression_level
,
1150 #if SPICE_NEEDS_SET_MM_TIME
1151 .set_mm_time
= interface_set_mm_time
,
1153 .get_init_info
= interface_get_init_info
,
1155 /* the callbacks below are called from spice server thread context */
1156 .get_command
= interface_get_command
,
1157 .req_cmd_notification
= interface_req_cmd_notification
,
1158 .release_resource
= interface_release_resource
,
1159 .get_cursor_command
= interface_get_cursor_command
,
1160 .req_cursor_notification
= interface_req_cursor_notification
,
1161 .notify_update
= interface_notify_update
,
1162 .flush_resources
= interface_flush_resources
,
1163 .async_complete
= interface_async_complete
,
1164 .update_area_complete
= interface_update_area_complete
,
1165 .set_client_capabilities
= interface_set_client_capabilities
,
1166 .client_monitors_config
= interface_client_monitors_config
,
1169 static const GraphicHwOps qxl_ops
= {
1170 .gfx_update
= qxl_hw_update
,
1173 static void qxl_enter_vga_mode(PCIQXLDevice
*d
)
1175 if (d
->mode
== QXL_MODE_VGA
) {
1178 trace_qxl_enter_vga_mode(d
->id
);
1179 #if SPICE_SERVER_VERSION >= 0x000c03 /* release 0.12.3 */
1180 spice_qxl_driver_unload(&d
->ssd
.qxl
);
1182 graphic_console_set_hwops(d
->ssd
.dcl
.con
, d
->vga
.hw_ops
, &d
->vga
);
1183 update_displaychangelistener(&d
->ssd
.dcl
, GUI_REFRESH_INTERVAL_DEFAULT
);
1184 qemu_spice_create_host_primary(&d
->ssd
);
1185 d
->mode
= QXL_MODE_VGA
;
1186 qemu_spice_display_switch(&d
->ssd
, d
->ssd
.ds
);
1187 vga_dirty_log_start(&d
->vga
);
1188 graphic_hw_update(d
->vga
.con
);
1191 static void qxl_exit_vga_mode(PCIQXLDevice
*d
)
1193 if (d
->mode
!= QXL_MODE_VGA
) {
1196 trace_qxl_exit_vga_mode(d
->id
);
1197 graphic_console_set_hwops(d
->ssd
.dcl
.con
, &qxl_ops
, d
);
1198 update_displaychangelistener(&d
->ssd
.dcl
, GUI_REFRESH_INTERVAL_IDLE
);
1199 vga_dirty_log_stop(&d
->vga
);
1200 qxl_destroy_primary(d
, QXL_SYNC
);
1203 static void qxl_update_irq(PCIQXLDevice
*d
)
1205 uint32_t pending
= le32_to_cpu(d
->ram
->int_pending
);
1206 uint32_t mask
= le32_to_cpu(d
->ram
->int_mask
);
1207 int level
= !!(pending
& mask
);
1208 pci_set_irq(&d
->pci
, level
);
1209 qxl_ring_set_dirty(d
);
1212 static void qxl_check_state(PCIQXLDevice
*d
)
1214 QXLRam
*ram
= d
->ram
;
1215 int spice_display_running
= qemu_spice_display_is_running(&d
->ssd
);
1217 assert(!spice_display_running
|| SPICE_RING_IS_EMPTY(&ram
->cmd_ring
));
1218 assert(!spice_display_running
|| SPICE_RING_IS_EMPTY(&ram
->cursor_ring
));
1221 static void qxl_reset_state(PCIQXLDevice
*d
)
1223 QXLRom
*rom
= d
->rom
;
1226 d
->shadow_rom
.update_id
= cpu_to_le32(0);
1227 *rom
= d
->shadow_rom
;
1228 qxl_rom_set_dirty(d
);
1230 d
->num_free_res
= 0;
1231 d
->last_release
= NULL
;
1232 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
1236 static void qxl_soft_reset(PCIQXLDevice
*d
)
1238 trace_qxl_soft_reset(d
->id
);
1240 qxl_clear_guest_bug(d
);
1241 qemu_mutex_lock(&d
->async_lock
);
1242 d
->current_async
= QXL_UNDEFINED_IO
;
1243 qemu_mutex_unlock(&d
->async_lock
);
1246 qxl_enter_vga_mode(d
);
1248 d
->mode
= QXL_MODE_UNDEFINED
;
1252 static void qxl_hard_reset(PCIQXLDevice
*d
, int loadvm
)
1254 bool startstop
= qemu_spice_display_is_running(&d
->ssd
);
1256 trace_qxl_hard_reset(d
->id
, loadvm
);
1259 qemu_spice_display_stop();
1262 qxl_spice_reset_cursor(d
);
1263 qxl_spice_reset_image_cache(d
);
1264 qxl_reset_surfaces(d
);
1265 qxl_reset_memslots(d
);
1267 /* pre loadvm reset must not touch QXLRam. This lives in
1268 * device memory, is migrated together with RAM and thus
1269 * already loaded at this point */
1273 qemu_spice_create_host_memslot(&d
->ssd
);
1276 if (d
->migration_blocker
) {
1277 migrate_del_blocker(d
->migration_blocker
);
1278 error_free(d
->migration_blocker
);
1279 d
->migration_blocker
= NULL
;
1283 qemu_spice_display_start();
1287 static void qxl_reset_handler(DeviceState
*dev
)
1289 PCIQXLDevice
*d
= PCI_QXL(PCI_DEVICE(dev
));
1291 qxl_hard_reset(d
, 0);
1294 static void qxl_vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
1296 VGACommonState
*vga
= opaque
;
1297 PCIQXLDevice
*qxl
= container_of(vga
, PCIQXLDevice
, vga
);
1299 trace_qxl_io_write_vga(qxl
->id
, qxl_mode_to_string(qxl
->mode
), addr
, val
);
1300 if (qxl
->mode
!= QXL_MODE_VGA
) {
1301 qxl_destroy_primary(qxl
, QXL_SYNC
);
1302 qxl_soft_reset(qxl
);
1304 vga_ioport_write(opaque
, addr
, val
);
1307 static const MemoryRegionPortio qxl_vga_portio_list
[] = {
1308 { 0x04, 2, 1, .read
= vga_ioport_read
,
1309 .write
= qxl_vga_ioport_write
}, /* 3b4 */
1310 { 0x0a, 1, 1, .read
= vga_ioport_read
,
1311 .write
= qxl_vga_ioport_write
}, /* 3ba */
1312 { 0x10, 16, 1, .read
= vga_ioport_read
,
1313 .write
= qxl_vga_ioport_write
}, /* 3c0 */
1314 { 0x24, 2, 1, .read
= vga_ioport_read
,
1315 .write
= qxl_vga_ioport_write
}, /* 3d4 */
1316 { 0x2a, 1, 1, .read
= vga_ioport_read
,
1317 .write
= qxl_vga_ioport_write
}, /* 3da */
1318 PORTIO_END_OF_LIST(),
1321 static int qxl_add_memslot(PCIQXLDevice
*d
, uint32_t slot_id
, uint64_t delta
,
1324 static const int regions
[] = {
1325 QXL_RAM_RANGE_INDEX
,
1326 QXL_VRAM_RANGE_INDEX
,
1327 QXL_VRAM64_RANGE_INDEX
,
1329 uint64_t guest_start
;
1335 intptr_t virt_start
;
1336 QXLDevMemSlot memslot
;
1339 guest_start
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_start
);
1340 guest_end
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_end
);
1342 trace_qxl_memslot_add_guest(d
->id
, slot_id
, guest_start
, guest_end
);
1344 if (slot_id
>= NUM_MEMSLOTS
) {
1345 qxl_set_guest_bug(d
, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__
,
1346 slot_id
, NUM_MEMSLOTS
);
1349 if (guest_start
> guest_end
) {
1350 qxl_set_guest_bug(d
, "%s: guest_start > guest_end 0x%" PRIx64
1351 " > 0x%" PRIx64
, __func__
, guest_start
, guest_end
);
1355 for (i
= 0; i
< ARRAY_SIZE(regions
); i
++) {
1356 pci_region
= regions
[i
];
1357 pci_start
= d
->pci
.io_regions
[pci_region
].addr
;
1358 pci_end
= pci_start
+ d
->pci
.io_regions
[pci_region
].size
;
1360 if (pci_start
== -1) {
1363 /* start address in range ? */
1364 if (guest_start
< pci_start
|| guest_start
> pci_end
) {
1367 /* end address in range ? */
1368 if (guest_end
> pci_end
) {
1374 if (i
== ARRAY_SIZE(regions
)) {
1375 qxl_set_guest_bug(d
, "%s: finished loop without match", __func__
);
1379 switch (pci_region
) {
1380 case QXL_RAM_RANGE_INDEX
:
1383 case QXL_VRAM_RANGE_INDEX
:
1384 case 4 /* vram 64bit */:
1388 /* should not happen */
1389 qxl_set_guest_bug(d
, "%s: pci_region = %d", __func__
, pci_region
);
1393 virt_start
= (intptr_t)memory_region_get_ram_ptr(mr
);
1394 memslot
.slot_id
= slot_id
;
1395 memslot
.slot_group_id
= MEMSLOT_GROUP_GUEST
; /* guest group */
1396 memslot
.virt_start
= virt_start
+ (guest_start
- pci_start
);
1397 memslot
.virt_end
= virt_start
+ (guest_end
- pci_start
);
1398 memslot
.addr_delta
= memslot
.virt_start
- delta
;
1399 memslot
.generation
= d
->rom
->slot_generation
= 0;
1400 qxl_rom_set_dirty(d
);
1402 qemu_spice_add_memslot(&d
->ssd
, &memslot
, async
);
1403 d
->guest_slots
[slot_id
].mr
= mr
;
1404 d
->guest_slots
[slot_id
].offset
= memslot
.virt_start
- virt_start
;
1405 d
->guest_slots
[slot_id
].size
= memslot
.virt_end
- memslot
.virt_start
;
1406 d
->guest_slots
[slot_id
].delta
= delta
;
1407 d
->guest_slots
[slot_id
].active
= 1;
1411 static void qxl_del_memslot(PCIQXLDevice
*d
, uint32_t slot_id
)
1413 qemu_spice_del_memslot(&d
->ssd
, MEMSLOT_GROUP_HOST
, slot_id
);
1414 d
->guest_slots
[slot_id
].active
= 0;
1417 static void qxl_reset_memslots(PCIQXLDevice
*d
)
1419 qxl_spice_reset_memslots(d
);
1420 memset(&d
->guest_slots
, 0, sizeof(d
->guest_slots
));
1423 static void qxl_reset_surfaces(PCIQXLDevice
*d
)
1425 trace_qxl_reset_surfaces(d
->id
);
1426 d
->mode
= QXL_MODE_UNDEFINED
;
1427 qxl_spice_destroy_surfaces(d
, QXL_SYNC
);
1430 /* can be also called from spice server thread context */
1431 static bool qxl_get_check_slot_offset(PCIQXLDevice
*qxl
, QXLPHYSICAL pqxl
,
1432 uint32_t *s
, uint64_t *o
)
1434 uint64_t phys
= le64_to_cpu(pqxl
);
1435 uint32_t slot
= (phys
>> (64 - 8)) & 0xff;
1436 uint64_t offset
= phys
& 0xffffffffffff;
1438 if (slot
>= NUM_MEMSLOTS
) {
1439 qxl_set_guest_bug(qxl
, "slot too large %d >= %d", slot
,
1443 if (!qxl
->guest_slots
[slot
].active
) {
1444 qxl_set_guest_bug(qxl
, "inactive slot %d\n", slot
);
1447 if (offset
< qxl
->guest_slots
[slot
].delta
) {
1448 qxl_set_guest_bug(qxl
,
1449 "slot %d offset %"PRIu64
" < delta %"PRIu64
"\n",
1450 slot
, offset
, qxl
->guest_slots
[slot
].delta
);
1453 offset
-= qxl
->guest_slots
[slot
].delta
;
1454 if (offset
> qxl
->guest_slots
[slot
].size
) {
1455 qxl_set_guest_bug(qxl
,
1456 "slot %d offset %"PRIu64
" > size %"PRIu64
"\n",
1457 slot
, offset
, qxl
->guest_slots
[slot
].size
);
1466 /* can be also called from spice server thread context */
1467 void *qxl_phys2virt(PCIQXLDevice
*qxl
, QXLPHYSICAL pqxl
, int group_id
)
1474 case MEMSLOT_GROUP_HOST
:
1475 offset
= le64_to_cpu(pqxl
) & 0xffffffffffff;
1476 return (void *)(intptr_t)offset
;
1477 case MEMSLOT_GROUP_GUEST
:
1478 if (!qxl_get_check_slot_offset(qxl
, pqxl
, &slot
, &offset
)) {
1481 ptr
= memory_region_get_ram_ptr(qxl
->guest_slots
[slot
].mr
);
1482 ptr
+= qxl
->guest_slots
[slot
].offset
;
1489 static void qxl_create_guest_primary_complete(PCIQXLDevice
*qxl
)
1491 /* for local rendering */
1492 qxl_render_resize(qxl
);
1495 static void qxl_create_guest_primary(PCIQXLDevice
*qxl
, int loadvm
,
1498 QXLDevSurfaceCreate surface
;
1499 QXLSurfaceCreate
*sc
= &qxl
->guest_primary
.surface
;
1500 uint32_t requested_height
= le32_to_cpu(sc
->height
);
1501 int requested_stride
= le32_to_cpu(sc
->stride
);
1503 if (requested_stride
== INT32_MIN
||
1504 abs(requested_stride
) * (uint64_t)requested_height
1505 > qxl
->vgamem_size
) {
1506 qxl_set_guest_bug(qxl
, "%s: requested primary larger than framebuffer"
1507 " stride %d x height %" PRIu32
" > %" PRIu32
,
1508 __func__
, requested_stride
, requested_height
,
1513 if (qxl
->mode
== QXL_MODE_NATIVE
) {
1514 qxl_set_guest_bug(qxl
, "%s: nop since already in QXL_MODE_NATIVE",
1517 qxl_exit_vga_mode(qxl
);
1519 surface
.format
= le32_to_cpu(sc
->format
);
1520 surface
.height
= le32_to_cpu(sc
->height
);
1521 surface
.mem
= le64_to_cpu(sc
->mem
);
1522 surface
.position
= le32_to_cpu(sc
->position
);
1523 surface
.stride
= le32_to_cpu(sc
->stride
);
1524 surface
.width
= le32_to_cpu(sc
->width
);
1525 surface
.type
= le32_to_cpu(sc
->type
);
1526 surface
.flags
= le32_to_cpu(sc
->flags
);
1527 trace_qxl_create_guest_primary(qxl
->id
, sc
->width
, sc
->height
, sc
->mem
,
1528 sc
->format
, sc
->position
);
1529 trace_qxl_create_guest_primary_rest(qxl
->id
, sc
->stride
, sc
->type
,
1532 if ((surface
.stride
& 0x3) != 0) {
1533 qxl_set_guest_bug(qxl
, "primary surface stride = %d %% 4 != 0",
1538 surface
.mouse_mode
= true;
1539 surface
.group_id
= MEMSLOT_GROUP_GUEST
;
1541 surface
.flags
|= QXL_SURF_FLAG_KEEP_DATA
;
1544 qxl
->mode
= QXL_MODE_NATIVE
;
1546 qemu_spice_create_primary_surface(&qxl
->ssd
, 0, &surface
, async
);
1548 if (async
== QXL_SYNC
) {
1549 qxl_create_guest_primary_complete(qxl
);
1553 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1554 * done (in QXL_SYNC case), 0 otherwise. */
1555 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
)
1557 if (d
->mode
== QXL_MODE_UNDEFINED
) {
1560 trace_qxl_destroy_primary(d
->id
);
1561 d
->mode
= QXL_MODE_UNDEFINED
;
1562 qemu_spice_destroy_primary_surface(&d
->ssd
, 0, async
);
1563 qxl_spice_reset_cursor(d
);
1567 static void qxl_set_mode(PCIQXLDevice
*d
, unsigned int modenr
, int loadvm
)
1569 pcibus_t start
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1570 pcibus_t end
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].size
+ start
;
1571 QXLMode
*mode
= d
->modes
->modes
+ modenr
;
1572 uint64_t devmem
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1578 if (modenr
>= d
->modes
->n_modes
) {
1579 qxl_set_guest_bug(d
, "mode number out of range");
1583 QXLSurfaceCreate surface
= {
1584 .width
= mode
->x_res
,
1585 .height
= mode
->y_res
,
1586 .stride
= -mode
->x_res
* 4,
1587 .format
= SPICE_SURFACE_FMT_32_xRGB
,
1588 .flags
= loadvm
? QXL_SURF_FLAG_KEEP_DATA
: 0,
1590 .mem
= devmem
+ d
->shadow_rom
.draw_area_offset
,
1593 trace_qxl_set_mode(d
->id
, modenr
, mode
->x_res
, mode
->y_res
, mode
->bits
,
1596 qxl_hard_reset(d
, 0);
1599 d
->guest_slots
[0].slot
= slot
;
1600 assert(qxl_add_memslot(d
, 0, devmem
, QXL_SYNC
) == 0);
1602 d
->guest_primary
.surface
= surface
;
1603 qxl_create_guest_primary(d
, 0, QXL_SYNC
);
1605 d
->mode
= QXL_MODE_COMPAT
;
1606 d
->cmdflags
= QXL_COMMAND_FLAG_COMPAT
;
1607 if (mode
->bits
== 16) {
1608 d
->cmdflags
|= QXL_COMMAND_FLAG_COMPAT_16BPP
;
1610 d
->shadow_rom
.mode
= cpu_to_le32(modenr
);
1611 d
->rom
->mode
= cpu_to_le32(modenr
);
1612 qxl_rom_set_dirty(d
);
1615 static void ioport_write(void *opaque
, hwaddr addr
,
1616 uint64_t val
, unsigned size
)
1618 PCIQXLDevice
*d
= opaque
;
1619 uint32_t io_port
= addr
;
1620 qxl_async_io async
= QXL_SYNC
;
1621 uint32_t orig_io_port
= io_port
;
1623 if (d
->guest_bug
&& io_port
!= QXL_IO_RESET
) {
1627 if (d
->revision
<= QXL_REVISION_STABLE_V10
&&
1628 io_port
> QXL_IO_FLUSH_RELEASE
) {
1629 qxl_set_guest_bug(d
, "unsupported io %d for revision %d\n",
1630 io_port
, d
->revision
);
1636 case QXL_IO_SET_MODE
:
1637 case QXL_IO_MEMSLOT_ADD
:
1638 case QXL_IO_MEMSLOT_DEL
:
1639 case QXL_IO_CREATE_PRIMARY
:
1640 case QXL_IO_UPDATE_IRQ
:
1642 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1643 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1646 if (d
->mode
!= QXL_MODE_VGA
) {
1649 trace_qxl_io_unexpected_vga_mode(d
->id
,
1650 addr
, val
, io_port_to_string(io_port
));
1651 /* be nice to buggy guest drivers */
1652 if (io_port
>= QXL_IO_UPDATE_AREA_ASYNC
&&
1653 io_port
< QXL_IO_RANGE_SIZE
) {
1654 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1659 /* we change the io_port to avoid ifdeffery in the main switch */
1660 orig_io_port
= io_port
;
1662 case QXL_IO_UPDATE_AREA_ASYNC
:
1663 io_port
= QXL_IO_UPDATE_AREA
;
1665 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1666 io_port
= QXL_IO_MEMSLOT_ADD
;
1668 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1669 io_port
= QXL_IO_CREATE_PRIMARY
;
1671 case QXL_IO_DESTROY_PRIMARY_ASYNC
:
1672 io_port
= QXL_IO_DESTROY_PRIMARY
;
1674 case QXL_IO_DESTROY_SURFACE_ASYNC
:
1675 io_port
= QXL_IO_DESTROY_SURFACE_WAIT
;
1677 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
1678 io_port
= QXL_IO_DESTROY_ALL_SURFACES
;
1680 case QXL_IO_FLUSH_SURFACES_ASYNC
:
1681 case QXL_IO_MONITORS_CONFIG_ASYNC
:
1684 qemu_mutex_lock(&d
->async_lock
);
1685 if (d
->current_async
!= QXL_UNDEFINED_IO
) {
1686 qxl_set_guest_bug(d
, "%d async started before last (%d) complete",
1687 io_port
, d
->current_async
);
1688 qemu_mutex_unlock(&d
->async_lock
);
1691 d
->current_async
= orig_io_port
;
1692 qemu_mutex_unlock(&d
->async_lock
);
1697 trace_qxl_io_write(d
->id
, qxl_mode_to_string(d
->mode
),
1698 addr
, io_port_to_string(addr
),
1702 case QXL_IO_UPDATE_AREA
:
1704 QXLCookie
*cookie
= NULL
;
1705 QXLRect update
= d
->ram
->update_area
;
1707 if (d
->ram
->update_surface
> d
->ssd
.num_surfaces
) {
1708 qxl_set_guest_bug(d
, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1709 d
->ram
->update_surface
);
1712 if (update
.left
>= update
.right
|| update
.top
>= update
.bottom
||
1713 update
.left
< 0 || update
.top
< 0) {
1714 qxl_set_guest_bug(d
,
1715 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1716 update
.left
, update
.top
, update
.right
, update
.bottom
);
1717 if (update
.left
== update
.right
|| update
.top
== update
.bottom
) {
1718 /* old drivers may provide empty area, keep going */
1719 qxl_clear_guest_bug(d
);
1724 if (async
== QXL_ASYNC
) {
1725 cookie
= qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
1726 QXL_IO_UPDATE_AREA_ASYNC
);
1727 cookie
->u
.area
= update
;
1729 qxl_spice_update_area(d
, d
->ram
->update_surface
,
1730 cookie
? &cookie
->u
.area
: &update
,
1731 NULL
, 0, 0, async
, cookie
);
1734 case QXL_IO_NOTIFY_CMD
:
1735 qemu_spice_wakeup(&d
->ssd
);
1737 case QXL_IO_NOTIFY_CURSOR
:
1738 qemu_spice_wakeup(&d
->ssd
);
1740 case QXL_IO_UPDATE_IRQ
:
1743 case QXL_IO_NOTIFY_OOM
:
1744 if (!SPICE_RING_IS_EMPTY(&d
->ram
->release_ring
)) {
1751 case QXL_IO_SET_MODE
:
1752 qxl_set_mode(d
, val
, 0);
1755 trace_qxl_io_log(d
->id
, d
->ram
->log_buf
);
1756 if (d
->guestdebug
) {
1757 fprintf(stderr
, "qxl/guest-%d: %" PRId64
": %s", d
->id
,
1758 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), d
->ram
->log_buf
);
1762 qxl_hard_reset(d
, 0);
1764 case QXL_IO_MEMSLOT_ADD
:
1765 if (val
>= NUM_MEMSLOTS
) {
1766 qxl_set_guest_bug(d
, "QXL_IO_MEMSLOT_ADD: val out of range");
1769 if (d
->guest_slots
[val
].active
) {
1770 qxl_set_guest_bug(d
,
1771 "QXL_IO_MEMSLOT_ADD: memory slot already active");
1774 d
->guest_slots
[val
].slot
= d
->ram
->mem_slot
;
1775 qxl_add_memslot(d
, val
, 0, async
);
1777 case QXL_IO_MEMSLOT_DEL
:
1778 if (val
>= NUM_MEMSLOTS
) {
1779 qxl_set_guest_bug(d
, "QXL_IO_MEMSLOT_DEL: val out of range");
1782 qxl_del_memslot(d
, val
);
1784 case QXL_IO_CREATE_PRIMARY
:
1786 qxl_set_guest_bug(d
, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1790 d
->guest_primary
.surface
= d
->ram
->create_surface
;
1791 qxl_create_guest_primary(d
, 0, async
);
1793 case QXL_IO_DESTROY_PRIMARY
:
1795 qxl_set_guest_bug(d
, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1799 if (!qxl_destroy_primary(d
, async
)) {
1800 trace_qxl_io_destroy_primary_ignored(d
->id
,
1801 qxl_mode_to_string(d
->mode
));
1805 case QXL_IO_DESTROY_SURFACE_WAIT
:
1806 if (val
>= d
->ssd
.num_surfaces
) {
1807 qxl_set_guest_bug(d
, "QXL_IO_DESTROY_SURFACE (async=%d):"
1808 "%" PRIu64
" >= NUM_SURFACES", async
, val
);
1811 qxl_spice_destroy_surface_wait(d
, val
, async
);
1813 case QXL_IO_FLUSH_RELEASE
: {
1814 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
1815 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
1817 "ERROR: no flush, full release ring [p%d,%dc]\n",
1818 ring
->prod
, ring
->cons
);
1820 qxl_push_free_res(d
, 1 /* flush */);
1823 case QXL_IO_FLUSH_SURFACES_ASYNC
:
1824 qxl_spice_flush_surfaces_async(d
);
1826 case QXL_IO_DESTROY_ALL_SURFACES
:
1827 d
->mode
= QXL_MODE_UNDEFINED
;
1828 qxl_spice_destroy_surfaces(d
, async
);
1830 case QXL_IO_MONITORS_CONFIG_ASYNC
:
1831 qxl_spice_monitors_config_async(d
, 0);
1834 qxl_set_guest_bug(d
, "%s: unexpected ioport=0x%x\n", __func__
, io_port
);
1839 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1840 qemu_mutex_lock(&d
->async_lock
);
1841 d
->current_async
= QXL_UNDEFINED_IO
;
1842 qemu_mutex_unlock(&d
->async_lock
);
1846 static uint64_t ioport_read(void *opaque
, hwaddr addr
,
1849 PCIQXLDevice
*qxl
= opaque
;
1851 trace_qxl_io_read_unexpected(qxl
->id
);
1855 static const MemoryRegionOps qxl_io_ops
= {
1856 .read
= ioport_read
,
1857 .write
= ioport_write
,
1859 .min_access_size
= 1,
1860 .max_access_size
= 1,
1864 static void qxl_update_irq_bh(void *opaque
)
1866 PCIQXLDevice
*d
= opaque
;
1870 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
)
1872 uint32_t old_pending
;
1873 uint32_t le_events
= cpu_to_le32(events
);
1875 trace_qxl_send_events(d
->id
, events
);
1876 if (!qemu_spice_display_is_running(&d
->ssd
)) {
1877 /* spice-server tracks guest running state and should not do this */
1878 fprintf(stderr
, "%s: spice-server bug: guest stopped, ignoring\n",
1880 trace_qxl_send_events_vm_stopped(d
->id
, events
);
1883 old_pending
= atomic_fetch_or(&d
->ram
->int_pending
, le_events
);
1884 if ((old_pending
& le_events
) == le_events
) {
1887 qemu_bh_schedule(d
->update_irq
);
1890 /* graphics console */
1892 static void qxl_hw_update(void *opaque
)
1894 PCIQXLDevice
*qxl
= opaque
;
1896 qxl_render_update(qxl
);
1899 static void qxl_dirty_one_surface(PCIQXLDevice
*qxl
, QXLPHYSICAL pqxl
,
1900 uint32_t height
, int32_t stride
)
1902 uint64_t offset
, size
;
1906 rc
= qxl_get_check_slot_offset(qxl
, pqxl
, &slot
, &offset
);
1908 size
= (uint64_t)height
* abs(stride
);
1909 trace_qxl_surfaces_dirty(qxl
->id
, offset
, size
);
1910 qxl_set_dirty(qxl
->guest_slots
[slot
].mr
,
1911 qxl
->guest_slots
[slot
].offset
+ offset
,
1912 qxl
->guest_slots
[slot
].offset
+ offset
+ size
);
1915 static void qxl_dirty_surfaces(PCIQXLDevice
*qxl
)
1919 if (qxl
->mode
!= QXL_MODE_NATIVE
&& qxl
->mode
!= QXL_MODE_COMPAT
) {
1923 /* dirty the primary surface */
1924 qxl_dirty_one_surface(qxl
, qxl
->guest_primary
.surface
.mem
,
1925 qxl
->guest_primary
.surface
.height
,
1926 qxl
->guest_primary
.surface
.stride
);
1928 /* dirty the off-screen surfaces */
1929 for (i
= 0; i
< qxl
->ssd
.num_surfaces
; i
++) {
1932 if (qxl
->guest_surfaces
.cmds
[i
] == 0) {
1936 cmd
= qxl_phys2virt(qxl
, qxl
->guest_surfaces
.cmds
[i
],
1937 MEMSLOT_GROUP_GUEST
);
1939 assert(cmd
->type
== QXL_SURFACE_CMD_CREATE
);
1940 qxl_dirty_one_surface(qxl
, cmd
->u
.surface_create
.data
,
1941 cmd
->u
.surface_create
.height
,
1942 cmd
->u
.surface_create
.stride
);
1946 static void qxl_vm_change_state_handler(void *opaque
, int running
,
1949 PCIQXLDevice
*qxl
= opaque
;
1953 * if qxl_send_events was called from spice server context before
1954 * migration ended, qxl_update_irq for these events might not have been
1957 qxl_update_irq(qxl
);
1959 /* make sure surfaces are saved before migration */
1960 qxl_dirty_surfaces(qxl
);
1964 /* display change listener */
1966 static void display_update(DisplayChangeListener
*dcl
,
1967 int x
, int y
, int w
, int h
)
1969 PCIQXLDevice
*qxl
= container_of(dcl
, PCIQXLDevice
, ssd
.dcl
);
1971 if (qxl
->mode
== QXL_MODE_VGA
) {
1972 qemu_spice_display_update(&qxl
->ssd
, x
, y
, w
, h
);
1976 static void display_switch(DisplayChangeListener
*dcl
,
1977 struct DisplaySurface
*surface
)
1979 PCIQXLDevice
*qxl
= container_of(dcl
, PCIQXLDevice
, ssd
.dcl
);
1981 qxl
->ssd
.ds
= surface
;
1982 if (qxl
->mode
== QXL_MODE_VGA
) {
1983 qemu_spice_display_switch(&qxl
->ssd
, surface
);
1987 static void display_refresh(DisplayChangeListener
*dcl
)
1989 PCIQXLDevice
*qxl
= container_of(dcl
, PCIQXLDevice
, ssd
.dcl
);
1991 if (qxl
->mode
== QXL_MODE_VGA
) {
1992 qemu_spice_display_refresh(&qxl
->ssd
);
1996 static DisplayChangeListenerOps display_listener_ops
= {
1997 .dpy_name
= "spice/qxl",
1998 .dpy_gfx_update
= display_update
,
1999 .dpy_gfx_switch
= display_switch
,
2000 .dpy_refresh
= display_refresh
,
2003 static void qxl_init_ramsize(PCIQXLDevice
*qxl
)
2005 /* vga mode framebuffer / primary surface (bar 0, first part) */
2006 if (qxl
->vgamem_size_mb
< 8) {
2007 qxl
->vgamem_size_mb
= 8;
2009 /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be
2010 * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now).
2012 if (qxl
->vgamem_size_mb
> 256) {
2013 qxl
->vgamem_size_mb
= 256;
2015 qxl
->vgamem_size
= qxl
->vgamem_size_mb
* 1024 * 1024;
2017 /* vga ram (bar 0, total) */
2018 if (qxl
->ram_size_mb
!= -1) {
2019 qxl
->vga
.vram_size
= qxl
->ram_size_mb
* 1024 * 1024;
2021 if (qxl
->vga
.vram_size
< qxl
->vgamem_size
* 2) {
2022 qxl
->vga
.vram_size
= qxl
->vgamem_size
* 2;
2025 /* vram32 (surfaces, 32bit, bar 1) */
2026 if (qxl
->vram32_size_mb
!= -1) {
2027 qxl
->vram32_size
= qxl
->vram32_size_mb
* 1024 * 1024;
2029 if (qxl
->vram32_size
< 4096) {
2030 qxl
->vram32_size
= 4096;
2033 /* vram (surfaces, 64bit, bar 4+5) */
2034 if (qxl
->vram_size_mb
!= -1) {
2035 qxl
->vram_size
= (uint64_t)qxl
->vram_size_mb
* 1024 * 1024;
2037 if (qxl
->vram_size
< qxl
->vram32_size
) {
2038 qxl
->vram_size
= qxl
->vram32_size
;
2041 if (qxl
->revision
== 1) {
2042 qxl
->vram32_size
= 4096;
2043 qxl
->vram_size
= 4096;
2045 qxl
->vgamem_size
= pow2ceil(qxl
->vgamem_size
);
2046 qxl
->vga
.vram_size
= pow2ceil(qxl
->vga
.vram_size
);
2047 qxl
->vram32_size
= pow2ceil(qxl
->vram32_size
);
2048 qxl
->vram_size
= pow2ceil(qxl
->vram_size
);
2051 static void qxl_realize_common(PCIQXLDevice
*qxl
, Error
**errp
)
2053 uint8_t* config
= qxl
->pci
.config
;
2054 uint32_t pci_device_rev
;
2057 qxl
->mode
= QXL_MODE_UNDEFINED
;
2058 qxl
->generation
= 1;
2059 qxl
->num_memslots
= NUM_MEMSLOTS
;
2060 qemu_mutex_init(&qxl
->track_lock
);
2061 qemu_mutex_init(&qxl
->async_lock
);
2062 qxl
->current_async
= QXL_UNDEFINED_IO
;
2065 switch (qxl
->revision
) {
2066 case 1: /* spice 0.4 -- qxl-1 */
2067 pci_device_rev
= QXL_REVISION_STABLE_V04
;
2070 case 2: /* spice 0.6 -- qxl-2 */
2071 pci_device_rev
= QXL_REVISION_STABLE_V06
;
2075 pci_device_rev
= QXL_REVISION_STABLE_V10
;
2076 io_size
= 32; /* PCI region size must be pow2 */
2079 pci_device_rev
= QXL_REVISION_STABLE_V12
;
2080 io_size
= pow2ceil(QXL_IO_RANGE_SIZE
);
2083 error_setg(errp
, "Invalid revision %d for qxl device (max %d)",
2084 qxl
->revision
, QXL_DEFAULT_REVISION
);
2088 pci_set_byte(&config
[PCI_REVISION_ID
], pci_device_rev
);
2089 pci_set_byte(&config
[PCI_INTERRUPT_PIN
], 1);
2091 qxl
->rom_size
= qxl_rom_size();
2092 memory_region_init_ram(&qxl
->rom_bar
, OBJECT(qxl
), "qxl.vrom",
2093 qxl
->rom_size
, &error_fatal
);
2094 vmstate_register_ram(&qxl
->rom_bar
, &qxl
->pci
.qdev
);
2098 qxl
->guest_surfaces
.cmds
= g_new0(QXLPHYSICAL
, qxl
->ssd
.num_surfaces
);
2099 memory_region_init_ram(&qxl
->vram_bar
, OBJECT(qxl
), "qxl.vram",
2100 qxl
->vram_size
, &error_fatal
);
2101 vmstate_register_ram(&qxl
->vram_bar
, &qxl
->pci
.qdev
);
2102 memory_region_init_alias(&qxl
->vram32_bar
, OBJECT(qxl
), "qxl.vram32",
2103 &qxl
->vram_bar
, 0, qxl
->vram32_size
);
2105 memory_region_init_io(&qxl
->io_bar
, OBJECT(qxl
), &qxl_io_ops
, qxl
,
2106 "qxl-ioports", io_size
);
2108 vga_dirty_log_start(&qxl
->vga
);
2110 memory_region_set_flush_coalesced(&qxl
->io_bar
);
2113 pci_register_bar(&qxl
->pci
, QXL_IO_RANGE_INDEX
,
2114 PCI_BASE_ADDRESS_SPACE_IO
, &qxl
->io_bar
);
2116 pci_register_bar(&qxl
->pci
, QXL_ROM_RANGE_INDEX
,
2117 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->rom_bar
);
2119 pci_register_bar(&qxl
->pci
, QXL_RAM_RANGE_INDEX
,
2120 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->vga
.vram
);
2122 pci_register_bar(&qxl
->pci
, QXL_VRAM_RANGE_INDEX
,
2123 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->vram32_bar
);
2125 if (qxl
->vram32_size
< qxl
->vram_size
) {
2127 * Make the 64bit vram bar show up only in case it is
2128 * configured to be larger than the 32bit vram bar.
2130 pci_register_bar(&qxl
->pci
, QXL_VRAM64_RANGE_INDEX
,
2131 PCI_BASE_ADDRESS_SPACE_MEMORY
|
2132 PCI_BASE_ADDRESS_MEM_TYPE_64
|
2133 PCI_BASE_ADDRESS_MEM_PREFETCH
,
2137 /* print pci bar details */
2138 dprint(qxl
, 1, "ram/%s: %d MB [region 0]\n",
2139 qxl
->id
== 0 ? "pri" : "sec",
2140 qxl
->vga
.vram_size
/ (1024*1024));
2141 dprint(qxl
, 1, "vram/32: %" PRIx64
"d MB [region 1]\n",
2142 qxl
->vram32_size
/ (1024*1024));
2143 dprint(qxl
, 1, "vram/64: %" PRIx64
"d MB %s\n",
2144 qxl
->vram_size
/ (1024*1024),
2145 qxl
->vram32_size
< qxl
->vram_size
? "[region 4]" : "[unmapped]");
2147 qxl
->ssd
.qxl
.base
.sif
= &qxl_interface
.base
;
2148 if (qemu_spice_add_display_interface(&qxl
->ssd
.qxl
, qxl
->vga
.con
) != 0) {
2149 error_setg(errp
, "qxl interface %d.%d not supported by spice-server",
2150 SPICE_INTERFACE_QXL_MAJOR
, SPICE_INTERFACE_QXL_MINOR
);
2153 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler
, qxl
);
2155 qxl
->update_irq
= qemu_bh_new(qxl_update_irq_bh
, qxl
);
2156 qxl_reset_state(qxl
);
2158 qxl
->update_area_bh
= qemu_bh_new(qxl_render_update_area_bh
, qxl
);
2159 qxl
->ssd
.cursor_bh
= qemu_bh_new(qemu_spice_cursor_refresh_bh
, &qxl
->ssd
);
2162 static void qxl_realize_primary(PCIDevice
*dev
, Error
**errp
)
2164 PCIQXLDevice
*qxl
= PCI_QXL(dev
);
2165 VGACommonState
*vga
= &qxl
->vga
;
2166 Error
*local_err
= NULL
;
2169 qxl_init_ramsize(qxl
);
2170 vga
->vbe_size
= qxl
->vgamem_size
;
2171 vga
->vram_size_mb
= qxl
->vga
.vram_size
>> 20;
2172 vga_common_init(vga
, OBJECT(dev
), true);
2173 vga_init(vga
, OBJECT(dev
),
2174 pci_address_space(dev
), pci_address_space_io(dev
), false);
2175 portio_list_init(&qxl
->vga_port_list
, OBJECT(dev
), qxl_vga_portio_list
,
2177 portio_list_set_flush_coalesced(&qxl
->vga_port_list
);
2178 portio_list_add(&qxl
->vga_port_list
, pci_address_space_io(dev
), 0x3b0);
2180 vga
->con
= graphic_console_init(DEVICE(dev
), 0, &qxl_ops
, qxl
);
2181 qemu_spice_display_init_common(&qxl
->ssd
);
2183 qxl_realize_common(qxl
, &local_err
);
2185 error_propagate(errp
, local_err
);
2189 qxl
->ssd
.dcl
.ops
= &display_listener_ops
;
2190 qxl
->ssd
.dcl
.con
= vga
->con
;
2191 register_displaychangelistener(&qxl
->ssd
.dcl
);
2194 static void qxl_realize_secondary(PCIDevice
*dev
, Error
**errp
)
2196 static int device_id
= 1;
2197 PCIQXLDevice
*qxl
= PCI_QXL(dev
);
2199 qxl
->id
= device_id
++;
2200 qxl_init_ramsize(qxl
);
2201 memory_region_init_ram(&qxl
->vga
.vram
, OBJECT(dev
), "qxl.vgavram",
2202 qxl
->vga
.vram_size
, &error_fatal
);
2203 vmstate_register_ram(&qxl
->vga
.vram
, &qxl
->pci
.qdev
);
2204 qxl
->vga
.vram_ptr
= memory_region_get_ram_ptr(&qxl
->vga
.vram
);
2205 qxl
->vga
.con
= graphic_console_init(DEVICE(dev
), 0, &qxl_ops
, qxl
);
2207 qxl_realize_common(qxl
, errp
);
2210 static void qxl_pre_save(void *opaque
)
2212 PCIQXLDevice
* d
= opaque
;
2213 uint8_t *ram_start
= d
->vga
.vram_ptr
;
2215 trace_qxl_pre_save(d
->id
);
2216 if (d
->last_release
== NULL
) {
2217 d
->last_release_offset
= 0;
2219 d
->last_release_offset
= (uint8_t *)d
->last_release
- ram_start
;
2221 assert(d
->last_release_offset
< d
->vga
.vram_size
);
2224 static int qxl_pre_load(void *opaque
)
2226 PCIQXLDevice
* d
= opaque
;
2228 trace_qxl_pre_load(d
->id
);
2229 qxl_hard_reset(d
, 1);
2230 qxl_exit_vga_mode(d
);
2234 static void qxl_create_memslots(PCIQXLDevice
*d
)
2238 for (i
= 0; i
< NUM_MEMSLOTS
; i
++) {
2239 if (!d
->guest_slots
[i
].active
) {
2242 qxl_add_memslot(d
, i
, 0, QXL_SYNC
);
2246 static int qxl_post_load(void *opaque
, int version
)
2248 PCIQXLDevice
* d
= opaque
;
2249 uint8_t *ram_start
= d
->vga
.vram_ptr
;
2250 QXLCommandExt
*cmds
;
2251 int in
, out
, newmode
;
2253 assert(d
->last_release_offset
< d
->vga
.vram_size
);
2254 if (d
->last_release_offset
== 0) {
2255 d
->last_release
= NULL
;
2257 d
->last_release
= (QXLReleaseInfo
*)(ram_start
+ d
->last_release_offset
);
2260 d
->modes
= (QXLModes
*)((uint8_t*)d
->rom
+ d
->rom
->modes_offset
);
2262 trace_qxl_post_load(d
->id
, qxl_mode_to_string(d
->mode
));
2264 d
->mode
= QXL_MODE_UNDEFINED
;
2267 case QXL_MODE_UNDEFINED
:
2268 qxl_create_memslots(d
);
2271 qxl_create_memslots(d
);
2272 qxl_enter_vga_mode(d
);
2274 case QXL_MODE_NATIVE
:
2275 qxl_create_memslots(d
);
2276 qxl_create_guest_primary(d
, 1, QXL_SYNC
);
2278 /* replay surface-create and cursor-set commands */
2279 cmds
= g_new0(QXLCommandExt
, d
->ssd
.num_surfaces
+ 1);
2280 for (in
= 0, out
= 0; in
< d
->ssd
.num_surfaces
; in
++) {
2281 if (d
->guest_surfaces
.cmds
[in
] == 0) {
2284 cmds
[out
].cmd
.data
= d
->guest_surfaces
.cmds
[in
];
2285 cmds
[out
].cmd
.type
= QXL_CMD_SURFACE
;
2286 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
2289 if (d
->guest_cursor
) {
2290 cmds
[out
].cmd
.data
= d
->guest_cursor
;
2291 cmds
[out
].cmd
.type
= QXL_CMD_CURSOR
;
2292 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
2295 qxl_spice_loadvm_commands(d
, cmds
, out
);
2297 if (d
->guest_monitors_config
) {
2298 qxl_spice_monitors_config_async(d
, 1);
2301 case QXL_MODE_COMPAT
:
2302 /* note: no need to call qxl_create_memslots, qxl_set_mode
2303 * creates the mem slot. */
2304 qxl_set_mode(d
, d
->shadow_rom
.mode
, 1);
2310 #define QXL_SAVE_VERSION 21
2312 static bool qxl_monitors_config_needed(void *opaque
)
2314 PCIQXLDevice
*qxl
= opaque
;
2316 return qxl
->guest_monitors_config
!= 0;
2320 static VMStateDescription qxl_memslot
= {
2321 .name
= "qxl-memslot",
2322 .version_id
= QXL_SAVE_VERSION
,
2323 .minimum_version_id
= QXL_SAVE_VERSION
,
2324 .fields
= (VMStateField
[]) {
2325 VMSTATE_UINT64(slot
.mem_start
, struct guest_slots
),
2326 VMSTATE_UINT64(slot
.mem_end
, struct guest_slots
),
2327 VMSTATE_UINT32(active
, struct guest_slots
),
2328 VMSTATE_END_OF_LIST()
2332 static VMStateDescription qxl_surface
= {
2333 .name
= "qxl-surface",
2334 .version_id
= QXL_SAVE_VERSION
,
2335 .minimum_version_id
= QXL_SAVE_VERSION
,
2336 .fields
= (VMStateField
[]) {
2337 VMSTATE_UINT32(width
, QXLSurfaceCreate
),
2338 VMSTATE_UINT32(height
, QXLSurfaceCreate
),
2339 VMSTATE_INT32(stride
, QXLSurfaceCreate
),
2340 VMSTATE_UINT32(format
, QXLSurfaceCreate
),
2341 VMSTATE_UINT32(position
, QXLSurfaceCreate
),
2342 VMSTATE_UINT32(mouse_mode
, QXLSurfaceCreate
),
2343 VMSTATE_UINT32(flags
, QXLSurfaceCreate
),
2344 VMSTATE_UINT32(type
, QXLSurfaceCreate
),
2345 VMSTATE_UINT64(mem
, QXLSurfaceCreate
),
2346 VMSTATE_END_OF_LIST()
2350 static VMStateDescription qxl_vmstate_monitors_config
= {
2351 .name
= "qxl/monitors-config",
2353 .minimum_version_id
= 1,
2354 .needed
= qxl_monitors_config_needed
,
2355 .fields
= (VMStateField
[]) {
2356 VMSTATE_UINT64(guest_monitors_config
, PCIQXLDevice
),
2357 VMSTATE_END_OF_LIST()
2361 static VMStateDescription qxl_vmstate
= {
2363 .version_id
= QXL_SAVE_VERSION
,
2364 .minimum_version_id
= QXL_SAVE_VERSION
,
2365 .pre_save
= qxl_pre_save
,
2366 .pre_load
= qxl_pre_load
,
2367 .post_load
= qxl_post_load
,
2368 .fields
= (VMStateField
[]) {
2369 VMSTATE_PCI_DEVICE(pci
, PCIQXLDevice
),
2370 VMSTATE_STRUCT(vga
, PCIQXLDevice
, 0, vmstate_vga_common
, VGACommonState
),
2371 VMSTATE_UINT32(shadow_rom
.mode
, PCIQXLDevice
),
2372 VMSTATE_UINT32(num_free_res
, PCIQXLDevice
),
2373 VMSTATE_UINT32(last_release_offset
, PCIQXLDevice
),
2374 VMSTATE_UINT32(mode
, PCIQXLDevice
),
2375 VMSTATE_UINT32(ssd
.unique
, PCIQXLDevice
),
2376 VMSTATE_INT32_EQUAL(num_memslots
, PCIQXLDevice
),
2377 VMSTATE_STRUCT_ARRAY(guest_slots
, PCIQXLDevice
, NUM_MEMSLOTS
, 0,
2378 qxl_memslot
, struct guest_slots
),
2379 VMSTATE_STRUCT(guest_primary
.surface
, PCIQXLDevice
, 0,
2380 qxl_surface
, QXLSurfaceCreate
),
2381 VMSTATE_INT32_EQUAL(ssd
.num_surfaces
, PCIQXLDevice
),
2382 VMSTATE_VARRAY_INT32(guest_surfaces
.cmds
, PCIQXLDevice
,
2383 ssd
.num_surfaces
, 0,
2384 vmstate_info_uint64
, uint64_t),
2385 VMSTATE_UINT64(guest_cursor
, PCIQXLDevice
),
2386 VMSTATE_END_OF_LIST()
2388 .subsections
= (const VMStateDescription
*[]) {
2389 &qxl_vmstate_monitors_config
,
2394 static Property qxl_properties
[] = {
2395 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice
, vga
.vram_size
,
2397 DEFINE_PROP_UINT64("vram_size", PCIQXLDevice
, vram32_size
,
2399 DEFINE_PROP_UINT32("revision", PCIQXLDevice
, revision
,
2400 QXL_DEFAULT_REVISION
),
2401 DEFINE_PROP_UINT32("debug", PCIQXLDevice
, debug
, 0),
2402 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice
, guestdebug
, 0),
2403 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice
, cmdlog
, 0),
2404 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice
, ram_size_mb
, -1),
2405 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice
, vram32_size_mb
, -1),
2406 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice
, vram_size_mb
, -1),
2407 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice
, vgamem_size_mb
, 16),
2408 DEFINE_PROP_INT32("surfaces", PCIQXLDevice
, ssd
.num_surfaces
, 1024),
2409 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
2410 DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice
, max_outputs
, 0),
2412 DEFINE_PROP_UINT32("xres", PCIQXLDevice
, xres
, 0),
2413 DEFINE_PROP_UINT32("yres", PCIQXLDevice
, yres
, 0),
2414 DEFINE_PROP_END_OF_LIST(),
2417 static void qxl_pci_class_init(ObjectClass
*klass
, void *data
)
2419 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2420 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2422 k
->vendor_id
= REDHAT_PCI_VENDOR_ID
;
2423 k
->device_id
= QXL_DEVICE_ID_STABLE
;
2424 set_bit(DEVICE_CATEGORY_DISPLAY
, dc
->categories
);
2425 dc
->reset
= qxl_reset_handler
;
2426 dc
->vmsd
= &qxl_vmstate
;
2427 dc
->props
= qxl_properties
;
2430 static const TypeInfo qxl_pci_type_info
= {
2431 .name
= TYPE_PCI_QXL
,
2432 .parent
= TYPE_PCI_DEVICE
,
2433 .instance_size
= sizeof(PCIQXLDevice
),
2435 .class_init
= qxl_pci_class_init
,
2438 static void qxl_primary_class_init(ObjectClass
*klass
, void *data
)
2440 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2441 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2443 k
->realize
= qxl_realize_primary
;
2444 k
->romfile
= "vgabios-qxl.bin";
2445 k
->class_id
= PCI_CLASS_DISPLAY_VGA
;
2446 dc
->desc
= "Spice QXL GPU (primary, vga compatible)";
2447 dc
->hotpluggable
= false;
2450 static const TypeInfo qxl_primary_info
= {
2452 .parent
= TYPE_PCI_QXL
,
2453 .class_init
= qxl_primary_class_init
,
2456 static void qxl_secondary_class_init(ObjectClass
*klass
, void *data
)
2458 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2459 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2461 k
->realize
= qxl_realize_secondary
;
2462 k
->class_id
= PCI_CLASS_DISPLAY_OTHER
;
2463 dc
->desc
= "Spice QXL GPU (secondary)";
2466 static const TypeInfo qxl_secondary_info
= {
2468 .parent
= TYPE_PCI_QXL
,
2469 .class_init
= qxl_secondary_class_init
,
2472 static void qxl_register_types(void)
2474 type_register_static(&qxl_pci_type_info
);
2475 type_register_static(&qxl_primary_info
);
2476 type_register_static(&qxl_secondary_info
);
2479 type_init(qxl_register_types
)