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ui/spice: Require spice-server >= 0.14.0
[mirror_qemu.git] / hw / display / qxl.c
1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include <zlib.h>
24
25 #include "qapi/error.h"
26 #include "qemu/timer.h"
27 #include "qemu/queue.h"
28 #include "qemu/atomic.h"
29 #include "qemu/main-loop.h"
30 #include "qemu/module.h"
31 #include "hw/qdev-properties.h"
32 #include "sysemu/runstate.h"
33 #include "migration/vmstate.h"
34 #include "trace.h"
35
36 #include "qxl.h"
37
38 #undef SPICE_RING_CONS_ITEM
39 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
40 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
41 if (cons >= ARRAY_SIZE((r)->items)) { \
42 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
43 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
44 ret = NULL; \
45 } else { \
46 ret = &(r)->items[cons].el; \
47 } \
48 }
49
50 #undef ALIGN
51 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
52
53 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
54
55 #define QXL_MODE(_x, _y, _b, _o) \
56 { .x_res = _x, \
57 .y_res = _y, \
58 .bits = _b, \
59 .stride = (_x) * (_b) / 8, \
60 .x_mili = PIXEL_SIZE * (_x), \
61 .y_mili = PIXEL_SIZE * (_y), \
62 .orientation = _o, \
63 }
64
65 #define QXL_MODE_16_32(x_res, y_res, orientation) \
66 QXL_MODE(x_res, y_res, 16, orientation), \
67 QXL_MODE(x_res, y_res, 32, orientation)
68
69 #define QXL_MODE_EX(x_res, y_res) \
70 QXL_MODE_16_32(x_res, y_res, 0), \
71 QXL_MODE_16_32(x_res, y_res, 1)
72
73 static QXLMode qxl_modes[] = {
74 QXL_MODE_EX(640, 480),
75 QXL_MODE_EX(800, 480),
76 QXL_MODE_EX(800, 600),
77 QXL_MODE_EX(832, 624),
78 QXL_MODE_EX(960, 640),
79 QXL_MODE_EX(1024, 600),
80 QXL_MODE_EX(1024, 768),
81 QXL_MODE_EX(1152, 864),
82 QXL_MODE_EX(1152, 870),
83 QXL_MODE_EX(1280, 720),
84 QXL_MODE_EX(1280, 760),
85 QXL_MODE_EX(1280, 768),
86 QXL_MODE_EX(1280, 800),
87 QXL_MODE_EX(1280, 960),
88 QXL_MODE_EX(1280, 1024),
89 QXL_MODE_EX(1360, 768),
90 QXL_MODE_EX(1366, 768),
91 QXL_MODE_EX(1400, 1050),
92 QXL_MODE_EX(1440, 900),
93 QXL_MODE_EX(1600, 900),
94 QXL_MODE_EX(1600, 1200),
95 QXL_MODE_EX(1680, 1050),
96 QXL_MODE_EX(1920, 1080),
97 /* these modes need more than 8 MB video memory */
98 QXL_MODE_EX(1920, 1200),
99 QXL_MODE_EX(1920, 1440),
100 QXL_MODE_EX(2000, 2000),
101 QXL_MODE_EX(2048, 1536),
102 QXL_MODE_EX(2048, 2048),
103 QXL_MODE_EX(2560, 1440),
104 QXL_MODE_EX(2560, 1600),
105 /* these modes need more than 16 MB video memory */
106 QXL_MODE_EX(2560, 2048),
107 QXL_MODE_EX(2800, 2100),
108 QXL_MODE_EX(3200, 2400),
109 /* these modes need more than 32 MB video memory */
110 QXL_MODE_EX(3840, 2160), /* 4k mainstream */
111 QXL_MODE_EX(4096, 2160), /* 4k */
112 /* these modes need more than 64 MB video memory */
113 QXL_MODE_EX(7680, 4320), /* 8k mainstream */
114 /* these modes need more than 128 MB video memory */
115 QXL_MODE_EX(8192, 4320), /* 8k */
116 };
117
118 static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
119 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
120 static void qxl_reset_memslots(PCIQXLDevice *d);
121 static void qxl_reset_surfaces(PCIQXLDevice *d);
122 static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
123
124 static void qxl_hw_update(void *opaque);
125
126 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
127 {
128 trace_qxl_set_guest_bug(qxl->id);
129 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
130 qxl->guest_bug = 1;
131 if (qxl->guestdebug) {
132 va_list ap;
133 va_start(ap, msg);
134 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
135 vfprintf(stderr, msg, ap);
136 fprintf(stderr, "\n");
137 va_end(ap);
138 }
139 }
140
141 static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
142 {
143 qxl->guest_bug = 0;
144 }
145
146 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
147 struct QXLRect *area, struct QXLRect *dirty_rects,
148 uint32_t num_dirty_rects,
149 uint32_t clear_dirty_region,
150 qxl_async_io async, struct QXLCookie *cookie)
151 {
152 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
153 area->top, area->bottom);
154 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
155 clear_dirty_region);
156 if (async == QXL_SYNC) {
157 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area,
158 dirty_rects, num_dirty_rects, clear_dirty_region);
159 } else {
160 assert(cookie != NULL);
161 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
162 clear_dirty_region, (uintptr_t)cookie);
163 }
164 }
165
166 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
167 uint32_t id)
168 {
169 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
170 qemu_mutex_lock(&qxl->track_lock);
171 qxl->guest_surfaces.cmds[id] = 0;
172 qxl->guest_surfaces.count--;
173 qemu_mutex_unlock(&qxl->track_lock);
174 }
175
176 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
177 qxl_async_io async)
178 {
179 QXLCookie *cookie;
180
181 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
182 if (async) {
183 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
184 QXL_IO_DESTROY_SURFACE_ASYNC);
185 cookie->u.surface_id = id;
186 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
187 } else {
188 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id);
189 qxl_spice_destroy_surface_wait_complete(qxl, id);
190 }
191 }
192
193 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
194 {
195 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
196 qxl->num_free_res);
197 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
198 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
199 QXL_IO_FLUSH_SURFACES_ASYNC));
200 }
201
202 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
203 uint32_t count)
204 {
205 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
206 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count);
207 }
208
209 void qxl_spice_oom(PCIQXLDevice *qxl)
210 {
211 trace_qxl_spice_oom(qxl->id);
212 spice_qxl_oom(&qxl->ssd.qxl);
213 }
214
215 void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
216 {
217 trace_qxl_spice_reset_memslots(qxl->id);
218 spice_qxl_reset_memslots(&qxl->ssd.qxl);
219 }
220
221 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
222 {
223 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
224 qemu_mutex_lock(&qxl->track_lock);
225 memset(qxl->guest_surfaces.cmds, 0,
226 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
227 qxl->guest_surfaces.count = 0;
228 qemu_mutex_unlock(&qxl->track_lock);
229 }
230
231 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
232 {
233 trace_qxl_spice_destroy_surfaces(qxl->id, async);
234 if (async) {
235 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
236 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
237 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
238 } else {
239 spice_qxl_destroy_surfaces(&qxl->ssd.qxl);
240 qxl_spice_destroy_surfaces_complete(qxl);
241 }
242 }
243
244 static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
245 {
246 QXLMonitorsConfig *cfg;
247
248 trace_qxl_spice_monitors_config(qxl->id);
249 if (replay) {
250 /*
251 * don't use QXL_COOKIE_TYPE_IO:
252 * - we are not running yet (post_load), we will assert
253 * in send_events
254 * - this is not a guest io, but a reply, so async_io isn't set.
255 */
256 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
257 qxl->guest_monitors_config,
258 MEMSLOT_GROUP_GUEST,
259 (uintptr_t)qxl_cookie_new(
260 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
261 0));
262 } else {
263 #if SPICE_SERVER_VERSION < 0x000e02 /* release 0.14.2 */
264 if (qxl->max_outputs) {
265 spice_qxl_set_max_monitors(&qxl->ssd.qxl, qxl->max_outputs);
266 }
267 #endif
268 qxl->guest_monitors_config = qxl->ram->monitors_config;
269 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
270 qxl->ram->monitors_config,
271 MEMSLOT_GROUP_GUEST,
272 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
273 QXL_IO_MONITORS_CONFIG_ASYNC));
274 }
275
276 cfg = qxl_phys2virt(qxl, qxl->guest_monitors_config, MEMSLOT_GROUP_GUEST,
277 sizeof(QXLMonitorsConfig));
278 if (cfg != NULL && cfg->count == 1) {
279 qxl->guest_primary.resized = 1;
280 qxl->guest_head0_width = cfg->heads[0].width;
281 qxl->guest_head0_height = cfg->heads[0].height;
282 } else {
283 qxl->guest_head0_width = 0;
284 qxl->guest_head0_height = 0;
285 }
286 }
287
288 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
289 {
290 trace_qxl_spice_reset_image_cache(qxl->id);
291 spice_qxl_reset_image_cache(&qxl->ssd.qxl);
292 }
293
294 void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
295 {
296 trace_qxl_spice_reset_cursor(qxl->id);
297 spice_qxl_reset_cursor(&qxl->ssd.qxl);
298 qemu_mutex_lock(&qxl->track_lock);
299 qxl->guest_cursor = 0;
300 qemu_mutex_unlock(&qxl->track_lock);
301 if (qxl->ssd.cursor) {
302 cursor_put(qxl->ssd.cursor);
303 }
304 qxl->ssd.cursor = cursor_builtin_hidden();
305 }
306
307 static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
308 {
309 /*
310 * zlib xors the seed with 0xffffffff, and xors the result
311 * again with 0xffffffff; Both are not done with linux's crc32,
312 * which we want to be compatible with, so undo that.
313 */
314 return crc32(0xffffffff, p, len) ^ 0xffffffff;
315 }
316
317 static ram_addr_t qxl_rom_size(void)
318 {
319 #define QXL_REQUIRED_SZ (sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes))
320 #define QXL_ROM_SZ 8192
321
322 QEMU_BUILD_BUG_ON(QXL_REQUIRED_SZ > QXL_ROM_SZ);
323 return QEMU_ALIGN_UP(QXL_REQUIRED_SZ, qemu_real_host_page_size());
324 }
325
326 static void init_qxl_rom(PCIQXLDevice *d)
327 {
328 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
329 QXLModes *modes = (QXLModes *)(rom + 1);
330 uint32_t ram_header_size;
331 uint32_t surface0_area_size;
332 uint32_t num_pages;
333 uint32_t fb;
334 int i, n;
335
336 memset(rom, 0, d->rom_size);
337
338 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
339 rom->id = cpu_to_le32(d->id);
340 rom->log_level = cpu_to_le32(d->guestdebug);
341 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
342
343 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
344 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
345 rom->slots_start = 1;
346 rom->slots_end = NUM_MEMSLOTS - 1;
347 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
348
349 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
350 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
351 if (fb > d->vgamem_size) {
352 continue;
353 }
354 modes->modes[n].id = cpu_to_le32(i);
355 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
356 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
357 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
358 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
359 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
360 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
361 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
362 n++;
363 }
364 modes->n_modes = cpu_to_le32(n);
365
366 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
367 surface0_area_size = ALIGN(d->vgamem_size, 4096);
368 num_pages = d->vga.vram_size;
369 num_pages -= ram_header_size;
370 num_pages -= surface0_area_size;
371 num_pages = num_pages / QXL_PAGE_SIZE;
372
373 assert(ram_header_size + surface0_area_size <= d->vga.vram_size);
374
375 rom->draw_area_offset = cpu_to_le32(0);
376 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
377 rom->pages_offset = cpu_to_le32(surface0_area_size);
378 rom->num_pages = cpu_to_le32(num_pages);
379 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
380
381 if (d->xres && d->yres) {
382 /* needs linux kernel 4.12+ to work */
383 rom->client_monitors_config.count = 1;
384 rom->client_monitors_config.heads[0].left = 0;
385 rom->client_monitors_config.heads[0].top = 0;
386 rom->client_monitors_config.heads[0].right = cpu_to_le32(d->xres);
387 rom->client_monitors_config.heads[0].bottom = cpu_to_le32(d->yres);
388 rom->client_monitors_config_crc = qxl_crc32(
389 (const uint8_t *)&rom->client_monitors_config,
390 sizeof(rom->client_monitors_config));
391 }
392
393 d->shadow_rom = *rom;
394 d->rom = rom;
395 d->modes = modes;
396 }
397
398 static void init_qxl_ram(PCIQXLDevice *d)
399 {
400 uint8_t *buf;
401 uint32_t prod;
402 QXLReleaseRing *ring;
403
404 buf = d->vga.vram_ptr;
405 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
406 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
407 d->ram->int_pending = cpu_to_le32(0);
408 d->ram->int_mask = cpu_to_le32(0);
409 d->ram->update_surface = 0;
410 d->ram->monitors_config = 0;
411 SPICE_RING_INIT(&d->ram->cmd_ring);
412 SPICE_RING_INIT(&d->ram->cursor_ring);
413 SPICE_RING_INIT(&d->ram->release_ring);
414
415 ring = &d->ram->release_ring;
416 prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
417 assert(prod < ARRAY_SIZE(ring->items));
418 ring->items[prod].el = 0;
419
420 qxl_ring_set_dirty(d);
421 }
422
423 /* can be called from spice server thread context */
424 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
425 {
426 memory_region_set_dirty(mr, addr, end - addr);
427 }
428
429 static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
430 {
431 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
432 }
433
434 /* called from spice server thread context only */
435 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
436 {
437 void *base = qxl->vga.vram_ptr;
438 intptr_t offset;
439
440 offset = ptr - base;
441 assert(offset < qxl->vga.vram_size);
442 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3);
443 }
444
445 /* can be called from spice server thread context */
446 static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
447 {
448 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
449 ram_addr_t end = qxl->vga.vram_size;
450 qxl_set_dirty(&qxl->vga.vram, addr, end);
451 }
452
453 /*
454 * keep track of some command state, for savevm/loadvm.
455 * called from spice server thread context only
456 */
457 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
458 {
459 switch (le32_to_cpu(ext->cmd.type)) {
460 case QXL_CMD_SURFACE:
461 {
462 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id,
463 sizeof(QXLSurfaceCmd));
464
465 if (!cmd) {
466 return 1;
467 }
468 uint32_t id = le32_to_cpu(cmd->surface_id);
469
470 if (id >= qxl->ssd.num_surfaces) {
471 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
472 qxl->ssd.num_surfaces);
473 return 1;
474 }
475 if (cmd->type == QXL_SURFACE_CMD_CREATE &&
476 (cmd->u.surface_create.stride & 0x03) != 0) {
477 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
478 cmd->u.surface_create.stride);
479 return 1;
480 }
481 WITH_QEMU_LOCK_GUARD(&qxl->track_lock) {
482 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
483 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
484 qxl->guest_surfaces.count++;
485 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count) {
486 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
487 }
488 }
489 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
490 qxl->guest_surfaces.cmds[id] = 0;
491 qxl->guest_surfaces.count--;
492 }
493 }
494 break;
495 }
496 case QXL_CMD_CURSOR:
497 {
498 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id,
499 sizeof(QXLCursorCmd));
500
501 if (!cmd) {
502 return 1;
503 }
504 if (cmd->type == QXL_CURSOR_SET) {
505 qemu_mutex_lock(&qxl->track_lock);
506 qxl->guest_cursor = ext->cmd.data;
507 qemu_mutex_unlock(&qxl->track_lock);
508 }
509 if (cmd->type == QXL_CURSOR_HIDE) {
510 qemu_mutex_lock(&qxl->track_lock);
511 qxl->guest_cursor = 0;
512 qemu_mutex_unlock(&qxl->track_lock);
513 }
514 break;
515 }
516 }
517 return 0;
518 }
519
520 /* spice display interface callbacks */
521
522 static void interface_attached_worker(QXLInstance *sin)
523 {
524 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
525
526 trace_qxl_interface_attach_worker(qxl->id);
527 }
528
529 #if !(SPICE_HAS_ATTACHED_WORKER)
530 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
531 {
532 interface_attached_worker(sin);
533 }
534 #endif
535
536 static void interface_set_compression_level(QXLInstance *sin, int level)
537 {
538 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
539
540 trace_qxl_interface_set_compression_level(qxl->id, level);
541 qxl->shadow_rom.compression_level = cpu_to_le32(level);
542 qxl->rom->compression_level = cpu_to_le32(level);
543 qxl_rom_set_dirty(qxl);
544 }
545
546 #if SPICE_NEEDS_SET_MM_TIME
547 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
548 {
549 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
550
551 if (!qemu_spice_display_is_running(&qxl->ssd)) {
552 return;
553 }
554
555 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
556 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
557 qxl->rom->mm_clock = cpu_to_le32(mm_time);
558 qxl_rom_set_dirty(qxl);
559 }
560 #endif
561
562 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
563 {
564 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
565
566 trace_qxl_interface_get_init_info(qxl->id);
567 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
568 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
569 info->num_memslots = NUM_MEMSLOTS;
570 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
571 info->internal_groupslot_id = 0;
572 info->qxl_ram_size =
573 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS;
574 info->n_surfaces = qxl->ssd.num_surfaces;
575 }
576
577 static const char *qxl_mode_to_string(int mode)
578 {
579 switch (mode) {
580 case QXL_MODE_COMPAT:
581 return "compat";
582 case QXL_MODE_NATIVE:
583 return "native";
584 case QXL_MODE_UNDEFINED:
585 return "undefined";
586 case QXL_MODE_VGA:
587 return "vga";
588 }
589 return "INVALID";
590 }
591
592 static const char *io_port_to_string(uint32_t io_port)
593 {
594 if (io_port >= QXL_IO_RANGE_SIZE) {
595 return "out of range";
596 }
597 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
598 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
599 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
600 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
601 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
602 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
603 [QXL_IO_RESET] = "QXL_IO_RESET",
604 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
605 [QXL_IO_LOG] = "QXL_IO_LOG",
606 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
607 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
608 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
609 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
610 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
611 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
612 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
613 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
614 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
615 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
616 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
617 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
618 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
619 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
620 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
621 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
622 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
623 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
624 };
625 return io_port_to_string[io_port];
626 }
627
628 /* called from spice server thread context only */
629 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
630 {
631 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
632 SimpleSpiceUpdate *update;
633 QXLCommandRing *ring;
634 QXLCommand *cmd;
635 int notify, ret;
636
637 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
638
639 switch (qxl->mode) {
640 case QXL_MODE_VGA:
641 ret = false;
642 qemu_mutex_lock(&qxl->ssd.lock);
643 update = QTAILQ_FIRST(&qxl->ssd.updates);
644 if (update != NULL) {
645 QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
646 *ext = update->ext;
647 ret = true;
648 }
649 qemu_mutex_unlock(&qxl->ssd.lock);
650 if (ret) {
651 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
652 qxl_log_command(qxl, "vga", ext);
653 }
654 return ret;
655 case QXL_MODE_COMPAT:
656 case QXL_MODE_NATIVE:
657 case QXL_MODE_UNDEFINED:
658 ring = &qxl->ram->cmd_ring;
659 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
660 return false;
661 }
662 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
663 if (!cmd) {
664 return false;
665 }
666 ext->cmd = *cmd;
667 ext->group_id = MEMSLOT_GROUP_GUEST;
668 ext->flags = qxl->cmdflags;
669 SPICE_RING_POP(ring, notify);
670 qxl_ring_set_dirty(qxl);
671 if (notify) {
672 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
673 }
674 qxl->guest_primary.commands++;
675 qxl_track_command(qxl, ext);
676 qxl_log_command(qxl, "cmd", ext);
677 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
678 return true;
679 default:
680 return false;
681 }
682 }
683
684 /* called from spice server thread context only */
685 static int interface_req_cmd_notification(QXLInstance *sin)
686 {
687 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
688 int wait = 1;
689
690 trace_qxl_ring_command_req_notification(qxl->id);
691 switch (qxl->mode) {
692 case QXL_MODE_COMPAT:
693 case QXL_MODE_NATIVE:
694 case QXL_MODE_UNDEFINED:
695 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
696 qxl_ring_set_dirty(qxl);
697 break;
698 default:
699 /* nothing */
700 break;
701 }
702 return wait;
703 }
704
705 /* called from spice server thread context only */
706 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
707 {
708 QXLReleaseRing *ring = &d->ram->release_ring;
709 uint32_t prod;
710 int notify;
711
712 #define QXL_FREE_BUNCH_SIZE 32
713
714 if (ring->prod - ring->cons + 1 == ring->num_items) {
715 /* ring full -- can't push */
716 return;
717 }
718 if (!flush && d->oom_running) {
719 /* collect everything from oom handler before pushing */
720 return;
721 }
722 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
723 /* collect a bit more before pushing */
724 return;
725 }
726
727 SPICE_RING_PUSH(ring, notify);
728 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
729 d->guest_surfaces.count, d->num_free_res,
730 d->last_release, notify ? "yes" : "no");
731 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
732 ring->num_items, ring->prod, ring->cons);
733 if (notify) {
734 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
735 }
736
737 ring = &d->ram->release_ring;
738 prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
739 if (prod >= ARRAY_SIZE(ring->items)) {
740 qxl_set_guest_bug(d, "SPICE_RING_PROD_ITEM indices mismatch "
741 "%u >= %zu", prod, ARRAY_SIZE(ring->items));
742 return;
743 }
744 ring->items[prod].el = 0;
745 d->num_free_res = 0;
746 d->last_release = NULL;
747 qxl_ring_set_dirty(d);
748 }
749
750 /* called from spice server thread context only */
751 static void interface_release_resource(QXLInstance *sin,
752 QXLReleaseInfoExt ext)
753 {
754 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
755 QXLReleaseRing *ring;
756 uint32_t prod;
757 uint64_t id;
758
759 if (!ext.info) {
760 return;
761 }
762 if (ext.group_id == MEMSLOT_GROUP_HOST) {
763 /* host group -> vga mode update request */
764 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id);
765 SimpleSpiceUpdate *update;
766 g_assert(cmdext->cmd.type == QXL_CMD_DRAW);
767 update = container_of(cmdext, SimpleSpiceUpdate, ext);
768 qemu_spice_destroy_update(&qxl->ssd, update);
769 return;
770 }
771
772 /*
773 * ext->info points into guest-visible memory
774 * pci bar 0, $command.release_info
775 */
776 ring = &qxl->ram->release_ring;
777 prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
778 if (prod >= ARRAY_SIZE(ring->items)) {
779 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch "
780 "%u >= %zu", prod, ARRAY_SIZE(ring->items));
781 return;
782 }
783 if (ring->items[prod].el == 0) {
784 /* stick head into the ring */
785 id = ext.info->id;
786 ext.info->next = 0;
787 qxl_ram_set_dirty(qxl, &ext.info->next);
788 ring->items[prod].el = id;
789 qxl_ring_set_dirty(qxl);
790 } else {
791 /* append item to the list */
792 qxl->last_release->next = ext.info->id;
793 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
794 ext.info->next = 0;
795 qxl_ram_set_dirty(qxl, &ext.info->next);
796 }
797 qxl->last_release = ext.info;
798 qxl->num_free_res++;
799 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
800 qxl_push_free_res(qxl, 0);
801 }
802
803 /* called from spice server thread context only */
804 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
805 {
806 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
807 QXLCursorRing *ring;
808 QXLCommand *cmd;
809 int notify;
810
811 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
812
813 switch (qxl->mode) {
814 case QXL_MODE_COMPAT:
815 case QXL_MODE_NATIVE:
816 case QXL_MODE_UNDEFINED:
817 ring = &qxl->ram->cursor_ring;
818 if (SPICE_RING_IS_EMPTY(ring)) {
819 return false;
820 }
821 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
822 if (!cmd) {
823 return false;
824 }
825 ext->cmd = *cmd;
826 ext->group_id = MEMSLOT_GROUP_GUEST;
827 ext->flags = qxl->cmdflags;
828 SPICE_RING_POP(ring, notify);
829 qxl_ring_set_dirty(qxl);
830 if (notify) {
831 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
832 }
833 qxl->guest_primary.commands++;
834 qxl_track_command(qxl, ext);
835 qxl_log_command(qxl, "csr", ext);
836 if (qxl->have_vga) {
837 qxl_render_cursor(qxl, ext);
838 }
839 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
840 return true;
841 default:
842 return false;
843 }
844 }
845
846 /* called from spice server thread context only */
847 static int interface_req_cursor_notification(QXLInstance *sin)
848 {
849 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
850 int wait = 1;
851
852 trace_qxl_ring_cursor_req_notification(qxl->id);
853 switch (qxl->mode) {
854 case QXL_MODE_COMPAT:
855 case QXL_MODE_NATIVE:
856 case QXL_MODE_UNDEFINED:
857 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
858 qxl_ring_set_dirty(qxl);
859 break;
860 default:
861 /* nothing */
862 break;
863 }
864 return wait;
865 }
866
867 /* called from spice server thread context */
868 static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
869 {
870 /*
871 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
872 * use by xf86-video-qxl and is defined out in the qxl windows driver.
873 * Probably was at some earlier version that is prior to git start (2009),
874 * and is still guest trigerrable.
875 */
876 fprintf(stderr, "%s: deprecated\n", __func__);
877 }
878
879 /* called from spice server thread context only */
880 static int interface_flush_resources(QXLInstance *sin)
881 {
882 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
883 int ret;
884
885 ret = qxl->num_free_res;
886 if (ret) {
887 qxl_push_free_res(qxl, 1);
888 }
889 return ret;
890 }
891
892 static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
893
894 /* called from spice server thread context only */
895 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
896 {
897 uint32_t current_async;
898
899 qemu_mutex_lock(&qxl->async_lock);
900 current_async = qxl->current_async;
901 qxl->current_async = QXL_UNDEFINED_IO;
902 qemu_mutex_unlock(&qxl->async_lock);
903
904 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
905 if (!cookie) {
906 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
907 return;
908 }
909 if (cookie && current_async != cookie->io) {
910 fprintf(stderr,
911 "qxl: %s: error: current_async = %d != %"
912 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
913 }
914 switch (current_async) {
915 case QXL_IO_MEMSLOT_ADD_ASYNC:
916 case QXL_IO_DESTROY_PRIMARY_ASYNC:
917 case QXL_IO_UPDATE_AREA_ASYNC:
918 case QXL_IO_FLUSH_SURFACES_ASYNC:
919 case QXL_IO_MONITORS_CONFIG_ASYNC:
920 break;
921 case QXL_IO_CREATE_PRIMARY_ASYNC:
922 qxl_create_guest_primary_complete(qxl);
923 break;
924 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
925 qxl_spice_destroy_surfaces_complete(qxl);
926 break;
927 case QXL_IO_DESTROY_SURFACE_ASYNC:
928 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
929 break;
930 default:
931 fprintf(stderr, "qxl: %s: unexpected current_async %u\n", __func__,
932 current_async);
933 }
934 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
935 }
936
937 /* called from spice server thread context only */
938 static void interface_update_area_complete(QXLInstance *sin,
939 uint32_t surface_id,
940 QXLRect *dirty, uint32_t num_updated_rects)
941 {
942 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
943 int i;
944 int qxl_i;
945
946 QEMU_LOCK_GUARD(&qxl->ssd.lock);
947 if (surface_id != 0 || !num_updated_rects ||
948 !qxl->render_update_cookie_num) {
949 return;
950 }
951 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
952 dirty->right, dirty->top, dirty->bottom);
953 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
954 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
955 /*
956 * overflow - treat this as a full update. Not expected to be common.
957 */
958 trace_qxl_interface_update_area_complete_overflow(qxl->id,
959 QXL_NUM_DIRTY_RECTS);
960 qxl->guest_primary.resized = 1;
961 }
962 if (qxl->guest_primary.resized) {
963 /*
964 * Don't bother copying or scheduling the bh since we will flip
965 * the whole area anyway on completion of the update_area async call
966 */
967 return;
968 }
969 qxl_i = qxl->num_dirty_rects;
970 for (i = 0; i < num_updated_rects; i++) {
971 qxl->dirty[qxl_i++] = dirty[i];
972 }
973 qxl->num_dirty_rects += num_updated_rects;
974 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
975 qxl->num_dirty_rects);
976 qemu_bh_schedule(qxl->update_area_bh);
977 }
978
979 /* called from spice server thread context only */
980 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
981 {
982 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
983 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
984
985 switch (cookie->type) {
986 case QXL_COOKIE_TYPE_IO:
987 interface_async_complete_io(qxl, cookie);
988 g_free(cookie);
989 break;
990 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
991 qxl_render_update_area_done(qxl, cookie);
992 break;
993 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
994 break;
995 default:
996 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
997 __func__, cookie->type);
998 g_free(cookie);
999 }
1000 }
1001
1002 /* called from spice server thread context only */
1003 static void interface_set_client_capabilities(QXLInstance *sin,
1004 uint8_t client_present,
1005 uint8_t caps[58])
1006 {
1007 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1008
1009 if (qxl->revision < 4) {
1010 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
1011 qxl->revision);
1012 return;
1013 }
1014
1015 if (runstate_check(RUN_STATE_INMIGRATE) ||
1016 runstate_check(RUN_STATE_POSTMIGRATE)) {
1017 return;
1018 }
1019
1020 qxl->shadow_rom.client_present = client_present;
1021 memcpy(qxl->shadow_rom.client_capabilities, caps,
1022 sizeof(qxl->shadow_rom.client_capabilities));
1023 qxl->rom->client_present = client_present;
1024 memcpy(qxl->rom->client_capabilities, caps,
1025 sizeof(qxl->rom->client_capabilities));
1026 qxl_rom_set_dirty(qxl);
1027
1028 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
1029 }
1030
1031 static bool qxl_rom_monitors_config_changed(QXLRom *rom,
1032 VDAgentMonitorsConfig *monitors_config,
1033 unsigned int max_outputs)
1034 {
1035 int i;
1036 unsigned int monitors_count;
1037
1038 monitors_count = MIN(monitors_config->num_of_monitors, max_outputs);
1039
1040 if (rom->client_monitors_config.count != monitors_count) {
1041 return true;
1042 }
1043
1044 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1045 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1046 QXLURect *rect = &rom->client_monitors_config.heads[i];
1047 /* monitor->depth ignored */
1048 if ((rect->left != monitor->x) ||
1049 (rect->top != monitor->y) ||
1050 (rect->right != monitor->x + monitor->width) ||
1051 (rect->bottom != monitor->y + monitor->height)) {
1052 return true;
1053 }
1054 }
1055
1056 return false;
1057 }
1058
1059 /* called from main context only */
1060 static int interface_client_monitors_config(QXLInstance *sin,
1061 VDAgentMonitorsConfig *monitors_config)
1062 {
1063 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1064 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
1065 int i;
1066 unsigned max_outputs = ARRAY_SIZE(rom->client_monitors_config.heads);
1067 bool config_changed = false;
1068
1069 if (qxl->revision < 4) {
1070 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
1071 qxl->revision);
1072 return 0;
1073 }
1074 /*
1075 * Older windows drivers set int_mask to 0 when their ISR is called,
1076 * then later set it to ~0. So it doesn't relate to the actual interrupts
1077 * handled. However, they are old, so clearly they don't support this
1078 * interrupt
1079 */
1080 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1081 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1082 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1083 qxl->ram->int_mask,
1084 monitors_config);
1085 return 0;
1086 }
1087 if (!monitors_config) {
1088 return 1;
1089 }
1090
1091 /* limit number of outputs based on setting limit */
1092 if (qxl->max_outputs && qxl->max_outputs <= max_outputs) {
1093 max_outputs = qxl->max_outputs;
1094 }
1095
1096 config_changed = qxl_rom_monitors_config_changed(rom,
1097 monitors_config,
1098 max_outputs);
1099
1100 memset(&rom->client_monitors_config, 0,
1101 sizeof(rom->client_monitors_config));
1102 rom->client_monitors_config.count = monitors_config->num_of_monitors;
1103 /* monitors_config->flags ignored */
1104 if (rom->client_monitors_config.count >= max_outputs) {
1105 trace_qxl_client_monitors_config_capped(qxl->id,
1106 monitors_config->num_of_monitors,
1107 max_outputs);
1108 rom->client_monitors_config.count = max_outputs;
1109 }
1110 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1111 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1112 QXLURect *rect = &rom->client_monitors_config.heads[i];
1113 /* monitor->depth ignored */
1114 rect->left = monitor->x;
1115 rect->top = monitor->y;
1116 rect->right = monitor->x + monitor->width;
1117 rect->bottom = monitor->y + monitor->height;
1118 }
1119 rom->client_monitors_config_crc = qxl_crc32(
1120 (const uint8_t *)&rom->client_monitors_config,
1121 sizeof(rom->client_monitors_config));
1122 trace_qxl_client_monitors_config_crc(qxl->id,
1123 sizeof(rom->client_monitors_config),
1124 rom->client_monitors_config_crc);
1125
1126 trace_qxl_interrupt_client_monitors_config(qxl->id,
1127 rom->client_monitors_config.count,
1128 rom->client_monitors_config.heads);
1129 if (config_changed) {
1130 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1131 }
1132 return 1;
1133 }
1134
1135 static const QXLInterface qxl_interface = {
1136 .base.type = SPICE_INTERFACE_QXL,
1137 .base.description = "qxl gpu",
1138 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
1139 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
1140
1141 #if SPICE_HAS_ATTACHED_WORKER
1142 .attached_worker = interface_attached_worker,
1143 #else
1144 .attache_worker = interface_attach_worker,
1145 #endif
1146
1147 .set_compression_level = interface_set_compression_level,
1148 #if SPICE_NEEDS_SET_MM_TIME
1149 .set_mm_time = interface_set_mm_time,
1150 #endif
1151 .get_init_info = interface_get_init_info,
1152
1153 /* the callbacks below are called from spice server thread context */
1154 .get_command = interface_get_command,
1155 .req_cmd_notification = interface_req_cmd_notification,
1156 .release_resource = interface_release_resource,
1157 .get_cursor_command = interface_get_cursor_command,
1158 .req_cursor_notification = interface_req_cursor_notification,
1159 .notify_update = interface_notify_update,
1160 .flush_resources = interface_flush_resources,
1161 .async_complete = interface_async_complete,
1162 .update_area_complete = interface_update_area_complete,
1163 .set_client_capabilities = interface_set_client_capabilities,
1164 .client_monitors_config = interface_client_monitors_config,
1165 };
1166
1167 static const GraphicHwOps qxl_ops = {
1168 .gfx_update = qxl_hw_update,
1169 .gfx_update_async = true,
1170 };
1171
1172 static void qxl_enter_vga_mode(PCIQXLDevice *d)
1173 {
1174 if (d->mode == QXL_MODE_VGA) {
1175 return;
1176 }
1177 trace_qxl_enter_vga_mode(d->id);
1178 spice_qxl_driver_unload(&d->ssd.qxl);
1179 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga);
1180 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT);
1181 qemu_spice_create_host_primary(&d->ssd);
1182 d->mode = QXL_MODE_VGA;
1183 qemu_spice_display_switch(&d->ssd, d->ssd.ds);
1184 vga_dirty_log_start(&d->vga);
1185 graphic_hw_update(d->vga.con);
1186 }
1187
1188 static void qxl_exit_vga_mode(PCIQXLDevice *d)
1189 {
1190 if (d->mode != QXL_MODE_VGA) {
1191 return;
1192 }
1193 trace_qxl_exit_vga_mode(d->id);
1194 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d);
1195 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE);
1196 vga_dirty_log_stop(&d->vga);
1197 qxl_destroy_primary(d, QXL_SYNC);
1198 }
1199
1200 static void qxl_update_irq(PCIQXLDevice *d)
1201 {
1202 uint32_t pending = le32_to_cpu(d->ram->int_pending);
1203 uint32_t mask = le32_to_cpu(d->ram->int_mask);
1204 int level = !!(pending & mask);
1205 pci_set_irq(&d->pci, level);
1206 qxl_ring_set_dirty(d);
1207 }
1208
1209 static void qxl_check_state(PCIQXLDevice *d)
1210 {
1211 QXLRam *ram = d->ram;
1212 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
1213
1214 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1215 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
1216 }
1217
1218 static void qxl_reset_state(PCIQXLDevice *d)
1219 {
1220 QXLRom *rom = d->rom;
1221
1222 qxl_check_state(d);
1223 d->shadow_rom.update_id = cpu_to_le32(0);
1224 *rom = d->shadow_rom;
1225 qxl_rom_set_dirty(d);
1226 init_qxl_ram(d);
1227 d->num_free_res = 0;
1228 d->last_release = NULL;
1229 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
1230 qxl_update_irq(d);
1231 }
1232
1233 static void qxl_soft_reset(PCIQXLDevice *d)
1234 {
1235 trace_qxl_soft_reset(d->id);
1236 qxl_check_state(d);
1237 qxl_clear_guest_bug(d);
1238 qemu_mutex_lock(&d->async_lock);
1239 d->current_async = QXL_UNDEFINED_IO;
1240 qemu_mutex_unlock(&d->async_lock);
1241
1242 if (d->have_vga) {
1243 qxl_enter_vga_mode(d);
1244 } else {
1245 d->mode = QXL_MODE_UNDEFINED;
1246 }
1247 }
1248
1249 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1250 {
1251 bool startstop = qemu_spice_display_is_running(&d->ssd);
1252
1253 trace_qxl_hard_reset(d->id, loadvm);
1254
1255 if (startstop) {
1256 qemu_spice_display_stop();
1257 }
1258
1259 qxl_spice_reset_cursor(d);
1260 qxl_spice_reset_image_cache(d);
1261 qxl_reset_surfaces(d);
1262 qxl_reset_memslots(d);
1263
1264 /* pre loadvm reset must not touch QXLRam. This lives in
1265 * device memory, is migrated together with RAM and thus
1266 * already loaded at this point */
1267 if (!loadvm) {
1268 qxl_reset_state(d);
1269 }
1270 qemu_spice_create_host_memslot(&d->ssd);
1271 qxl_soft_reset(d);
1272
1273 if (startstop) {
1274 qemu_spice_display_start();
1275 }
1276 }
1277
1278 static void qxl_reset_handler(DeviceState *dev)
1279 {
1280 PCIQXLDevice *d = PCI_QXL(PCI_DEVICE(dev));
1281
1282 qxl_hard_reset(d, 0);
1283 }
1284
1285 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1286 {
1287 VGACommonState *vga = opaque;
1288 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1289
1290 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
1291 if (qxl->mode != QXL_MODE_VGA &&
1292 qxl->revision <= QXL_REVISION_STABLE_V12) {
1293 qxl_destroy_primary(qxl, QXL_SYNC);
1294 qxl_soft_reset(qxl);
1295 }
1296 vga_ioport_write(opaque, addr, val);
1297 }
1298
1299 static const MemoryRegionPortio qxl_vga_portio_list[] = {
1300 { 0x04, 2, 1, .read = vga_ioport_read,
1301 .write = qxl_vga_ioport_write }, /* 3b4 */
1302 { 0x0a, 1, 1, .read = vga_ioport_read,
1303 .write = qxl_vga_ioport_write }, /* 3ba */
1304 { 0x10, 16, 1, .read = vga_ioport_read,
1305 .write = qxl_vga_ioport_write }, /* 3c0 */
1306 { 0x24, 2, 1, .read = vga_ioport_read,
1307 .write = qxl_vga_ioport_write }, /* 3d4 */
1308 { 0x2a, 1, 1, .read = vga_ioport_read,
1309 .write = qxl_vga_ioport_write }, /* 3da */
1310 PORTIO_END_OF_LIST(),
1311 };
1312
1313 static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1314 qxl_async_io async)
1315 {
1316 static const int regions[] = {
1317 QXL_RAM_RANGE_INDEX,
1318 QXL_VRAM_RANGE_INDEX,
1319 QXL_VRAM64_RANGE_INDEX,
1320 };
1321 uint64_t guest_start;
1322 uint64_t guest_end;
1323 int pci_region;
1324 pcibus_t pci_start;
1325 pcibus_t pci_end;
1326 MemoryRegion *mr;
1327 intptr_t virt_start;
1328 QXLDevMemSlot memslot;
1329 int i;
1330
1331 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1332 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1333
1334 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
1335
1336 if (slot_id >= NUM_MEMSLOTS) {
1337 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
1338 slot_id, NUM_MEMSLOTS);
1339 return 1;
1340 }
1341 if (guest_start > guest_end) {
1342 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
1343 " > 0x%" PRIx64, __func__, guest_start, guest_end);
1344 return 1;
1345 }
1346
1347 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1348 pci_region = regions[i];
1349 pci_start = d->pci.io_regions[pci_region].addr;
1350 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1351 /* mapped? */
1352 if (pci_start == -1) {
1353 continue;
1354 }
1355 /* start address in range ? */
1356 if (guest_start < pci_start || guest_start > pci_end) {
1357 continue;
1358 }
1359 /* end address in range ? */
1360 if (guest_end > pci_end) {
1361 continue;
1362 }
1363 /* passed */
1364 break;
1365 }
1366 if (i == ARRAY_SIZE(regions)) {
1367 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
1368 return 1;
1369 }
1370
1371 switch (pci_region) {
1372 case QXL_RAM_RANGE_INDEX:
1373 mr = &d->vga.vram;
1374 break;
1375 case QXL_VRAM_RANGE_INDEX:
1376 case 4 /* vram 64bit */:
1377 mr = &d->vram_bar;
1378 break;
1379 default:
1380 /* should not happen */
1381 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
1382 return 1;
1383 }
1384 assert(guest_end - pci_start <= memory_region_size(mr));
1385
1386 virt_start = (intptr_t)memory_region_get_ram_ptr(mr);
1387 memslot.slot_id = slot_id;
1388 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1389 memslot.virt_start = virt_start + (guest_start - pci_start);
1390 memslot.virt_end = virt_start + (guest_end - pci_start);
1391 memslot.addr_delta = memslot.virt_start - delta;
1392 memslot.generation = d->rom->slot_generation = 0;
1393 qxl_rom_set_dirty(d);
1394
1395 qemu_spice_add_memslot(&d->ssd, &memslot, async);
1396 d->guest_slots[slot_id].mr = mr;
1397 d->guest_slots[slot_id].offset = memslot.virt_start - virt_start;
1398 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1399 d->guest_slots[slot_id].delta = delta;
1400 d->guest_slots[slot_id].active = 1;
1401 return 0;
1402 }
1403
1404 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1405 {
1406 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
1407 d->guest_slots[slot_id].active = 0;
1408 }
1409
1410 static void qxl_reset_memslots(PCIQXLDevice *d)
1411 {
1412 qxl_spice_reset_memslots(d);
1413 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1414 }
1415
1416 static void qxl_reset_surfaces(PCIQXLDevice *d)
1417 {
1418 trace_qxl_reset_surfaces(d->id);
1419 d->mode = QXL_MODE_UNDEFINED;
1420 qxl_spice_destroy_surfaces(d, QXL_SYNC);
1421 }
1422
1423 /* can be also called from spice server thread context */
1424 static bool qxl_get_check_slot_offset(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1425 uint32_t *s, uint64_t *o,
1426 size_t size_requested)
1427 {
1428 uint64_t phys = le64_to_cpu(pqxl);
1429 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1430 uint64_t offset = phys & 0xffffffffffff;
1431 uint64_t size_available;
1432
1433 if (slot >= NUM_MEMSLOTS) {
1434 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1435 NUM_MEMSLOTS);
1436 return false;
1437 }
1438 if (!qxl->guest_slots[slot].active) {
1439 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
1440 return false;
1441 }
1442 if (offset < qxl->guest_slots[slot].delta) {
1443 qxl_set_guest_bug(qxl,
1444 "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
1445 slot, offset, qxl->guest_slots[slot].delta);
1446 return false;
1447 }
1448 offset -= qxl->guest_slots[slot].delta;
1449 if (offset > qxl->guest_slots[slot].size) {
1450 qxl_set_guest_bug(qxl,
1451 "slot %d offset %"PRIu64" > size %"PRIu64"\n",
1452 slot, offset, qxl->guest_slots[slot].size);
1453 return false;
1454 }
1455 size_available = memory_region_size(qxl->guest_slots[slot].mr);
1456 if (qxl->guest_slots[slot].offset + offset >= size_available) {
1457 qxl_set_guest_bug(qxl,
1458 "slot %d offset %"PRIu64" > region size %"PRIu64"\n",
1459 slot, qxl->guest_slots[slot].offset + offset,
1460 size_available);
1461 return false;
1462 }
1463 size_available -= qxl->guest_slots[slot].offset + offset;
1464 if (size_requested > size_available) {
1465 qxl_set_guest_bug(qxl,
1466 "slot %d offset %"PRIu64" size %zu: "
1467 "overrun by %"PRIu64" bytes\n",
1468 slot, offset, size_requested,
1469 size_requested - size_available);
1470 return false;
1471 }
1472
1473 *s = slot;
1474 *o = offset;
1475 return true;
1476 }
1477
1478 /* can be also called from spice server thread context */
1479 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id,
1480 size_t size)
1481 {
1482 uint64_t offset;
1483 uint32_t slot;
1484 void *ptr;
1485
1486 switch (group_id) {
1487 case MEMSLOT_GROUP_HOST:
1488 offset = le64_to_cpu(pqxl) & 0xffffffffffff;
1489 return (void *)(intptr_t)offset;
1490 case MEMSLOT_GROUP_GUEST:
1491 if (!qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset, size)) {
1492 return NULL;
1493 }
1494 ptr = memory_region_get_ram_ptr(qxl->guest_slots[slot].mr);
1495 ptr += qxl->guest_slots[slot].offset;
1496 ptr += offset;
1497 return ptr;
1498 }
1499 return NULL;
1500 }
1501
1502 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1503 {
1504 /* for local rendering */
1505 qxl_render_resize(qxl);
1506 }
1507
1508 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1509 qxl_async_io async)
1510 {
1511 QXLDevSurfaceCreate surface;
1512 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1513 uint32_t requested_height = le32_to_cpu(sc->height);
1514 int requested_stride = le32_to_cpu(sc->stride);
1515
1516 if (requested_stride == INT32_MIN ||
1517 abs(requested_stride) * (uint64_t)requested_height
1518 > qxl->vgamem_size) {
1519 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer"
1520 " stride %d x height %" PRIu32 " > %" PRIu32,
1521 __func__, requested_stride, requested_height,
1522 qxl->vgamem_size);
1523 return;
1524 }
1525
1526 if (qxl->mode == QXL_MODE_NATIVE) {
1527 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
1528 __func__);
1529 }
1530 qxl_exit_vga_mode(qxl);
1531
1532 surface.format = le32_to_cpu(sc->format);
1533 surface.height = le32_to_cpu(sc->height);
1534 surface.mem = le64_to_cpu(sc->mem);
1535 surface.position = le32_to_cpu(sc->position);
1536 surface.stride = le32_to_cpu(sc->stride);
1537 surface.width = le32_to_cpu(sc->width);
1538 surface.type = le32_to_cpu(sc->type);
1539 surface.flags = le32_to_cpu(sc->flags);
1540 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1541 sc->format, sc->position);
1542 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1543 sc->flags);
1544
1545 if ((surface.stride & 0x3) != 0) {
1546 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1547 surface.stride);
1548 return;
1549 }
1550
1551 surface.mouse_mode = true;
1552 surface.group_id = MEMSLOT_GROUP_GUEST;
1553 if (loadvm) {
1554 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1555 }
1556
1557 qxl->mode = QXL_MODE_NATIVE;
1558 qxl->cmdflags = 0;
1559 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1560
1561 if (async == QXL_SYNC) {
1562 qxl_create_guest_primary_complete(qxl);
1563 }
1564 }
1565
1566 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1567 * done (in QXL_SYNC case), 0 otherwise. */
1568 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1569 {
1570 if (d->mode == QXL_MODE_UNDEFINED) {
1571 return 0;
1572 }
1573 trace_qxl_destroy_primary(d->id);
1574 d->mode = QXL_MODE_UNDEFINED;
1575 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1576 qxl_spice_reset_cursor(d);
1577 return 1;
1578 }
1579
1580 static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm)
1581 {
1582 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1583 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1584 QXLMode *mode = d->modes->modes + modenr;
1585 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1586 QXLMemSlot slot = {
1587 .mem_start = start,
1588 .mem_end = end
1589 };
1590
1591 if (modenr >= d->modes->n_modes) {
1592 qxl_set_guest_bug(d, "mode number out of range");
1593 return;
1594 }
1595
1596 QXLSurfaceCreate surface = {
1597 .width = mode->x_res,
1598 .height = mode->y_res,
1599 .stride = -mode->x_res * 4,
1600 .format = SPICE_SURFACE_FMT_32_xRGB,
1601 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1602 .mouse_mode = true,
1603 .mem = devmem + d->shadow_rom.draw_area_offset,
1604 };
1605
1606 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1607 devmem);
1608 if (!loadvm) {
1609 qxl_hard_reset(d, 0);
1610 }
1611
1612 d->guest_slots[0].slot = slot;
1613 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
1614
1615 d->guest_primary.surface = surface;
1616 qxl_create_guest_primary(d, 0, QXL_SYNC);
1617
1618 d->mode = QXL_MODE_COMPAT;
1619 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1620 if (mode->bits == 16) {
1621 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1622 }
1623 d->shadow_rom.mode = cpu_to_le32(modenr);
1624 d->rom->mode = cpu_to_le32(modenr);
1625 qxl_rom_set_dirty(d);
1626 }
1627
1628 static void ioport_write(void *opaque, hwaddr addr,
1629 uint64_t val, unsigned size)
1630 {
1631 PCIQXLDevice *d = opaque;
1632 uint32_t io_port = addr;
1633 qxl_async_io async = QXL_SYNC;
1634 uint32_t orig_io_port;
1635
1636 if (d->guest_bug && io_port != QXL_IO_RESET) {
1637 return;
1638 }
1639
1640 if (d->revision <= QXL_REVISION_STABLE_V10 &&
1641 io_port > QXL_IO_FLUSH_RELEASE) {
1642 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1643 io_port, d->revision);
1644 return;
1645 }
1646
1647 switch (io_port) {
1648 case QXL_IO_RESET:
1649 case QXL_IO_SET_MODE:
1650 case QXL_IO_MEMSLOT_ADD:
1651 case QXL_IO_MEMSLOT_DEL:
1652 case QXL_IO_CREATE_PRIMARY:
1653 case QXL_IO_UPDATE_IRQ:
1654 case QXL_IO_LOG:
1655 case QXL_IO_MEMSLOT_ADD_ASYNC:
1656 case QXL_IO_CREATE_PRIMARY_ASYNC:
1657 break;
1658 default:
1659 if (d->mode != QXL_MODE_VGA) {
1660 break;
1661 }
1662 trace_qxl_io_unexpected_vga_mode(d->id,
1663 addr, val, io_port_to_string(io_port));
1664 /* be nice to buggy guest drivers */
1665 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1666 io_port < QXL_IO_RANGE_SIZE) {
1667 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1668 }
1669 return;
1670 }
1671
1672 /* we change the io_port to avoid ifdeffery in the main switch */
1673 orig_io_port = io_port;
1674 switch (io_port) {
1675 case QXL_IO_UPDATE_AREA_ASYNC:
1676 io_port = QXL_IO_UPDATE_AREA;
1677 goto async_common;
1678 case QXL_IO_MEMSLOT_ADD_ASYNC:
1679 io_port = QXL_IO_MEMSLOT_ADD;
1680 goto async_common;
1681 case QXL_IO_CREATE_PRIMARY_ASYNC:
1682 io_port = QXL_IO_CREATE_PRIMARY;
1683 goto async_common;
1684 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1685 io_port = QXL_IO_DESTROY_PRIMARY;
1686 goto async_common;
1687 case QXL_IO_DESTROY_SURFACE_ASYNC:
1688 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1689 goto async_common;
1690 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1691 io_port = QXL_IO_DESTROY_ALL_SURFACES;
1692 goto async_common;
1693 case QXL_IO_FLUSH_SURFACES_ASYNC:
1694 case QXL_IO_MONITORS_CONFIG_ASYNC:
1695 async_common:
1696 async = QXL_ASYNC;
1697 WITH_QEMU_LOCK_GUARD(&d->async_lock) {
1698 if (d->current_async != QXL_UNDEFINED_IO) {
1699 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
1700 io_port, d->current_async);
1701 return;
1702 }
1703 d->current_async = orig_io_port;
1704 }
1705 break;
1706 default:
1707 break;
1708 }
1709 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode),
1710 addr, io_port_to_string(addr),
1711 val, size, async);
1712
1713 switch (io_port) {
1714 case QXL_IO_UPDATE_AREA:
1715 {
1716 QXLCookie *cookie = NULL;
1717 QXLRect update = d->ram->update_area;
1718
1719 if (d->ram->update_surface > d->ssd.num_surfaces) {
1720 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1721 d->ram->update_surface);
1722 break;
1723 }
1724 if (update.left >= update.right || update.top >= update.bottom ||
1725 update.left < 0 || update.top < 0) {
1726 qxl_set_guest_bug(d,
1727 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1728 update.left, update.top, update.right, update.bottom);
1729 if (update.left == update.right || update.top == update.bottom) {
1730 /* old drivers may provide empty area, keep going */
1731 qxl_clear_guest_bug(d);
1732 goto cancel_async;
1733 }
1734 break;
1735 }
1736 if (async == QXL_ASYNC) {
1737 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1738 QXL_IO_UPDATE_AREA_ASYNC);
1739 cookie->u.area = update;
1740 }
1741 qxl_spice_update_area(d, d->ram->update_surface,
1742 cookie ? &cookie->u.area : &update,
1743 NULL, 0, 0, async, cookie);
1744 break;
1745 }
1746 case QXL_IO_NOTIFY_CMD:
1747 qemu_spice_wakeup(&d->ssd);
1748 break;
1749 case QXL_IO_NOTIFY_CURSOR:
1750 qemu_spice_wakeup(&d->ssd);
1751 break;
1752 case QXL_IO_UPDATE_IRQ:
1753 qxl_update_irq(d);
1754 break;
1755 case QXL_IO_NOTIFY_OOM:
1756 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1757 break;
1758 }
1759 d->oom_running = 1;
1760 qxl_spice_oom(d);
1761 d->oom_running = 0;
1762 break;
1763 case QXL_IO_SET_MODE:
1764 qxl_set_mode(d, val, 0);
1765 break;
1766 case QXL_IO_LOG:
1767 #ifdef CONFIG_MODULES
1768 /*
1769 * FIXME
1770 * trace_event_get_state_backends() does not work for modules,
1771 * it leads to "undefined symbol: qemu_qxl_io_log_semaphore"
1772 */
1773 if (true) {
1774 #else
1775 if (trace_event_get_state_backends(TRACE_QXL_IO_LOG) || d->guestdebug) {
1776 #endif
1777 /* We cannot trust the guest to NUL terminate d->ram->log_buf */
1778 char *log_buf = g_strndup((const char *)d->ram->log_buf,
1779 sizeof(d->ram->log_buf));
1780 trace_qxl_io_log(d->id, log_buf);
1781 if (d->guestdebug) {
1782 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1783 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), log_buf);
1784 }
1785 g_free(log_buf);
1786 }
1787 break;
1788 case QXL_IO_RESET:
1789 qxl_hard_reset(d, 0);
1790 break;
1791 case QXL_IO_MEMSLOT_ADD:
1792 if (val >= NUM_MEMSLOTS) {
1793 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1794 break;
1795 }
1796 if (d->guest_slots[val].active) {
1797 qxl_set_guest_bug(d,
1798 "QXL_IO_MEMSLOT_ADD: memory slot already active");
1799 break;
1800 }
1801 d->guest_slots[val].slot = d->ram->mem_slot;
1802 qxl_add_memslot(d, val, 0, async);
1803 break;
1804 case QXL_IO_MEMSLOT_DEL:
1805 if (val >= NUM_MEMSLOTS) {
1806 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1807 break;
1808 }
1809 qxl_del_memslot(d, val);
1810 break;
1811 case QXL_IO_CREATE_PRIMARY:
1812 if (val != 0) {
1813 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1814 async);
1815 goto cancel_async;
1816 }
1817 d->guest_primary.surface = d->ram->create_surface;
1818 qxl_create_guest_primary(d, 0, async);
1819 break;
1820 case QXL_IO_DESTROY_PRIMARY:
1821 if (val != 0) {
1822 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1823 async);
1824 goto cancel_async;
1825 }
1826 if (!qxl_destroy_primary(d, async)) {
1827 trace_qxl_io_destroy_primary_ignored(d->id,
1828 qxl_mode_to_string(d->mode));
1829 goto cancel_async;
1830 }
1831 break;
1832 case QXL_IO_DESTROY_SURFACE_WAIT:
1833 if (val >= d->ssd.num_surfaces) {
1834 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1835 "%" PRIu64 " >= NUM_SURFACES", async, val);
1836 goto cancel_async;
1837 }
1838 qxl_spice_destroy_surface_wait(d, val, async);
1839 break;
1840 case QXL_IO_FLUSH_RELEASE: {
1841 QXLReleaseRing *ring = &d->ram->release_ring;
1842 if (ring->prod - ring->cons + 1 == ring->num_items) {
1843 fprintf(stderr,
1844 "ERROR: no flush, full release ring [p%d,%dc]\n",
1845 ring->prod, ring->cons);
1846 }
1847 qxl_push_free_res(d, 1 /* flush */);
1848 break;
1849 }
1850 case QXL_IO_FLUSH_SURFACES_ASYNC:
1851 qxl_spice_flush_surfaces_async(d);
1852 break;
1853 case QXL_IO_DESTROY_ALL_SURFACES:
1854 d->mode = QXL_MODE_UNDEFINED;
1855 qxl_spice_destroy_surfaces(d, async);
1856 break;
1857 case QXL_IO_MONITORS_CONFIG_ASYNC:
1858 qxl_spice_monitors_config_async(d, 0);
1859 break;
1860 default:
1861 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
1862 }
1863 return;
1864 cancel_async:
1865 if (async) {
1866 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1867 qemu_mutex_lock(&d->async_lock);
1868 d->current_async = QXL_UNDEFINED_IO;
1869 qemu_mutex_unlock(&d->async_lock);
1870 }
1871 }
1872
1873 static uint64_t ioport_read(void *opaque, hwaddr addr,
1874 unsigned size)
1875 {
1876 PCIQXLDevice *qxl = opaque;
1877
1878 trace_qxl_io_read_unexpected(qxl->id);
1879 return 0xff;
1880 }
1881
1882 static const MemoryRegionOps qxl_io_ops = {
1883 .read = ioport_read,
1884 .write = ioport_write,
1885 .valid = {
1886 .min_access_size = 1,
1887 .max_access_size = 1,
1888 },
1889 };
1890
1891 static void qxl_update_irq_bh(void *opaque)
1892 {
1893 PCIQXLDevice *d = opaque;
1894 qxl_update_irq(d);
1895 }
1896
1897 static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1898 {
1899 uint32_t old_pending;
1900 uint32_t le_events = cpu_to_le32(events);
1901
1902 trace_qxl_send_events(d->id, events);
1903 if (!qemu_spice_display_is_running(&d->ssd)) {
1904 /* spice-server tracks guest running state and should not do this */
1905 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1906 __func__);
1907 trace_qxl_send_events_vm_stopped(d->id, events);
1908 return;
1909 }
1910 /*
1911 * Older versions of Spice forgot to define the QXLRam struct
1912 * with the '__aligned__(4)' attribute. clang 7 and newer will
1913 * thus warn that qatomic_fetch_or(&d->ram->int_pending, ...)
1914 * might be a misaligned atomic access, and will generate an
1915 * out-of-line call for it, which results in a link error since
1916 * we don't currently link against libatomic.
1917 *
1918 * In fact we set up d->ram in init_qxl_ram() so it always starts
1919 * at a 4K boundary, so we know that &d->ram->int_pending is
1920 * naturally aligned for a uint32_t. Newer Spice versions
1921 * (with Spice commit beda5ec7a6848be20c0cac2a9a8ef2a41e8069c1)
1922 * will fix the bug directly. To deal with older versions,
1923 * we tell the compiler to assume the address really is aligned.
1924 * Any compiler which cares about the misalignment will have
1925 * __builtin_assume_aligned.
1926 */
1927 #ifdef HAS_ASSUME_ALIGNED
1928 #define ALIGNED_UINT32_PTR(P) ((uint32_t *)__builtin_assume_aligned(P, 4))
1929 #else
1930 #define ALIGNED_UINT32_PTR(P) ((uint32_t *)P)
1931 #endif
1932
1933 old_pending = qatomic_fetch_or(ALIGNED_UINT32_PTR(&d->ram->int_pending),
1934 le_events);
1935 if ((old_pending & le_events) == le_events) {
1936 return;
1937 }
1938 qemu_bh_schedule(d->update_irq);
1939 }
1940
1941 /* graphics console */
1942
1943 static void qxl_hw_update(void *opaque)
1944 {
1945 PCIQXLDevice *qxl = opaque;
1946
1947 qxl_render_update(qxl);
1948 }
1949
1950 static void qxl_dirty_one_surface(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1951 uint32_t height, int32_t stride)
1952 {
1953 uint64_t offset, size;
1954 uint32_t slot;
1955 bool rc;
1956
1957 size = (uint64_t)height * abs(stride);
1958 rc = qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset, size);
1959 assert(rc == true);
1960 trace_qxl_surfaces_dirty(qxl->id, offset, size);
1961 qxl_set_dirty(qxl->guest_slots[slot].mr,
1962 qxl->guest_slots[slot].offset + offset,
1963 qxl->guest_slots[slot].offset + offset + size);
1964 }
1965
1966 static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1967 {
1968 int i;
1969
1970 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
1971 return;
1972 }
1973
1974 /* dirty the primary surface */
1975 qxl_dirty_one_surface(qxl, qxl->guest_primary.surface.mem,
1976 qxl->guest_primary.surface.height,
1977 qxl->guest_primary.surface.stride);
1978
1979 /* dirty the off-screen surfaces */
1980 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
1981 QXLSurfaceCmd *cmd;
1982
1983 if (qxl->guest_surfaces.cmds[i] == 0) {
1984 continue;
1985 }
1986
1987 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1988 MEMSLOT_GROUP_GUEST, sizeof(QXLSurfaceCmd));
1989 assert(cmd);
1990 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1991 qxl_dirty_one_surface(qxl, cmd->u.surface_create.data,
1992 cmd->u.surface_create.height,
1993 cmd->u.surface_create.stride);
1994 }
1995 }
1996
1997 static void qxl_vm_change_state_handler(void *opaque, bool running,
1998 RunState state)
1999 {
2000 PCIQXLDevice *qxl = opaque;
2001
2002 if (running) {
2003 /*
2004 * if qxl_send_events was called from spice server context before
2005 * migration ended, qxl_update_irq for these events might not have been
2006 * called
2007 */
2008 qxl_update_irq(qxl);
2009 } else {
2010 /* make sure surfaces are saved before migration */
2011 qxl_dirty_surfaces(qxl);
2012 }
2013 }
2014
2015 /* display change listener */
2016
2017 static void display_update(DisplayChangeListener *dcl,
2018 int x, int y, int w, int h)
2019 {
2020 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2021
2022 if (qxl->mode == QXL_MODE_VGA) {
2023 qemu_spice_display_update(&qxl->ssd, x, y, w, h);
2024 }
2025 }
2026
2027 static void display_switch(DisplayChangeListener *dcl,
2028 struct DisplaySurface *surface)
2029 {
2030 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2031
2032 qxl->ssd.ds = surface;
2033 if (qxl->mode == QXL_MODE_VGA) {
2034 qemu_spice_display_switch(&qxl->ssd, surface);
2035 }
2036 }
2037
2038 static void display_refresh(DisplayChangeListener *dcl)
2039 {
2040 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2041
2042 if (qxl->mode == QXL_MODE_VGA) {
2043 qemu_spice_display_refresh(&qxl->ssd);
2044 }
2045 }
2046
2047 static DisplayChangeListenerOps display_listener_ops = {
2048 .dpy_name = "spice/qxl",
2049 .dpy_gfx_update = display_update,
2050 .dpy_gfx_switch = display_switch,
2051 .dpy_refresh = display_refresh,
2052 };
2053
2054 static void qxl_init_ramsize(PCIQXLDevice *qxl)
2055 {
2056 /* vga mode framebuffer / primary surface (bar 0, first part) */
2057 if (qxl->vgamem_size_mb < 8) {
2058 qxl->vgamem_size_mb = 8;
2059 }
2060 /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be
2061 * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now).
2062 */
2063 if (qxl->vgamem_size_mb > 256) {
2064 qxl->vgamem_size_mb = 256;
2065 }
2066 qxl->vgamem_size = qxl->vgamem_size_mb * MiB;
2067
2068 /* vga ram (bar 0, total) */
2069 if (qxl->ram_size_mb != -1) {
2070 qxl->vga.vram_size = qxl->ram_size_mb * MiB;
2071 }
2072 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
2073 qxl->vga.vram_size = qxl->vgamem_size * 2;
2074 }
2075
2076 /* vram32 (surfaces, 32bit, bar 1) */
2077 if (qxl->vram32_size_mb != -1) {
2078 qxl->vram32_size = qxl->vram32_size_mb * MiB;
2079 }
2080 if (qxl->vram32_size < 4096) {
2081 qxl->vram32_size = 4096;
2082 }
2083
2084 /* vram (surfaces, 64bit, bar 4+5) */
2085 if (qxl->vram_size_mb != -1) {
2086 qxl->vram_size = (uint64_t)qxl->vram_size_mb * MiB;
2087 }
2088 if (qxl->vram_size < qxl->vram32_size) {
2089 qxl->vram_size = qxl->vram32_size;
2090 }
2091
2092 if (qxl->revision == 1) {
2093 qxl->vram32_size = 4096;
2094 qxl->vram_size = 4096;
2095 }
2096 qxl->vgamem_size = pow2ceil(qxl->vgamem_size);
2097 qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size);
2098 qxl->vram32_size = pow2ceil(qxl->vram32_size);
2099 qxl->vram_size = pow2ceil(qxl->vram_size);
2100 }
2101
2102 static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
2103 {
2104 uint8_t* config = qxl->pci.config;
2105 uint32_t pci_device_rev;
2106 uint32_t io_size;
2107
2108 qemu_spice_display_init_common(&qxl->ssd);
2109 qxl->mode = QXL_MODE_UNDEFINED;
2110 qxl->num_memslots = NUM_MEMSLOTS;
2111 qemu_mutex_init(&qxl->track_lock);
2112 qemu_mutex_init(&qxl->async_lock);
2113 qxl->current_async = QXL_UNDEFINED_IO;
2114 qxl->guest_bug = 0;
2115
2116 switch (qxl->revision) {
2117 case 1: /* spice 0.4 -- qxl-1 */
2118 pci_device_rev = QXL_REVISION_STABLE_V04;
2119 io_size = 8;
2120 break;
2121 case 2: /* spice 0.6 -- qxl-2 */
2122 pci_device_rev = QXL_REVISION_STABLE_V06;
2123 io_size = 16;
2124 break;
2125 case 3: /* qxl-3 */
2126 pci_device_rev = QXL_REVISION_STABLE_V10;
2127 io_size = 32; /* PCI region size must be pow2 */
2128 break;
2129 case 4: /* qxl-4 */
2130 pci_device_rev = QXL_REVISION_STABLE_V12;
2131 io_size = pow2ceil(QXL_IO_RANGE_SIZE);
2132 break;
2133 case 5: /* qxl-5 */
2134 pci_device_rev = QXL_REVISION_STABLE_V12 + 1;
2135 io_size = pow2ceil(QXL_IO_RANGE_SIZE);
2136 break;
2137 default:
2138 error_setg(errp, "Invalid revision %d for qxl device (max %d)",
2139 qxl->revision, QXL_DEFAULT_REVISION);
2140 return;
2141 }
2142
2143 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
2144 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
2145
2146 qxl->rom_size = qxl_rom_size();
2147 memory_region_init_rom(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom",
2148 qxl->rom_size, &error_fatal);
2149 init_qxl_rom(qxl);
2150 init_qxl_ram(qxl);
2151
2152 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
2153 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram",
2154 qxl->vram_size, &error_fatal);
2155 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32",
2156 &qxl->vram_bar, 0, qxl->vram32_size);
2157
2158 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl,
2159 "qxl-ioports", io_size);
2160 if (qxl->have_vga) {
2161 vga_dirty_log_start(&qxl->vga);
2162 }
2163 memory_region_set_flush_coalesced(&qxl->io_bar);
2164
2165
2166 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
2167 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
2168
2169 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
2170 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
2171
2172 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
2173 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
2174
2175 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
2176 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2177
2178 if (qxl->vram32_size < qxl->vram_size) {
2179 /*
2180 * Make the 64bit vram bar show up only in case it is
2181 * configured to be larger than the 32bit vram bar.
2182 */
2183 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2184 PCI_BASE_ADDRESS_SPACE_MEMORY |
2185 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2186 PCI_BASE_ADDRESS_MEM_PREFETCH,
2187 &qxl->vram_bar);
2188 }
2189
2190 /* print pci bar details */
2191 dprint(qxl, 1, "ram/%s: %" PRId64 " MB [region 0]\n",
2192 qxl->have_vga ? "pri" : "sec", qxl->vga.vram_size / MiB);
2193 dprint(qxl, 1, "vram/32: %" PRIx64 " MB [region 1]\n",
2194 qxl->vram32_size / MiB);
2195 dprint(qxl, 1, "vram/64: %" PRIx64 " MB %s\n",
2196 qxl->vram_size / MiB,
2197 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
2198
2199 qxl->ssd.qxl.base.sif = &qxl_interface.base;
2200 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
2201 error_setg(errp, "qxl interface %d.%d not supported by spice-server",
2202 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2203 return;
2204 }
2205
2206 #if SPICE_SERVER_VERSION >= 0x000e02 /* release 0.14.2 */
2207 Error *err = NULL;
2208 char device_address[256] = "";
2209 if (qemu_console_fill_device_address(qxl->vga.con,
2210 device_address, sizeof(device_address),
2211 &err)) {
2212 spice_qxl_set_device_info(&qxl->ssd.qxl,
2213 device_address,
2214 0,
2215 qxl->max_outputs);
2216 } else {
2217 error_report_err(err);
2218 }
2219 #endif
2220
2221 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2222
2223 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl);
2224 qxl_reset_state(qxl);
2225
2226 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
2227 qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd);
2228 }
2229
2230 static void qxl_realize_primary(PCIDevice *dev, Error **errp)
2231 {
2232 PCIQXLDevice *qxl = PCI_QXL(dev);
2233 VGACommonState *vga = &qxl->vga;
2234 Error *local_err = NULL;
2235
2236 qxl_init_ramsize(qxl);
2237 vga->vbe_size = qxl->vgamem_size;
2238 vga->vram_size_mb = qxl->vga.vram_size / MiB;
2239 vga_common_init(vga, OBJECT(dev), &local_err);
2240 if (local_err) {
2241 error_propagate(errp, local_err);
2242 return;
2243 }
2244 vga_init(vga, OBJECT(dev),
2245 pci_address_space(dev), pci_address_space_io(dev), false);
2246 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list,
2247 vga, "vga");
2248 portio_list_set_flush_coalesced(&qxl->vga_port_list);
2249 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0);
2250 qxl->have_vga = true;
2251
2252 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
2253 qxl->id = qemu_console_get_index(vga->con); /* == channel_id */
2254 if (qxl->id != 0) {
2255 error_setg(errp, "primary qxl-vga device must be console 0 "
2256 "(first display device on the command line)");
2257 return;
2258 }
2259
2260 qxl_realize_common(qxl, &local_err);
2261 if (local_err) {
2262 error_propagate(errp, local_err);
2263 return;
2264 }
2265
2266 qxl->ssd.dcl.ops = &display_listener_ops;
2267 qxl->ssd.dcl.con = vga->con;
2268 register_displaychangelistener(&qxl->ssd.dcl);
2269 }
2270
2271 static void qxl_realize_secondary(PCIDevice *dev, Error **errp)
2272 {
2273 PCIQXLDevice *qxl = PCI_QXL(dev);
2274
2275 qxl_init_ramsize(qxl);
2276 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram",
2277 qxl->vga.vram_size, &error_fatal);
2278 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
2279 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
2280 qxl->ssd.dcl.con = qxl->vga.con;
2281 qxl->id = qemu_console_get_index(qxl->vga.con); /* == channel_id */
2282
2283 qxl_realize_common(qxl, errp);
2284 }
2285
2286 static int qxl_pre_save(void *opaque)
2287 {
2288 PCIQXLDevice* d = opaque;
2289 uint8_t *ram_start = d->vga.vram_ptr;
2290
2291 trace_qxl_pre_save(d->id);
2292 if (d->last_release == NULL) {
2293 d->last_release_offset = 0;
2294 } else {
2295 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2296 }
2297 if (d->last_release_offset >= d->vga.vram_size) {
2298 return 1;
2299 }
2300
2301 return 0;
2302 }
2303
2304 static int qxl_pre_load(void *opaque)
2305 {
2306 PCIQXLDevice* d = opaque;
2307
2308 trace_qxl_pre_load(d->id);
2309 qxl_hard_reset(d, 1);
2310 qxl_exit_vga_mode(d);
2311 return 0;
2312 }
2313
2314 static void qxl_create_memslots(PCIQXLDevice *d)
2315 {
2316 int i;
2317
2318 for (i = 0; i < NUM_MEMSLOTS; i++) {
2319 if (!d->guest_slots[i].active) {
2320 continue;
2321 }
2322 qxl_add_memslot(d, i, 0, QXL_SYNC);
2323 }
2324 }
2325
2326 static int qxl_post_load(void *opaque, int version)
2327 {
2328 PCIQXLDevice* d = opaque;
2329 uint8_t *ram_start = d->vga.vram_ptr;
2330 QXLCommandExt *cmds;
2331 int in, out, newmode;
2332
2333 assert(d->last_release_offset < d->vga.vram_size);
2334 if (d->last_release_offset == 0) {
2335 d->last_release = NULL;
2336 } else {
2337 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2338 }
2339
2340 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2341
2342 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
2343 newmode = d->mode;
2344 d->mode = QXL_MODE_UNDEFINED;
2345
2346 switch (newmode) {
2347 case QXL_MODE_UNDEFINED:
2348 qxl_create_memslots(d);
2349 break;
2350 case QXL_MODE_VGA:
2351 qxl_create_memslots(d);
2352 qxl_enter_vga_mode(d);
2353 break;
2354 case QXL_MODE_NATIVE:
2355 qxl_create_memslots(d);
2356 qxl_create_guest_primary(d, 1, QXL_SYNC);
2357
2358 /* replay surface-create and cursor-set commands */
2359 cmds = g_new0(QXLCommandExt, d->ssd.num_surfaces + 1);
2360 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
2361 if (d->guest_surfaces.cmds[in] == 0) {
2362 continue;
2363 }
2364 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2365 cmds[out].cmd.type = QXL_CMD_SURFACE;
2366 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2367 out++;
2368 }
2369 if (d->guest_cursor) {
2370 cmds[out].cmd.data = d->guest_cursor;
2371 cmds[out].cmd.type = QXL_CMD_CURSOR;
2372 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2373 out++;
2374 }
2375 qxl_spice_loadvm_commands(d, cmds, out);
2376 g_free(cmds);
2377 if (d->guest_monitors_config) {
2378 qxl_spice_monitors_config_async(d, 1);
2379 }
2380 break;
2381 case QXL_MODE_COMPAT:
2382 /* note: no need to call qxl_create_memslots, qxl_set_mode
2383 * creates the mem slot. */
2384 qxl_set_mode(d, d->shadow_rom.mode, 1);
2385 break;
2386 }
2387 return 0;
2388 }
2389
2390 #define QXL_SAVE_VERSION 21
2391
2392 static bool qxl_monitors_config_needed(void *opaque)
2393 {
2394 PCIQXLDevice *qxl = opaque;
2395
2396 return qxl->guest_monitors_config != 0;
2397 }
2398
2399
2400 static const VMStateDescription qxl_memslot = {
2401 .name = "qxl-memslot",
2402 .version_id = QXL_SAVE_VERSION,
2403 .minimum_version_id = QXL_SAVE_VERSION,
2404 .fields = (VMStateField[]) {
2405 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2406 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
2407 VMSTATE_UINT32(active, struct guest_slots),
2408 VMSTATE_END_OF_LIST()
2409 }
2410 };
2411
2412 static const VMStateDescription qxl_surface = {
2413 .name = "qxl-surface",
2414 .version_id = QXL_SAVE_VERSION,
2415 .minimum_version_id = QXL_SAVE_VERSION,
2416 .fields = (VMStateField[]) {
2417 VMSTATE_UINT32(width, QXLSurfaceCreate),
2418 VMSTATE_UINT32(height, QXLSurfaceCreate),
2419 VMSTATE_INT32(stride, QXLSurfaceCreate),
2420 VMSTATE_UINT32(format, QXLSurfaceCreate),
2421 VMSTATE_UINT32(position, QXLSurfaceCreate),
2422 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2423 VMSTATE_UINT32(flags, QXLSurfaceCreate),
2424 VMSTATE_UINT32(type, QXLSurfaceCreate),
2425 VMSTATE_UINT64(mem, QXLSurfaceCreate),
2426 VMSTATE_END_OF_LIST()
2427 }
2428 };
2429
2430 static const VMStateDescription qxl_vmstate_monitors_config = {
2431 .name = "qxl/monitors-config",
2432 .version_id = 1,
2433 .minimum_version_id = 1,
2434 .needed = qxl_monitors_config_needed,
2435 .fields = (VMStateField[]) {
2436 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2437 VMSTATE_END_OF_LIST()
2438 },
2439 };
2440
2441 static const VMStateDescription qxl_vmstate = {
2442 .name = "qxl",
2443 .version_id = QXL_SAVE_VERSION,
2444 .minimum_version_id = QXL_SAVE_VERSION,
2445 .pre_save = qxl_pre_save,
2446 .pre_load = qxl_pre_load,
2447 .post_load = qxl_post_load,
2448 .fields = (VMStateField[]) {
2449 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2450 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2451 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2452 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2453 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2454 VMSTATE_UINT32(mode, PCIQXLDevice),
2455 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
2456 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice, NULL),
2457 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2458 qxl_memslot, struct guest_slots),
2459 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2460 qxl_surface, QXLSurfaceCreate),
2461 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice, NULL),
2462 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2463 ssd.num_surfaces, 0,
2464 vmstate_info_uint64, uint64_t),
2465 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
2466 VMSTATE_END_OF_LIST()
2467 },
2468 .subsections = (const VMStateDescription*[]) {
2469 &qxl_vmstate_monitors_config,
2470 NULL
2471 }
2472 };
2473
2474 static Property qxl_properties[] = {
2475 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * MiB),
2476 DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size, 64 * MiB),
2477 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2478 QXL_DEFAULT_REVISION),
2479 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2480 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2481 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
2482 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
2483 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2484 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
2485 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
2486 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
2487 DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice, max_outputs, 0),
2488 DEFINE_PROP_UINT32("xres", PCIQXLDevice, xres, 0),
2489 DEFINE_PROP_UINT32("yres", PCIQXLDevice, yres, 0),
2490 DEFINE_PROP_BOOL("global-vmstate", PCIQXLDevice, vga.global_vmstate, false),
2491 DEFINE_PROP_END_OF_LIST(),
2492 };
2493
2494 static void qxl_pci_class_init(ObjectClass *klass, void *data)
2495 {
2496 DeviceClass *dc = DEVICE_CLASS(klass);
2497 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2498
2499 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2500 k->device_id = QXL_DEVICE_ID_STABLE;
2501 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
2502 dc->reset = qxl_reset_handler;
2503 dc->vmsd = &qxl_vmstate;
2504 device_class_set_props(dc, qxl_properties);
2505 }
2506
2507 static const TypeInfo qxl_pci_type_info = {
2508 .name = TYPE_PCI_QXL,
2509 .parent = TYPE_PCI_DEVICE,
2510 .instance_size = sizeof(PCIQXLDevice),
2511 .abstract = true,
2512 .class_init = qxl_pci_class_init,
2513 .interfaces = (InterfaceInfo[]) {
2514 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2515 { },
2516 },
2517 };
2518
2519 static void qxl_primary_class_init(ObjectClass *klass, void *data)
2520 {
2521 DeviceClass *dc = DEVICE_CLASS(klass);
2522 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2523
2524 k->realize = qxl_realize_primary;
2525 k->romfile = "vgabios-qxl.bin";
2526 k->class_id = PCI_CLASS_DISPLAY_VGA;
2527 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2528 dc->hotpluggable = false;
2529 }
2530
2531 static const TypeInfo qxl_primary_info = {
2532 .name = "qxl-vga",
2533 .parent = TYPE_PCI_QXL,
2534 .class_init = qxl_primary_class_init,
2535 };
2536 module_obj("qxl-vga");
2537 module_kconfig(QXL);
2538
2539 static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2540 {
2541 DeviceClass *dc = DEVICE_CLASS(klass);
2542 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2543
2544 k->realize = qxl_realize_secondary;
2545 k->class_id = PCI_CLASS_DISPLAY_OTHER;
2546 dc->desc = "Spice QXL GPU (secondary)";
2547 }
2548
2549 static const TypeInfo qxl_secondary_info = {
2550 .name = "qxl",
2551 .parent = TYPE_PCI_QXL,
2552 .class_init = qxl_secondary_class_init,
2553 };
2554 module_obj("qxl");
2555
2556 static void qxl_register_types(void)
2557 {
2558 type_register_static(&qxl_pci_type_info);
2559 type_register_static(&qxl_primary_info);
2560 type_register_static(&qxl_secondary_info);
2561 }
2562
2563 type_init(qxl_register_types)
2564
2565 module_dep("ui-spice-core");
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