2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
24 #include "qemu-common.h"
25 #include "qemu/timer.h"
26 #include "qemu/queue.h"
27 #include "qemu/atomic.h"
28 #include "sysemu/sysemu.h"
34 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
35 * such can be changed by the guest, so to avoid a guest trigerrable
36 * abort we just qxl_set_guest_bug and set the return to NULL. Still
37 * it may happen as a result of emulator bug as well.
39 #undef SPICE_RING_PROD_ITEM
40 #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
41 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
42 if (prod >= ARRAY_SIZE((r)->items)) { \
43 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
44 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \
47 ret = &(r)->items[prod].el; \
51 #undef SPICE_RING_CONS_ITEM
52 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
53 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
54 if (cons >= ARRAY_SIZE((r)->items)) { \
55 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
56 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
59 ret = &(r)->items[cons].el; \
64 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
66 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
68 #define QXL_MODE(_x, _y, _b, _o) \
72 .stride = (_x) * (_b) / 8, \
73 .x_mili = PIXEL_SIZE * (_x), \
74 .y_mili = PIXEL_SIZE * (_y), \
78 #define QXL_MODE_16_32(x_res, y_res, orientation) \
79 QXL_MODE(x_res, y_res, 16, orientation), \
80 QXL_MODE(x_res, y_res, 32, orientation)
82 #define QXL_MODE_EX(x_res, y_res) \
83 QXL_MODE_16_32(x_res, y_res, 0), \
84 QXL_MODE_16_32(x_res, y_res, 1)
86 static QXLMode qxl_modes
[] = {
87 QXL_MODE_EX(640, 480),
88 QXL_MODE_EX(800, 480),
89 QXL_MODE_EX(800, 600),
90 QXL_MODE_EX(832, 624),
91 QXL_MODE_EX(960, 640),
92 QXL_MODE_EX(1024, 600),
93 QXL_MODE_EX(1024, 768),
94 QXL_MODE_EX(1152, 864),
95 QXL_MODE_EX(1152, 870),
96 QXL_MODE_EX(1280, 720),
97 QXL_MODE_EX(1280, 760),
98 QXL_MODE_EX(1280, 768),
99 QXL_MODE_EX(1280, 800),
100 QXL_MODE_EX(1280, 960),
101 QXL_MODE_EX(1280, 1024),
102 QXL_MODE_EX(1360, 768),
103 QXL_MODE_EX(1366, 768),
104 QXL_MODE_EX(1400, 1050),
105 QXL_MODE_EX(1440, 900),
106 QXL_MODE_EX(1600, 900),
107 QXL_MODE_EX(1600, 1200),
108 QXL_MODE_EX(1680, 1050),
109 QXL_MODE_EX(1920, 1080),
110 /* these modes need more than 8 MB video memory */
111 QXL_MODE_EX(1920, 1200),
112 QXL_MODE_EX(1920, 1440),
113 QXL_MODE_EX(2000, 2000),
114 QXL_MODE_EX(2048, 1536),
115 QXL_MODE_EX(2048, 2048),
116 QXL_MODE_EX(2560, 1440),
117 QXL_MODE_EX(2560, 1600),
118 /* these modes need more than 16 MB video memory */
119 QXL_MODE_EX(2560, 2048),
120 QXL_MODE_EX(2800, 2100),
121 QXL_MODE_EX(3200, 2400),
122 /* these modes need more than 32 MB video memory */
123 QXL_MODE_EX(3840, 2160), /* 4k mainstream */
124 QXL_MODE_EX(4096, 2160), /* 4k */
125 /* these modes need more than 64 MB video memory */
126 QXL_MODE_EX(7680, 4320), /* 8k mainstream */
127 /* these modes need more than 128 MB video memory */
128 QXL_MODE_EX(8192, 4320), /* 8k */
131 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
);
132 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
);
133 static void qxl_reset_memslots(PCIQXLDevice
*d
);
134 static void qxl_reset_surfaces(PCIQXLDevice
*d
);
135 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
);
137 static void qxl_hw_update(void *opaque
);
139 void qxl_set_guest_bug(PCIQXLDevice
*qxl
, const char *msg
, ...)
141 trace_qxl_set_guest_bug(qxl
->id
);
142 qxl_send_events(qxl
, QXL_INTERRUPT_ERROR
);
144 if (qxl
->guestdebug
) {
147 fprintf(stderr
, "qxl-%d: guest bug: ", qxl
->id
);
148 vfprintf(stderr
, msg
, ap
);
149 fprintf(stderr
, "\n");
154 static void qxl_clear_guest_bug(PCIQXLDevice
*qxl
)
159 void qxl_spice_update_area(PCIQXLDevice
*qxl
, uint32_t surface_id
,
160 struct QXLRect
*area
, struct QXLRect
*dirty_rects
,
161 uint32_t num_dirty_rects
,
162 uint32_t clear_dirty_region
,
163 qxl_async_io async
, struct QXLCookie
*cookie
)
165 trace_qxl_spice_update_area(qxl
->id
, surface_id
, area
->left
, area
->right
,
166 area
->top
, area
->bottom
);
167 trace_qxl_spice_update_area_rest(qxl
->id
, num_dirty_rects
,
169 if (async
== QXL_SYNC
) {
170 spice_qxl_update_area(&qxl
->ssd
.qxl
, surface_id
, area
,
171 dirty_rects
, num_dirty_rects
, clear_dirty_region
);
173 assert(cookie
!= NULL
);
174 spice_qxl_update_area_async(&qxl
->ssd
.qxl
, surface_id
, area
,
175 clear_dirty_region
, (uintptr_t)cookie
);
179 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice
*qxl
,
182 trace_qxl_spice_destroy_surface_wait_complete(qxl
->id
, id
);
183 qemu_mutex_lock(&qxl
->track_lock
);
184 qxl
->guest_surfaces
.cmds
[id
] = 0;
185 qxl
->guest_surfaces
.count
--;
186 qemu_mutex_unlock(&qxl
->track_lock
);
189 static void qxl_spice_destroy_surface_wait(PCIQXLDevice
*qxl
, uint32_t id
,
194 trace_qxl_spice_destroy_surface_wait(qxl
->id
, id
, async
);
196 cookie
= qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
197 QXL_IO_DESTROY_SURFACE_ASYNC
);
198 cookie
->u
.surface_id
= id
;
199 spice_qxl_destroy_surface_async(&qxl
->ssd
.qxl
, id
, (uintptr_t)cookie
);
201 spice_qxl_destroy_surface_wait(&qxl
->ssd
.qxl
, id
);
202 qxl_spice_destroy_surface_wait_complete(qxl
, id
);
206 static void qxl_spice_flush_surfaces_async(PCIQXLDevice
*qxl
)
208 trace_qxl_spice_flush_surfaces_async(qxl
->id
, qxl
->guest_surfaces
.count
,
210 spice_qxl_flush_surfaces_async(&qxl
->ssd
.qxl
,
211 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
212 QXL_IO_FLUSH_SURFACES_ASYNC
));
215 void qxl_spice_loadvm_commands(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
,
218 trace_qxl_spice_loadvm_commands(qxl
->id
, ext
, count
);
219 spice_qxl_loadvm_commands(&qxl
->ssd
.qxl
, ext
, count
);
222 void qxl_spice_oom(PCIQXLDevice
*qxl
)
224 trace_qxl_spice_oom(qxl
->id
);
225 spice_qxl_oom(&qxl
->ssd
.qxl
);
228 void qxl_spice_reset_memslots(PCIQXLDevice
*qxl
)
230 trace_qxl_spice_reset_memslots(qxl
->id
);
231 spice_qxl_reset_memslots(&qxl
->ssd
.qxl
);
234 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice
*qxl
)
236 trace_qxl_spice_destroy_surfaces_complete(qxl
->id
);
237 qemu_mutex_lock(&qxl
->track_lock
);
238 memset(qxl
->guest_surfaces
.cmds
, 0,
239 sizeof(qxl
->guest_surfaces
.cmds
[0]) * qxl
->ssd
.num_surfaces
);
240 qxl
->guest_surfaces
.count
= 0;
241 qemu_mutex_unlock(&qxl
->track_lock
);
244 static void qxl_spice_destroy_surfaces(PCIQXLDevice
*qxl
, qxl_async_io async
)
246 trace_qxl_spice_destroy_surfaces(qxl
->id
, async
);
248 spice_qxl_destroy_surfaces_async(&qxl
->ssd
.qxl
,
249 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
250 QXL_IO_DESTROY_ALL_SURFACES_ASYNC
));
252 spice_qxl_destroy_surfaces(&qxl
->ssd
.qxl
);
253 qxl_spice_destroy_surfaces_complete(qxl
);
257 static void qxl_spice_monitors_config_async(PCIQXLDevice
*qxl
, int replay
)
259 trace_qxl_spice_monitors_config(qxl
->id
);
262 * don't use QXL_COOKIE_TYPE_IO:
263 * - we are not running yet (post_load), we will assert
265 * - this is not a guest io, but a reply, so async_io isn't set.
267 spice_qxl_monitors_config_async(&qxl
->ssd
.qxl
,
268 qxl
->guest_monitors_config
,
270 (uintptr_t)qxl_cookie_new(
271 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG
,
274 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
275 if (qxl
->max_outputs
) {
276 spice_qxl_set_max_monitors(&qxl
->ssd
.qxl
, qxl
->max_outputs
);
279 qxl
->guest_monitors_config
= qxl
->ram
->monitors_config
;
280 spice_qxl_monitors_config_async(&qxl
->ssd
.qxl
,
281 qxl
->ram
->monitors_config
,
283 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
284 QXL_IO_MONITORS_CONFIG_ASYNC
));
288 void qxl_spice_reset_image_cache(PCIQXLDevice
*qxl
)
290 trace_qxl_spice_reset_image_cache(qxl
->id
);
291 spice_qxl_reset_image_cache(&qxl
->ssd
.qxl
);
294 void qxl_spice_reset_cursor(PCIQXLDevice
*qxl
)
296 trace_qxl_spice_reset_cursor(qxl
->id
);
297 spice_qxl_reset_cursor(&qxl
->ssd
.qxl
);
298 qemu_mutex_lock(&qxl
->track_lock
);
299 qxl
->guest_cursor
= 0;
300 qemu_mutex_unlock(&qxl
->track_lock
);
301 if (qxl
->ssd
.cursor
) {
302 cursor_put(qxl
->ssd
.cursor
);
304 qxl
->ssd
.cursor
= cursor_builtin_hidden();
307 static ram_addr_t
qxl_rom_size(void)
309 uint32_t required_rom_size
= sizeof(QXLRom
) + sizeof(QXLModes
) +
311 uint32_t rom_size
= 8192; /* two pages */
313 QEMU_BUILD_BUG_ON(required_rom_size
> rom_size
);
317 static void init_qxl_rom(PCIQXLDevice
*d
)
319 QXLRom
*rom
= memory_region_get_ram_ptr(&d
->rom_bar
);
320 QXLModes
*modes
= (QXLModes
*)(rom
+ 1);
321 uint32_t ram_header_size
;
322 uint32_t surface0_area_size
;
327 memset(rom
, 0, d
->rom_size
);
329 rom
->magic
= cpu_to_le32(QXL_ROM_MAGIC
);
330 rom
->id
= cpu_to_le32(d
->id
);
331 rom
->log_level
= cpu_to_le32(d
->guestdebug
);
332 rom
->modes_offset
= cpu_to_le32(sizeof(QXLRom
));
334 rom
->slot_gen_bits
= MEMSLOT_GENERATION_BITS
;
335 rom
->slot_id_bits
= MEMSLOT_SLOT_BITS
;
336 rom
->slots_start
= 1;
337 rom
->slots_end
= NUM_MEMSLOTS
- 1;
338 rom
->n_surfaces
= cpu_to_le32(d
->ssd
.num_surfaces
);
340 for (i
= 0, n
= 0; i
< ARRAY_SIZE(qxl_modes
); i
++) {
341 fb
= qxl_modes
[i
].y_res
* qxl_modes
[i
].stride
;
342 if (fb
> d
->vgamem_size
) {
345 modes
->modes
[n
].id
= cpu_to_le32(i
);
346 modes
->modes
[n
].x_res
= cpu_to_le32(qxl_modes
[i
].x_res
);
347 modes
->modes
[n
].y_res
= cpu_to_le32(qxl_modes
[i
].y_res
);
348 modes
->modes
[n
].bits
= cpu_to_le32(qxl_modes
[i
].bits
);
349 modes
->modes
[n
].stride
= cpu_to_le32(qxl_modes
[i
].stride
);
350 modes
->modes
[n
].x_mili
= cpu_to_le32(qxl_modes
[i
].x_mili
);
351 modes
->modes
[n
].y_mili
= cpu_to_le32(qxl_modes
[i
].y_mili
);
352 modes
->modes
[n
].orientation
= cpu_to_le32(qxl_modes
[i
].orientation
);
355 modes
->n_modes
= cpu_to_le32(n
);
357 ram_header_size
= ALIGN(sizeof(QXLRam
), 4096);
358 surface0_area_size
= ALIGN(d
->vgamem_size
, 4096);
359 num_pages
= d
->vga
.vram_size
;
360 num_pages
-= ram_header_size
;
361 num_pages
-= surface0_area_size
;
362 num_pages
= num_pages
/ QXL_PAGE_SIZE
;
364 assert(ram_header_size
+ surface0_area_size
<= d
->vga
.vram_size
);
366 rom
->draw_area_offset
= cpu_to_le32(0);
367 rom
->surface0_area_size
= cpu_to_le32(surface0_area_size
);
368 rom
->pages_offset
= cpu_to_le32(surface0_area_size
);
369 rom
->num_pages
= cpu_to_le32(num_pages
);
370 rom
->ram_header_offset
= cpu_to_le32(d
->vga
.vram_size
- ram_header_size
);
372 d
->shadow_rom
= *rom
;
377 static void init_qxl_ram(PCIQXLDevice
*d
)
382 buf
= d
->vga
.vram_ptr
;
383 d
->ram
= (QXLRam
*)(buf
+ le32_to_cpu(d
->shadow_rom
.ram_header_offset
));
384 d
->ram
->magic
= cpu_to_le32(QXL_RAM_MAGIC
);
385 d
->ram
->int_pending
= cpu_to_le32(0);
386 d
->ram
->int_mask
= cpu_to_le32(0);
387 d
->ram
->update_surface
= 0;
388 d
->ram
->monitors_config
= 0;
389 SPICE_RING_INIT(&d
->ram
->cmd_ring
);
390 SPICE_RING_INIT(&d
->ram
->cursor_ring
);
391 SPICE_RING_INIT(&d
->ram
->release_ring
);
392 SPICE_RING_PROD_ITEM(d
, &d
->ram
->release_ring
, item
);
395 qxl_ring_set_dirty(d
);
398 /* can be called from spice server thread context */
399 static void qxl_set_dirty(MemoryRegion
*mr
, ram_addr_t addr
, ram_addr_t end
)
401 memory_region_set_dirty(mr
, addr
, end
- addr
);
404 static void qxl_rom_set_dirty(PCIQXLDevice
*qxl
)
406 qxl_set_dirty(&qxl
->rom_bar
, 0, qxl
->rom_size
);
409 /* called from spice server thread context only */
410 static void qxl_ram_set_dirty(PCIQXLDevice
*qxl
, void *ptr
)
412 void *base
= qxl
->vga
.vram_ptr
;
416 assert(offset
< qxl
->vga
.vram_size
);
417 qxl_set_dirty(&qxl
->vga
.vram
, offset
, offset
+ 3);
420 /* can be called from spice server thread context */
421 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
)
423 ram_addr_t addr
= qxl
->shadow_rom
.ram_header_offset
;
424 ram_addr_t end
= qxl
->vga
.vram_size
;
425 qxl_set_dirty(&qxl
->vga
.vram
, addr
, end
);
429 * keep track of some command state, for savevm/loadvm.
430 * called from spice server thread context only
432 static int qxl_track_command(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
)
434 switch (le32_to_cpu(ext
->cmd
.type
)) {
435 case QXL_CMD_SURFACE
:
437 QXLSurfaceCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
442 uint32_t id
= le32_to_cpu(cmd
->surface_id
);
444 if (id
>= qxl
->ssd
.num_surfaces
) {
445 qxl_set_guest_bug(qxl
, "QXL_CMD_SURFACE id %d >= %d", id
,
446 qxl
->ssd
.num_surfaces
);
449 if (cmd
->type
== QXL_SURFACE_CMD_CREATE
&&
450 (cmd
->u
.surface_create
.stride
& 0x03) != 0) {
451 qxl_set_guest_bug(qxl
, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
452 cmd
->u
.surface_create
.stride
);
455 qemu_mutex_lock(&qxl
->track_lock
);
456 if (cmd
->type
== QXL_SURFACE_CMD_CREATE
) {
457 qxl
->guest_surfaces
.cmds
[id
] = ext
->cmd
.data
;
458 qxl
->guest_surfaces
.count
++;
459 if (qxl
->guest_surfaces
.max
< qxl
->guest_surfaces
.count
)
460 qxl
->guest_surfaces
.max
= qxl
->guest_surfaces
.count
;
462 if (cmd
->type
== QXL_SURFACE_CMD_DESTROY
) {
463 qxl
->guest_surfaces
.cmds
[id
] = 0;
464 qxl
->guest_surfaces
.count
--;
466 qemu_mutex_unlock(&qxl
->track_lock
);
471 QXLCursorCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
476 if (cmd
->type
== QXL_CURSOR_SET
) {
477 qemu_mutex_lock(&qxl
->track_lock
);
478 qxl
->guest_cursor
= ext
->cmd
.data
;
479 qemu_mutex_unlock(&qxl
->track_lock
);
487 /* spice display interface callbacks */
489 static void interface_attach_worker(QXLInstance
*sin
, QXLWorker
*qxl_worker
)
491 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
493 trace_qxl_interface_attach_worker(qxl
->id
);
494 qxl
->ssd
.worker
= qxl_worker
;
497 static void interface_set_compression_level(QXLInstance
*sin
, int level
)
499 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
501 trace_qxl_interface_set_compression_level(qxl
->id
, level
);
502 qxl
->shadow_rom
.compression_level
= cpu_to_le32(level
);
503 qxl
->rom
->compression_level
= cpu_to_le32(level
);
504 qxl_rom_set_dirty(qxl
);
507 static void interface_set_mm_time(QXLInstance
*sin
, uint32_t mm_time
)
509 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
511 if (!qemu_spice_display_is_running(&qxl
->ssd
)) {
515 trace_qxl_interface_set_mm_time(qxl
->id
, mm_time
);
516 qxl
->shadow_rom
.mm_clock
= cpu_to_le32(mm_time
);
517 qxl
->rom
->mm_clock
= cpu_to_le32(mm_time
);
518 qxl_rom_set_dirty(qxl
);
521 static void interface_get_init_info(QXLInstance
*sin
, QXLDevInitInfo
*info
)
523 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
525 trace_qxl_interface_get_init_info(qxl
->id
);
526 info
->memslot_gen_bits
= MEMSLOT_GENERATION_BITS
;
527 info
->memslot_id_bits
= MEMSLOT_SLOT_BITS
;
528 info
->num_memslots
= NUM_MEMSLOTS
;
529 info
->num_memslots_groups
= NUM_MEMSLOTS_GROUPS
;
530 info
->internal_groupslot_id
= 0;
532 le32_to_cpu(qxl
->shadow_rom
.num_pages
) << QXL_PAGE_BITS
;
533 info
->n_surfaces
= qxl
->ssd
.num_surfaces
;
536 static const char *qxl_mode_to_string(int mode
)
539 case QXL_MODE_COMPAT
:
541 case QXL_MODE_NATIVE
:
543 case QXL_MODE_UNDEFINED
:
551 static const char *io_port_to_string(uint32_t io_port
)
553 if (io_port
>= QXL_IO_RANGE_SIZE
) {
554 return "out of range";
556 static const char *io_port_to_string
[QXL_IO_RANGE_SIZE
+ 1] = {
557 [QXL_IO_NOTIFY_CMD
] = "QXL_IO_NOTIFY_CMD",
558 [QXL_IO_NOTIFY_CURSOR
] = "QXL_IO_NOTIFY_CURSOR",
559 [QXL_IO_UPDATE_AREA
] = "QXL_IO_UPDATE_AREA",
560 [QXL_IO_UPDATE_IRQ
] = "QXL_IO_UPDATE_IRQ",
561 [QXL_IO_NOTIFY_OOM
] = "QXL_IO_NOTIFY_OOM",
562 [QXL_IO_RESET
] = "QXL_IO_RESET",
563 [QXL_IO_SET_MODE
] = "QXL_IO_SET_MODE",
564 [QXL_IO_LOG
] = "QXL_IO_LOG",
565 [QXL_IO_MEMSLOT_ADD
] = "QXL_IO_MEMSLOT_ADD",
566 [QXL_IO_MEMSLOT_DEL
] = "QXL_IO_MEMSLOT_DEL",
567 [QXL_IO_DETACH_PRIMARY
] = "QXL_IO_DETACH_PRIMARY",
568 [QXL_IO_ATTACH_PRIMARY
] = "QXL_IO_ATTACH_PRIMARY",
569 [QXL_IO_CREATE_PRIMARY
] = "QXL_IO_CREATE_PRIMARY",
570 [QXL_IO_DESTROY_PRIMARY
] = "QXL_IO_DESTROY_PRIMARY",
571 [QXL_IO_DESTROY_SURFACE_WAIT
] = "QXL_IO_DESTROY_SURFACE_WAIT",
572 [QXL_IO_DESTROY_ALL_SURFACES
] = "QXL_IO_DESTROY_ALL_SURFACES",
573 [QXL_IO_UPDATE_AREA_ASYNC
] = "QXL_IO_UPDATE_AREA_ASYNC",
574 [QXL_IO_MEMSLOT_ADD_ASYNC
] = "QXL_IO_MEMSLOT_ADD_ASYNC",
575 [QXL_IO_CREATE_PRIMARY_ASYNC
] = "QXL_IO_CREATE_PRIMARY_ASYNC",
576 [QXL_IO_DESTROY_PRIMARY_ASYNC
] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
577 [QXL_IO_DESTROY_SURFACE_ASYNC
] = "QXL_IO_DESTROY_SURFACE_ASYNC",
578 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC
]
579 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
580 [QXL_IO_FLUSH_SURFACES_ASYNC
] = "QXL_IO_FLUSH_SURFACES_ASYNC",
581 [QXL_IO_FLUSH_RELEASE
] = "QXL_IO_FLUSH_RELEASE",
582 [QXL_IO_MONITORS_CONFIG_ASYNC
] = "QXL_IO_MONITORS_CONFIG_ASYNC",
584 return io_port_to_string
[io_port
];
587 /* called from spice server thread context only */
588 static int interface_get_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
590 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
591 SimpleSpiceUpdate
*update
;
592 QXLCommandRing
*ring
;
596 trace_qxl_ring_command_check(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
601 qemu_mutex_lock(&qxl
->ssd
.lock
);
602 update
= QTAILQ_FIRST(&qxl
->ssd
.updates
);
603 if (update
!= NULL
) {
604 QTAILQ_REMOVE(&qxl
->ssd
.updates
, update
, next
);
608 qemu_mutex_unlock(&qxl
->ssd
.lock
);
610 trace_qxl_ring_command_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
611 qxl_log_command(qxl
, "vga", ext
);
614 case QXL_MODE_COMPAT
:
615 case QXL_MODE_NATIVE
:
616 case QXL_MODE_UNDEFINED
:
617 ring
= &qxl
->ram
->cmd_ring
;
618 if (qxl
->guest_bug
|| SPICE_RING_IS_EMPTY(ring
)) {
621 SPICE_RING_CONS_ITEM(qxl
, ring
, cmd
);
626 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
627 ext
->flags
= qxl
->cmdflags
;
628 SPICE_RING_POP(ring
, notify
);
629 qxl_ring_set_dirty(qxl
);
631 qxl_send_events(qxl
, QXL_INTERRUPT_DISPLAY
);
633 qxl
->guest_primary
.commands
++;
634 qxl_track_command(qxl
, ext
);
635 qxl_log_command(qxl
, "cmd", ext
);
636 trace_qxl_ring_command_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
643 /* called from spice server thread context only */
644 static int interface_req_cmd_notification(QXLInstance
*sin
)
646 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
649 trace_qxl_ring_command_req_notification(qxl
->id
);
651 case QXL_MODE_COMPAT
:
652 case QXL_MODE_NATIVE
:
653 case QXL_MODE_UNDEFINED
:
654 SPICE_RING_CONS_WAIT(&qxl
->ram
->cmd_ring
, wait
);
655 qxl_ring_set_dirty(qxl
);
664 /* called from spice server thread context only */
665 static inline void qxl_push_free_res(PCIQXLDevice
*d
, int flush
)
667 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
671 #define QXL_FREE_BUNCH_SIZE 32
673 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
674 /* ring full -- can't push */
677 if (!flush
&& d
->oom_running
) {
678 /* collect everything from oom handler before pushing */
681 if (!flush
&& d
->num_free_res
< QXL_FREE_BUNCH_SIZE
) {
682 /* collect a bit more before pushing */
686 SPICE_RING_PUSH(ring
, notify
);
687 trace_qxl_ring_res_push(d
->id
, qxl_mode_to_string(d
->mode
),
688 d
->guest_surfaces
.count
, d
->num_free_res
,
689 d
->last_release
, notify
? "yes" : "no");
690 trace_qxl_ring_res_push_rest(d
->id
, ring
->prod
- ring
->cons
,
691 ring
->num_items
, ring
->prod
, ring
->cons
);
693 qxl_send_events(d
, QXL_INTERRUPT_DISPLAY
);
695 SPICE_RING_PROD_ITEM(d
, ring
, item
);
701 d
->last_release
= NULL
;
702 qxl_ring_set_dirty(d
);
705 /* called from spice server thread context only */
706 static void interface_release_resource(QXLInstance
*sin
,
707 QXLReleaseInfoExt ext
)
709 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
710 QXLReleaseRing
*ring
;
713 if (ext
.group_id
== MEMSLOT_GROUP_HOST
) {
714 /* host group -> vga mode update request */
715 QXLCommandExt
*cmdext
= (void *)(intptr_t)(ext
.info
->id
);
716 SimpleSpiceUpdate
*update
;
717 g_assert(cmdext
->cmd
.type
== QXL_CMD_DRAW
);
718 update
= container_of(cmdext
, SimpleSpiceUpdate
, ext
);
719 qemu_spice_destroy_update(&qxl
->ssd
, update
);
724 * ext->info points into guest-visible memory
725 * pci bar 0, $command.release_info
727 ring
= &qxl
->ram
->release_ring
;
728 SPICE_RING_PROD_ITEM(qxl
, ring
, item
);
733 /* stick head into the ring */
736 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
738 qxl_ring_set_dirty(qxl
);
740 /* append item to the list */
741 qxl
->last_release
->next
= ext
.info
->id
;
742 qxl_ram_set_dirty(qxl
, &qxl
->last_release
->next
);
744 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
746 qxl
->last_release
= ext
.info
;
748 trace_qxl_ring_res_put(qxl
->id
, qxl
->num_free_res
);
749 qxl_push_free_res(qxl
, 0);
752 /* called from spice server thread context only */
753 static int interface_get_cursor_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
755 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
760 trace_qxl_ring_cursor_check(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
763 case QXL_MODE_COMPAT
:
764 case QXL_MODE_NATIVE
:
765 case QXL_MODE_UNDEFINED
:
766 ring
= &qxl
->ram
->cursor_ring
;
767 if (SPICE_RING_IS_EMPTY(ring
)) {
770 SPICE_RING_CONS_ITEM(qxl
, ring
, cmd
);
775 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
776 ext
->flags
= qxl
->cmdflags
;
777 SPICE_RING_POP(ring
, notify
);
778 qxl_ring_set_dirty(qxl
);
780 qxl_send_events(qxl
, QXL_INTERRUPT_CURSOR
);
782 qxl
->guest_primary
.commands
++;
783 qxl_track_command(qxl
, ext
);
784 qxl_log_command(qxl
, "csr", ext
);
786 qxl_render_cursor(qxl
, ext
);
788 trace_qxl_ring_cursor_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
795 /* called from spice server thread context only */
796 static int interface_req_cursor_notification(QXLInstance
*sin
)
798 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
801 trace_qxl_ring_cursor_req_notification(qxl
->id
);
803 case QXL_MODE_COMPAT
:
804 case QXL_MODE_NATIVE
:
805 case QXL_MODE_UNDEFINED
:
806 SPICE_RING_CONS_WAIT(&qxl
->ram
->cursor_ring
, wait
);
807 qxl_ring_set_dirty(qxl
);
816 /* called from spice server thread context */
817 static void interface_notify_update(QXLInstance
*sin
, uint32_t update_id
)
820 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
821 * use by xf86-video-qxl and is defined out in the qxl windows driver.
822 * Probably was at some earlier version that is prior to git start (2009),
823 * and is still guest trigerrable.
825 fprintf(stderr
, "%s: deprecated\n", __func__
);
828 /* called from spice server thread context only */
829 static int interface_flush_resources(QXLInstance
*sin
)
831 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
834 ret
= qxl
->num_free_res
;
836 qxl_push_free_res(qxl
, 1);
841 static void qxl_create_guest_primary_complete(PCIQXLDevice
*d
);
843 /* called from spice server thread context only */
844 static void interface_async_complete_io(PCIQXLDevice
*qxl
, QXLCookie
*cookie
)
846 uint32_t current_async
;
848 qemu_mutex_lock(&qxl
->async_lock
);
849 current_async
= qxl
->current_async
;
850 qxl
->current_async
= QXL_UNDEFINED_IO
;
851 qemu_mutex_unlock(&qxl
->async_lock
);
853 trace_qxl_interface_async_complete_io(qxl
->id
, current_async
, cookie
);
855 fprintf(stderr
, "qxl: %s: error, cookie is NULL\n", __func__
);
858 if (cookie
&& current_async
!= cookie
->io
) {
860 "qxl: %s: error: current_async = %d != %"
861 PRId64
" = cookie->io\n", __func__
, current_async
, cookie
->io
);
863 switch (current_async
) {
864 case QXL_IO_MEMSLOT_ADD_ASYNC
:
865 case QXL_IO_DESTROY_PRIMARY_ASYNC
:
866 case QXL_IO_UPDATE_AREA_ASYNC
:
867 case QXL_IO_FLUSH_SURFACES_ASYNC
:
868 case QXL_IO_MONITORS_CONFIG_ASYNC
:
870 case QXL_IO_CREATE_PRIMARY_ASYNC
:
871 qxl_create_guest_primary_complete(qxl
);
873 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
874 qxl_spice_destroy_surfaces_complete(qxl
);
876 case QXL_IO_DESTROY_SURFACE_ASYNC
:
877 qxl_spice_destroy_surface_wait_complete(qxl
, cookie
->u
.surface_id
);
880 fprintf(stderr
, "qxl: %s: unexpected current_async %d\n", __func__
,
883 qxl_send_events(qxl
, QXL_INTERRUPT_IO_CMD
);
886 /* called from spice server thread context only */
887 static void interface_update_area_complete(QXLInstance
*sin
,
889 QXLRect
*dirty
, uint32_t num_updated_rects
)
891 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
895 qemu_mutex_lock(&qxl
->ssd
.lock
);
896 if (surface_id
!= 0 || !num_updated_rects
||
897 !qxl
->render_update_cookie_num
) {
898 qemu_mutex_unlock(&qxl
->ssd
.lock
);
901 trace_qxl_interface_update_area_complete(qxl
->id
, surface_id
, dirty
->left
,
902 dirty
->right
, dirty
->top
, dirty
->bottom
);
903 trace_qxl_interface_update_area_complete_rest(qxl
->id
, num_updated_rects
);
904 if (qxl
->num_dirty_rects
+ num_updated_rects
> QXL_NUM_DIRTY_RECTS
) {
906 * overflow - treat this as a full update. Not expected to be common.
908 trace_qxl_interface_update_area_complete_overflow(qxl
->id
,
909 QXL_NUM_DIRTY_RECTS
);
910 qxl
->guest_primary
.resized
= 1;
912 if (qxl
->guest_primary
.resized
) {
914 * Don't bother copying or scheduling the bh since we will flip
915 * the whole area anyway on completion of the update_area async call
917 qemu_mutex_unlock(&qxl
->ssd
.lock
);
920 qxl_i
= qxl
->num_dirty_rects
;
921 for (i
= 0; i
< num_updated_rects
; i
++) {
922 qxl
->dirty
[qxl_i
++] = dirty
[i
];
924 qxl
->num_dirty_rects
+= num_updated_rects
;
925 trace_qxl_interface_update_area_complete_schedule_bh(qxl
->id
,
926 qxl
->num_dirty_rects
);
927 qemu_bh_schedule(qxl
->update_area_bh
);
928 qemu_mutex_unlock(&qxl
->ssd
.lock
);
931 /* called from spice server thread context only */
932 static void interface_async_complete(QXLInstance
*sin
, uint64_t cookie_token
)
934 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
935 QXLCookie
*cookie
= (QXLCookie
*)(uintptr_t)cookie_token
;
937 switch (cookie
->type
) {
938 case QXL_COOKIE_TYPE_IO
:
939 interface_async_complete_io(qxl
, cookie
);
942 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA
:
943 qxl_render_update_area_done(qxl
, cookie
);
945 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG
:
948 fprintf(stderr
, "qxl: %s: unexpected cookie type %d\n",
949 __func__
, cookie
->type
);
954 /* called from spice server thread context only */
955 static void interface_set_client_capabilities(QXLInstance
*sin
,
956 uint8_t client_present
,
959 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
961 if (qxl
->revision
< 4) {
962 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl
->id
,
967 if (runstate_check(RUN_STATE_INMIGRATE
) ||
968 runstate_check(RUN_STATE_POSTMIGRATE
)) {
972 qxl
->shadow_rom
.client_present
= client_present
;
973 memcpy(qxl
->shadow_rom
.client_capabilities
, caps
,
974 sizeof(qxl
->shadow_rom
.client_capabilities
));
975 qxl
->rom
->client_present
= client_present
;
976 memcpy(qxl
->rom
->client_capabilities
, caps
,
977 sizeof(qxl
->rom
->client_capabilities
));
978 qxl_rom_set_dirty(qxl
);
980 qxl_send_events(qxl
, QXL_INTERRUPT_CLIENT
);
983 static uint32_t qxl_crc32(const uint8_t *p
, unsigned len
)
986 * zlib xors the seed with 0xffffffff, and xors the result
987 * again with 0xffffffff; Both are not done with linux's crc32,
988 * which we want to be compatible with, so undo that.
990 return crc32(0xffffffff, p
, len
) ^ 0xffffffff;
993 /* called from main context only */
994 static int interface_client_monitors_config(QXLInstance
*sin
,
995 VDAgentMonitorsConfig
*monitors_config
)
997 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
998 QXLRom
*rom
= memory_region_get_ram_ptr(&qxl
->rom_bar
);
1000 unsigned max_outputs
= ARRAY_SIZE(rom
->client_monitors_config
.heads
);
1002 if (qxl
->revision
< 4) {
1003 trace_qxl_client_monitors_config_unsupported_by_device(qxl
->id
,
1008 * Older windows drivers set int_mask to 0 when their ISR is called,
1009 * then later set it to ~0. So it doesn't relate to the actual interrupts
1010 * handled. However, they are old, so clearly they don't support this
1013 if (qxl
->ram
->int_mask
== 0 || qxl
->ram
->int_mask
== ~0 ||
1014 !(qxl
->ram
->int_mask
& QXL_INTERRUPT_CLIENT_MONITORS_CONFIG
)) {
1015 trace_qxl_client_monitors_config_unsupported_by_guest(qxl
->id
,
1020 if (!monitors_config
) {
1024 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
1025 /* limit number of outputs based on setting limit */
1026 if (qxl
->max_outputs
&& qxl
->max_outputs
<= max_outputs
) {
1027 max_outputs
= qxl
->max_outputs
;
1031 memset(&rom
->client_monitors_config
, 0,
1032 sizeof(rom
->client_monitors_config
));
1033 rom
->client_monitors_config
.count
= monitors_config
->num_of_monitors
;
1034 /* monitors_config->flags ignored */
1035 if (rom
->client_monitors_config
.count
>= max_outputs
) {
1036 trace_qxl_client_monitors_config_capped(qxl
->id
,
1037 monitors_config
->num_of_monitors
,
1039 rom
->client_monitors_config
.count
= max_outputs
;
1041 for (i
= 0 ; i
< rom
->client_monitors_config
.count
; ++i
) {
1042 VDAgentMonConfig
*monitor
= &monitors_config
->monitors
[i
];
1043 QXLURect
*rect
= &rom
->client_monitors_config
.heads
[i
];
1044 /* monitor->depth ignored */
1045 rect
->left
= monitor
->x
;
1046 rect
->top
= monitor
->y
;
1047 rect
->right
= monitor
->x
+ monitor
->width
;
1048 rect
->bottom
= monitor
->y
+ monitor
->height
;
1050 rom
->client_monitors_config_crc
= qxl_crc32(
1051 (const uint8_t *)&rom
->client_monitors_config
,
1052 sizeof(rom
->client_monitors_config
));
1053 trace_qxl_client_monitors_config_crc(qxl
->id
,
1054 sizeof(rom
->client_monitors_config
),
1055 rom
->client_monitors_config_crc
);
1057 trace_qxl_interrupt_client_monitors_config(qxl
->id
,
1058 rom
->client_monitors_config
.count
,
1059 rom
->client_monitors_config
.heads
);
1060 qxl_send_events(qxl
, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG
);
1064 static const QXLInterface qxl_interface
= {
1065 .base
.type
= SPICE_INTERFACE_QXL
,
1066 .base
.description
= "qxl gpu",
1067 .base
.major_version
= SPICE_INTERFACE_QXL_MAJOR
,
1068 .base
.minor_version
= SPICE_INTERFACE_QXL_MINOR
,
1070 .attache_worker
= interface_attach_worker
,
1071 .set_compression_level
= interface_set_compression_level
,
1072 .set_mm_time
= interface_set_mm_time
,
1073 .get_init_info
= interface_get_init_info
,
1075 /* the callbacks below are called from spice server thread context */
1076 .get_command
= interface_get_command
,
1077 .req_cmd_notification
= interface_req_cmd_notification
,
1078 .release_resource
= interface_release_resource
,
1079 .get_cursor_command
= interface_get_cursor_command
,
1080 .req_cursor_notification
= interface_req_cursor_notification
,
1081 .notify_update
= interface_notify_update
,
1082 .flush_resources
= interface_flush_resources
,
1083 .async_complete
= interface_async_complete
,
1084 .update_area_complete
= interface_update_area_complete
,
1085 .set_client_capabilities
= interface_set_client_capabilities
,
1086 .client_monitors_config
= interface_client_monitors_config
,
1089 static const GraphicHwOps qxl_ops
= {
1090 .gfx_update
= qxl_hw_update
,
1093 static void qxl_enter_vga_mode(PCIQXLDevice
*d
)
1095 if (d
->mode
== QXL_MODE_VGA
) {
1098 trace_qxl_enter_vga_mode(d
->id
);
1099 #if SPICE_SERVER_VERSION >= 0x000c03 /* release 0.12.3 */
1100 spice_qxl_driver_unload(&d
->ssd
.qxl
);
1102 graphic_console_set_hwops(d
->ssd
.dcl
.con
, d
->vga
.hw_ops
, &d
->vga
);
1103 update_displaychangelistener(&d
->ssd
.dcl
, GUI_REFRESH_INTERVAL_DEFAULT
);
1104 qemu_spice_create_host_primary(&d
->ssd
);
1105 d
->mode
= QXL_MODE_VGA
;
1106 vga_dirty_log_start(&d
->vga
);
1107 graphic_hw_update(d
->vga
.con
);
1110 static void qxl_exit_vga_mode(PCIQXLDevice
*d
)
1112 if (d
->mode
!= QXL_MODE_VGA
) {
1115 trace_qxl_exit_vga_mode(d
->id
);
1116 graphic_console_set_hwops(d
->ssd
.dcl
.con
, &qxl_ops
, d
);
1117 update_displaychangelistener(&d
->ssd
.dcl
, GUI_REFRESH_INTERVAL_IDLE
);
1118 vga_dirty_log_stop(&d
->vga
);
1119 qxl_destroy_primary(d
, QXL_SYNC
);
1122 static void qxl_update_irq(PCIQXLDevice
*d
)
1124 uint32_t pending
= le32_to_cpu(d
->ram
->int_pending
);
1125 uint32_t mask
= le32_to_cpu(d
->ram
->int_mask
);
1126 int level
= !!(pending
& mask
);
1127 pci_set_irq(&d
->pci
, level
);
1128 qxl_ring_set_dirty(d
);
1131 static void qxl_check_state(PCIQXLDevice
*d
)
1133 QXLRam
*ram
= d
->ram
;
1134 int spice_display_running
= qemu_spice_display_is_running(&d
->ssd
);
1136 assert(!spice_display_running
|| SPICE_RING_IS_EMPTY(&ram
->cmd_ring
));
1137 assert(!spice_display_running
|| SPICE_RING_IS_EMPTY(&ram
->cursor_ring
));
1140 static void qxl_reset_state(PCIQXLDevice
*d
)
1142 QXLRom
*rom
= d
->rom
;
1145 d
->shadow_rom
.update_id
= cpu_to_le32(0);
1146 *rom
= d
->shadow_rom
;
1147 qxl_rom_set_dirty(d
);
1149 d
->num_free_res
= 0;
1150 d
->last_release
= NULL
;
1151 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
1155 static void qxl_soft_reset(PCIQXLDevice
*d
)
1157 trace_qxl_soft_reset(d
->id
);
1159 qxl_clear_guest_bug(d
);
1160 qemu_mutex_lock(&d
->async_lock
);
1161 d
->current_async
= QXL_UNDEFINED_IO
;
1162 qemu_mutex_unlock(&d
->async_lock
);
1165 qxl_enter_vga_mode(d
);
1167 d
->mode
= QXL_MODE_UNDEFINED
;
1171 static void qxl_hard_reset(PCIQXLDevice
*d
, int loadvm
)
1173 bool startstop
= qemu_spice_display_is_running(&d
->ssd
);
1175 trace_qxl_hard_reset(d
->id
, loadvm
);
1178 qemu_spice_display_stop();
1181 qxl_spice_reset_cursor(d
);
1182 qxl_spice_reset_image_cache(d
);
1183 qxl_reset_surfaces(d
);
1184 qxl_reset_memslots(d
);
1186 /* pre loadvm reset must not touch QXLRam. This lives in
1187 * device memory, is migrated together with RAM and thus
1188 * already loaded at this point */
1192 qemu_spice_create_host_memslot(&d
->ssd
);
1196 qemu_spice_display_start();
1200 static void qxl_reset_handler(DeviceState
*dev
)
1202 PCIQXLDevice
*d
= PCI_QXL(PCI_DEVICE(dev
));
1204 qxl_hard_reset(d
, 0);
1207 static void qxl_vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
1209 VGACommonState
*vga
= opaque
;
1210 PCIQXLDevice
*qxl
= container_of(vga
, PCIQXLDevice
, vga
);
1212 trace_qxl_io_write_vga(qxl
->id
, qxl_mode_to_string(qxl
->mode
), addr
, val
);
1213 if (qxl
->mode
!= QXL_MODE_VGA
) {
1214 qxl_destroy_primary(qxl
, QXL_SYNC
);
1215 qxl_soft_reset(qxl
);
1217 vga_ioport_write(opaque
, addr
, val
);
1220 static const MemoryRegionPortio qxl_vga_portio_list
[] = {
1221 { 0x04, 2, 1, .read
= vga_ioport_read
,
1222 .write
= qxl_vga_ioport_write
}, /* 3b4 */
1223 { 0x0a, 1, 1, .read
= vga_ioport_read
,
1224 .write
= qxl_vga_ioport_write
}, /* 3ba */
1225 { 0x10, 16, 1, .read
= vga_ioport_read
,
1226 .write
= qxl_vga_ioport_write
}, /* 3c0 */
1227 { 0x24, 2, 1, .read
= vga_ioport_read
,
1228 .write
= qxl_vga_ioport_write
}, /* 3d4 */
1229 { 0x2a, 1, 1, .read
= vga_ioport_read
,
1230 .write
= qxl_vga_ioport_write
}, /* 3da */
1231 PORTIO_END_OF_LIST(),
1234 static int qxl_add_memslot(PCIQXLDevice
*d
, uint32_t slot_id
, uint64_t delta
,
1237 static const int regions
[] = {
1238 QXL_RAM_RANGE_INDEX
,
1239 QXL_VRAM_RANGE_INDEX
,
1240 QXL_VRAM64_RANGE_INDEX
,
1242 uint64_t guest_start
;
1248 intptr_t virt_start
;
1249 QXLDevMemSlot memslot
;
1252 guest_start
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_start
);
1253 guest_end
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_end
);
1255 trace_qxl_memslot_add_guest(d
->id
, slot_id
, guest_start
, guest_end
);
1257 if (slot_id
>= NUM_MEMSLOTS
) {
1258 qxl_set_guest_bug(d
, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__
,
1259 slot_id
, NUM_MEMSLOTS
);
1262 if (guest_start
> guest_end
) {
1263 qxl_set_guest_bug(d
, "%s: guest_start > guest_end 0x%" PRIx64
1264 " > 0x%" PRIx64
, __func__
, guest_start
, guest_end
);
1268 for (i
= 0; i
< ARRAY_SIZE(regions
); i
++) {
1269 pci_region
= regions
[i
];
1270 pci_start
= d
->pci
.io_regions
[pci_region
].addr
;
1271 pci_end
= pci_start
+ d
->pci
.io_regions
[pci_region
].size
;
1273 if (pci_start
== -1) {
1276 /* start address in range ? */
1277 if (guest_start
< pci_start
|| guest_start
> pci_end
) {
1280 /* end address in range ? */
1281 if (guest_end
> pci_end
) {
1287 if (i
== ARRAY_SIZE(regions
)) {
1288 qxl_set_guest_bug(d
, "%s: finished loop without match", __func__
);
1292 switch (pci_region
) {
1293 case QXL_RAM_RANGE_INDEX
:
1296 case QXL_VRAM_RANGE_INDEX
:
1297 case 4 /* vram 64bit */:
1301 /* should not happen */
1302 qxl_set_guest_bug(d
, "%s: pci_region = %d", __func__
, pci_region
);
1306 virt_start
= (intptr_t)memory_region_get_ram_ptr(mr
);
1307 memslot
.slot_id
= slot_id
;
1308 memslot
.slot_group_id
= MEMSLOT_GROUP_GUEST
; /* guest group */
1309 memslot
.virt_start
= virt_start
+ (guest_start
- pci_start
);
1310 memslot
.virt_end
= virt_start
+ (guest_end
- pci_start
);
1311 memslot
.addr_delta
= memslot
.virt_start
- delta
;
1312 memslot
.generation
= d
->rom
->slot_generation
= 0;
1313 qxl_rom_set_dirty(d
);
1315 qemu_spice_add_memslot(&d
->ssd
, &memslot
, async
);
1316 d
->guest_slots
[slot_id
].mr
= mr
;
1317 d
->guest_slots
[slot_id
].offset
= memslot
.virt_start
- virt_start
;
1318 d
->guest_slots
[slot_id
].size
= memslot
.virt_end
- memslot
.virt_start
;
1319 d
->guest_slots
[slot_id
].delta
= delta
;
1320 d
->guest_slots
[slot_id
].active
= 1;
1324 static void qxl_del_memslot(PCIQXLDevice
*d
, uint32_t slot_id
)
1326 qemu_spice_del_memslot(&d
->ssd
, MEMSLOT_GROUP_HOST
, slot_id
);
1327 d
->guest_slots
[slot_id
].active
= 0;
1330 static void qxl_reset_memslots(PCIQXLDevice
*d
)
1332 qxl_spice_reset_memslots(d
);
1333 memset(&d
->guest_slots
, 0, sizeof(d
->guest_slots
));
1336 static void qxl_reset_surfaces(PCIQXLDevice
*d
)
1338 trace_qxl_reset_surfaces(d
->id
);
1339 d
->mode
= QXL_MODE_UNDEFINED
;
1340 qxl_spice_destroy_surfaces(d
, QXL_SYNC
);
1343 /* can be also called from spice server thread context */
1344 static bool qxl_get_check_slot_offset(PCIQXLDevice
*qxl
, QXLPHYSICAL pqxl
,
1345 uint32_t *s
, uint64_t *o
)
1347 uint64_t phys
= le64_to_cpu(pqxl
);
1348 uint32_t slot
= (phys
>> (64 - 8)) & 0xff;
1349 uint64_t offset
= phys
& 0xffffffffffff;
1351 if (slot
>= NUM_MEMSLOTS
) {
1352 qxl_set_guest_bug(qxl
, "slot too large %d >= %d", slot
,
1356 if (!qxl
->guest_slots
[slot
].active
) {
1357 qxl_set_guest_bug(qxl
, "inactive slot %d\n", slot
);
1360 if (offset
< qxl
->guest_slots
[slot
].delta
) {
1361 qxl_set_guest_bug(qxl
,
1362 "slot %d offset %"PRIu64
" < delta %"PRIu64
"\n",
1363 slot
, offset
, qxl
->guest_slots
[slot
].delta
);
1366 offset
-= qxl
->guest_slots
[slot
].delta
;
1367 if (offset
> qxl
->guest_slots
[slot
].size
) {
1368 qxl_set_guest_bug(qxl
,
1369 "slot %d offset %"PRIu64
" > size %"PRIu64
"\n",
1370 slot
, offset
, qxl
->guest_slots
[slot
].size
);
1379 /* can be also called from spice server thread context */
1380 void *qxl_phys2virt(PCIQXLDevice
*qxl
, QXLPHYSICAL pqxl
, int group_id
)
1387 case MEMSLOT_GROUP_HOST
:
1388 offset
= le64_to_cpu(pqxl
) & 0xffffffffffff;
1389 return (void *)(intptr_t)offset
;
1390 case MEMSLOT_GROUP_GUEST
:
1391 if (!qxl_get_check_slot_offset(qxl
, pqxl
, &slot
, &offset
)) {
1394 ptr
= memory_region_get_ram_ptr(qxl
->guest_slots
[slot
].mr
);
1395 ptr
+= qxl
->guest_slots
[slot
].offset
;
1402 static void qxl_create_guest_primary_complete(PCIQXLDevice
*qxl
)
1404 /* for local rendering */
1405 qxl_render_resize(qxl
);
1408 static void qxl_create_guest_primary(PCIQXLDevice
*qxl
, int loadvm
,
1411 QXLDevSurfaceCreate surface
;
1412 QXLSurfaceCreate
*sc
= &qxl
->guest_primary
.surface
;
1413 uint32_t requested_height
= le32_to_cpu(sc
->height
);
1414 int requested_stride
= le32_to_cpu(sc
->stride
);
1416 if (requested_stride
== INT32_MIN
||
1417 abs(requested_stride
) * (uint64_t)requested_height
1418 > qxl
->vgamem_size
) {
1419 qxl_set_guest_bug(qxl
, "%s: requested primary larger than framebuffer"
1420 " stride %d x height %" PRIu32
" > %" PRIu32
,
1421 __func__
, requested_stride
, requested_height
,
1426 if (qxl
->mode
== QXL_MODE_NATIVE
) {
1427 qxl_set_guest_bug(qxl
, "%s: nop since already in QXL_MODE_NATIVE",
1430 qxl_exit_vga_mode(qxl
);
1432 surface
.format
= le32_to_cpu(sc
->format
);
1433 surface
.height
= le32_to_cpu(sc
->height
);
1434 surface
.mem
= le64_to_cpu(sc
->mem
);
1435 surface
.position
= le32_to_cpu(sc
->position
);
1436 surface
.stride
= le32_to_cpu(sc
->stride
);
1437 surface
.width
= le32_to_cpu(sc
->width
);
1438 surface
.type
= le32_to_cpu(sc
->type
);
1439 surface
.flags
= le32_to_cpu(sc
->flags
);
1440 trace_qxl_create_guest_primary(qxl
->id
, sc
->width
, sc
->height
, sc
->mem
,
1441 sc
->format
, sc
->position
);
1442 trace_qxl_create_guest_primary_rest(qxl
->id
, sc
->stride
, sc
->type
,
1445 if ((surface
.stride
& 0x3) != 0) {
1446 qxl_set_guest_bug(qxl
, "primary surface stride = %d %% 4 != 0",
1451 surface
.mouse_mode
= true;
1452 surface
.group_id
= MEMSLOT_GROUP_GUEST
;
1454 surface
.flags
|= QXL_SURF_FLAG_KEEP_DATA
;
1457 qxl
->mode
= QXL_MODE_NATIVE
;
1459 qemu_spice_create_primary_surface(&qxl
->ssd
, 0, &surface
, async
);
1461 if (async
== QXL_SYNC
) {
1462 qxl_create_guest_primary_complete(qxl
);
1466 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1467 * done (in QXL_SYNC case), 0 otherwise. */
1468 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
)
1470 if (d
->mode
== QXL_MODE_UNDEFINED
) {
1473 trace_qxl_destroy_primary(d
->id
);
1474 d
->mode
= QXL_MODE_UNDEFINED
;
1475 qemu_spice_destroy_primary_surface(&d
->ssd
, 0, async
);
1476 qxl_spice_reset_cursor(d
);
1480 static void qxl_set_mode(PCIQXLDevice
*d
, unsigned int modenr
, int loadvm
)
1482 pcibus_t start
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1483 pcibus_t end
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].size
+ start
;
1484 QXLMode
*mode
= d
->modes
->modes
+ modenr
;
1485 uint64_t devmem
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1491 if (modenr
>= d
->modes
->n_modes
) {
1492 qxl_set_guest_bug(d
, "mode number out of range");
1496 QXLSurfaceCreate surface
= {
1497 .width
= mode
->x_res
,
1498 .height
= mode
->y_res
,
1499 .stride
= -mode
->x_res
* 4,
1500 .format
= SPICE_SURFACE_FMT_32_xRGB
,
1501 .flags
= loadvm
? QXL_SURF_FLAG_KEEP_DATA
: 0,
1503 .mem
= devmem
+ d
->shadow_rom
.draw_area_offset
,
1506 trace_qxl_set_mode(d
->id
, modenr
, mode
->x_res
, mode
->y_res
, mode
->bits
,
1509 qxl_hard_reset(d
, 0);
1512 d
->guest_slots
[0].slot
= slot
;
1513 assert(qxl_add_memslot(d
, 0, devmem
, QXL_SYNC
) == 0);
1515 d
->guest_primary
.surface
= surface
;
1516 qxl_create_guest_primary(d
, 0, QXL_SYNC
);
1518 d
->mode
= QXL_MODE_COMPAT
;
1519 d
->cmdflags
= QXL_COMMAND_FLAG_COMPAT
;
1520 if (mode
->bits
== 16) {
1521 d
->cmdflags
|= QXL_COMMAND_FLAG_COMPAT_16BPP
;
1523 d
->shadow_rom
.mode
= cpu_to_le32(modenr
);
1524 d
->rom
->mode
= cpu_to_le32(modenr
);
1525 qxl_rom_set_dirty(d
);
1528 static void ioport_write(void *opaque
, hwaddr addr
,
1529 uint64_t val
, unsigned size
)
1531 PCIQXLDevice
*d
= opaque
;
1532 uint32_t io_port
= addr
;
1533 qxl_async_io async
= QXL_SYNC
;
1534 uint32_t orig_io_port
= io_port
;
1536 if (d
->guest_bug
&& io_port
!= QXL_IO_RESET
) {
1540 if (d
->revision
<= QXL_REVISION_STABLE_V10
&&
1541 io_port
> QXL_IO_FLUSH_RELEASE
) {
1542 qxl_set_guest_bug(d
, "unsupported io %d for revision %d\n",
1543 io_port
, d
->revision
);
1549 case QXL_IO_SET_MODE
:
1550 case QXL_IO_MEMSLOT_ADD
:
1551 case QXL_IO_MEMSLOT_DEL
:
1552 case QXL_IO_CREATE_PRIMARY
:
1553 case QXL_IO_UPDATE_IRQ
:
1555 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1556 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1559 if (d
->mode
!= QXL_MODE_VGA
) {
1562 trace_qxl_io_unexpected_vga_mode(d
->id
,
1563 addr
, val
, io_port_to_string(io_port
));
1564 /* be nice to buggy guest drivers */
1565 if (io_port
>= QXL_IO_UPDATE_AREA_ASYNC
&&
1566 io_port
< QXL_IO_RANGE_SIZE
) {
1567 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1572 /* we change the io_port to avoid ifdeffery in the main switch */
1573 orig_io_port
= io_port
;
1575 case QXL_IO_UPDATE_AREA_ASYNC
:
1576 io_port
= QXL_IO_UPDATE_AREA
;
1578 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1579 io_port
= QXL_IO_MEMSLOT_ADD
;
1581 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1582 io_port
= QXL_IO_CREATE_PRIMARY
;
1584 case QXL_IO_DESTROY_PRIMARY_ASYNC
:
1585 io_port
= QXL_IO_DESTROY_PRIMARY
;
1587 case QXL_IO_DESTROY_SURFACE_ASYNC
:
1588 io_port
= QXL_IO_DESTROY_SURFACE_WAIT
;
1590 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
1591 io_port
= QXL_IO_DESTROY_ALL_SURFACES
;
1593 case QXL_IO_FLUSH_SURFACES_ASYNC
:
1594 case QXL_IO_MONITORS_CONFIG_ASYNC
:
1597 qemu_mutex_lock(&d
->async_lock
);
1598 if (d
->current_async
!= QXL_UNDEFINED_IO
) {
1599 qxl_set_guest_bug(d
, "%d async started before last (%d) complete",
1600 io_port
, d
->current_async
);
1601 qemu_mutex_unlock(&d
->async_lock
);
1604 d
->current_async
= orig_io_port
;
1605 qemu_mutex_unlock(&d
->async_lock
);
1610 trace_qxl_io_write(d
->id
, qxl_mode_to_string(d
->mode
),
1611 addr
, io_port_to_string(addr
),
1615 case QXL_IO_UPDATE_AREA
:
1617 QXLCookie
*cookie
= NULL
;
1618 QXLRect update
= d
->ram
->update_area
;
1620 if (d
->ram
->update_surface
> d
->ssd
.num_surfaces
) {
1621 qxl_set_guest_bug(d
, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1622 d
->ram
->update_surface
);
1625 if (update
.left
>= update
.right
|| update
.top
>= update
.bottom
||
1626 update
.left
< 0 || update
.top
< 0) {
1627 qxl_set_guest_bug(d
,
1628 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1629 update
.left
, update
.top
, update
.right
, update
.bottom
);
1630 if (update
.left
== update
.right
|| update
.top
== update
.bottom
) {
1631 /* old drivers may provide empty area, keep going */
1632 qxl_clear_guest_bug(d
);
1637 if (async
== QXL_ASYNC
) {
1638 cookie
= qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
1639 QXL_IO_UPDATE_AREA_ASYNC
);
1640 cookie
->u
.area
= update
;
1642 qxl_spice_update_area(d
, d
->ram
->update_surface
,
1643 cookie
? &cookie
->u
.area
: &update
,
1644 NULL
, 0, 0, async
, cookie
);
1647 case QXL_IO_NOTIFY_CMD
:
1648 qemu_spice_wakeup(&d
->ssd
);
1650 case QXL_IO_NOTIFY_CURSOR
:
1651 qemu_spice_wakeup(&d
->ssd
);
1653 case QXL_IO_UPDATE_IRQ
:
1656 case QXL_IO_NOTIFY_OOM
:
1657 if (!SPICE_RING_IS_EMPTY(&d
->ram
->release_ring
)) {
1664 case QXL_IO_SET_MODE
:
1665 qxl_set_mode(d
, val
, 0);
1668 trace_qxl_io_log(d
->id
, d
->ram
->log_buf
);
1669 if (d
->guestdebug
) {
1670 fprintf(stderr
, "qxl/guest-%d: %" PRId64
": %s", d
->id
,
1671 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), d
->ram
->log_buf
);
1675 qxl_hard_reset(d
, 0);
1677 case QXL_IO_MEMSLOT_ADD
:
1678 if (val
>= NUM_MEMSLOTS
) {
1679 qxl_set_guest_bug(d
, "QXL_IO_MEMSLOT_ADD: val out of range");
1682 if (d
->guest_slots
[val
].active
) {
1683 qxl_set_guest_bug(d
,
1684 "QXL_IO_MEMSLOT_ADD: memory slot already active");
1687 d
->guest_slots
[val
].slot
= d
->ram
->mem_slot
;
1688 qxl_add_memslot(d
, val
, 0, async
);
1690 case QXL_IO_MEMSLOT_DEL
:
1691 if (val
>= NUM_MEMSLOTS
) {
1692 qxl_set_guest_bug(d
, "QXL_IO_MEMSLOT_DEL: val out of range");
1695 qxl_del_memslot(d
, val
);
1697 case QXL_IO_CREATE_PRIMARY
:
1699 qxl_set_guest_bug(d
, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1703 d
->guest_primary
.surface
= d
->ram
->create_surface
;
1704 qxl_create_guest_primary(d
, 0, async
);
1706 case QXL_IO_DESTROY_PRIMARY
:
1708 qxl_set_guest_bug(d
, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1712 if (!qxl_destroy_primary(d
, async
)) {
1713 trace_qxl_io_destroy_primary_ignored(d
->id
,
1714 qxl_mode_to_string(d
->mode
));
1718 case QXL_IO_DESTROY_SURFACE_WAIT
:
1719 if (val
>= d
->ssd
.num_surfaces
) {
1720 qxl_set_guest_bug(d
, "QXL_IO_DESTROY_SURFACE (async=%d):"
1721 "%" PRIu64
" >= NUM_SURFACES", async
, val
);
1724 qxl_spice_destroy_surface_wait(d
, val
, async
);
1726 case QXL_IO_FLUSH_RELEASE
: {
1727 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
1728 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
1730 "ERROR: no flush, full release ring [p%d,%dc]\n",
1731 ring
->prod
, ring
->cons
);
1733 qxl_push_free_res(d
, 1 /* flush */);
1736 case QXL_IO_FLUSH_SURFACES_ASYNC
:
1737 qxl_spice_flush_surfaces_async(d
);
1739 case QXL_IO_DESTROY_ALL_SURFACES
:
1740 d
->mode
= QXL_MODE_UNDEFINED
;
1741 qxl_spice_destroy_surfaces(d
, async
);
1743 case QXL_IO_MONITORS_CONFIG_ASYNC
:
1744 qxl_spice_monitors_config_async(d
, 0);
1747 qxl_set_guest_bug(d
, "%s: unexpected ioport=0x%x\n", __func__
, io_port
);
1752 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1753 qemu_mutex_lock(&d
->async_lock
);
1754 d
->current_async
= QXL_UNDEFINED_IO
;
1755 qemu_mutex_unlock(&d
->async_lock
);
1759 static uint64_t ioport_read(void *opaque
, hwaddr addr
,
1762 PCIQXLDevice
*qxl
= opaque
;
1764 trace_qxl_io_read_unexpected(qxl
->id
);
1768 static const MemoryRegionOps qxl_io_ops
= {
1769 .read
= ioport_read
,
1770 .write
= ioport_write
,
1772 .min_access_size
= 1,
1773 .max_access_size
= 1,
1777 static void qxl_update_irq_bh(void *opaque
)
1779 PCIQXLDevice
*d
= opaque
;
1783 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
)
1785 uint32_t old_pending
;
1786 uint32_t le_events
= cpu_to_le32(events
);
1788 trace_qxl_send_events(d
->id
, events
);
1789 if (!qemu_spice_display_is_running(&d
->ssd
)) {
1790 /* spice-server tracks guest running state and should not do this */
1791 fprintf(stderr
, "%s: spice-server bug: guest stopped, ignoring\n",
1793 trace_qxl_send_events_vm_stopped(d
->id
, events
);
1796 old_pending
= atomic_fetch_or(&d
->ram
->int_pending
, le_events
);
1797 if ((old_pending
& le_events
) == le_events
) {
1800 qemu_bh_schedule(d
->update_irq
);
1803 /* graphics console */
1805 static void qxl_hw_update(void *opaque
)
1807 PCIQXLDevice
*qxl
= opaque
;
1809 qxl_render_update(qxl
);
1812 static void qxl_dirty_surfaces(PCIQXLDevice
*qxl
)
1814 uintptr_t vram_start
;
1817 if (qxl
->mode
!= QXL_MODE_NATIVE
&& qxl
->mode
!= QXL_MODE_COMPAT
) {
1821 /* dirty the primary surface */
1822 qxl_set_dirty(&qxl
->vga
.vram
, qxl
->shadow_rom
.draw_area_offset
,
1823 qxl
->shadow_rom
.surface0_area_size
);
1825 vram_start
= (uintptr_t)memory_region_get_ram_ptr(&qxl
->vram_bar
);
1827 /* dirty the off-screen surfaces */
1828 for (i
= 0; i
< qxl
->ssd
.num_surfaces
; i
++) {
1830 intptr_t surface_offset
;
1833 if (qxl
->guest_surfaces
.cmds
[i
] == 0) {
1837 cmd
= qxl_phys2virt(qxl
, qxl
->guest_surfaces
.cmds
[i
],
1838 MEMSLOT_GROUP_GUEST
);
1840 assert(cmd
->type
== QXL_SURFACE_CMD_CREATE
);
1841 surface_offset
= (intptr_t)qxl_phys2virt(qxl
,
1842 cmd
->u
.surface_create
.data
,
1843 MEMSLOT_GROUP_GUEST
);
1844 assert(surface_offset
);
1845 surface_offset
-= vram_start
;
1846 surface_size
= cmd
->u
.surface_create
.height
*
1847 abs(cmd
->u
.surface_create
.stride
);
1848 trace_qxl_surfaces_dirty(qxl
->id
, i
, (int)surface_offset
, surface_size
);
1849 qxl_set_dirty(&qxl
->vram_bar
, surface_offset
, surface_size
);
1853 static void qxl_vm_change_state_handler(void *opaque
, int running
,
1856 PCIQXLDevice
*qxl
= opaque
;
1860 * if qxl_send_events was called from spice server context before
1861 * migration ended, qxl_update_irq for these events might not have been
1864 qxl_update_irq(qxl
);
1866 /* make sure surfaces are saved before migration */
1867 qxl_dirty_surfaces(qxl
);
1871 /* display change listener */
1873 static void display_update(DisplayChangeListener
*dcl
,
1874 int x
, int y
, int w
, int h
)
1876 PCIQXLDevice
*qxl
= container_of(dcl
, PCIQXLDevice
, ssd
.dcl
);
1878 if (qxl
->mode
== QXL_MODE_VGA
) {
1879 qemu_spice_display_update(&qxl
->ssd
, x
, y
, w
, h
);
1883 static void display_switch(DisplayChangeListener
*dcl
,
1884 struct DisplaySurface
*surface
)
1886 PCIQXLDevice
*qxl
= container_of(dcl
, PCIQXLDevice
, ssd
.dcl
);
1888 qxl
->ssd
.ds
= surface
;
1889 if (qxl
->mode
== QXL_MODE_VGA
) {
1890 qemu_spice_display_switch(&qxl
->ssd
, surface
);
1894 static void display_refresh(DisplayChangeListener
*dcl
)
1896 PCIQXLDevice
*qxl
= container_of(dcl
, PCIQXLDevice
, ssd
.dcl
);
1898 if (qxl
->mode
== QXL_MODE_VGA
) {
1899 qemu_spice_display_refresh(&qxl
->ssd
);
1903 static DisplayChangeListenerOps display_listener_ops
= {
1904 .dpy_name
= "spice/qxl",
1905 .dpy_gfx_update
= display_update
,
1906 .dpy_gfx_switch
= display_switch
,
1907 .dpy_refresh
= display_refresh
,
1910 static void qxl_init_ramsize(PCIQXLDevice
*qxl
)
1912 /* vga mode framebuffer / primary surface (bar 0, first part) */
1913 if (qxl
->vgamem_size_mb
< 8) {
1914 qxl
->vgamem_size_mb
= 8;
1916 /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be
1917 * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now).
1919 if (qxl
->vgamem_size_mb
> 256) {
1920 qxl
->vgamem_size_mb
= 256;
1922 qxl
->vgamem_size
= qxl
->vgamem_size_mb
* 1024 * 1024;
1924 /* vga ram (bar 0, total) */
1925 if (qxl
->ram_size_mb
!= -1) {
1926 qxl
->vga
.vram_size
= qxl
->ram_size_mb
* 1024 * 1024;
1928 if (qxl
->vga
.vram_size
< qxl
->vgamem_size
* 2) {
1929 qxl
->vga
.vram_size
= qxl
->vgamem_size
* 2;
1932 /* vram32 (surfaces, 32bit, bar 1) */
1933 if (qxl
->vram32_size_mb
!= -1) {
1934 qxl
->vram32_size
= qxl
->vram32_size_mb
* 1024 * 1024;
1936 if (qxl
->vram32_size
< 4096) {
1937 qxl
->vram32_size
= 4096;
1940 /* vram (surfaces, 64bit, bar 4+5) */
1941 if (qxl
->vram_size_mb
!= -1) {
1942 qxl
->vram_size
= (uint64_t)qxl
->vram_size_mb
* 1024 * 1024;
1944 if (qxl
->vram_size
< qxl
->vram32_size
) {
1945 qxl
->vram_size
= qxl
->vram32_size
;
1948 if (qxl
->revision
== 1) {
1949 qxl
->vram32_size
= 4096;
1950 qxl
->vram_size
= 4096;
1952 qxl
->vgamem_size
= pow2ceil(qxl
->vgamem_size
);
1953 qxl
->vga
.vram_size
= pow2ceil(qxl
->vga
.vram_size
);
1954 qxl
->vram32_size
= pow2ceil(qxl
->vram32_size
);
1955 qxl
->vram_size
= pow2ceil(qxl
->vram_size
);
1958 static void qxl_realize_common(PCIQXLDevice
*qxl
, Error
**errp
)
1960 uint8_t* config
= qxl
->pci
.config
;
1961 uint32_t pci_device_rev
;
1964 qxl
->mode
= QXL_MODE_UNDEFINED
;
1965 qxl
->generation
= 1;
1966 qxl
->num_memslots
= NUM_MEMSLOTS
;
1967 qemu_mutex_init(&qxl
->track_lock
);
1968 qemu_mutex_init(&qxl
->async_lock
);
1969 qxl
->current_async
= QXL_UNDEFINED_IO
;
1972 switch (qxl
->revision
) {
1973 case 1: /* spice 0.4 -- qxl-1 */
1974 pci_device_rev
= QXL_REVISION_STABLE_V04
;
1977 case 2: /* spice 0.6 -- qxl-2 */
1978 pci_device_rev
= QXL_REVISION_STABLE_V06
;
1982 pci_device_rev
= QXL_REVISION_STABLE_V10
;
1983 io_size
= 32; /* PCI region size must be pow2 */
1986 pci_device_rev
= QXL_REVISION_STABLE_V12
;
1987 io_size
= pow2ceil(QXL_IO_RANGE_SIZE
);
1990 error_setg(errp
, "Invalid revision %d for qxl device (max %d)",
1991 qxl
->revision
, QXL_DEFAULT_REVISION
);
1995 pci_set_byte(&config
[PCI_REVISION_ID
], pci_device_rev
);
1996 pci_set_byte(&config
[PCI_INTERRUPT_PIN
], 1);
1998 qxl
->rom_size
= qxl_rom_size();
1999 memory_region_init_ram(&qxl
->rom_bar
, OBJECT(qxl
), "qxl.vrom",
2000 qxl
->rom_size
, &error_fatal
);
2001 vmstate_register_ram(&qxl
->rom_bar
, &qxl
->pci
.qdev
);
2005 qxl
->guest_surfaces
.cmds
= g_new0(QXLPHYSICAL
, qxl
->ssd
.num_surfaces
);
2006 memory_region_init_ram(&qxl
->vram_bar
, OBJECT(qxl
), "qxl.vram",
2007 qxl
->vram_size
, &error_fatal
);
2008 vmstate_register_ram(&qxl
->vram_bar
, &qxl
->pci
.qdev
);
2009 memory_region_init_alias(&qxl
->vram32_bar
, OBJECT(qxl
), "qxl.vram32",
2010 &qxl
->vram_bar
, 0, qxl
->vram32_size
);
2012 memory_region_init_io(&qxl
->io_bar
, OBJECT(qxl
), &qxl_io_ops
, qxl
,
2013 "qxl-ioports", io_size
);
2015 vga_dirty_log_start(&qxl
->vga
);
2017 memory_region_set_flush_coalesced(&qxl
->io_bar
);
2020 pci_register_bar(&qxl
->pci
, QXL_IO_RANGE_INDEX
,
2021 PCI_BASE_ADDRESS_SPACE_IO
, &qxl
->io_bar
);
2023 pci_register_bar(&qxl
->pci
, QXL_ROM_RANGE_INDEX
,
2024 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->rom_bar
);
2026 pci_register_bar(&qxl
->pci
, QXL_RAM_RANGE_INDEX
,
2027 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->vga
.vram
);
2029 pci_register_bar(&qxl
->pci
, QXL_VRAM_RANGE_INDEX
,
2030 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->vram32_bar
);
2032 if (qxl
->vram32_size
< qxl
->vram_size
) {
2034 * Make the 64bit vram bar show up only in case it is
2035 * configured to be larger than the 32bit vram bar.
2037 pci_register_bar(&qxl
->pci
, QXL_VRAM64_RANGE_INDEX
,
2038 PCI_BASE_ADDRESS_SPACE_MEMORY
|
2039 PCI_BASE_ADDRESS_MEM_TYPE_64
|
2040 PCI_BASE_ADDRESS_MEM_PREFETCH
,
2044 /* print pci bar details */
2045 dprint(qxl
, 1, "ram/%s: %d MB [region 0]\n",
2046 qxl
->id
== 0 ? "pri" : "sec",
2047 qxl
->vga
.vram_size
/ (1024*1024));
2048 dprint(qxl
, 1, "vram/32: %" PRIx64
"d MB [region 1]\n",
2049 qxl
->vram32_size
/ (1024*1024));
2050 dprint(qxl
, 1, "vram/64: %" PRIx64
"d MB %s\n",
2051 qxl
->vram_size
/ (1024*1024),
2052 qxl
->vram32_size
< qxl
->vram_size
? "[region 4]" : "[unmapped]");
2054 qxl
->ssd
.qxl
.base
.sif
= &qxl_interface
.base
;
2055 if (qemu_spice_add_display_interface(&qxl
->ssd
.qxl
, qxl
->vga
.con
) != 0) {
2056 error_setg(errp
, "qxl interface %d.%d not supported by spice-server",
2057 SPICE_INTERFACE_QXL_MAJOR
, SPICE_INTERFACE_QXL_MINOR
);
2060 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler
, qxl
);
2062 qxl
->update_irq
= qemu_bh_new(qxl_update_irq_bh
, qxl
);
2063 qxl_reset_state(qxl
);
2065 qxl
->update_area_bh
= qemu_bh_new(qxl_render_update_area_bh
, qxl
);
2066 qxl
->ssd
.cursor_bh
= qemu_bh_new(qemu_spice_cursor_refresh_bh
, &qxl
->ssd
);
2069 static void qxl_realize_primary(PCIDevice
*dev
, Error
**errp
)
2071 PCIQXLDevice
*qxl
= PCI_QXL(dev
);
2072 VGACommonState
*vga
= &qxl
->vga
;
2073 Error
*local_err
= NULL
;
2076 qxl_init_ramsize(qxl
);
2077 vga
->vbe_size
= qxl
->vgamem_size
;
2078 vga
->vram_size_mb
= qxl
->vga
.vram_size
>> 20;
2079 vga_common_init(vga
, OBJECT(dev
), true);
2080 vga_init(vga
, OBJECT(dev
),
2081 pci_address_space(dev
), pci_address_space_io(dev
), false);
2082 portio_list_init(&qxl
->vga_port_list
, OBJECT(dev
), qxl_vga_portio_list
,
2084 portio_list_set_flush_coalesced(&qxl
->vga_port_list
);
2085 portio_list_add(&qxl
->vga_port_list
, pci_address_space_io(dev
), 0x3b0);
2087 vga
->con
= graphic_console_init(DEVICE(dev
), 0, &qxl_ops
, qxl
);
2088 qemu_spice_display_init_common(&qxl
->ssd
);
2090 qxl_realize_common(qxl
, &local_err
);
2092 error_propagate(errp
, local_err
);
2096 qxl
->ssd
.dcl
.ops
= &display_listener_ops
;
2097 qxl
->ssd
.dcl
.con
= vga
->con
;
2098 register_displaychangelistener(&qxl
->ssd
.dcl
);
2101 static void qxl_realize_secondary(PCIDevice
*dev
, Error
**errp
)
2103 static int device_id
= 1;
2104 PCIQXLDevice
*qxl
= PCI_QXL(dev
);
2106 qxl
->id
= device_id
++;
2107 qxl_init_ramsize(qxl
);
2108 memory_region_init_ram(&qxl
->vga
.vram
, OBJECT(dev
), "qxl.vgavram",
2109 qxl
->vga
.vram_size
, &error_fatal
);
2110 vmstate_register_ram(&qxl
->vga
.vram
, &qxl
->pci
.qdev
);
2111 qxl
->vga
.vram_ptr
= memory_region_get_ram_ptr(&qxl
->vga
.vram
);
2112 qxl
->vga
.con
= graphic_console_init(DEVICE(dev
), 0, &qxl_ops
, qxl
);
2114 qxl_realize_common(qxl
, errp
);
2117 static void qxl_pre_save(void *opaque
)
2119 PCIQXLDevice
* d
= opaque
;
2120 uint8_t *ram_start
= d
->vga
.vram_ptr
;
2122 trace_qxl_pre_save(d
->id
);
2123 if (d
->last_release
== NULL
) {
2124 d
->last_release_offset
= 0;
2126 d
->last_release_offset
= (uint8_t *)d
->last_release
- ram_start
;
2128 assert(d
->last_release_offset
< d
->vga
.vram_size
);
2131 static int qxl_pre_load(void *opaque
)
2133 PCIQXLDevice
* d
= opaque
;
2135 trace_qxl_pre_load(d
->id
);
2136 qxl_hard_reset(d
, 1);
2137 qxl_exit_vga_mode(d
);
2141 static void qxl_create_memslots(PCIQXLDevice
*d
)
2145 for (i
= 0; i
< NUM_MEMSLOTS
; i
++) {
2146 if (!d
->guest_slots
[i
].active
) {
2149 qxl_add_memslot(d
, i
, 0, QXL_SYNC
);
2153 static int qxl_post_load(void *opaque
, int version
)
2155 PCIQXLDevice
* d
= opaque
;
2156 uint8_t *ram_start
= d
->vga
.vram_ptr
;
2157 QXLCommandExt
*cmds
;
2158 int in
, out
, newmode
;
2160 assert(d
->last_release_offset
< d
->vga
.vram_size
);
2161 if (d
->last_release_offset
== 0) {
2162 d
->last_release
= NULL
;
2164 d
->last_release
= (QXLReleaseInfo
*)(ram_start
+ d
->last_release_offset
);
2167 d
->modes
= (QXLModes
*)((uint8_t*)d
->rom
+ d
->rom
->modes_offset
);
2169 trace_qxl_post_load(d
->id
, qxl_mode_to_string(d
->mode
));
2171 d
->mode
= QXL_MODE_UNDEFINED
;
2174 case QXL_MODE_UNDEFINED
:
2175 qxl_create_memslots(d
);
2178 qxl_create_memslots(d
);
2179 qxl_enter_vga_mode(d
);
2181 case QXL_MODE_NATIVE
:
2182 qxl_create_memslots(d
);
2183 qxl_create_guest_primary(d
, 1, QXL_SYNC
);
2185 /* replay surface-create and cursor-set commands */
2186 cmds
= g_new0(QXLCommandExt
, d
->ssd
.num_surfaces
+ 1);
2187 for (in
= 0, out
= 0; in
< d
->ssd
.num_surfaces
; in
++) {
2188 if (d
->guest_surfaces
.cmds
[in
] == 0) {
2191 cmds
[out
].cmd
.data
= d
->guest_surfaces
.cmds
[in
];
2192 cmds
[out
].cmd
.type
= QXL_CMD_SURFACE
;
2193 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
2196 if (d
->guest_cursor
) {
2197 cmds
[out
].cmd
.data
= d
->guest_cursor
;
2198 cmds
[out
].cmd
.type
= QXL_CMD_CURSOR
;
2199 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
2202 qxl_spice_loadvm_commands(d
, cmds
, out
);
2204 if (d
->guest_monitors_config
) {
2205 qxl_spice_monitors_config_async(d
, 1);
2208 case QXL_MODE_COMPAT
:
2209 /* note: no need to call qxl_create_memslots, qxl_set_mode
2210 * creates the mem slot. */
2211 qxl_set_mode(d
, d
->shadow_rom
.mode
, 1);
2217 #define QXL_SAVE_VERSION 21
2219 static bool qxl_monitors_config_needed(void *opaque
)
2221 PCIQXLDevice
*qxl
= opaque
;
2223 return qxl
->guest_monitors_config
!= 0;
2227 static VMStateDescription qxl_memslot
= {
2228 .name
= "qxl-memslot",
2229 .version_id
= QXL_SAVE_VERSION
,
2230 .minimum_version_id
= QXL_SAVE_VERSION
,
2231 .fields
= (VMStateField
[]) {
2232 VMSTATE_UINT64(slot
.mem_start
, struct guest_slots
),
2233 VMSTATE_UINT64(slot
.mem_end
, struct guest_slots
),
2234 VMSTATE_UINT32(active
, struct guest_slots
),
2235 VMSTATE_END_OF_LIST()
2239 static VMStateDescription qxl_surface
= {
2240 .name
= "qxl-surface",
2241 .version_id
= QXL_SAVE_VERSION
,
2242 .minimum_version_id
= QXL_SAVE_VERSION
,
2243 .fields
= (VMStateField
[]) {
2244 VMSTATE_UINT32(width
, QXLSurfaceCreate
),
2245 VMSTATE_UINT32(height
, QXLSurfaceCreate
),
2246 VMSTATE_INT32(stride
, QXLSurfaceCreate
),
2247 VMSTATE_UINT32(format
, QXLSurfaceCreate
),
2248 VMSTATE_UINT32(position
, QXLSurfaceCreate
),
2249 VMSTATE_UINT32(mouse_mode
, QXLSurfaceCreate
),
2250 VMSTATE_UINT32(flags
, QXLSurfaceCreate
),
2251 VMSTATE_UINT32(type
, QXLSurfaceCreate
),
2252 VMSTATE_UINT64(mem
, QXLSurfaceCreate
),
2253 VMSTATE_END_OF_LIST()
2257 static VMStateDescription qxl_vmstate_monitors_config
= {
2258 .name
= "qxl/monitors-config",
2260 .minimum_version_id
= 1,
2261 .needed
= qxl_monitors_config_needed
,
2262 .fields
= (VMStateField
[]) {
2263 VMSTATE_UINT64(guest_monitors_config
, PCIQXLDevice
),
2264 VMSTATE_END_OF_LIST()
2268 static VMStateDescription qxl_vmstate
= {
2270 .version_id
= QXL_SAVE_VERSION
,
2271 .minimum_version_id
= QXL_SAVE_VERSION
,
2272 .pre_save
= qxl_pre_save
,
2273 .pre_load
= qxl_pre_load
,
2274 .post_load
= qxl_post_load
,
2275 .fields
= (VMStateField
[]) {
2276 VMSTATE_PCI_DEVICE(pci
, PCIQXLDevice
),
2277 VMSTATE_STRUCT(vga
, PCIQXLDevice
, 0, vmstate_vga_common
, VGACommonState
),
2278 VMSTATE_UINT32(shadow_rom
.mode
, PCIQXLDevice
),
2279 VMSTATE_UINT32(num_free_res
, PCIQXLDevice
),
2280 VMSTATE_UINT32(last_release_offset
, PCIQXLDevice
),
2281 VMSTATE_UINT32(mode
, PCIQXLDevice
),
2282 VMSTATE_UINT32(ssd
.unique
, PCIQXLDevice
),
2283 VMSTATE_INT32_EQUAL(num_memslots
, PCIQXLDevice
),
2284 VMSTATE_STRUCT_ARRAY(guest_slots
, PCIQXLDevice
, NUM_MEMSLOTS
, 0,
2285 qxl_memslot
, struct guest_slots
),
2286 VMSTATE_STRUCT(guest_primary
.surface
, PCIQXLDevice
, 0,
2287 qxl_surface
, QXLSurfaceCreate
),
2288 VMSTATE_INT32_EQUAL(ssd
.num_surfaces
, PCIQXLDevice
),
2289 VMSTATE_VARRAY_INT32(guest_surfaces
.cmds
, PCIQXLDevice
,
2290 ssd
.num_surfaces
, 0,
2291 vmstate_info_uint64
, uint64_t),
2292 VMSTATE_UINT64(guest_cursor
, PCIQXLDevice
),
2293 VMSTATE_END_OF_LIST()
2295 .subsections
= (const VMStateDescription
*[]) {
2296 &qxl_vmstate_monitors_config
,
2301 static Property qxl_properties
[] = {
2302 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice
, vga
.vram_size
,
2304 DEFINE_PROP_UINT64("vram_size", PCIQXLDevice
, vram32_size
,
2306 DEFINE_PROP_UINT32("revision", PCIQXLDevice
, revision
,
2307 QXL_DEFAULT_REVISION
),
2308 DEFINE_PROP_UINT32("debug", PCIQXLDevice
, debug
, 0),
2309 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice
, guestdebug
, 0),
2310 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice
, cmdlog
, 0),
2311 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice
, ram_size_mb
, -1),
2312 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice
, vram32_size_mb
, -1),
2313 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice
, vram_size_mb
, -1),
2314 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice
, vgamem_size_mb
, 16),
2315 DEFINE_PROP_INT32("surfaces", PCIQXLDevice
, ssd
.num_surfaces
, 1024),
2316 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
2317 DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice
, max_outputs
, 0),
2319 DEFINE_PROP_END_OF_LIST(),
2322 static void qxl_pci_class_init(ObjectClass
*klass
, void *data
)
2324 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2325 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2327 k
->vendor_id
= REDHAT_PCI_VENDOR_ID
;
2328 k
->device_id
= QXL_DEVICE_ID_STABLE
;
2329 set_bit(DEVICE_CATEGORY_DISPLAY
, dc
->categories
);
2330 dc
->reset
= qxl_reset_handler
;
2331 dc
->vmsd
= &qxl_vmstate
;
2332 dc
->props
= qxl_properties
;
2335 static const TypeInfo qxl_pci_type_info
= {
2336 .name
= TYPE_PCI_QXL
,
2337 .parent
= TYPE_PCI_DEVICE
,
2338 .instance_size
= sizeof(PCIQXLDevice
),
2340 .class_init
= qxl_pci_class_init
,
2343 static void qxl_primary_class_init(ObjectClass
*klass
, void *data
)
2345 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2346 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2348 k
->realize
= qxl_realize_primary
;
2349 k
->romfile
= "vgabios-qxl.bin";
2350 k
->class_id
= PCI_CLASS_DISPLAY_VGA
;
2351 dc
->desc
= "Spice QXL GPU (primary, vga compatible)";
2352 dc
->hotpluggable
= false;
2355 static const TypeInfo qxl_primary_info
= {
2357 .parent
= TYPE_PCI_QXL
,
2358 .class_init
= qxl_primary_class_init
,
2361 static void qxl_secondary_class_init(ObjectClass
*klass
, void *data
)
2363 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2364 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2366 k
->realize
= qxl_realize_secondary
;
2367 k
->class_id
= PCI_CLASS_DISPLAY_OTHER
;
2368 dc
->desc
= "Spice QXL GPU (secondary)";
2371 static const TypeInfo qxl_secondary_info
= {
2373 .parent
= TYPE_PCI_QXL
,
2374 .class_init
= qxl_secondary_class_init
,
2377 static void qxl_register_types(void)
2379 type_register_static(&qxl_pci_type_info
);
2380 type_register_static(&qxl_primary_info
);
2381 type_register_static(&qxl_secondary_info
);
2384 type_init(qxl_register_types
)