hw/display/vga-pci.c

   1 /*
   2  * QEMU PCI VGA Emulator.
   3  *
   4  * see docs/specs/standard-vga.txt for virtual hardware specs.
   5  *
   6  * Copyright (c) 2003 Fabrice Bellard
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26 #include "hw/hw.h"
  27 #include "ui/console.h"
  28 #include "hw/pci/pci.h"
  29 #include "vga_int.h"
  30 #include "ui/pixel_ops.h"
  31 #include "qemu/timer.h"
  32 #include "hw/loader.h"
  33
  34 #define PCI_VGA_IOPORT_OFFSET 0x400
  35 #define PCI_VGA_IOPORT_SIZE   (0x3e0 - 0x3c0)
  36 #define PCI_VGA_BOCHS_OFFSET  0x500
  37 #define PCI_VGA_BOCHS_SIZE    (0x0b * 2)
  38 #define PCI_VGA_QEXT_OFFSET   0x600
  39 #define PCI_VGA_QEXT_SIZE     (2 * 4)
  40 #define PCI_VGA_MMIO_SIZE     0x1000
  41
  42 #define PCI_VGA_QEXT_REG_SIZE         (0 * 4)
  43 #define PCI_VGA_QEXT_REG_BYTEORDER    (1 * 4)
  44 #define  PCI_VGA_QEXT_LITTLE_ENDIAN   0x1e1e1e1e
  45 #define  PCI_VGA_QEXT_BIG_ENDIAN      0xbebebebe
  46
  47 enum vga_pci_flags {
  48     PCI_VGA_FLAG_ENABLE_MMIO = 1,
  49     PCI_VGA_FLAG_ENABLE_QEXT = 2,
  50 };
  51
  52 typedef struct PCIVGAState {
  53     PCIDevice dev;
  54     VGACommonState vga;
  55     uint32_t flags;
  56     MemoryRegion mmio;
  57     MemoryRegion ioport;
  58     MemoryRegion bochs;
  59     MemoryRegion qext;
  60 } PCIVGAState;
  61
  62 #define TYPE_PCI_VGA "pci-vga"
  63 #define PCI_VGA(obj) OBJECT_CHECK(PCIVGAState, (obj), TYPE_PCI_VGA)
  64
  65 static const VMStateDescription vmstate_vga_pci = {
  66     .name = "vga",
  67     .version_id = 2,
  68     .minimum_version_id = 2,
  69     .fields = (VMStateField[]) {
  70         VMSTATE_PCI_DEVICE(dev, PCIVGAState),
  71         VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState),
  72         VMSTATE_END_OF_LIST()
  73     }
  74 };
  75
  76 static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
  77                                     unsigned size)
  78 {
  79     PCIVGAState *d = ptr;
  80     uint64_t ret = 0;
  81
  82     switch (size) {
  83     case 1:
  84         ret = vga_ioport_read(&d->vga, addr);
  85         break;
  86     case 2:
  87         ret  = vga_ioport_read(&d->vga, addr);
  88         ret |= vga_ioport_read(&d->vga, addr+1) << 8;
  89         break;
  90     }
  91     return ret;
  92 }
  93
  94 static void pci_vga_ioport_write(void *ptr, hwaddr addr,
  95                                  uint64_t val, unsigned size)
  96 {
  97     PCIVGAState *d = ptr;
  98
  99     switch (size) {
 100     case 1:
 101         vga_ioport_write(&d->vga, addr + 0x3c0, val);
 102         break;
 103     case 2:
 104         /*
 105          * Update bytes in little endian order.  Allows to update
 106          * indexed registers with a single word write because the
 107          * index byte is updated first.
 108          */
 109         vga_ioport_write(&d->vga, addr + 0x3c0, val & 0xff);
 110         vga_ioport_write(&d->vga, addr + 0x3c1, (val >> 8) & 0xff);
 111         break;
 112     }
 113 }
 114
 115 static const MemoryRegionOps pci_vga_ioport_ops = {
 116     .read = pci_vga_ioport_read,
 117     .write = pci_vga_ioport_write,
 118     .valid.min_access_size = 1,
 119     .valid.max_access_size = 4,
 120     .impl.min_access_size = 1,
 121     .impl.max_access_size = 2,
 122     .endianness = DEVICE_LITTLE_ENDIAN,
 123 };
 124
 125 static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
 126                                    unsigned size)
 127 {
 128     PCIVGAState *d = ptr;
 129     int index = addr >> 1;
 130
 131     vbe_ioport_write_index(&d->vga, 0, index);
 132     return vbe_ioport_read_data(&d->vga, 0);
 133 }
 134
 135 static void pci_vga_bochs_write(void *ptr, hwaddr addr,
 136                                 uint64_t val, unsigned size)
 137 {
 138     PCIVGAState *d = ptr;
 139     int index = addr >> 1;
 140
 141     vbe_ioport_write_index(&d->vga, 0, index);
 142     vbe_ioport_write_data(&d->vga, 0, val);
 143 }
 144
 145 static const MemoryRegionOps pci_vga_bochs_ops = {
 146     .read = pci_vga_bochs_read,
 147     .write = pci_vga_bochs_write,
 148     .valid.min_access_size = 1,
 149     .valid.max_access_size = 4,
 150     .impl.min_access_size = 2,
 151     .impl.max_access_size = 2,
 152     .endianness = DEVICE_LITTLE_ENDIAN,
 153 };
 154
 155 static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
 156 {
 157     PCIVGAState *d = ptr;
 158
 159     switch (addr) {
 160     case PCI_VGA_QEXT_REG_SIZE:
 161         return PCI_VGA_QEXT_SIZE;
 162     case PCI_VGA_QEXT_REG_BYTEORDER:
 163         return d->vga.big_endian_fb ?
 164             PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
 165     default:
 166         return 0;
 167     }
 168 }
 169
 170 static void pci_vga_qext_write(void *ptr, hwaddr addr,
 171                                uint64_t val, unsigned size)
 172 {
 173     PCIVGAState *d = ptr;
 174
 175     switch (addr) {
 176     case PCI_VGA_QEXT_REG_BYTEORDER:
 177         if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
 178             d->vga.big_endian_fb = true;
 179         }
 180         if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
 181             d->vga.big_endian_fb = false;
 182         }
 183         break;
 184     }
 185 }
 186
 187 static bool vga_get_big_endian_fb(Object *obj, Error **errp)
 188 {
 189     PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
 190
 191     return d->vga.big_endian_fb;
 192 }
 193
 194 static void vga_set_big_endian_fb(Object *obj, bool value, Error **errp)
 195 {
 196     PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
 197
 198     d->vga.big_endian_fb = value;
 199 }
 200
 201 static const MemoryRegionOps pci_vga_qext_ops = {
 202     .read = pci_vga_qext_read,
 203     .write = pci_vga_qext_write,
 204     .valid.min_access_size = 4,
 205     .valid.max_access_size = 4,
 206     .endianness = DEVICE_LITTLE_ENDIAN,
 207 };
 208
 209 static void pci_std_vga_realize(PCIDevice *dev, Error **errp)
 210 {
 211     PCIVGAState *d = PCI_VGA(dev);
 212     VGACommonState *s = &d->vga;
 213
 214     /* vga + console init */
 215     vga_common_init(s, OBJECT(dev), true);
 216     vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
 217              true);
 218
 219     s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
 220
 221     /* XXX: VGA_RAM_SIZE must be a power of two */
 222     pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
 223
 224     /* mmio bar for vga register access */
 225     if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
 226         memory_region_init(&d->mmio, NULL, "vga.mmio", 4096);
 227         memory_region_init_io(&d->ioport, NULL, &pci_vga_ioport_ops, d,
 228                               "vga ioports remapped", PCI_VGA_IOPORT_SIZE);
 229         memory_region_init_io(&d->bochs, NULL, &pci_vga_bochs_ops, d,
 230                               "bochs dispi interface", PCI_VGA_BOCHS_SIZE);
 231
 232         memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET,
 233                                     &d->ioport);
 234         memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET,
 235                                     &d->bochs);
 236
 237         if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
 238             memory_region_init_io(&d->qext, NULL, &pci_vga_qext_ops, d,
 239                                   "qemu extended regs", PCI_VGA_QEXT_SIZE);
 240             memory_region_add_subregion(&d->mmio, PCI_VGA_QEXT_OFFSET,
 241                                         &d->qext);
 242             pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
 243         }
 244
 245         pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
 246     }
 247
 248     if (!dev->rom_bar) {
 249         /* compatibility with pc-0.13 and older */
 250         vga_init_vbe(s, OBJECT(dev), pci_address_space(dev));
 251     }
 252 }
 253
 254 static void pci_std_vga_init(Object *obj)
 255 {
 256     /* Expose framebuffer byteorder via QOM */
 257     object_property_add_bool(obj, "big-endian-framebuffer",
 258                              vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
 259 }
 260
 261 static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp)
 262 {
 263     PCIVGAState *d = PCI_VGA(dev);
 264     VGACommonState *s = &d->vga;
 265
 266     /* vga + console init */
 267     vga_common_init(s, OBJECT(dev), false);
 268     s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
 269
 270     /* mmio bar */
 271     memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio", 4096);
 272     memory_region_init_io(&d->ioport, OBJECT(dev), &pci_vga_ioport_ops, d,
 273                           "vga ioports remapped", PCI_VGA_IOPORT_SIZE);
 274     memory_region_init_io(&d->bochs, OBJECT(dev), &pci_vga_bochs_ops, d,
 275                           "bochs dispi interface", PCI_VGA_BOCHS_SIZE);
 276
 277     memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET,
 278                                 &d->ioport);
 279     memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET,
 280                                 &d->bochs);
 281
 282     if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
 283         memory_region_init_io(&d->qext, NULL, &pci_vga_qext_ops, d,
 284                               "qemu extended regs", PCI_VGA_QEXT_SIZE);
 285         memory_region_add_subregion(&d->mmio, PCI_VGA_QEXT_OFFSET,
 286                                     &d->qext);
 287         pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
 288     }
 289
 290     pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
 291     pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
 292 }
 293
 294 static void pci_secondary_vga_init(Object *obj)
 295 {
 296     /* Expose framebuffer byteorder via QOM */
 297     object_property_add_bool(obj, "big-endian-framebuffer",
 298                              vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
 299 }
 300
 301 static void pci_secondary_vga_reset(DeviceState *dev)
 302 {
 303     PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev));
 304     vga_common_reset(&d->vga);
 305 }
 306
 307 static Property vga_pci_properties[] = {
 308     DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
 309     DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
 310     DEFINE_PROP_BIT("qemu-extended-regs",
 311                     PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
 312     DEFINE_PROP_END_OF_LIST(),
 313 };
 314
 315 static Property secondary_pci_properties[] = {
 316     DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
 317     DEFINE_PROP_BIT("qemu-extended-regs",
 318                     PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
 319     DEFINE_PROP_END_OF_LIST(),
 320 };
 321
 322 static void vga_pci_class_init(ObjectClass *klass, void *data)
 323 {
 324     DeviceClass *dc = DEVICE_CLASS(klass);
 325     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 326
 327     k->vendor_id = PCI_VENDOR_ID_QEMU;
 328     k->device_id = PCI_DEVICE_ID_QEMU_VGA;
 329     dc->vmsd = &vmstate_vga_pci;
 330     set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
 331 }
 332
 333 static const TypeInfo vga_pci_type_info = {
 334     .name = TYPE_PCI_VGA,
 335     .parent = TYPE_PCI_DEVICE,
 336     .instance_size = sizeof(PCIVGAState),
 337     .abstract = true,
 338     .class_init = vga_pci_class_init,
 339 };
 340
 341 static void vga_class_init(ObjectClass *klass, void *data)
 342 {
 343     DeviceClass *dc = DEVICE_CLASS(klass);
 344     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 345
 346     k->realize = pci_std_vga_realize;
 347     k->romfile = "vgabios-stdvga.bin";
 348     k->class_id = PCI_CLASS_DISPLAY_VGA;
 349     dc->props = vga_pci_properties;
 350     dc->hotpluggable = false;
 351 }
 352
 353 static void secondary_class_init(ObjectClass *klass, void *data)
 354 {
 355     DeviceClass *dc = DEVICE_CLASS(klass);
 356     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 357
 358     k->realize = pci_secondary_vga_realize;
 359     k->class_id = PCI_CLASS_DISPLAY_OTHER;
 360     dc->props = secondary_pci_properties;
 361     dc->reset = pci_secondary_vga_reset;
 362 }
 363
 364 static const TypeInfo vga_info = {
 365     .name          = "VGA",
 366     .parent        = TYPE_PCI_VGA,
 367     .instance_init = pci_std_vga_init,
 368     .class_init    = vga_class_init,
 369 };
 370
 371 static const TypeInfo secondary_info = {
 372     .name          = "secondary-vga",
 373     .parent        = TYPE_PCI_VGA,
 374     .instance_init = pci_secondary_vga_init,
 375     .class_init    = secondary_class_init,
 376 };
 377
 378 static void vga_register_types(void)
 379 {
 380     type_register_static(&vga_pci_type_info);
 381     type_register_static(&vga_info);
 382     type_register_static(&secondary_info);
 383 }
 384
 385 type_init(vga_register_types)