hw/display/virtio-gpu-virgl.c

   1 /*
   2  * Virtio GPU Device
   3  *
   4  * Copyright Red Hat, Inc. 2013-2014
   5  *
   6  * Authors:
   7  *     Dave Airlie <airlied@redhat.com>
   8  *     Gerd Hoffmann <kraxel@redhat.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "qemu/error-report.h"
  16 #include "qemu/iov.h"
  17 #include "trace.h"
  18 #include "hw/virtio/virtio.h"
  19 #include "hw/virtio/virtio-gpu.h"
  20
  21 #include "ui/egl-helpers.h"
  22
  23 #include <virglrenderer.h>
  24
  25 #if VIRGL_RENDERER_CALLBACKS_VERSION >= 4
  26 static void *
  27 virgl_get_egl_display(G_GNUC_UNUSED void *cookie)
  28 {
  29     return qemu_egl_display;
  30 }
  31 #endif
  32
  33 static void virgl_cmd_create_resource_2d(VirtIOGPU *g,
  34                                          struct virtio_gpu_ctrl_command *cmd)
  35 {
  36     struct virtio_gpu_resource_create_2d c2d;
  37     struct virgl_renderer_resource_create_args args;
  38
  39     VIRTIO_GPU_FILL_CMD(c2d);
  40     trace_virtio_gpu_cmd_res_create_2d(c2d.resource_id, c2d.format,
  41                                        c2d.width, c2d.height);
  42
  43     args.handle = c2d.resource_id;
  44     args.target = 2;
  45     args.format = c2d.format;
  46     args.bind = (1 << 1);
  47     args.width = c2d.width;
  48     args.height = c2d.height;
  49     args.depth = 1;
  50     args.array_size = 1;
  51     args.last_level = 0;
  52     args.nr_samples = 0;
  53     args.flags = VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP;
  54     virgl_renderer_resource_create(&args, NULL, 0);
  55 }
  56
  57 static void virgl_cmd_create_resource_3d(VirtIOGPU *g,
  58                                          struct virtio_gpu_ctrl_command *cmd)
  59 {
  60     struct virtio_gpu_resource_create_3d c3d;
  61     struct virgl_renderer_resource_create_args args;
  62
  63     VIRTIO_GPU_FILL_CMD(c3d);
  64     trace_virtio_gpu_cmd_res_create_3d(c3d.resource_id, c3d.format,
  65                                        c3d.width, c3d.height, c3d.depth);
  66
  67     args.handle = c3d.resource_id;
  68     args.target = c3d.target;
  69     args.format = c3d.format;
  70     args.bind = c3d.bind;
  71     args.width = c3d.width;
  72     args.height = c3d.height;
  73     args.depth = c3d.depth;
  74     args.array_size = c3d.array_size;
  75     args.last_level = c3d.last_level;
  76     args.nr_samples = c3d.nr_samples;
  77     args.flags = c3d.flags;
  78     virgl_renderer_resource_create(&args, NULL, 0);
  79 }
  80
  81 static void virgl_cmd_resource_unref(VirtIOGPU *g,
  82                                      struct virtio_gpu_ctrl_command *cmd)
  83 {
  84     struct virtio_gpu_resource_unref unref;
  85     struct iovec *res_iovs = NULL;
  86     int num_iovs = 0;
  87
  88     VIRTIO_GPU_FILL_CMD(unref);
  89     trace_virtio_gpu_cmd_res_unref(unref.resource_id);
  90
  91     virgl_renderer_resource_detach_iov(unref.resource_id,
  92                                        &res_iovs,
  93                                        &num_iovs);
  94     if (res_iovs != NULL && num_iovs != 0) {
  95         virtio_gpu_cleanup_mapping_iov(g, res_iovs, num_iovs);
  96     }
  97     virgl_renderer_resource_unref(unref.resource_id);
  98 }
  99
 100 static void virgl_cmd_context_create(VirtIOGPU *g,
 101                                      struct virtio_gpu_ctrl_command *cmd)
 102 {
 103     struct virtio_gpu_ctx_create cc;
 104
 105     VIRTIO_GPU_FILL_CMD(cc);
 106     trace_virtio_gpu_cmd_ctx_create(cc.hdr.ctx_id,
 107                                     cc.debug_name);
 108
 109     virgl_renderer_context_create(cc.hdr.ctx_id, cc.nlen,
 110                                   cc.debug_name);
 111 }
 112
 113 static void virgl_cmd_context_destroy(VirtIOGPU *g,
 114                                       struct virtio_gpu_ctrl_command *cmd)
 115 {
 116     struct virtio_gpu_ctx_destroy cd;
 117
 118     VIRTIO_GPU_FILL_CMD(cd);
 119     trace_virtio_gpu_cmd_ctx_destroy(cd.hdr.ctx_id);
 120
 121     virgl_renderer_context_destroy(cd.hdr.ctx_id);
 122 }
 123
 124 static void virtio_gpu_rect_update(VirtIOGPU *g, int idx, int x, int y,
 125                                 int width, int height)
 126 {
 127     if (!g->parent_obj.scanout[idx].con) {
 128         return;
 129     }
 130
 131     dpy_gl_update(g->parent_obj.scanout[idx].con, x, y, width, height);
 132 }
 133
 134 static void virgl_cmd_resource_flush(VirtIOGPU *g,
 135                                      struct virtio_gpu_ctrl_command *cmd)
 136 {
 137     struct virtio_gpu_resource_flush rf;
 138     int i;
 139
 140     VIRTIO_GPU_FILL_CMD(rf);
 141     trace_virtio_gpu_cmd_res_flush(rf.resource_id,
 142                                    rf.r.width, rf.r.height, rf.r.x, rf.r.y);
 143
 144     for (i = 0; i < g->parent_obj.conf.max_outputs; i++) {
 145         if (g->parent_obj.scanout[i].resource_id != rf.resource_id) {
 146             continue;
 147         }
 148         virtio_gpu_rect_update(g, i, rf.r.x, rf.r.y, rf.r.width, rf.r.height);
 149     }
 150 }
 151
 152 static void virgl_cmd_set_scanout(VirtIOGPU *g,
 153                                   struct virtio_gpu_ctrl_command *cmd)
 154 {
 155     struct virtio_gpu_set_scanout ss;
 156     struct virgl_renderer_resource_info info;
 157     int ret;
 158
 159     VIRTIO_GPU_FILL_CMD(ss);
 160     trace_virtio_gpu_cmd_set_scanout(ss.scanout_id, ss.resource_id,
 161                                      ss.r.width, ss.r.height, ss.r.x, ss.r.y);
 162
 163     if (ss.scanout_id >= g->parent_obj.conf.max_outputs) {
 164         qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal scanout id specified %d",
 165                       __func__, ss.scanout_id);
 166         cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID;
 167         return;
 168     }
 169     g->parent_obj.enable = 1;
 170
 171     memset(&info, 0, sizeof(info));
 172
 173     if (ss.resource_id && ss.r.width && ss.r.height) {
 174         ret = virgl_renderer_resource_get_info(ss.resource_id, &info);
 175         if (ret == -1) {
 176             qemu_log_mask(LOG_GUEST_ERROR,
 177                           "%s: illegal resource specified %d\n",
 178                           __func__, ss.resource_id);
 179             cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
 180             return;
 181         }
 182         qemu_console_resize(g->parent_obj.scanout[ss.scanout_id].con,
 183                             ss.r.width, ss.r.height);
 184         virgl_renderer_force_ctx_0();
 185         dpy_gl_scanout_texture(
 186             g->parent_obj.scanout[ss.scanout_id].con, info.tex_id,
 187             info.flags & VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP,
 188             info.width, info.height,
 189             ss.r.x, ss.r.y, ss.r.width, ss.r.height);
 190     } else {
 191         dpy_gfx_replace_surface(
 192             g->parent_obj.scanout[ss.scanout_id].con, NULL);
 193         dpy_gl_scanout_disable(g->parent_obj.scanout[ss.scanout_id].con);
 194     }
 195     g->parent_obj.scanout[ss.scanout_id].resource_id = ss.resource_id;
 196 }
 197
 198 static void virgl_cmd_submit_3d(VirtIOGPU *g,
 199                                 struct virtio_gpu_ctrl_command *cmd)
 200 {
 201     struct virtio_gpu_cmd_submit cs;
 202     void *buf;
 203     size_t s;
 204
 205     VIRTIO_GPU_FILL_CMD(cs);
 206     trace_virtio_gpu_cmd_ctx_submit(cs.hdr.ctx_id, cs.size);
 207
 208     buf = g_malloc(cs.size);
 209     s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num,
 210                    sizeof(cs), buf, cs.size);
 211     if (s != cs.size) {
 212         qemu_log_mask(LOG_GUEST_ERROR, "%s: size mismatch (%zd/%d)",
 213                       __func__, s, cs.size);
 214         cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
 215         goto out;
 216     }
 217
 218     if (virtio_gpu_stats_enabled(g->parent_obj.conf)) {
 219         g->stats.req_3d++;
 220         g->stats.bytes_3d += cs.size;
 221     }
 222
 223     virgl_renderer_submit_cmd(buf, cs.hdr.ctx_id, cs.size / 4);
 224
 225 out:
 226     g_free(buf);
 227 }
 228
 229 static void virgl_cmd_transfer_to_host_2d(VirtIOGPU *g,
 230                                           struct virtio_gpu_ctrl_command *cmd)
 231 {
 232     struct virtio_gpu_transfer_to_host_2d t2d;
 233     struct virtio_gpu_box box;
 234
 235     VIRTIO_GPU_FILL_CMD(t2d);
 236     trace_virtio_gpu_cmd_res_xfer_toh_2d(t2d.resource_id);
 237
 238     box.x = t2d.r.x;
 239     box.y = t2d.r.y;
 240     box.z = 0;
 241     box.w = t2d.r.width;
 242     box.h = t2d.r.height;
 243     box.d = 1;
 244
 245     virgl_renderer_transfer_write_iov(t2d.resource_id,
 246                                       0,
 247                                       0,
 248                                       0,
 249                                       0,
 250                                       (struct virgl_box *)&box,
 251                                       t2d.offset, NULL, 0);
 252 }
 253
 254 static void virgl_cmd_transfer_to_host_3d(VirtIOGPU *g,
 255                                           struct virtio_gpu_ctrl_command *cmd)
 256 {
 257     struct virtio_gpu_transfer_host_3d t3d;
 258
 259     VIRTIO_GPU_FILL_CMD(t3d);
 260     trace_virtio_gpu_cmd_res_xfer_toh_3d(t3d.resource_id);
 261
 262     virgl_renderer_transfer_write_iov(t3d.resource_id,
 263                                       t3d.hdr.ctx_id,
 264                                       t3d.level,
 265                                       t3d.stride,
 266                                       t3d.layer_stride,
 267                                       (struct virgl_box *)&t3d.box,
 268                                       t3d.offset, NULL, 0);
 269 }
 270
 271 static void
 272 virgl_cmd_transfer_from_host_3d(VirtIOGPU *g,
 273                                 struct virtio_gpu_ctrl_command *cmd)
 274 {
 275     struct virtio_gpu_transfer_host_3d tf3d;
 276
 277     VIRTIO_GPU_FILL_CMD(tf3d);
 278     trace_virtio_gpu_cmd_res_xfer_fromh_3d(tf3d.resource_id);
 279
 280     virgl_renderer_transfer_read_iov(tf3d.resource_id,
 281                                      tf3d.hdr.ctx_id,
 282                                      tf3d.level,
 283                                      tf3d.stride,
 284                                      tf3d.layer_stride,
 285                                      (struct virgl_box *)&tf3d.box,
 286                                      tf3d.offset, NULL, 0);
 287 }
 288
 289
 290 static void virgl_resource_attach_backing(VirtIOGPU *g,
 291                                           struct virtio_gpu_ctrl_command *cmd)
 292 {
 293     struct virtio_gpu_resource_attach_backing att_rb;
 294     struct iovec *res_iovs;
 295     uint32_t res_niov;
 296     int ret;
 297
 298     VIRTIO_GPU_FILL_CMD(att_rb);
 299     trace_virtio_gpu_cmd_res_back_attach(att_rb.resource_id);
 300
 301     ret = virtio_gpu_create_mapping_iov(g, att_rb.nr_entries, sizeof(att_rb),
 302                                         cmd, NULL, &res_iovs, &res_niov);
 303     if (ret != 0) {
 304         cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
 305         return;
 306     }
 307
 308     ret = virgl_renderer_resource_attach_iov(att_rb.resource_id,
 309                                              res_iovs, res_niov);
 310
 311     if (ret != 0)
 312         virtio_gpu_cleanup_mapping_iov(g, res_iovs, res_niov);
 313 }
 314
 315 static void virgl_resource_detach_backing(VirtIOGPU *g,
 316                                           struct virtio_gpu_ctrl_command *cmd)
 317 {
 318     struct virtio_gpu_resource_detach_backing detach_rb;
 319     struct iovec *res_iovs = NULL;
 320     int num_iovs = 0;
 321
 322     VIRTIO_GPU_FILL_CMD(detach_rb);
 323     trace_virtio_gpu_cmd_res_back_detach(detach_rb.resource_id);
 324
 325     virgl_renderer_resource_detach_iov(detach_rb.resource_id,
 326                                        &res_iovs,
 327                                        &num_iovs);
 328     if (res_iovs == NULL || num_iovs == 0) {
 329         return;
 330     }
 331     virtio_gpu_cleanup_mapping_iov(g, res_iovs, num_iovs);
 332 }
 333
 334
 335 static void virgl_cmd_ctx_attach_resource(VirtIOGPU *g,
 336                                           struct virtio_gpu_ctrl_command *cmd)
 337 {
 338     struct virtio_gpu_ctx_resource att_res;
 339
 340     VIRTIO_GPU_FILL_CMD(att_res);
 341     trace_virtio_gpu_cmd_ctx_res_attach(att_res.hdr.ctx_id,
 342                                         att_res.resource_id);
 343
 344     virgl_renderer_ctx_attach_resource(att_res.hdr.ctx_id, att_res.resource_id);
 345 }
 346
 347 static void virgl_cmd_ctx_detach_resource(VirtIOGPU *g,
 348                                           struct virtio_gpu_ctrl_command *cmd)
 349 {
 350     struct virtio_gpu_ctx_resource det_res;
 351
 352     VIRTIO_GPU_FILL_CMD(det_res);
 353     trace_virtio_gpu_cmd_ctx_res_detach(det_res.hdr.ctx_id,
 354                                         det_res.resource_id);
 355
 356     virgl_renderer_ctx_detach_resource(det_res.hdr.ctx_id, det_res.resource_id);
 357 }
 358
 359 static void virgl_cmd_get_capset_info(VirtIOGPU *g,
 360                                       struct virtio_gpu_ctrl_command *cmd)
 361 {
 362     struct virtio_gpu_get_capset_info info;
 363     struct virtio_gpu_resp_capset_info resp;
 364
 365     VIRTIO_GPU_FILL_CMD(info);
 366
 367     memset(&resp, 0, sizeof(resp));
 368     if (info.capset_index == 0) {
 369         resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL;
 370         virgl_renderer_get_cap_set(resp.capset_id,
 371                                    &resp.capset_max_version,
 372                                    &resp.capset_max_size);
 373     } else if (info.capset_index == 1) {
 374         resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL2;
 375         virgl_renderer_get_cap_set(resp.capset_id,
 376                                    &resp.capset_max_version,
 377                                    &resp.capset_max_size);
 378     } else {
 379         resp.capset_max_version = 0;
 380         resp.capset_max_size = 0;
 381     }
 382     resp.hdr.type = VIRTIO_GPU_RESP_OK_CAPSET_INFO;
 383     virtio_gpu_ctrl_response(g, cmd, &resp.hdr, sizeof(resp));
 384 }
 385
 386 static void virgl_cmd_get_capset(VirtIOGPU *g,
 387                                  struct virtio_gpu_ctrl_command *cmd)
 388 {
 389     struct virtio_gpu_get_capset gc;
 390     struct virtio_gpu_resp_capset *resp;
 391     uint32_t max_ver, max_size;
 392     VIRTIO_GPU_FILL_CMD(gc);
 393
 394     virgl_renderer_get_cap_set(gc.capset_id, &max_ver,
 395                                &max_size);
 396     if (!max_size) {
 397         cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
 398         return;
 399     }
 400
 401     resp = g_malloc0(sizeof(*resp) + max_size);
 402     resp->hdr.type = VIRTIO_GPU_RESP_OK_CAPSET;
 403     virgl_renderer_fill_caps(gc.capset_id,
 404                              gc.capset_version,
 405                              (void *)resp->capset_data);
 406     virtio_gpu_ctrl_response(g, cmd, &resp->hdr, sizeof(*resp) + max_size);
 407     g_free(resp);
 408 }
 409
 410 void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
 411                                       struct virtio_gpu_ctrl_command *cmd)
 412 {
 413     VIRTIO_GPU_FILL_CMD(cmd->cmd_hdr);
 414
 415     virgl_renderer_force_ctx_0();
 416     switch (cmd->cmd_hdr.type) {
 417     case VIRTIO_GPU_CMD_CTX_CREATE:
 418         virgl_cmd_context_create(g, cmd);
 419         break;
 420     case VIRTIO_GPU_CMD_CTX_DESTROY:
 421         virgl_cmd_context_destroy(g, cmd);
 422         break;
 423     case VIRTIO_GPU_CMD_RESOURCE_CREATE_2D:
 424         virgl_cmd_create_resource_2d(g, cmd);
 425         break;
 426     case VIRTIO_GPU_CMD_RESOURCE_CREATE_3D:
 427         virgl_cmd_create_resource_3d(g, cmd);
 428         break;
 429     case VIRTIO_GPU_CMD_SUBMIT_3D:
 430         virgl_cmd_submit_3d(g, cmd);
 431         break;
 432     case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D:
 433         virgl_cmd_transfer_to_host_2d(g, cmd);
 434         break;
 435     case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D:
 436         virgl_cmd_transfer_to_host_3d(g, cmd);
 437         break;
 438     case VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D:
 439         virgl_cmd_transfer_from_host_3d(g, cmd);
 440         break;
 441     case VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING:
 442         virgl_resource_attach_backing(g, cmd);
 443         break;
 444     case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING:
 445         virgl_resource_detach_backing(g, cmd);
 446         break;
 447     case VIRTIO_GPU_CMD_SET_SCANOUT:
 448         virgl_cmd_set_scanout(g, cmd);
 449         break;
 450     case VIRTIO_GPU_CMD_RESOURCE_FLUSH:
 451         virgl_cmd_resource_flush(g, cmd);
 452         break;
 453     case VIRTIO_GPU_CMD_RESOURCE_UNREF:
 454         virgl_cmd_resource_unref(g, cmd);
 455         break;
 456     case VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE:
 457         /* TODO add security */
 458         virgl_cmd_ctx_attach_resource(g, cmd);
 459         break;
 460     case VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE:
 461         /* TODO add security */
 462         virgl_cmd_ctx_detach_resource(g, cmd);
 463         break;
 464     case VIRTIO_GPU_CMD_GET_CAPSET_INFO:
 465         virgl_cmd_get_capset_info(g, cmd);
 466         break;
 467     case VIRTIO_GPU_CMD_GET_CAPSET:
 468         virgl_cmd_get_capset(g, cmd);
 469         break;
 470     case VIRTIO_GPU_CMD_GET_DISPLAY_INFO:
 471         virtio_gpu_get_display_info(g, cmd);
 472         break;
 473     case VIRTIO_GPU_CMD_GET_EDID:
 474         virtio_gpu_get_edid(g, cmd);
 475         break;
 476     default:
 477         cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
 478         break;
 479     }
 480
 481     if (cmd->finished) {
 482         return;
 483     }
 484     if (cmd->error) {
 485         fprintf(stderr, "%s: ctrl 0x%x, error 0x%x\n", __func__,
 486                 cmd->cmd_hdr.type, cmd->error);
 487         virtio_gpu_ctrl_response_nodata(g, cmd, cmd->error);
 488         return;
 489     }
 490     if (!(cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE)) {
 491         virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
 492         return;
 493     }
 494
 495     trace_virtio_gpu_fence_ctrl(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
 496     virgl_renderer_create_fence(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
 497 }
 498
 499 static void virgl_write_fence(void *opaque, uint32_t fence)
 500 {
 501     VirtIOGPU *g = opaque;
 502     struct virtio_gpu_ctrl_command *cmd, *tmp;
 503
 504     QTAILQ_FOREACH_SAFE(cmd, &g->fenceq, next, tmp) {
 505         /*
 506          * the guest can end up emitting fences out of order
 507          * so we should check all fenced cmds not just the first one.
 508          */
 509         if (cmd->cmd_hdr.fence_id > fence) {
 510             continue;
 511         }
 512         trace_virtio_gpu_fence_resp(cmd->cmd_hdr.fence_id);
 513         virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
 514         QTAILQ_REMOVE(&g->fenceq, cmd, next);
 515         g_free(cmd);
 516         g->inflight--;
 517         if (virtio_gpu_stats_enabled(g->parent_obj.conf)) {
 518             fprintf(stderr, "inflight: %3d (-)\r", g->inflight);
 519         }
 520     }
 521 }
 522
 523 static virgl_renderer_gl_context
 524 virgl_create_context(void *opaque, int scanout_idx,
 525                      struct virgl_renderer_gl_ctx_param *params)
 526 {
 527     VirtIOGPU *g = opaque;
 528     QEMUGLContext ctx;
 529     QEMUGLParams qparams;
 530
 531     qparams.major_ver = params->major_ver;
 532     qparams.minor_ver = params->minor_ver;
 533
 534     ctx = dpy_gl_ctx_create(g->parent_obj.scanout[scanout_idx].con, &qparams);
 535     return (virgl_renderer_gl_context)ctx;
 536 }
 537
 538 static void virgl_destroy_context(void *opaque, virgl_renderer_gl_context ctx)
 539 {
 540     VirtIOGPU *g = opaque;
 541     QEMUGLContext qctx = (QEMUGLContext)ctx;
 542
 543     dpy_gl_ctx_destroy(g->parent_obj.scanout[0].con, qctx);
 544 }
 545
 546 static int virgl_make_context_current(void *opaque, int scanout_idx,
 547                                       virgl_renderer_gl_context ctx)
 548 {
 549     VirtIOGPU *g = opaque;
 550     QEMUGLContext qctx = (QEMUGLContext)ctx;
 551
 552     return dpy_gl_ctx_make_current(g->parent_obj.scanout[scanout_idx].con,
 553                                    qctx);
 554 }
 555
 556 static struct virgl_renderer_callbacks virtio_gpu_3d_cbs = {
 557     .version             = 1,
 558     .write_fence         = virgl_write_fence,
 559     .create_gl_context   = virgl_create_context,
 560     .destroy_gl_context  = virgl_destroy_context,
 561     .make_current        = virgl_make_context_current,
 562 };
 563
 564 static void virtio_gpu_print_stats(void *opaque)
 565 {
 566     VirtIOGPU *g = opaque;
 567
 568     if (g->stats.requests) {
 569         fprintf(stderr, "stats: vq req %4d, %3d -- 3D %4d (%5d)\n",
 570                 g->stats.requests,
 571                 g->stats.max_inflight,
 572                 g->stats.req_3d,
 573                 g->stats.bytes_3d);
 574         g->stats.requests     = 0;
 575         g->stats.max_inflight = 0;
 576         g->stats.req_3d       = 0;
 577         g->stats.bytes_3d     = 0;
 578     } else {
 579         fprintf(stderr, "stats: idle\r");
 580     }
 581     timer_mod(g->print_stats, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
 582 }
 583
 584 static void virtio_gpu_fence_poll(void *opaque)
 585 {
 586     VirtIOGPU *g = opaque;
 587
 588     virgl_renderer_poll();
 589     virtio_gpu_process_cmdq(g);
 590     if (!QTAILQ_EMPTY(&g->cmdq) || !QTAILQ_EMPTY(&g->fenceq)) {
 591         timer_mod(g->fence_poll, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 10);
 592     }
 593 }
 594
 595 void virtio_gpu_virgl_fence_poll(VirtIOGPU *g)
 596 {
 597     virtio_gpu_fence_poll(g);
 598 }
 599
 600 void virtio_gpu_virgl_reset_scanout(VirtIOGPU *g)
 601 {
 602     int i;
 603
 604     for (i = 0; i < g->parent_obj.conf.max_outputs; i++) {
 605         dpy_gfx_replace_surface(g->parent_obj.scanout[i].con, NULL);
 606         dpy_gl_scanout_disable(g->parent_obj.scanout[i].con);
 607     }
 608 }
 609
 610 void virtio_gpu_virgl_reset(VirtIOGPU *g)
 611 {
 612     virgl_renderer_reset();
 613 }
 614
 615 int virtio_gpu_virgl_init(VirtIOGPU *g)
 616 {
 617     int ret;
 618
 619 #if VIRGL_RENDERER_CALLBACKS_VERSION >= 4
 620     if (qemu_egl_display) {
 621         virtio_gpu_3d_cbs.version = 4;
 622         virtio_gpu_3d_cbs.get_egl_display = virgl_get_egl_display;
 623     }
 624 #endif
 625
 626     ret = virgl_renderer_init(g, 0, &virtio_gpu_3d_cbs);
 627     if (ret != 0) {
 628         error_report("virgl could not be initialized: %d", ret);
 629         return ret;
 630     }
 631
 632     g->fence_poll = timer_new_ms(QEMU_CLOCK_VIRTUAL,
 633                                  virtio_gpu_fence_poll, g);
 634
 635     if (virtio_gpu_stats_enabled(g->parent_obj.conf)) {
 636         g->print_stats = timer_new_ms(QEMU_CLOCK_VIRTUAL,
 637                                       virtio_gpu_print_stats, g);
 638         timer_mod(g->print_stats, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
 639     }
 640     return 0;
 641 }
 642
 643 int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g)
 644 {
 645     uint32_t capset2_max_ver, capset2_max_size;
 646     virgl_renderer_get_cap_set(VIRTIO_GPU_CAPSET_VIRGL2,
 647                               &capset2_max_ver,
 648                               &capset2_max_size);
 649
 650     return capset2_max_ver ? 2 : 1;
 651 }