hw/display/vmware_vga.c

   1 /*
   2  * QEMU VMware-SVGA "chipset".
   3  *
   4  * Copyright (c) 2007 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw/hw.h"
  25 #include "hw/loader.h"
  26 #include "trace.h"
  27 #include "ui/console.h"
  28 #include "ui/vnc.h"
  29 #include "hw/pci/pci.h"
  30
  31 #undef VERBOSE
  32 #define HW_RECT_ACCEL
  33 #define HW_FILL_ACCEL
  34 #define HW_MOUSE_ACCEL
  35
  36 #include "vga_int.h"
  37
  38 /* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */
  39
  40 struct vmsvga_state_s {
  41     VGACommonState vga;
  42
  43     int invalidated;
  44     int enable;
  45     int config;
  46     struct {
  47         int id;
  48         int x;
  49         int y;
  50         int on;
  51     } cursor;
  52
  53     int index;
  54     int scratch_size;
  55     uint32_t *scratch;
  56     int new_width;
  57     int new_height;
  58     int new_depth;
  59     uint32_t guest;
  60     uint32_t svgaid;
  61     int syncing;
  62
  63     MemoryRegion fifo_ram;
  64     uint8_t *fifo_ptr;
  65     unsigned int fifo_size;
  66
  67     union {
  68         uint32_t *fifo;
  69         struct QEMU_PACKED {
  70             uint32_t min;
  71             uint32_t max;
  72             uint32_t next_cmd;
  73             uint32_t stop;
  74             /* Add registers here when adding capabilities.  */
  75             uint32_t fifo[0];
  76         } *cmd;
  77     };
  78
  79 #define REDRAW_FIFO_LEN  512
  80     struct vmsvga_rect_s {
  81         int x, y, w, h;
  82     } redraw_fifo[REDRAW_FIFO_LEN];
  83     int redraw_fifo_first, redraw_fifo_last;
  84 };
  85
  86 #define TYPE_VMWARE_SVGA "vmware-svga"
  87
  88 #define VMWARE_SVGA(obj) \
  89     OBJECT_CHECK(struct pci_vmsvga_state_s, (obj), TYPE_VMWARE_SVGA)
  90
  91 struct pci_vmsvga_state_s {
  92     /*< private >*/
  93     PCIDevice parent_obj;
  94     /*< public >*/
  95
  96     struct vmsvga_state_s chip;
  97     MemoryRegion io_bar;
  98 };
  99
 100 #define SVGA_MAGIC              0x900000UL
 101 #define SVGA_MAKE_ID(ver)       (SVGA_MAGIC << 8 | (ver))
 102 #define SVGA_ID_0               SVGA_MAKE_ID(0)
 103 #define SVGA_ID_1               SVGA_MAKE_ID(1)
 104 #define SVGA_ID_2               SVGA_MAKE_ID(2)
 105
 106 #define SVGA_LEGACY_BASE_PORT   0x4560
 107 #define SVGA_INDEX_PORT         0x0
 108 #define SVGA_VALUE_PORT         0x1
 109 #define SVGA_BIOS_PORT          0x2
 110
 111 #define SVGA_VERSION_2
 112
 113 #ifdef SVGA_VERSION_2
 114 # define SVGA_ID                SVGA_ID_2
 115 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 116 # define SVGA_IO_MUL            1
 117 # define SVGA_FIFO_SIZE         0x10000
 118 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA2
 119 #else
 120 # define SVGA_ID                SVGA_ID_1
 121 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 122 # define SVGA_IO_MUL            4
 123 # define SVGA_FIFO_SIZE         0x10000
 124 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA
 125 #endif
 126
 127 enum {
 128     /* ID 0, 1 and 2 registers */
 129     SVGA_REG_ID = 0,
 130     SVGA_REG_ENABLE = 1,
 131     SVGA_REG_WIDTH = 2,
 132     SVGA_REG_HEIGHT = 3,
 133     SVGA_REG_MAX_WIDTH = 4,
 134     SVGA_REG_MAX_HEIGHT = 5,
 135     SVGA_REG_DEPTH = 6,
 136     SVGA_REG_BITS_PER_PIXEL = 7,        /* Current bpp in the guest */
 137     SVGA_REG_PSEUDOCOLOR = 8,
 138     SVGA_REG_RED_MASK = 9,
 139     SVGA_REG_GREEN_MASK = 10,
 140     SVGA_REG_BLUE_MASK = 11,
 141     SVGA_REG_BYTES_PER_LINE = 12,
 142     SVGA_REG_FB_START = 13,
 143     SVGA_REG_FB_OFFSET = 14,
 144     SVGA_REG_VRAM_SIZE = 15,
 145     SVGA_REG_FB_SIZE = 16,
 146
 147     /* ID 1 and 2 registers */
 148     SVGA_REG_CAPABILITIES = 17,
 149     SVGA_REG_MEM_START = 18,            /* Memory for command FIFO */
 150     SVGA_REG_MEM_SIZE = 19,
 151     SVGA_REG_CONFIG_DONE = 20,          /* Set when memory area configured */
 152     SVGA_REG_SYNC = 21,                 /* Write to force synchronization */
 153     SVGA_REG_BUSY = 22,                 /* Read to check if sync is done */
 154     SVGA_REG_GUEST_ID = 23,             /* Set guest OS identifier */
 155     SVGA_REG_CURSOR_ID = 24,            /* ID of cursor */
 156     SVGA_REG_CURSOR_X = 25,             /* Set cursor X position */
 157     SVGA_REG_CURSOR_Y = 26,             /* Set cursor Y position */
 158     SVGA_REG_CURSOR_ON = 27,            /* Turn cursor on/off */
 159     SVGA_REG_HOST_BITS_PER_PIXEL = 28,  /* Current bpp in the host */
 160     SVGA_REG_SCRATCH_SIZE = 29,         /* Number of scratch registers */
 161     SVGA_REG_MEM_REGS = 30,             /* Number of FIFO registers */
 162     SVGA_REG_NUM_DISPLAYS = 31,         /* Number of guest displays */
 163     SVGA_REG_PITCHLOCK = 32,            /* Fixed pitch for all modes */
 164
 165     SVGA_PALETTE_BASE = 1024,           /* Base of SVGA color map */
 166     SVGA_PALETTE_END  = SVGA_PALETTE_BASE + 767,
 167     SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
 168 };
 169
 170 #define SVGA_CAP_NONE                   0
 171 #define SVGA_CAP_RECT_FILL              (1 << 0)
 172 #define SVGA_CAP_RECT_COPY              (1 << 1)
 173 #define SVGA_CAP_RECT_PAT_FILL          (1 << 2)
 174 #define SVGA_CAP_LEGACY_OFFSCREEN       (1 << 3)
 175 #define SVGA_CAP_RASTER_OP              (1 << 4)
 176 #define SVGA_CAP_CURSOR                 (1 << 5)
 177 #define SVGA_CAP_CURSOR_BYPASS          (1 << 6)
 178 #define SVGA_CAP_CURSOR_BYPASS_2        (1 << 7)
 179 #define SVGA_CAP_8BIT_EMULATION         (1 << 8)
 180 #define SVGA_CAP_ALPHA_CURSOR           (1 << 9)
 181 #define SVGA_CAP_GLYPH                  (1 << 10)
 182 #define SVGA_CAP_GLYPH_CLIPPING         (1 << 11)
 183 #define SVGA_CAP_OFFSCREEN_1            (1 << 12)
 184 #define SVGA_CAP_ALPHA_BLEND            (1 << 13)
 185 #define SVGA_CAP_3D                     (1 << 14)
 186 #define SVGA_CAP_EXTENDED_FIFO          (1 << 15)
 187 #define SVGA_CAP_MULTIMON               (1 << 16)
 188 #define SVGA_CAP_PITCHLOCK              (1 << 17)
 189
 190 /*
 191  * FIFO offsets (seen as an array of 32-bit words)
 192  */
 193 enum {
 194     /*
 195      * The original defined FIFO offsets
 196      */
 197     SVGA_FIFO_MIN = 0,
 198     SVGA_FIFO_MAX,      /* The distance from MIN to MAX must be at least 10K */
 199     SVGA_FIFO_NEXT_CMD,
 200     SVGA_FIFO_STOP,
 201
 202     /*
 203      * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
 204      */
 205     SVGA_FIFO_CAPABILITIES = 4,
 206     SVGA_FIFO_FLAGS,
 207     SVGA_FIFO_FENCE,
 208     SVGA_FIFO_3D_HWVERSION,
 209     SVGA_FIFO_PITCHLOCK,
 210 };
 211
 212 #define SVGA_FIFO_CAP_NONE              0
 213 #define SVGA_FIFO_CAP_FENCE             (1 << 0)
 214 #define SVGA_FIFO_CAP_ACCELFRONT        (1 << 1)
 215 #define SVGA_FIFO_CAP_PITCHLOCK         (1 << 2)
 216
 217 #define SVGA_FIFO_FLAG_NONE             0
 218 #define SVGA_FIFO_FLAG_ACCELFRONT       (1 << 0)
 219
 220 /* These values can probably be changed arbitrarily.  */
 221 #define SVGA_SCRATCH_SIZE               0x8000
 222 #define SVGA_MAX_WIDTH                  ROUND_UP(2360, VNC_DIRTY_PIXELS_PER_BIT)
 223 #define SVGA_MAX_HEIGHT                 1770
 224
 225 #ifdef VERBOSE
 226 # define GUEST_OS_BASE          0x5001
 227 static const char *vmsvga_guest_id[] = {
 228     [0x00] = "Dos",
 229     [0x01] = "Windows 3.1",
 230     [0x02] = "Windows 95",
 231     [0x03] = "Windows 98",
 232     [0x04] = "Windows ME",
 233     [0x05] = "Windows NT",
 234     [0x06] = "Windows 2000",
 235     [0x07] = "Linux",
 236     [0x08] = "OS/2",
 237     [0x09] = "an unknown OS",
 238     [0x0a] = "BSD",
 239     [0x0b] = "Whistler",
 240     [0x0c] = "an unknown OS",
 241     [0x0d] = "an unknown OS",
 242     [0x0e] = "an unknown OS",
 243     [0x0f] = "an unknown OS",
 244     [0x10] = "an unknown OS",
 245     [0x11] = "an unknown OS",
 246     [0x12] = "an unknown OS",
 247     [0x13] = "an unknown OS",
 248     [0x14] = "an unknown OS",
 249     [0x15] = "Windows 2003",
 250 };
 251 #endif
 252
 253 enum {
 254     SVGA_CMD_INVALID_CMD = 0,
 255     SVGA_CMD_UPDATE = 1,
 256     SVGA_CMD_RECT_FILL = 2,
 257     SVGA_CMD_RECT_COPY = 3,
 258     SVGA_CMD_DEFINE_BITMAP = 4,
 259     SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
 260     SVGA_CMD_DEFINE_PIXMAP = 6,
 261     SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
 262     SVGA_CMD_RECT_BITMAP_FILL = 8,
 263     SVGA_CMD_RECT_PIXMAP_FILL = 9,
 264     SVGA_CMD_RECT_BITMAP_COPY = 10,
 265     SVGA_CMD_RECT_PIXMAP_COPY = 11,
 266     SVGA_CMD_FREE_OBJECT = 12,
 267     SVGA_CMD_RECT_ROP_FILL = 13,
 268     SVGA_CMD_RECT_ROP_COPY = 14,
 269     SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
 270     SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
 271     SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
 272     SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
 273     SVGA_CMD_DEFINE_CURSOR = 19,
 274     SVGA_CMD_DISPLAY_CURSOR = 20,
 275     SVGA_CMD_MOVE_CURSOR = 21,
 276     SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
 277     SVGA_CMD_DRAW_GLYPH = 23,
 278     SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
 279     SVGA_CMD_UPDATE_VERBOSE = 25,
 280     SVGA_CMD_SURFACE_FILL = 26,
 281     SVGA_CMD_SURFACE_COPY = 27,
 282     SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
 283     SVGA_CMD_FRONT_ROP_FILL = 29,
 284     SVGA_CMD_FENCE = 30,
 285 };
 286
 287 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
 288 enum {
 289     SVGA_CURSOR_ON_HIDE = 0,
 290     SVGA_CURSOR_ON_SHOW = 1,
 291     SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
 292     SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
 293 };
 294
 295 static inline bool vmsvga_verify_rect(DisplaySurface *surface,
 296                                       const char *name,
 297                                       int x, int y, int w, int h)
 298 {
 299     if (x < 0) {
 300         fprintf(stderr, "%s: x was < 0 (%d)\n", name, x);
 301         return false;
 302     }
 303     if (x > SVGA_MAX_WIDTH) {
 304         fprintf(stderr, "%s: x was > %d (%d)\n", name, SVGA_MAX_WIDTH, x);
 305         return false;
 306     }
 307     if (w < 0) {
 308         fprintf(stderr, "%s: w was < 0 (%d)\n", name, w);
 309         return false;
 310     }
 311     if (w > SVGA_MAX_WIDTH) {
 312         fprintf(stderr, "%s: w was > %d (%d)\n", name, SVGA_MAX_WIDTH, w);
 313         return false;
 314     }
 315     if (x + w > surface_width(surface)) {
 316         fprintf(stderr, "%s: width was > %d (x: %d, w: %d)\n",
 317                 name, surface_width(surface), x, w);
 318         return false;
 319     }
 320
 321     if (y < 0) {
 322         fprintf(stderr, "%s: y was < 0 (%d)\n", name, y);
 323         return false;
 324     }
 325     if (y > SVGA_MAX_HEIGHT) {
 326         fprintf(stderr, "%s: y was > %d (%d)\n", name, SVGA_MAX_HEIGHT, y);
 327         return false;
 328     }
 329     if (h < 0) {
 330         fprintf(stderr, "%s: h was < 0 (%d)\n", name, h);
 331         return false;
 332     }
 333     if (h > SVGA_MAX_HEIGHT) {
 334         fprintf(stderr, "%s: h was > %d (%d)\n", name, SVGA_MAX_HEIGHT, h);
 335         return false;
 336     }
 337     if (y + h > surface_height(surface)) {
 338         fprintf(stderr, "%s: update height > %d (y: %d, h: %d)\n",
 339                 name, surface_height(surface), y, h);
 340         return false;
 341     }
 342
 343     return true;
 344 }
 345
 346 static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
 347                                       int x, int y, int w, int h)
 348 {
 349     DisplaySurface *surface = qemu_console_surface(s->vga.con);
 350     int line;
 351     int bypl;
 352     int width;
 353     int start;
 354     uint8_t *src;
 355     uint8_t *dst;
 356
 357     if (!vmsvga_verify_rect(surface, __func__, x, y, w, h)) {
 358         /* go for a fullscreen update as fallback */
 359         x = 0;
 360         y = 0;
 361         w = surface_width(surface);
 362         h = surface_height(surface);
 363     }
 364
 365     bypl = surface_stride(surface);
 366     width = surface_bytes_per_pixel(surface) * w;
 367     start = surface_bytes_per_pixel(surface) * x + bypl * y;
 368     src = s->vga.vram_ptr + start;
 369     dst = surface_data(surface) + start;
 370
 371     for (line = h; line > 0; line--, src += bypl, dst += bypl) {
 372         memcpy(dst, src, width);
 373     }
 374     dpy_gfx_update(s->vga.con, x, y, w, h);
 375 }
 376
 377 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
 378                 int x, int y, int w, int h)
 379 {
 380     struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++];
 381
 382     s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
 383     rect->x = x;
 384     rect->y = y;
 385     rect->w = w;
 386     rect->h = h;
 387 }
 388
 389 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
 390 {
 391     struct vmsvga_rect_s *rect;
 392
 393     if (s->invalidated) {
 394         s->redraw_fifo_first = s->redraw_fifo_last;
 395         return;
 396     }
 397     /* Overlapping region updates can be optimised out here - if someone
 398      * knows a smart algorithm to do that, please share.  */
 399     while (s->redraw_fifo_first != s->redraw_fifo_last) {
 400         rect = &s->redraw_fifo[s->redraw_fifo_first++];
 401         s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
 402         vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
 403     }
 404 }
 405
 406 #ifdef HW_RECT_ACCEL
 407 static inline int vmsvga_copy_rect(struct vmsvga_state_s *s,
 408                 int x0, int y0, int x1, int y1, int w, int h)
 409 {
 410     DisplaySurface *surface = qemu_console_surface(s->vga.con);
 411     uint8_t *vram = s->vga.vram_ptr;
 412     int bypl = surface_stride(surface);
 413     int bypp = surface_bytes_per_pixel(surface);
 414     int width = bypp * w;
 415     int line = h;
 416     uint8_t *ptr[2];
 417
 418     if (!vmsvga_verify_rect(surface, "vmsvga_copy_rect/src", x0, y0, w, h)) {
 419         return -1;
 420     }
 421     if (!vmsvga_verify_rect(surface, "vmsvga_copy_rect/dst", x1, y1, w, h)) {
 422         return -1;
 423     }
 424
 425     if (y1 > y0) {
 426         ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1);
 427         ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1);
 428         for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) {
 429             memmove(ptr[1], ptr[0], width);
 430         }
 431     } else {
 432         ptr[0] = vram + bypp * x0 + bypl * y0;
 433         ptr[1] = vram + bypp * x1 + bypl * y1;
 434         for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) {
 435             memmove(ptr[1], ptr[0], width);
 436         }
 437     }
 438
 439     vmsvga_update_rect_delayed(s, x1, y1, w, h);
 440     return 0;
 441 }
 442 #endif
 443
 444 #ifdef HW_FILL_ACCEL
 445 static inline int vmsvga_fill_rect(struct vmsvga_state_s *s,
 446                 uint32_t c, int x, int y, int w, int h)
 447 {
 448     DisplaySurface *surface = qemu_console_surface(s->vga.con);
 449     int bypl = surface_stride(surface);
 450     int width = surface_bytes_per_pixel(surface) * w;
 451     int line = h;
 452     int column;
 453     uint8_t *fst;
 454     uint8_t *dst;
 455     uint8_t *src;
 456     uint8_t col[4];
 457
 458     if (!vmsvga_verify_rect(surface, __func__, x, y, w, h)) {
 459         return -1;
 460     }
 461
 462     col[0] = c;
 463     col[1] = c >> 8;
 464     col[2] = c >> 16;
 465     col[3] = c >> 24;
 466
 467     fst = s->vga.vram_ptr + surface_bytes_per_pixel(surface) * x + bypl * y;
 468
 469     if (line--) {
 470         dst = fst;
 471         src = col;
 472         for (column = width; column > 0; column--) {
 473             *(dst++) = *(src++);
 474             if (src - col == surface_bytes_per_pixel(surface)) {
 475                 src = col;
 476             }
 477         }
 478         dst = fst;
 479         for (; line > 0; line--) {
 480             dst += bypl;
 481             memcpy(dst, fst, width);
 482         }
 483     }
 484
 485     vmsvga_update_rect_delayed(s, x, y, w, h);
 486     return 0;
 487 }
 488 #endif
 489
 490 struct vmsvga_cursor_definition_s {
 491     int width;
 492     int height;
 493     int id;
 494     int bpp;
 495     int hot_x;
 496     int hot_y;
 497     uint32_t mask[1024];
 498     uint32_t image[4096];
 499 };
 500
 501 #define SVGA_BITMAP_SIZE(w, h)          ((((w) + 31) >> 5) * (h))
 502 #define SVGA_PIXMAP_SIZE(w, h, bpp)     (((((w) * (bpp)) + 31) >> 5) * (h))
 503
 504 #ifdef HW_MOUSE_ACCEL
 505 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
 506                 struct vmsvga_cursor_definition_s *c)
 507 {
 508     QEMUCursor *qc;
 509     int i, pixels;
 510
 511     qc = cursor_alloc(c->width, c->height);
 512     qc->hot_x = c->hot_x;
 513     qc->hot_y = c->hot_y;
 514     switch (c->bpp) {
 515     case 1:
 516         cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image,
 517                         1, (void *)c->mask);
 518 #ifdef DEBUG
 519         cursor_print_ascii_art(qc, "vmware/mono");
 520 #endif
 521         break;
 522     case 32:
 523         /* fill alpha channel from mask, set color to zero */
 524         cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask,
 525                         1, (void *)c->mask);
 526         /* add in rgb values */
 527         pixels = c->width * c->height;
 528         for (i = 0; i < pixels; i++) {
 529             qc->data[i] |= c->image[i] & 0xffffff;
 530         }
 531 #ifdef DEBUG
 532         cursor_print_ascii_art(qc, "vmware/32bit");
 533 #endif
 534         break;
 535     default:
 536         fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
 537                 __func__, c->bpp);
 538         cursor_put(qc);
 539         qc = cursor_builtin_left_ptr();
 540     }
 541
 542     dpy_cursor_define(s->vga.con, qc);
 543     cursor_put(qc);
 544 }
 545 #endif
 546
 547 #define CMD(f)  le32_to_cpu(s->cmd->f)
 548
 549 static inline int vmsvga_fifo_length(struct vmsvga_state_s *s)
 550 {
 551     int num;
 552
 553     if (!s->config || !s->enable) {
 554         return 0;
 555     }
 556     num = CMD(next_cmd) - CMD(stop);
 557     if (num < 0) {
 558         num += CMD(max) - CMD(min);
 559     }
 560     return num >> 2;
 561 }
 562
 563 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
 564 {
 565     uint32_t cmd = s->fifo[CMD(stop) >> 2];
 566
 567     s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
 568     if (CMD(stop) >= CMD(max)) {
 569         s->cmd->stop = s->cmd->min;
 570     }
 571     return cmd;
 572 }
 573
 574 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
 575 {
 576     return le32_to_cpu(vmsvga_fifo_read_raw(s));
 577 }
 578
 579 static void vmsvga_fifo_run(struct vmsvga_state_s *s)
 580 {
 581     uint32_t cmd, colour;
 582     int args, len;
 583     int x, y, dx, dy, width, height;
 584     struct vmsvga_cursor_definition_s cursor;
 585     uint32_t cmd_start;
 586
 587     len = vmsvga_fifo_length(s);
 588     while (len > 0) {
 589         /* May need to go back to the start of the command if incomplete */
 590         cmd_start = s->cmd->stop;
 591
 592         switch (cmd = vmsvga_fifo_read(s)) {
 593         case SVGA_CMD_UPDATE:
 594         case SVGA_CMD_UPDATE_VERBOSE:
 595             len -= 5;
 596             if (len < 0) {
 597                 goto rewind;
 598             }
 599
 600             x = vmsvga_fifo_read(s);
 601             y = vmsvga_fifo_read(s);
 602             width = vmsvga_fifo_read(s);
 603             height = vmsvga_fifo_read(s);
 604             vmsvga_update_rect_delayed(s, x, y, width, height);
 605             break;
 606
 607         case SVGA_CMD_RECT_FILL:
 608             len -= 6;
 609             if (len < 0) {
 610                 goto rewind;
 611             }
 612
 613             colour = vmsvga_fifo_read(s);
 614             x = vmsvga_fifo_read(s);
 615             y = vmsvga_fifo_read(s);
 616             width = vmsvga_fifo_read(s);
 617             height = vmsvga_fifo_read(s);
 618 #ifdef HW_FILL_ACCEL
 619             if (vmsvga_fill_rect(s, colour, x, y, width, height) == 0) {
 620                 break;
 621             }
 622 #endif
 623             args = 0;
 624             goto badcmd;
 625
 626         case SVGA_CMD_RECT_COPY:
 627             len -= 7;
 628             if (len < 0) {
 629                 goto rewind;
 630             }
 631
 632             x = vmsvga_fifo_read(s);
 633             y = vmsvga_fifo_read(s);
 634             dx = vmsvga_fifo_read(s);
 635             dy = vmsvga_fifo_read(s);
 636             width = vmsvga_fifo_read(s);
 637             height = vmsvga_fifo_read(s);
 638 #ifdef HW_RECT_ACCEL
 639             if (vmsvga_copy_rect(s, x, y, dx, dy, width, height) == 0) {
 640                 break;
 641             }
 642 #endif
 643             args = 0;
 644             goto badcmd;
 645
 646         case SVGA_CMD_DEFINE_CURSOR:
 647             len -= 8;
 648             if (len < 0) {
 649                 goto rewind;
 650             }
 651
 652             cursor.id = vmsvga_fifo_read(s);
 653             cursor.hot_x = vmsvga_fifo_read(s);
 654             cursor.hot_y = vmsvga_fifo_read(s);
 655             cursor.width = x = vmsvga_fifo_read(s);
 656             cursor.height = y = vmsvga_fifo_read(s);
 657             vmsvga_fifo_read(s);
 658             cursor.bpp = vmsvga_fifo_read(s);
 659
 660             args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp);
 661             if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask ||
 662                 SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) {
 663                     goto badcmd;
 664             }
 665
 666             len -= args;
 667             if (len < 0) {
 668                 goto rewind;
 669             }
 670
 671             for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) {
 672                 cursor.mask[args] = vmsvga_fifo_read_raw(s);
 673             }
 674             for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) {
 675                 cursor.image[args] = vmsvga_fifo_read_raw(s);
 676             }
 677 #ifdef HW_MOUSE_ACCEL
 678             vmsvga_cursor_define(s, &cursor);
 679             break;
 680 #else
 681             args = 0;
 682             goto badcmd;
 683 #endif
 684
 685         /*
 686          * Other commands that we at least know the number of arguments
 687          * for so we can avoid FIFO desync if driver uses them illegally.
 688          */
 689         case SVGA_CMD_DEFINE_ALPHA_CURSOR:
 690             len -= 6;
 691             if (len < 0) {
 692                 goto rewind;
 693             }
 694             vmsvga_fifo_read(s);
 695             vmsvga_fifo_read(s);
 696             vmsvga_fifo_read(s);
 697             x = vmsvga_fifo_read(s);
 698             y = vmsvga_fifo_read(s);
 699             args = x * y;
 700             goto badcmd;
 701         case SVGA_CMD_RECT_ROP_FILL:
 702             args = 6;
 703             goto badcmd;
 704         case SVGA_CMD_RECT_ROP_COPY:
 705             args = 7;
 706             goto badcmd;
 707         case SVGA_CMD_DRAW_GLYPH_CLIPPED:
 708             len -= 4;
 709             if (len < 0) {
 710                 goto rewind;
 711             }
 712             vmsvga_fifo_read(s);
 713             vmsvga_fifo_read(s);
 714             args = 7 + (vmsvga_fifo_read(s) >> 2);
 715             goto badcmd;
 716         case SVGA_CMD_SURFACE_ALPHA_BLEND:
 717             args = 12;
 718             goto badcmd;
 719
 720         /*
 721          * Other commands that are not listed as depending on any
 722          * CAPABILITIES bits, but are not described in the README either.
 723          */
 724         case SVGA_CMD_SURFACE_FILL:
 725         case SVGA_CMD_SURFACE_COPY:
 726         case SVGA_CMD_FRONT_ROP_FILL:
 727         case SVGA_CMD_FENCE:
 728         case SVGA_CMD_INVALID_CMD:
 729             break; /* Nop */
 730
 731         default:
 732             args = 0;
 733         badcmd:
 734             len -= args;
 735             if (len < 0) {
 736                 goto rewind;
 737             }
 738             while (args--) {
 739                 vmsvga_fifo_read(s);
 740             }
 741             printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
 742                    __func__, cmd);
 743             break;
 744
 745         rewind:
 746             s->cmd->stop = cmd_start;
 747             break;
 748         }
 749     }
 750
 751     s->syncing = 0;
 752 }
 753
 754 static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
 755 {
 756     struct vmsvga_state_s *s = opaque;
 757
 758     return s->index;
 759 }
 760
 761 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
 762 {
 763     struct vmsvga_state_s *s = opaque;
 764
 765     s->index = index;
 766 }
 767
 768 static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
 769 {
 770     uint32_t caps;
 771     struct vmsvga_state_s *s = opaque;
 772     DisplaySurface *surface = qemu_console_surface(s->vga.con);
 773     PixelFormat pf;
 774     uint32_t ret;
 775
 776     switch (s->index) {
 777     case SVGA_REG_ID:
 778         ret = s->svgaid;
 779         break;
 780
 781     case SVGA_REG_ENABLE:
 782         ret = s->enable;
 783         break;
 784
 785     case SVGA_REG_WIDTH:
 786         ret = s->new_width ? s->new_width : surface_width(surface);
 787         break;
 788
 789     case SVGA_REG_HEIGHT:
 790         ret = s->new_height ? s->new_height : surface_height(surface);
 791         break;
 792
 793     case SVGA_REG_MAX_WIDTH:
 794         ret = SVGA_MAX_WIDTH;
 795         break;
 796
 797     case SVGA_REG_MAX_HEIGHT:
 798         ret = SVGA_MAX_HEIGHT;
 799         break;
 800
 801     case SVGA_REG_DEPTH:
 802         ret = (s->new_depth == 32) ? 24 : s->new_depth;
 803         break;
 804
 805     case SVGA_REG_BITS_PER_PIXEL:
 806     case SVGA_REG_HOST_BITS_PER_PIXEL:
 807         ret = s->new_depth;
 808         break;
 809
 810     case SVGA_REG_PSEUDOCOLOR:
 811         ret = 0x0;
 812         break;
 813
 814     case SVGA_REG_RED_MASK:
 815         pf = qemu_default_pixelformat(s->new_depth);
 816         ret = pf.rmask;
 817         break;
 818
 819     case SVGA_REG_GREEN_MASK:
 820         pf = qemu_default_pixelformat(s->new_depth);
 821         ret = pf.gmask;
 822         break;
 823
 824     case SVGA_REG_BLUE_MASK:
 825         pf = qemu_default_pixelformat(s->new_depth);
 826         ret = pf.bmask;
 827         break;
 828
 829     case SVGA_REG_BYTES_PER_LINE:
 830         if (s->new_width) {
 831             ret = (s->new_depth * s->new_width) / 8;
 832         } else {
 833             ret = surface_stride(surface);
 834         }
 835         break;
 836
 837     case SVGA_REG_FB_START: {
 838         struct pci_vmsvga_state_s *pci_vmsvga
 839             = container_of(s, struct pci_vmsvga_state_s, chip);
 840         ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 1);
 841         break;
 842     }
 843
 844     case SVGA_REG_FB_OFFSET:
 845         ret = 0x0;
 846         break;
 847
 848     case SVGA_REG_VRAM_SIZE:
 849         ret = s->vga.vram_size; /* No physical VRAM besides the framebuffer */
 850         break;
 851
 852     case SVGA_REG_FB_SIZE:
 853         ret = s->vga.vram_size;
 854         break;
 855
 856     case SVGA_REG_CAPABILITIES:
 857         caps = SVGA_CAP_NONE;
 858 #ifdef HW_RECT_ACCEL
 859         caps |= SVGA_CAP_RECT_COPY;
 860 #endif
 861 #ifdef HW_FILL_ACCEL
 862         caps |= SVGA_CAP_RECT_FILL;
 863 #endif
 864 #ifdef HW_MOUSE_ACCEL
 865         if (dpy_cursor_define_supported(s->vga.con)) {
 866             caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
 867                     SVGA_CAP_CURSOR_BYPASS;
 868         }
 869 #endif
 870         ret = caps;
 871         break;
 872
 873     case SVGA_REG_MEM_START: {
 874         struct pci_vmsvga_state_s *pci_vmsvga
 875             = container_of(s, struct pci_vmsvga_state_s, chip);
 876         ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 2);
 877         break;
 878     }
 879
 880     case SVGA_REG_MEM_SIZE:
 881         ret = s->fifo_size;
 882         break;
 883
 884     case SVGA_REG_CONFIG_DONE:
 885         ret = s->config;
 886         break;
 887
 888     case SVGA_REG_SYNC:
 889     case SVGA_REG_BUSY:
 890         ret = s->syncing;
 891         break;
 892
 893     case SVGA_REG_GUEST_ID:
 894         ret = s->guest;
 895         break;
 896
 897     case SVGA_REG_CURSOR_ID:
 898         ret = s->cursor.id;
 899         break;
 900
 901     case SVGA_REG_CURSOR_X:
 902         ret = s->cursor.x;
 903         break;
 904
 905     case SVGA_REG_CURSOR_Y:
 906         ret = s->cursor.y;
 907         break;
 908
 909     case SVGA_REG_CURSOR_ON:
 910         ret = s->cursor.on;
 911         break;
 912
 913     case SVGA_REG_SCRATCH_SIZE:
 914         ret = s->scratch_size;
 915         break;
 916
 917     case SVGA_REG_MEM_REGS:
 918     case SVGA_REG_NUM_DISPLAYS:
 919     case SVGA_REG_PITCHLOCK:
 920     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 921         ret = 0;
 922         break;
 923
 924     default:
 925         if (s->index >= SVGA_SCRATCH_BASE &&
 926             s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
 927             ret = s->scratch[s->index - SVGA_SCRATCH_BASE];
 928             break;
 929         }
 930         printf("%s: Bad register %02x\n", __func__, s->index);
 931         ret = 0;
 932         break;
 933     }
 934
 935     if (s->index >= SVGA_SCRATCH_BASE) {
 936         trace_vmware_scratch_read(s->index, ret);
 937     } else if (s->index >= SVGA_PALETTE_BASE) {
 938         trace_vmware_palette_read(s->index, ret);
 939     } else {
 940         trace_vmware_value_read(s->index, ret);
 941     }
 942     return ret;
 943 }
 944
 945 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
 946 {
 947     struct vmsvga_state_s *s = opaque;
 948
 949     if (s->index >= SVGA_SCRATCH_BASE) {
 950         trace_vmware_scratch_write(s->index, value);
 951     } else if (s->index >= SVGA_PALETTE_BASE) {
 952         trace_vmware_palette_write(s->index, value);
 953     } else {
 954         trace_vmware_value_write(s->index, value);
 955     }
 956     switch (s->index) {
 957     case SVGA_REG_ID:
 958         if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) {
 959             s->svgaid = value;
 960         }
 961         break;
 962
 963     case SVGA_REG_ENABLE:
 964         s->enable = !!value;
 965         s->invalidated = 1;
 966         s->vga.hw_ops->invalidate(&s->vga);
 967         if (s->enable && s->config) {
 968             vga_dirty_log_stop(&s->vga);
 969         } else {
 970             vga_dirty_log_start(&s->vga);
 971         }
 972         break;
 973
 974     case SVGA_REG_WIDTH:
 975         if (value <= SVGA_MAX_WIDTH) {
 976             s->new_width = value;
 977             s->invalidated = 1;
 978         } else {
 979             printf("%s: Bad width: %i\n", __func__, value);
 980         }
 981         break;
 982
 983     case SVGA_REG_HEIGHT:
 984         if (value <= SVGA_MAX_HEIGHT) {
 985             s->new_height = value;
 986             s->invalidated = 1;
 987         } else {
 988             printf("%s: Bad height: %i\n", __func__, value);
 989         }
 990         break;
 991
 992     case SVGA_REG_BITS_PER_PIXEL:
 993         if (value != 32) {
 994             printf("%s: Bad bits per pixel: %i bits\n", __func__, value);
 995             s->config = 0;
 996             s->invalidated = 1;
 997         }
 998         break;
 999
1000     case SVGA_REG_CONFIG_DONE:
1001         if (value) {
1002             s->fifo = (uint32_t *) s->fifo_ptr;
1003             /* Check range and alignment.  */
1004             if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) {
1005                 break;
1006             }
1007             if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) {
1008                 break;
1009             }
1010             if (CMD(max) > SVGA_FIFO_SIZE) {
1011                 break;
1012             }
1013             if (CMD(max) < CMD(min) + 10 * 1024) {
1014                 break;
1015             }
1016             vga_dirty_log_stop(&s->vga);
1017         }
1018         s->config = !!value;
1019         break;
1020
1021     case SVGA_REG_SYNC:
1022         s->syncing = 1;
1023         vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
1024         break;
1025
1026     case SVGA_REG_GUEST_ID:
1027         s->guest = value;
1028 #ifdef VERBOSE
1029         if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
1030             ARRAY_SIZE(vmsvga_guest_id)) {
1031             printf("%s: guest runs %s.\n", __func__,
1032                    vmsvga_guest_id[value - GUEST_OS_BASE]);
1033         }
1034 #endif
1035         break;
1036
1037     case SVGA_REG_CURSOR_ID:
1038         s->cursor.id = value;
1039         break;
1040
1041     case SVGA_REG_CURSOR_X:
1042         s->cursor.x = value;
1043         break;
1044
1045     case SVGA_REG_CURSOR_Y:
1046         s->cursor.y = value;
1047         break;
1048
1049     case SVGA_REG_CURSOR_ON:
1050         s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
1051         s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
1052 #ifdef HW_MOUSE_ACCEL
1053         if (value <= SVGA_CURSOR_ON_SHOW) {
1054             dpy_mouse_set(s->vga.con, s->cursor.x, s->cursor.y, s->cursor.on);
1055         }
1056 #endif
1057         break;
1058
1059     case SVGA_REG_DEPTH:
1060     case SVGA_REG_MEM_REGS:
1061     case SVGA_REG_NUM_DISPLAYS:
1062     case SVGA_REG_PITCHLOCK:
1063     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
1064         break;
1065
1066     default:
1067         if (s->index >= SVGA_SCRATCH_BASE &&
1068                 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
1069             s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
1070             break;
1071         }
1072         printf("%s: Bad register %02x\n", __func__, s->index);
1073     }
1074 }
1075
1076 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
1077 {
1078     printf("%s: what are we supposed to return?\n", __func__);
1079     return 0xcafe;
1080 }
1081
1082 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
1083 {
1084     printf("%s: what are we supposed to do with (%08x)?\n", __func__, data);
1085 }
1086
1087 static inline void vmsvga_check_size(struct vmsvga_state_s *s)
1088 {
1089     DisplaySurface *surface = qemu_console_surface(s->vga.con);
1090
1091     if (s->new_width != surface_width(surface) ||
1092         s->new_height != surface_height(surface) ||
1093         s->new_depth != surface_bits_per_pixel(surface)) {
1094         int stride = (s->new_depth * s->new_width) / 8;
1095         pixman_format_code_t format =
1096             qemu_default_pixman_format(s->new_depth, true);
1097         trace_vmware_setmode(s->new_width, s->new_height, s->new_depth);
1098         surface = qemu_create_displaysurface_from(s->new_width, s->new_height,
1099                                                   format, stride,
1100                                                   s->vga.vram_ptr);
1101         dpy_gfx_replace_surface(s->vga.con, surface);
1102         s->invalidated = 1;
1103     }
1104 }
1105
1106 static void vmsvga_update_display(void *opaque)
1107 {
1108     struct vmsvga_state_s *s = opaque;
1109     DisplaySurface *surface;
1110     bool dirty = false;
1111
1112     if (!s->enable) {
1113         s->vga.hw_ops->gfx_update(&s->vga);
1114         return;
1115     }
1116
1117     vmsvga_check_size(s);
1118     surface = qemu_console_surface(s->vga.con);
1119
1120     vmsvga_fifo_run(s);
1121     vmsvga_update_rect_flush(s);
1122
1123     /*
1124      * Is it more efficient to look at vram VGA-dirty bits or wait
1125      * for the driver to issue SVGA_CMD_UPDATE?
1126      */
1127     if (memory_region_is_logging(&s->vga.vram, DIRTY_MEMORY_VGA)) {
1128         vga_sync_dirty_bitmap(&s->vga);
1129         dirty = memory_region_get_dirty(&s->vga.vram, 0,
1130             surface_stride(surface) * surface_height(surface),
1131             DIRTY_MEMORY_VGA);
1132     }
1133     if (s->invalidated || dirty) {
1134         s->invalidated = 0;
1135         dpy_gfx_update(s->vga.con, 0, 0,
1136                    surface_width(surface), surface_height(surface));
1137     }
1138     if (dirty) {
1139         memory_region_reset_dirty(&s->vga.vram, 0,
1140             surface_stride(surface) * surface_height(surface),
1141             DIRTY_MEMORY_VGA);
1142     }
1143 }
1144
1145 static void vmsvga_reset(DeviceState *dev)
1146 {
1147     struct pci_vmsvga_state_s *pci = VMWARE_SVGA(dev);
1148     struct vmsvga_state_s *s = &pci->chip;
1149
1150     s->index = 0;
1151     s->enable = 0;
1152     s->config = 0;
1153     s->svgaid = SVGA_ID;
1154     s->cursor.on = 0;
1155     s->redraw_fifo_first = 0;
1156     s->redraw_fifo_last = 0;
1157     s->syncing = 0;
1158
1159     vga_dirty_log_start(&s->vga);
1160 }
1161
1162 static void vmsvga_invalidate_display(void *opaque)
1163 {
1164     struct vmsvga_state_s *s = opaque;
1165     if (!s->enable) {
1166         s->vga.hw_ops->invalidate(&s->vga);
1167         return;
1168     }
1169
1170     s->invalidated = 1;
1171 }
1172
1173 static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
1174 {
1175     struct vmsvga_state_s *s = opaque;
1176
1177     if (s->vga.hw_ops->text_update) {
1178         s->vga.hw_ops->text_update(&s->vga, chardata);
1179     }
1180 }
1181
1182 static int vmsvga_post_load(void *opaque, int version_id)
1183 {
1184     struct vmsvga_state_s *s = opaque;
1185
1186     s->invalidated = 1;
1187     if (s->config) {
1188         s->fifo = (uint32_t *) s->fifo_ptr;
1189     }
1190     return 0;
1191 }
1192
1193 static const VMStateDescription vmstate_vmware_vga_internal = {
1194     .name = "vmware_vga_internal",
1195     .version_id = 0,
1196     .minimum_version_id = 0,
1197     .post_load = vmsvga_post_load,
1198     .fields = (VMStateField[]) {
1199         VMSTATE_INT32_EQUAL(new_depth, struct vmsvga_state_s),
1200         VMSTATE_INT32(enable, struct vmsvga_state_s),
1201         VMSTATE_INT32(config, struct vmsvga_state_s),
1202         VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
1203         VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
1204         VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
1205         VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
1206         VMSTATE_INT32(index, struct vmsvga_state_s),
1207         VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
1208                              scratch_size, 0, vmstate_info_uint32, uint32_t),
1209         VMSTATE_INT32(new_width, struct vmsvga_state_s),
1210         VMSTATE_INT32(new_height, struct vmsvga_state_s),
1211         VMSTATE_UINT32(guest, struct vmsvga_state_s),
1212         VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
1213         VMSTATE_INT32(syncing, struct vmsvga_state_s),
1214         VMSTATE_UNUSED(4), /* was fb_size */
1215         VMSTATE_END_OF_LIST()
1216     }
1217 };
1218
1219 static const VMStateDescription vmstate_vmware_vga = {
1220     .name = "vmware_vga",
1221     .version_id = 0,
1222     .minimum_version_id = 0,
1223     .fields = (VMStateField[]) {
1224         VMSTATE_PCI_DEVICE(parent_obj, struct pci_vmsvga_state_s),
1225         VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
1226                        vmstate_vmware_vga_internal, struct vmsvga_state_s),
1227         VMSTATE_END_OF_LIST()
1228     }
1229 };
1230
1231 static const GraphicHwOps vmsvga_ops = {
1232     .invalidate  = vmsvga_invalidate_display,
1233     .gfx_update  = vmsvga_update_display,
1234     .text_update = vmsvga_text_update,
1235 };
1236
1237 static void vmsvga_init(DeviceState *dev, struct vmsvga_state_s *s,
1238                         MemoryRegion *address_space, MemoryRegion *io)
1239 {
1240     s->scratch_size = SVGA_SCRATCH_SIZE;
1241     s->scratch = g_malloc(s->scratch_size * 4);
1242
1243     s->vga.con = graphic_console_init(dev, 0, &vmsvga_ops, s);
1244
1245     s->fifo_size = SVGA_FIFO_SIZE;
1246     memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size,
1247                            &error_abort);
1248     vmstate_register_ram_global(&s->fifo_ram);
1249     s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
1250
1251     vga_common_init(&s->vga, OBJECT(dev), true);
1252     vga_init(&s->vga, OBJECT(dev), address_space, io, true);
1253     vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
1254     s->new_depth = 32;
1255 }
1256
1257 static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size)
1258 {
1259     struct vmsvga_state_s *s = opaque;
1260
1261     switch (addr) {
1262     case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr);
1263     case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr);
1264     case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr);
1265     default: return -1u;
1266     }
1267 }
1268
1269 static void vmsvga_io_write(void *opaque, hwaddr addr,
1270                             uint64_t data, unsigned size)
1271 {
1272     struct vmsvga_state_s *s = opaque;
1273
1274     switch (addr) {
1275     case SVGA_IO_MUL * SVGA_INDEX_PORT:
1276         vmsvga_index_write(s, addr, data);
1277         break;
1278     case SVGA_IO_MUL * SVGA_VALUE_PORT:
1279         vmsvga_value_write(s, addr, data);
1280         break;
1281     case SVGA_IO_MUL * SVGA_BIOS_PORT:
1282         vmsvga_bios_write(s, addr, data);
1283         break;
1284     }
1285 }
1286
1287 static const MemoryRegionOps vmsvga_io_ops = {
1288     .read = vmsvga_io_read,
1289     .write = vmsvga_io_write,
1290     .endianness = DEVICE_LITTLE_ENDIAN,
1291     .valid = {
1292         .min_access_size = 4,
1293         .max_access_size = 4,
1294         .unaligned = true,
1295     },
1296     .impl = {
1297         .unaligned = true,
1298     },
1299 };
1300
1301 static void pci_vmsvga_realize(PCIDevice *dev, Error **errp)
1302 {
1303     struct pci_vmsvga_state_s *s = VMWARE_SVGA(dev);
1304
1305     dev->config[PCI_CACHE_LINE_SIZE] = 0x08;
1306     dev->config[PCI_LATENCY_TIMER] = 0x40;
1307     dev->config[PCI_INTERRUPT_LINE] = 0xff;          /* End */
1308
1309     memory_region_init_io(&s->io_bar, NULL, &vmsvga_io_ops, &s->chip,
1310                           "vmsvga-io", 0x10);
1311     memory_region_set_flush_coalesced(&s->io_bar);
1312     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1313
1314     vmsvga_init(DEVICE(dev), &s->chip,
1315                 pci_address_space(dev), pci_address_space_io(dev));
1316
1317     pci_register_bar(dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
1318                      &s->chip.vga.vram);
1319     pci_register_bar(dev, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
1320                      &s->chip.fifo_ram);
1321
1322     if (!dev->rom_bar) {
1323         /* compatibility with pc-0.13 and older */
1324         vga_init_vbe(&s->chip.vga, OBJECT(dev), pci_address_space(dev));
1325     }
1326 }
1327
1328 static Property vga_vmware_properties[] = {
1329     DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s,
1330                        chip.vga.vram_size_mb, 16),
1331     DEFINE_PROP_END_OF_LIST(),
1332 };
1333
1334 static void vmsvga_class_init(ObjectClass *klass, void *data)
1335 {
1336     DeviceClass *dc = DEVICE_CLASS(klass);
1337     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1338
1339     k->realize = pci_vmsvga_realize;
1340     k->romfile = "vgabios-vmware.bin";
1341     k->vendor_id = PCI_VENDOR_ID_VMWARE;
1342     k->device_id = SVGA_PCI_DEVICE_ID;
1343     k->class_id = PCI_CLASS_DISPLAY_VGA;
1344     k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
1345     k->subsystem_id = SVGA_PCI_DEVICE_ID;
1346     dc->reset = vmsvga_reset;
1347     dc->vmsd = &vmstate_vmware_vga;
1348     dc->props = vga_vmware_properties;
1349     dc->hotpluggable = false;
1350     set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
1351 }
1352
1353 static const TypeInfo vmsvga_info = {
1354     .name          = TYPE_VMWARE_SVGA,
1355     .parent        = TYPE_PCI_DEVICE,
1356     .instance_size = sizeof(struct pci_vmsvga_state_s),
1357     .class_init    = vmsvga_class_init,
1358 };
1359
1360 static void vmsvga_register_types(void)
1361 {
1362     type_register_static(&vmsvga_info);
1363 }
1364
1365 type_init(vmsvga_register_types)