2 * QEMU VMware-SVGA "chipset".
4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/module.h"
27 #include "qemu/units.h"
28 #include "qapi/error.h"
30 #include "hw/loader.h"
33 #include "hw/pci/pci.h"
34 #include "migration/vmstate.h"
39 #define HW_MOUSE_ACCEL
43 /* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */
45 struct vmsvga_state_s
{
68 MemoryRegion fifo_ram
;
70 unsigned int fifo_size
;
78 #define REDRAW_FIFO_LEN 512
79 struct vmsvga_rect_s
{
81 } redraw_fifo
[REDRAW_FIFO_LEN
];
82 int redraw_fifo_first
, redraw_fifo_last
;
85 #define TYPE_VMWARE_SVGA "vmware-svga"
87 #define VMWARE_SVGA(obj) \
88 OBJECT_CHECK(struct pci_vmsvga_state_s, (obj), TYPE_VMWARE_SVGA)
90 struct pci_vmsvga_state_s
{
95 struct vmsvga_state_s chip
;
99 #define SVGA_MAGIC 0x900000UL
100 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
101 #define SVGA_ID_0 SVGA_MAKE_ID(0)
102 #define SVGA_ID_1 SVGA_MAKE_ID(1)
103 #define SVGA_ID_2 SVGA_MAKE_ID(2)
105 #define SVGA_LEGACY_BASE_PORT 0x4560
106 #define SVGA_INDEX_PORT 0x0
107 #define SVGA_VALUE_PORT 0x1
108 #define SVGA_BIOS_PORT 0x2
110 #define SVGA_VERSION_2
112 #ifdef SVGA_VERSION_2
113 # define SVGA_ID SVGA_ID_2
114 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
115 # define SVGA_IO_MUL 1
116 # define SVGA_FIFO_SIZE 0x10000
117 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
119 # define SVGA_ID SVGA_ID_1
120 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
121 # define SVGA_IO_MUL 4
122 # define SVGA_FIFO_SIZE 0x10000
123 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
127 /* ID 0, 1 and 2 registers */
132 SVGA_REG_MAX_WIDTH
= 4,
133 SVGA_REG_MAX_HEIGHT
= 5,
135 SVGA_REG_BITS_PER_PIXEL
= 7, /* Current bpp in the guest */
136 SVGA_REG_PSEUDOCOLOR
= 8,
137 SVGA_REG_RED_MASK
= 9,
138 SVGA_REG_GREEN_MASK
= 10,
139 SVGA_REG_BLUE_MASK
= 11,
140 SVGA_REG_BYTES_PER_LINE
= 12,
141 SVGA_REG_FB_START
= 13,
142 SVGA_REG_FB_OFFSET
= 14,
143 SVGA_REG_VRAM_SIZE
= 15,
144 SVGA_REG_FB_SIZE
= 16,
146 /* ID 1 and 2 registers */
147 SVGA_REG_CAPABILITIES
= 17,
148 SVGA_REG_MEM_START
= 18, /* Memory for command FIFO */
149 SVGA_REG_MEM_SIZE
= 19,
150 SVGA_REG_CONFIG_DONE
= 20, /* Set when memory area configured */
151 SVGA_REG_SYNC
= 21, /* Write to force synchronization */
152 SVGA_REG_BUSY
= 22, /* Read to check if sync is done */
153 SVGA_REG_GUEST_ID
= 23, /* Set guest OS identifier */
154 SVGA_REG_CURSOR_ID
= 24, /* ID of cursor */
155 SVGA_REG_CURSOR_X
= 25, /* Set cursor X position */
156 SVGA_REG_CURSOR_Y
= 26, /* Set cursor Y position */
157 SVGA_REG_CURSOR_ON
= 27, /* Turn cursor on/off */
158 SVGA_REG_HOST_BITS_PER_PIXEL
= 28, /* Current bpp in the host */
159 SVGA_REG_SCRATCH_SIZE
= 29, /* Number of scratch registers */
160 SVGA_REG_MEM_REGS
= 30, /* Number of FIFO registers */
161 SVGA_REG_NUM_DISPLAYS
= 31, /* Number of guest displays */
162 SVGA_REG_PITCHLOCK
= 32, /* Fixed pitch for all modes */
164 SVGA_PALETTE_BASE
= 1024, /* Base of SVGA color map */
165 SVGA_PALETTE_END
= SVGA_PALETTE_BASE
+ 767,
166 SVGA_SCRATCH_BASE
= SVGA_PALETTE_BASE
+ 768,
169 #define SVGA_CAP_NONE 0
170 #define SVGA_CAP_RECT_FILL (1 << 0)
171 #define SVGA_CAP_RECT_COPY (1 << 1)
172 #define SVGA_CAP_RECT_PAT_FILL (1 << 2)
173 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
174 #define SVGA_CAP_RASTER_OP (1 << 4)
175 #define SVGA_CAP_CURSOR (1 << 5)
176 #define SVGA_CAP_CURSOR_BYPASS (1 << 6)
177 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
178 #define SVGA_CAP_8BIT_EMULATION (1 << 8)
179 #define SVGA_CAP_ALPHA_CURSOR (1 << 9)
180 #define SVGA_CAP_GLYPH (1 << 10)
181 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
182 #define SVGA_CAP_OFFSCREEN_1 (1 << 12)
183 #define SVGA_CAP_ALPHA_BLEND (1 << 13)
184 #define SVGA_CAP_3D (1 << 14)
185 #define SVGA_CAP_EXTENDED_FIFO (1 << 15)
186 #define SVGA_CAP_MULTIMON (1 << 16)
187 #define SVGA_CAP_PITCHLOCK (1 << 17)
190 * FIFO offsets (seen as an array of 32-bit words)
194 * The original defined FIFO offsets
197 SVGA_FIFO_MAX
, /* The distance from MIN to MAX must be at least 10K */
202 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
204 SVGA_FIFO_CAPABILITIES
= 4,
207 SVGA_FIFO_3D_HWVERSION
,
211 #define SVGA_FIFO_CAP_NONE 0
212 #define SVGA_FIFO_CAP_FENCE (1 << 0)
213 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
214 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
216 #define SVGA_FIFO_FLAG_NONE 0
217 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
219 /* These values can probably be changed arbitrarily. */
220 #define SVGA_SCRATCH_SIZE 0x8000
221 #define SVGA_MAX_WIDTH ROUND_UP(2360, VNC_DIRTY_PIXELS_PER_BIT)
222 #define SVGA_MAX_HEIGHT 1770
225 # define GUEST_OS_BASE 0x5001
226 static const char *vmsvga_guest_id
[] = {
228 [0x01] = "Windows 3.1",
229 [0x02] = "Windows 95",
230 [0x03] = "Windows 98",
231 [0x04] = "Windows ME",
232 [0x05] = "Windows NT",
233 [0x06] = "Windows 2000",
236 [0x09] = "an unknown OS",
239 [0x0c] = "an unknown OS",
240 [0x0d] = "an unknown OS",
241 [0x0e] = "an unknown OS",
242 [0x0f] = "an unknown OS",
243 [0x10] = "an unknown OS",
244 [0x11] = "an unknown OS",
245 [0x12] = "an unknown OS",
246 [0x13] = "an unknown OS",
247 [0x14] = "an unknown OS",
248 [0x15] = "Windows 2003",
253 SVGA_CMD_INVALID_CMD
= 0,
255 SVGA_CMD_RECT_FILL
= 2,
256 SVGA_CMD_RECT_COPY
= 3,
257 SVGA_CMD_DEFINE_BITMAP
= 4,
258 SVGA_CMD_DEFINE_BITMAP_SCANLINE
= 5,
259 SVGA_CMD_DEFINE_PIXMAP
= 6,
260 SVGA_CMD_DEFINE_PIXMAP_SCANLINE
= 7,
261 SVGA_CMD_RECT_BITMAP_FILL
= 8,
262 SVGA_CMD_RECT_PIXMAP_FILL
= 9,
263 SVGA_CMD_RECT_BITMAP_COPY
= 10,
264 SVGA_CMD_RECT_PIXMAP_COPY
= 11,
265 SVGA_CMD_FREE_OBJECT
= 12,
266 SVGA_CMD_RECT_ROP_FILL
= 13,
267 SVGA_CMD_RECT_ROP_COPY
= 14,
268 SVGA_CMD_RECT_ROP_BITMAP_FILL
= 15,
269 SVGA_CMD_RECT_ROP_PIXMAP_FILL
= 16,
270 SVGA_CMD_RECT_ROP_BITMAP_COPY
= 17,
271 SVGA_CMD_RECT_ROP_PIXMAP_COPY
= 18,
272 SVGA_CMD_DEFINE_CURSOR
= 19,
273 SVGA_CMD_DISPLAY_CURSOR
= 20,
274 SVGA_CMD_MOVE_CURSOR
= 21,
275 SVGA_CMD_DEFINE_ALPHA_CURSOR
= 22,
276 SVGA_CMD_DRAW_GLYPH
= 23,
277 SVGA_CMD_DRAW_GLYPH_CLIPPED
= 24,
278 SVGA_CMD_UPDATE_VERBOSE
= 25,
279 SVGA_CMD_SURFACE_FILL
= 26,
280 SVGA_CMD_SURFACE_COPY
= 27,
281 SVGA_CMD_SURFACE_ALPHA_BLEND
= 28,
282 SVGA_CMD_FRONT_ROP_FILL
= 29,
286 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
288 SVGA_CURSOR_ON_HIDE
= 0,
289 SVGA_CURSOR_ON_SHOW
= 1,
290 SVGA_CURSOR_ON_REMOVE_FROM_FB
= 2,
291 SVGA_CURSOR_ON_RESTORE_TO_FB
= 3,
294 static inline bool vmsvga_verify_rect(DisplaySurface
*surface
,
296 int x
, int y
, int w
, int h
)
299 fprintf(stderr
, "%s: x was < 0 (%d)\n", name
, x
);
302 if (x
> SVGA_MAX_WIDTH
) {
303 fprintf(stderr
, "%s: x was > %d (%d)\n", name
, SVGA_MAX_WIDTH
, x
);
307 fprintf(stderr
, "%s: w was < 0 (%d)\n", name
, w
);
310 if (w
> SVGA_MAX_WIDTH
) {
311 fprintf(stderr
, "%s: w was > %d (%d)\n", name
, SVGA_MAX_WIDTH
, w
);
314 if (x
+ w
> surface_width(surface
)) {
315 fprintf(stderr
, "%s: width was > %d (x: %d, w: %d)\n",
316 name
, surface_width(surface
), x
, w
);
321 fprintf(stderr
, "%s: y was < 0 (%d)\n", name
, y
);
324 if (y
> SVGA_MAX_HEIGHT
) {
325 fprintf(stderr
, "%s: y was > %d (%d)\n", name
, SVGA_MAX_HEIGHT
, y
);
329 fprintf(stderr
, "%s: h was < 0 (%d)\n", name
, h
);
332 if (h
> SVGA_MAX_HEIGHT
) {
333 fprintf(stderr
, "%s: h was > %d (%d)\n", name
, SVGA_MAX_HEIGHT
, h
);
336 if (y
+ h
> surface_height(surface
)) {
337 fprintf(stderr
, "%s: update height > %d (y: %d, h: %d)\n",
338 name
, surface_height(surface
), y
, h
);
345 static inline void vmsvga_update_rect(struct vmsvga_state_s
*s
,
346 int x
, int y
, int w
, int h
)
348 DisplaySurface
*surface
= qemu_console_surface(s
->vga
.con
);
356 if (!vmsvga_verify_rect(surface
, __func__
, x
, y
, w
, h
)) {
357 /* go for a fullscreen update as fallback */
360 w
= surface_width(surface
);
361 h
= surface_height(surface
);
364 bypl
= surface_stride(surface
);
365 width
= surface_bytes_per_pixel(surface
) * w
;
366 start
= surface_bytes_per_pixel(surface
) * x
+ bypl
* y
;
367 src
= s
->vga
.vram_ptr
+ start
;
368 dst
= surface_data(surface
) + start
;
370 for (line
= h
; line
> 0; line
--, src
+= bypl
, dst
+= bypl
) {
371 memcpy(dst
, src
, width
);
373 dpy_gfx_update(s
->vga
.con
, x
, y
, w
, h
);
376 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s
*s
,
377 int x
, int y
, int w
, int h
)
379 struct vmsvga_rect_s
*rect
= &s
->redraw_fifo
[s
->redraw_fifo_last
++];
381 s
->redraw_fifo_last
&= REDRAW_FIFO_LEN
- 1;
388 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s
*s
)
390 struct vmsvga_rect_s
*rect
;
392 if (s
->invalidated
) {
393 s
->redraw_fifo_first
= s
->redraw_fifo_last
;
396 /* Overlapping region updates can be optimised out here - if someone
397 * knows a smart algorithm to do that, please share. */
398 while (s
->redraw_fifo_first
!= s
->redraw_fifo_last
) {
399 rect
= &s
->redraw_fifo
[s
->redraw_fifo_first
++];
400 s
->redraw_fifo_first
&= REDRAW_FIFO_LEN
- 1;
401 vmsvga_update_rect(s
, rect
->x
, rect
->y
, rect
->w
, rect
->h
);
406 static inline int vmsvga_copy_rect(struct vmsvga_state_s
*s
,
407 int x0
, int y0
, int x1
, int y1
, int w
, int h
)
409 DisplaySurface
*surface
= qemu_console_surface(s
->vga
.con
);
410 uint8_t *vram
= s
->vga
.vram_ptr
;
411 int bypl
= surface_stride(surface
);
412 int bypp
= surface_bytes_per_pixel(surface
);
413 int width
= bypp
* w
;
417 if (!vmsvga_verify_rect(surface
, "vmsvga_copy_rect/src", x0
, y0
, w
, h
)) {
420 if (!vmsvga_verify_rect(surface
, "vmsvga_copy_rect/dst", x1
, y1
, w
, h
)) {
425 ptr
[0] = vram
+ bypp
* x0
+ bypl
* (y0
+ h
- 1);
426 ptr
[1] = vram
+ bypp
* x1
+ bypl
* (y1
+ h
- 1);
427 for (; line
> 0; line
--, ptr
[0] -= bypl
, ptr
[1] -= bypl
) {
428 memmove(ptr
[1], ptr
[0], width
);
431 ptr
[0] = vram
+ bypp
* x0
+ bypl
* y0
;
432 ptr
[1] = vram
+ bypp
* x1
+ bypl
* y1
;
433 for (; line
> 0; line
--, ptr
[0] += bypl
, ptr
[1] += bypl
) {
434 memmove(ptr
[1], ptr
[0], width
);
438 vmsvga_update_rect_delayed(s
, x1
, y1
, w
, h
);
444 static inline int vmsvga_fill_rect(struct vmsvga_state_s
*s
,
445 uint32_t c
, int x
, int y
, int w
, int h
)
447 DisplaySurface
*surface
= qemu_console_surface(s
->vga
.con
);
448 int bypl
= surface_stride(surface
);
449 int width
= surface_bytes_per_pixel(surface
) * w
;
457 if (!vmsvga_verify_rect(surface
, __func__
, x
, y
, w
, h
)) {
466 fst
= s
->vga
.vram_ptr
+ surface_bytes_per_pixel(surface
) * x
+ bypl
* y
;
471 for (column
= width
; column
> 0; column
--) {
473 if (src
- col
== surface_bytes_per_pixel(surface
)) {
478 for (; line
> 0; line
--) {
480 memcpy(dst
, fst
, width
);
484 vmsvga_update_rect_delayed(s
, x
, y
, w
, h
);
489 struct vmsvga_cursor_definition_s
{
497 uint32_t image
[4096];
500 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
501 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
503 #ifdef HW_MOUSE_ACCEL
504 static inline void vmsvga_cursor_define(struct vmsvga_state_s
*s
,
505 struct vmsvga_cursor_definition_s
*c
)
510 qc
= cursor_alloc(c
->width
, c
->height
);
511 qc
->hot_x
= c
->hot_x
;
512 qc
->hot_y
= c
->hot_y
;
515 cursor_set_mono(qc
, 0xffffff, 0x000000, (void *)c
->image
,
518 cursor_print_ascii_art(qc
, "vmware/mono");
522 /* fill alpha channel from mask, set color to zero */
523 cursor_set_mono(qc
, 0x000000, 0x000000, (void *)c
->mask
,
525 /* add in rgb values */
526 pixels
= c
->width
* c
->height
;
527 for (i
= 0; i
< pixels
; i
++) {
528 qc
->data
[i
] |= c
->image
[i
] & 0xffffff;
531 cursor_print_ascii_art(qc
, "vmware/32bit");
535 fprintf(stderr
, "%s: unhandled bpp %d, using fallback cursor\n",
538 qc
= cursor_builtin_left_ptr();
541 dpy_cursor_define(s
->vga
.con
, qc
);
546 static inline int vmsvga_fifo_length(struct vmsvga_state_s
*s
)
550 if (!s
->config
|| !s
->enable
) {
554 s
->fifo_min
= le32_to_cpu(s
->fifo
[SVGA_FIFO_MIN
]);
555 s
->fifo_max
= le32_to_cpu(s
->fifo
[SVGA_FIFO_MAX
]);
556 s
->fifo_next
= le32_to_cpu(s
->fifo
[SVGA_FIFO_NEXT
]);
557 s
->fifo_stop
= le32_to_cpu(s
->fifo
[SVGA_FIFO_STOP
]);
559 /* Check range and alignment. */
560 if ((s
->fifo_min
| s
->fifo_max
| s
->fifo_next
| s
->fifo_stop
) & 3) {
563 if (s
->fifo_min
< sizeof(uint32_t) * 4) {
566 if (s
->fifo_max
> SVGA_FIFO_SIZE
||
567 s
->fifo_min
>= SVGA_FIFO_SIZE
||
568 s
->fifo_stop
>= SVGA_FIFO_SIZE
||
569 s
->fifo_next
>= SVGA_FIFO_SIZE
) {
572 if (s
->fifo_max
< s
->fifo_min
+ 10 * KiB
) {
576 num
= s
->fifo_next
- s
->fifo_stop
;
578 num
+= s
->fifo_max
- s
->fifo_min
;
583 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s
*s
)
585 uint32_t cmd
= s
->fifo
[s
->fifo_stop
>> 2];
588 if (s
->fifo_stop
>= s
->fifo_max
) {
589 s
->fifo_stop
= s
->fifo_min
;
591 s
->fifo
[SVGA_FIFO_STOP
] = cpu_to_le32(s
->fifo_stop
);
595 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s
*s
)
597 return le32_to_cpu(vmsvga_fifo_read_raw(s
));
600 static void vmsvga_fifo_run(struct vmsvga_state_s
*s
)
602 uint32_t cmd
, colour
;
603 int args
, len
, maxloop
= 1024;
604 int x
, y
, dx
, dy
, width
, height
;
605 struct vmsvga_cursor_definition_s cursor
;
608 len
= vmsvga_fifo_length(s
);
609 while (len
> 0 && --maxloop
> 0) {
610 /* May need to go back to the start of the command if incomplete */
611 cmd_start
= s
->fifo_stop
;
613 switch (cmd
= vmsvga_fifo_read(s
)) {
614 case SVGA_CMD_UPDATE
:
615 case SVGA_CMD_UPDATE_VERBOSE
:
621 x
= vmsvga_fifo_read(s
);
622 y
= vmsvga_fifo_read(s
);
623 width
= vmsvga_fifo_read(s
);
624 height
= vmsvga_fifo_read(s
);
625 vmsvga_update_rect_delayed(s
, x
, y
, width
, height
);
628 case SVGA_CMD_RECT_FILL
:
634 colour
= vmsvga_fifo_read(s
);
635 x
= vmsvga_fifo_read(s
);
636 y
= vmsvga_fifo_read(s
);
637 width
= vmsvga_fifo_read(s
);
638 height
= vmsvga_fifo_read(s
);
640 if (vmsvga_fill_rect(s
, colour
, x
, y
, width
, height
) == 0) {
647 case SVGA_CMD_RECT_COPY
:
653 x
= vmsvga_fifo_read(s
);
654 y
= vmsvga_fifo_read(s
);
655 dx
= vmsvga_fifo_read(s
);
656 dy
= vmsvga_fifo_read(s
);
657 width
= vmsvga_fifo_read(s
);
658 height
= vmsvga_fifo_read(s
);
660 if (vmsvga_copy_rect(s
, x
, y
, dx
, dy
, width
, height
) == 0) {
667 case SVGA_CMD_DEFINE_CURSOR
:
673 cursor
.id
= vmsvga_fifo_read(s
);
674 cursor
.hot_x
= vmsvga_fifo_read(s
);
675 cursor
.hot_y
= vmsvga_fifo_read(s
);
676 cursor
.width
= x
= vmsvga_fifo_read(s
);
677 cursor
.height
= y
= vmsvga_fifo_read(s
);
679 cursor
.bpp
= vmsvga_fifo_read(s
);
681 args
= SVGA_BITMAP_SIZE(x
, y
) + SVGA_PIXMAP_SIZE(x
, y
, cursor
.bpp
);
682 if (cursor
.width
> 256
683 || cursor
.height
> 256
685 || SVGA_BITMAP_SIZE(x
, y
) > ARRAY_SIZE(cursor
.mask
)
686 || SVGA_PIXMAP_SIZE(x
, y
, cursor
.bpp
)
687 > ARRAY_SIZE(cursor
.image
)) {
696 for (args
= 0; args
< SVGA_BITMAP_SIZE(x
, y
); args
++) {
697 cursor
.mask
[args
] = vmsvga_fifo_read_raw(s
);
699 for (args
= 0; args
< SVGA_PIXMAP_SIZE(x
, y
, cursor
.bpp
); args
++) {
700 cursor
.image
[args
] = vmsvga_fifo_read_raw(s
);
702 #ifdef HW_MOUSE_ACCEL
703 vmsvga_cursor_define(s
, &cursor
);
711 * Other commands that we at least know the number of arguments
712 * for so we can avoid FIFO desync if driver uses them illegally.
714 case SVGA_CMD_DEFINE_ALPHA_CURSOR
:
722 x
= vmsvga_fifo_read(s
);
723 y
= vmsvga_fifo_read(s
);
726 case SVGA_CMD_RECT_ROP_FILL
:
729 case SVGA_CMD_RECT_ROP_COPY
:
732 case SVGA_CMD_DRAW_GLYPH_CLIPPED
:
739 args
= 7 + (vmsvga_fifo_read(s
) >> 2);
741 case SVGA_CMD_SURFACE_ALPHA_BLEND
:
746 * Other commands that are not listed as depending on any
747 * CAPABILITIES bits, but are not described in the README either.
749 case SVGA_CMD_SURFACE_FILL
:
750 case SVGA_CMD_SURFACE_COPY
:
751 case SVGA_CMD_FRONT_ROP_FILL
:
753 case SVGA_CMD_INVALID_CMD
:
766 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
771 s
->fifo_stop
= cmd_start
;
772 s
->fifo
[SVGA_FIFO_STOP
] = cpu_to_le32(s
->fifo_stop
);
780 static uint32_t vmsvga_index_read(void *opaque
, uint32_t address
)
782 struct vmsvga_state_s
*s
= opaque
;
787 static void vmsvga_index_write(void *opaque
, uint32_t address
, uint32_t index
)
789 struct vmsvga_state_s
*s
= opaque
;
794 static uint32_t vmsvga_value_read(void *opaque
, uint32_t address
)
797 struct vmsvga_state_s
*s
= opaque
;
798 DisplaySurface
*surface
= qemu_console_surface(s
->vga
.con
);
807 case SVGA_REG_ENABLE
:
812 ret
= s
->new_width
? s
->new_width
: surface_width(surface
);
815 case SVGA_REG_HEIGHT
:
816 ret
= s
->new_height
? s
->new_height
: surface_height(surface
);
819 case SVGA_REG_MAX_WIDTH
:
820 ret
= SVGA_MAX_WIDTH
;
823 case SVGA_REG_MAX_HEIGHT
:
824 ret
= SVGA_MAX_HEIGHT
;
828 ret
= (s
->new_depth
== 32) ? 24 : s
->new_depth
;
831 case SVGA_REG_BITS_PER_PIXEL
:
832 case SVGA_REG_HOST_BITS_PER_PIXEL
:
836 case SVGA_REG_PSEUDOCOLOR
:
840 case SVGA_REG_RED_MASK
:
841 pf
= qemu_default_pixelformat(s
->new_depth
);
845 case SVGA_REG_GREEN_MASK
:
846 pf
= qemu_default_pixelformat(s
->new_depth
);
850 case SVGA_REG_BLUE_MASK
:
851 pf
= qemu_default_pixelformat(s
->new_depth
);
855 case SVGA_REG_BYTES_PER_LINE
:
857 ret
= (s
->new_depth
* s
->new_width
) / 8;
859 ret
= surface_stride(surface
);
863 case SVGA_REG_FB_START
: {
864 struct pci_vmsvga_state_s
*pci_vmsvga
865 = container_of(s
, struct pci_vmsvga_state_s
, chip
);
866 ret
= pci_get_bar_addr(PCI_DEVICE(pci_vmsvga
), 1);
870 case SVGA_REG_FB_OFFSET
:
874 case SVGA_REG_VRAM_SIZE
:
875 ret
= s
->vga
.vram_size
; /* No physical VRAM besides the framebuffer */
878 case SVGA_REG_FB_SIZE
:
879 ret
= s
->vga
.vram_size
;
882 case SVGA_REG_CAPABILITIES
:
883 caps
= SVGA_CAP_NONE
;
885 caps
|= SVGA_CAP_RECT_COPY
;
888 caps
|= SVGA_CAP_RECT_FILL
;
890 #ifdef HW_MOUSE_ACCEL
891 if (dpy_cursor_define_supported(s
->vga
.con
)) {
892 caps
|= SVGA_CAP_CURSOR
| SVGA_CAP_CURSOR_BYPASS_2
|
893 SVGA_CAP_CURSOR_BYPASS
;
899 case SVGA_REG_MEM_START
: {
900 struct pci_vmsvga_state_s
*pci_vmsvga
901 = container_of(s
, struct pci_vmsvga_state_s
, chip
);
902 ret
= pci_get_bar_addr(PCI_DEVICE(pci_vmsvga
), 2);
906 case SVGA_REG_MEM_SIZE
:
910 case SVGA_REG_CONFIG_DONE
:
919 case SVGA_REG_GUEST_ID
:
923 case SVGA_REG_CURSOR_ID
:
927 case SVGA_REG_CURSOR_X
:
931 case SVGA_REG_CURSOR_Y
:
935 case SVGA_REG_CURSOR_ON
:
939 case SVGA_REG_SCRATCH_SIZE
:
940 ret
= s
->scratch_size
;
943 case SVGA_REG_MEM_REGS
:
944 case SVGA_REG_NUM_DISPLAYS
:
945 case SVGA_REG_PITCHLOCK
:
946 case SVGA_PALETTE_BASE
... SVGA_PALETTE_END
:
951 if (s
->index
>= SVGA_SCRATCH_BASE
&&
952 s
->index
< SVGA_SCRATCH_BASE
+ s
->scratch_size
) {
953 ret
= s
->scratch
[s
->index
- SVGA_SCRATCH_BASE
];
956 printf("%s: Bad register %02x\n", __func__
, s
->index
);
961 if (s
->index
>= SVGA_SCRATCH_BASE
) {
962 trace_vmware_scratch_read(s
->index
, ret
);
963 } else if (s
->index
>= SVGA_PALETTE_BASE
) {
964 trace_vmware_palette_read(s
->index
, ret
);
966 trace_vmware_value_read(s
->index
, ret
);
971 static void vmsvga_value_write(void *opaque
, uint32_t address
, uint32_t value
)
973 struct vmsvga_state_s
*s
= opaque
;
975 if (s
->index
>= SVGA_SCRATCH_BASE
) {
976 trace_vmware_scratch_write(s
->index
, value
);
977 } else if (s
->index
>= SVGA_PALETTE_BASE
) {
978 trace_vmware_palette_write(s
->index
, value
);
980 trace_vmware_value_write(s
->index
, value
);
984 if (value
== SVGA_ID_2
|| value
== SVGA_ID_1
|| value
== SVGA_ID_0
) {
989 case SVGA_REG_ENABLE
:
992 s
->vga
.hw_ops
->invalidate(&s
->vga
);
993 if (s
->enable
&& s
->config
) {
994 vga_dirty_log_stop(&s
->vga
);
996 vga_dirty_log_start(&s
->vga
);
1000 case SVGA_REG_WIDTH
:
1001 if (value
<= SVGA_MAX_WIDTH
) {
1002 s
->new_width
= value
;
1005 printf("%s: Bad width: %i\n", __func__
, value
);
1009 case SVGA_REG_HEIGHT
:
1010 if (value
<= SVGA_MAX_HEIGHT
) {
1011 s
->new_height
= value
;
1014 printf("%s: Bad height: %i\n", __func__
, value
);
1018 case SVGA_REG_BITS_PER_PIXEL
:
1020 printf("%s: Bad bits per pixel: %i bits\n", __func__
, value
);
1026 case SVGA_REG_CONFIG_DONE
:
1028 s
->fifo
= (uint32_t *) s
->fifo_ptr
;
1029 vga_dirty_log_stop(&s
->vga
);
1031 s
->config
= !!value
;
1036 vmsvga_fifo_run(s
); /* Or should we just wait for update_display? */
1039 case SVGA_REG_GUEST_ID
:
1042 if (value
>= GUEST_OS_BASE
&& value
< GUEST_OS_BASE
+
1043 ARRAY_SIZE(vmsvga_guest_id
)) {
1044 printf("%s: guest runs %s.\n", __func__
,
1045 vmsvga_guest_id
[value
- GUEST_OS_BASE
]);
1050 case SVGA_REG_CURSOR_ID
:
1051 s
->cursor
.id
= value
;
1054 case SVGA_REG_CURSOR_X
:
1055 s
->cursor
.x
= value
;
1058 case SVGA_REG_CURSOR_Y
:
1059 s
->cursor
.y
= value
;
1062 case SVGA_REG_CURSOR_ON
:
1063 s
->cursor
.on
|= (value
== SVGA_CURSOR_ON_SHOW
);
1064 s
->cursor
.on
&= (value
!= SVGA_CURSOR_ON_HIDE
);
1065 #ifdef HW_MOUSE_ACCEL
1066 if (value
<= SVGA_CURSOR_ON_SHOW
) {
1067 dpy_mouse_set(s
->vga
.con
, s
->cursor
.x
, s
->cursor
.y
, s
->cursor
.on
);
1072 case SVGA_REG_DEPTH
:
1073 case SVGA_REG_MEM_REGS
:
1074 case SVGA_REG_NUM_DISPLAYS
:
1075 case SVGA_REG_PITCHLOCK
:
1076 case SVGA_PALETTE_BASE
... SVGA_PALETTE_END
:
1080 if (s
->index
>= SVGA_SCRATCH_BASE
&&
1081 s
->index
< SVGA_SCRATCH_BASE
+ s
->scratch_size
) {
1082 s
->scratch
[s
->index
- SVGA_SCRATCH_BASE
] = value
;
1085 printf("%s: Bad register %02x\n", __func__
, s
->index
);
1089 static uint32_t vmsvga_bios_read(void *opaque
, uint32_t address
)
1091 printf("%s: what are we supposed to return?\n", __func__
);
1095 static void vmsvga_bios_write(void *opaque
, uint32_t address
, uint32_t data
)
1097 printf("%s: what are we supposed to do with (%08x)?\n", __func__
, data
);
1100 static inline void vmsvga_check_size(struct vmsvga_state_s
*s
)
1102 DisplaySurface
*surface
= qemu_console_surface(s
->vga
.con
);
1104 if (s
->new_width
!= surface_width(surface
) ||
1105 s
->new_height
!= surface_height(surface
) ||
1106 s
->new_depth
!= surface_bits_per_pixel(surface
)) {
1107 int stride
= (s
->new_depth
* s
->new_width
) / 8;
1108 pixman_format_code_t format
=
1109 qemu_default_pixman_format(s
->new_depth
, true);
1110 trace_vmware_setmode(s
->new_width
, s
->new_height
, s
->new_depth
);
1111 surface
= qemu_create_displaysurface_from(s
->new_width
, s
->new_height
,
1114 dpy_gfx_replace_surface(s
->vga
.con
, surface
);
1119 static void vmsvga_update_display(void *opaque
)
1121 struct vmsvga_state_s
*s
= opaque
;
1123 if (!s
->enable
|| !s
->config
) {
1124 /* in standard vga mode */
1125 s
->vga
.hw_ops
->gfx_update(&s
->vga
);
1129 vmsvga_check_size(s
);
1132 vmsvga_update_rect_flush(s
);
1134 if (s
->invalidated
) {
1136 dpy_gfx_update_full(s
->vga
.con
);
1140 static void vmsvga_reset(DeviceState
*dev
)
1142 struct pci_vmsvga_state_s
*pci
= VMWARE_SVGA(dev
);
1143 struct vmsvga_state_s
*s
= &pci
->chip
;
1148 s
->svgaid
= SVGA_ID
;
1150 s
->redraw_fifo_first
= 0;
1151 s
->redraw_fifo_last
= 0;
1154 vga_dirty_log_start(&s
->vga
);
1157 static void vmsvga_invalidate_display(void *opaque
)
1159 struct vmsvga_state_s
*s
= opaque
;
1161 s
->vga
.hw_ops
->invalidate(&s
->vga
);
1168 static void vmsvga_text_update(void *opaque
, console_ch_t
*chardata
)
1170 struct vmsvga_state_s
*s
= opaque
;
1172 if (s
->vga
.hw_ops
->text_update
) {
1173 s
->vga
.hw_ops
->text_update(&s
->vga
, chardata
);
1177 static int vmsvga_post_load(void *opaque
, int version_id
)
1179 struct vmsvga_state_s
*s
= opaque
;
1183 s
->fifo
= (uint32_t *) s
->fifo_ptr
;
1188 static const VMStateDescription vmstate_vmware_vga_internal
= {
1189 .name
= "vmware_vga_internal",
1191 .minimum_version_id
= 0,
1192 .post_load
= vmsvga_post_load
,
1193 .fields
= (VMStateField
[]) {
1194 VMSTATE_INT32_EQUAL(new_depth
, struct vmsvga_state_s
, NULL
),
1195 VMSTATE_INT32(enable
, struct vmsvga_state_s
),
1196 VMSTATE_INT32(config
, struct vmsvga_state_s
),
1197 VMSTATE_INT32(cursor
.id
, struct vmsvga_state_s
),
1198 VMSTATE_INT32(cursor
.x
, struct vmsvga_state_s
),
1199 VMSTATE_INT32(cursor
.y
, struct vmsvga_state_s
),
1200 VMSTATE_INT32(cursor
.on
, struct vmsvga_state_s
),
1201 VMSTATE_INT32(index
, struct vmsvga_state_s
),
1202 VMSTATE_VARRAY_INT32(scratch
, struct vmsvga_state_s
,
1203 scratch_size
, 0, vmstate_info_uint32
, uint32_t),
1204 VMSTATE_INT32(new_width
, struct vmsvga_state_s
),
1205 VMSTATE_INT32(new_height
, struct vmsvga_state_s
),
1206 VMSTATE_UINT32(guest
, struct vmsvga_state_s
),
1207 VMSTATE_UINT32(svgaid
, struct vmsvga_state_s
),
1208 VMSTATE_INT32(syncing
, struct vmsvga_state_s
),
1209 VMSTATE_UNUSED(4), /* was fb_size */
1210 VMSTATE_END_OF_LIST()
1214 static const VMStateDescription vmstate_vmware_vga
= {
1215 .name
= "vmware_vga",
1217 .minimum_version_id
= 0,
1218 .fields
= (VMStateField
[]) {
1219 VMSTATE_PCI_DEVICE(parent_obj
, struct pci_vmsvga_state_s
),
1220 VMSTATE_STRUCT(chip
, struct pci_vmsvga_state_s
, 0,
1221 vmstate_vmware_vga_internal
, struct vmsvga_state_s
),
1222 VMSTATE_END_OF_LIST()
1226 static const GraphicHwOps vmsvga_ops
= {
1227 .invalidate
= vmsvga_invalidate_display
,
1228 .gfx_update
= vmsvga_update_display
,
1229 .text_update
= vmsvga_text_update
,
1232 static void vmsvga_init(DeviceState
*dev
, struct vmsvga_state_s
*s
,
1233 MemoryRegion
*address_space
, MemoryRegion
*io
)
1235 s
->scratch_size
= SVGA_SCRATCH_SIZE
;
1236 s
->scratch
= g_malloc(s
->scratch_size
* 4);
1238 s
->vga
.con
= graphic_console_init(dev
, 0, &vmsvga_ops
, s
);
1240 s
->fifo_size
= SVGA_FIFO_SIZE
;
1241 memory_region_init_ram(&s
->fifo_ram
, NULL
, "vmsvga.fifo", s
->fifo_size
,
1243 s
->fifo_ptr
= memory_region_get_ram_ptr(&s
->fifo_ram
);
1245 vga_common_init(&s
->vga
, OBJECT(dev
));
1246 vga_init(&s
->vga
, OBJECT(dev
), address_space
, io
, true);
1247 vmstate_register(NULL
, 0, &vmstate_vga_common
, &s
->vga
);
1251 static uint64_t vmsvga_io_read(void *opaque
, hwaddr addr
, unsigned size
)
1253 struct vmsvga_state_s
*s
= opaque
;
1256 case SVGA_IO_MUL
* SVGA_INDEX_PORT
: return vmsvga_index_read(s
, addr
);
1257 case SVGA_IO_MUL
* SVGA_VALUE_PORT
: return vmsvga_value_read(s
, addr
);
1258 case SVGA_IO_MUL
* SVGA_BIOS_PORT
: return vmsvga_bios_read(s
, addr
);
1259 default: return -1u;
1263 static void vmsvga_io_write(void *opaque
, hwaddr addr
,
1264 uint64_t data
, unsigned size
)
1266 struct vmsvga_state_s
*s
= opaque
;
1269 case SVGA_IO_MUL
* SVGA_INDEX_PORT
:
1270 vmsvga_index_write(s
, addr
, data
);
1272 case SVGA_IO_MUL
* SVGA_VALUE_PORT
:
1273 vmsvga_value_write(s
, addr
, data
);
1275 case SVGA_IO_MUL
* SVGA_BIOS_PORT
:
1276 vmsvga_bios_write(s
, addr
, data
);
1281 static const MemoryRegionOps vmsvga_io_ops
= {
1282 .read
= vmsvga_io_read
,
1283 .write
= vmsvga_io_write
,
1284 .endianness
= DEVICE_LITTLE_ENDIAN
,
1286 .min_access_size
= 4,
1287 .max_access_size
= 4,
1295 static void pci_vmsvga_realize(PCIDevice
*dev
, Error
**errp
)
1297 struct pci_vmsvga_state_s
*s
= VMWARE_SVGA(dev
);
1299 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x08;
1300 dev
->config
[PCI_LATENCY_TIMER
] = 0x40;
1301 dev
->config
[PCI_INTERRUPT_LINE
] = 0xff; /* End */
1303 memory_region_init_io(&s
->io_bar
, NULL
, &vmsvga_io_ops
, &s
->chip
,
1305 memory_region_set_flush_coalesced(&s
->io_bar
);
1306 pci_register_bar(dev
, 0, PCI_BASE_ADDRESS_SPACE_IO
, &s
->io_bar
);
1308 vmsvga_init(DEVICE(dev
), &s
->chip
,
1309 pci_address_space(dev
), pci_address_space_io(dev
));
1311 pci_register_bar(dev
, 1, PCI_BASE_ADDRESS_MEM_PREFETCH
,
1313 pci_register_bar(dev
, 2, PCI_BASE_ADDRESS_MEM_PREFETCH
,
1316 if (!dev
->rom_bar
) {
1317 /* compatibility with pc-0.13 and older */
1318 vga_init_vbe(&s
->chip
.vga
, OBJECT(dev
), pci_address_space(dev
));
1322 static Property vga_vmware_properties
[] = {
1323 DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s
,
1324 chip
.vga
.vram_size_mb
, 16),
1325 DEFINE_PROP_BOOL("global-vmstate", struct pci_vmsvga_state_s
,
1326 chip
.vga
.global_vmstate
, false),
1327 DEFINE_PROP_END_OF_LIST(),
1330 static void vmsvga_class_init(ObjectClass
*klass
, void *data
)
1332 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1333 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1335 k
->realize
= pci_vmsvga_realize
;
1336 k
->romfile
= "vgabios-vmware.bin";
1337 k
->vendor_id
= PCI_VENDOR_ID_VMWARE
;
1338 k
->device_id
= SVGA_PCI_DEVICE_ID
;
1339 k
->class_id
= PCI_CLASS_DISPLAY_VGA
;
1340 k
->subsystem_vendor_id
= PCI_VENDOR_ID_VMWARE
;
1341 k
->subsystem_id
= SVGA_PCI_DEVICE_ID
;
1342 dc
->reset
= vmsvga_reset
;
1343 dc
->vmsd
= &vmstate_vmware_vga
;
1344 dc
->props
= vga_vmware_properties
;
1345 dc
->hotpluggable
= false;
1346 set_bit(DEVICE_CATEGORY_DISPLAY
, dc
->categories
);
1349 static const TypeInfo vmsvga_info
= {
1350 .name
= TYPE_VMWARE_SVGA
,
1351 .parent
= TYPE_PCI_DEVICE
,
1352 .instance_size
= sizeof(struct pci_vmsvga_state_s
),
1353 .class_init
= vmsvga_class_init
,
1354 .interfaces
= (InterfaceInfo
[]) {
1355 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
1360 static void vmsvga_register_types(void)
1362 type_register_static(&vmsvga_info
);
1365 type_init(vmsvga_register_types
)