2 * QEMU VMware-SVGA "chipset".
4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/module.h"
27 #include "qemu/units.h"
28 #include "qapi/error.h"
30 #include "hw/loader.h"
33 #include "hw/pci/pci.h"
34 #include "hw/qdev-properties.h"
35 #include "migration/vmstate.h"
40 #define HW_MOUSE_ACCEL
44 /* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */
46 struct vmsvga_state_s
{
69 MemoryRegion fifo_ram
;
71 unsigned int fifo_size
;
79 #define REDRAW_FIFO_LEN 512
80 struct vmsvga_rect_s
{
82 } redraw_fifo
[REDRAW_FIFO_LEN
];
83 int redraw_fifo_first
, redraw_fifo_last
;
86 #define TYPE_VMWARE_SVGA "vmware-svga"
88 #define VMWARE_SVGA(obj) \
89 OBJECT_CHECK(struct pci_vmsvga_state_s, (obj), TYPE_VMWARE_SVGA)
91 struct pci_vmsvga_state_s
{
96 struct vmsvga_state_s chip
;
100 #define SVGA_MAGIC 0x900000UL
101 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
102 #define SVGA_ID_0 SVGA_MAKE_ID(0)
103 #define SVGA_ID_1 SVGA_MAKE_ID(1)
104 #define SVGA_ID_2 SVGA_MAKE_ID(2)
106 #define SVGA_LEGACY_BASE_PORT 0x4560
107 #define SVGA_INDEX_PORT 0x0
108 #define SVGA_VALUE_PORT 0x1
109 #define SVGA_BIOS_PORT 0x2
111 #define SVGA_VERSION_2
113 #ifdef SVGA_VERSION_2
114 # define SVGA_ID SVGA_ID_2
115 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
116 # define SVGA_IO_MUL 1
117 # define SVGA_FIFO_SIZE 0x10000
118 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
120 # define SVGA_ID SVGA_ID_1
121 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
122 # define SVGA_IO_MUL 4
123 # define SVGA_FIFO_SIZE 0x10000
124 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
128 /* ID 0, 1 and 2 registers */
133 SVGA_REG_MAX_WIDTH
= 4,
134 SVGA_REG_MAX_HEIGHT
= 5,
136 SVGA_REG_BITS_PER_PIXEL
= 7, /* Current bpp in the guest */
137 SVGA_REG_PSEUDOCOLOR
= 8,
138 SVGA_REG_RED_MASK
= 9,
139 SVGA_REG_GREEN_MASK
= 10,
140 SVGA_REG_BLUE_MASK
= 11,
141 SVGA_REG_BYTES_PER_LINE
= 12,
142 SVGA_REG_FB_START
= 13,
143 SVGA_REG_FB_OFFSET
= 14,
144 SVGA_REG_VRAM_SIZE
= 15,
145 SVGA_REG_FB_SIZE
= 16,
147 /* ID 1 and 2 registers */
148 SVGA_REG_CAPABILITIES
= 17,
149 SVGA_REG_MEM_START
= 18, /* Memory for command FIFO */
150 SVGA_REG_MEM_SIZE
= 19,
151 SVGA_REG_CONFIG_DONE
= 20, /* Set when memory area configured */
152 SVGA_REG_SYNC
= 21, /* Write to force synchronization */
153 SVGA_REG_BUSY
= 22, /* Read to check if sync is done */
154 SVGA_REG_GUEST_ID
= 23, /* Set guest OS identifier */
155 SVGA_REG_CURSOR_ID
= 24, /* ID of cursor */
156 SVGA_REG_CURSOR_X
= 25, /* Set cursor X position */
157 SVGA_REG_CURSOR_Y
= 26, /* Set cursor Y position */
158 SVGA_REG_CURSOR_ON
= 27, /* Turn cursor on/off */
159 SVGA_REG_HOST_BITS_PER_PIXEL
= 28, /* Current bpp in the host */
160 SVGA_REG_SCRATCH_SIZE
= 29, /* Number of scratch registers */
161 SVGA_REG_MEM_REGS
= 30, /* Number of FIFO registers */
162 SVGA_REG_NUM_DISPLAYS
= 31, /* Number of guest displays */
163 SVGA_REG_PITCHLOCK
= 32, /* Fixed pitch for all modes */
165 SVGA_PALETTE_BASE
= 1024, /* Base of SVGA color map */
166 SVGA_PALETTE_END
= SVGA_PALETTE_BASE
+ 767,
167 SVGA_SCRATCH_BASE
= SVGA_PALETTE_BASE
+ 768,
170 #define SVGA_CAP_NONE 0
171 #define SVGA_CAP_RECT_FILL (1 << 0)
172 #define SVGA_CAP_RECT_COPY (1 << 1)
173 #define SVGA_CAP_RECT_PAT_FILL (1 << 2)
174 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
175 #define SVGA_CAP_RASTER_OP (1 << 4)
176 #define SVGA_CAP_CURSOR (1 << 5)
177 #define SVGA_CAP_CURSOR_BYPASS (1 << 6)
178 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
179 #define SVGA_CAP_8BIT_EMULATION (1 << 8)
180 #define SVGA_CAP_ALPHA_CURSOR (1 << 9)
181 #define SVGA_CAP_GLYPH (1 << 10)
182 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
183 #define SVGA_CAP_OFFSCREEN_1 (1 << 12)
184 #define SVGA_CAP_ALPHA_BLEND (1 << 13)
185 #define SVGA_CAP_3D (1 << 14)
186 #define SVGA_CAP_EXTENDED_FIFO (1 << 15)
187 #define SVGA_CAP_MULTIMON (1 << 16)
188 #define SVGA_CAP_PITCHLOCK (1 << 17)
191 * FIFO offsets (seen as an array of 32-bit words)
195 * The original defined FIFO offsets
198 SVGA_FIFO_MAX
, /* The distance from MIN to MAX must be at least 10K */
203 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
205 SVGA_FIFO_CAPABILITIES
= 4,
208 SVGA_FIFO_3D_HWVERSION
,
212 #define SVGA_FIFO_CAP_NONE 0
213 #define SVGA_FIFO_CAP_FENCE (1 << 0)
214 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
215 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
217 #define SVGA_FIFO_FLAG_NONE 0
218 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
220 /* These values can probably be changed arbitrarily. */
221 #define SVGA_SCRATCH_SIZE 0x8000
222 #define SVGA_MAX_WIDTH ROUND_UP(2360, VNC_DIRTY_PIXELS_PER_BIT)
223 #define SVGA_MAX_HEIGHT 1770
226 # define GUEST_OS_BASE 0x5001
227 static const char *vmsvga_guest_id
[] = {
229 [0x01] = "Windows 3.1",
230 [0x02] = "Windows 95",
231 [0x03] = "Windows 98",
232 [0x04] = "Windows ME",
233 [0x05] = "Windows NT",
234 [0x06] = "Windows 2000",
237 [0x09] = "an unknown OS",
240 [0x0c] = "an unknown OS",
241 [0x0d] = "an unknown OS",
242 [0x0e] = "an unknown OS",
243 [0x0f] = "an unknown OS",
244 [0x10] = "an unknown OS",
245 [0x11] = "an unknown OS",
246 [0x12] = "an unknown OS",
247 [0x13] = "an unknown OS",
248 [0x14] = "an unknown OS",
249 [0x15] = "Windows 2003",
254 SVGA_CMD_INVALID_CMD
= 0,
256 SVGA_CMD_RECT_FILL
= 2,
257 SVGA_CMD_RECT_COPY
= 3,
258 SVGA_CMD_DEFINE_BITMAP
= 4,
259 SVGA_CMD_DEFINE_BITMAP_SCANLINE
= 5,
260 SVGA_CMD_DEFINE_PIXMAP
= 6,
261 SVGA_CMD_DEFINE_PIXMAP_SCANLINE
= 7,
262 SVGA_CMD_RECT_BITMAP_FILL
= 8,
263 SVGA_CMD_RECT_PIXMAP_FILL
= 9,
264 SVGA_CMD_RECT_BITMAP_COPY
= 10,
265 SVGA_CMD_RECT_PIXMAP_COPY
= 11,
266 SVGA_CMD_FREE_OBJECT
= 12,
267 SVGA_CMD_RECT_ROP_FILL
= 13,
268 SVGA_CMD_RECT_ROP_COPY
= 14,
269 SVGA_CMD_RECT_ROP_BITMAP_FILL
= 15,
270 SVGA_CMD_RECT_ROP_PIXMAP_FILL
= 16,
271 SVGA_CMD_RECT_ROP_BITMAP_COPY
= 17,
272 SVGA_CMD_RECT_ROP_PIXMAP_COPY
= 18,
273 SVGA_CMD_DEFINE_CURSOR
= 19,
274 SVGA_CMD_DISPLAY_CURSOR
= 20,
275 SVGA_CMD_MOVE_CURSOR
= 21,
276 SVGA_CMD_DEFINE_ALPHA_CURSOR
= 22,
277 SVGA_CMD_DRAW_GLYPH
= 23,
278 SVGA_CMD_DRAW_GLYPH_CLIPPED
= 24,
279 SVGA_CMD_UPDATE_VERBOSE
= 25,
280 SVGA_CMD_SURFACE_FILL
= 26,
281 SVGA_CMD_SURFACE_COPY
= 27,
282 SVGA_CMD_SURFACE_ALPHA_BLEND
= 28,
283 SVGA_CMD_FRONT_ROP_FILL
= 29,
287 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
289 SVGA_CURSOR_ON_HIDE
= 0,
290 SVGA_CURSOR_ON_SHOW
= 1,
291 SVGA_CURSOR_ON_REMOVE_FROM_FB
= 2,
292 SVGA_CURSOR_ON_RESTORE_TO_FB
= 3,
295 static inline bool vmsvga_verify_rect(DisplaySurface
*surface
,
297 int x
, int y
, int w
, int h
)
300 fprintf(stderr
, "%s: x was < 0 (%d)\n", name
, x
);
303 if (x
> SVGA_MAX_WIDTH
) {
304 fprintf(stderr
, "%s: x was > %d (%d)\n", name
, SVGA_MAX_WIDTH
, x
);
308 fprintf(stderr
, "%s: w was < 0 (%d)\n", name
, w
);
311 if (w
> SVGA_MAX_WIDTH
) {
312 fprintf(stderr
, "%s: w was > %d (%d)\n", name
, SVGA_MAX_WIDTH
, w
);
315 if (x
+ w
> surface_width(surface
)) {
316 fprintf(stderr
, "%s: width was > %d (x: %d, w: %d)\n",
317 name
, surface_width(surface
), x
, w
);
322 fprintf(stderr
, "%s: y was < 0 (%d)\n", name
, y
);
325 if (y
> SVGA_MAX_HEIGHT
) {
326 fprintf(stderr
, "%s: y was > %d (%d)\n", name
, SVGA_MAX_HEIGHT
, y
);
330 fprintf(stderr
, "%s: h was < 0 (%d)\n", name
, h
);
333 if (h
> SVGA_MAX_HEIGHT
) {
334 fprintf(stderr
, "%s: h was > %d (%d)\n", name
, SVGA_MAX_HEIGHT
, h
);
337 if (y
+ h
> surface_height(surface
)) {
338 fprintf(stderr
, "%s: update height > %d (y: %d, h: %d)\n",
339 name
, surface_height(surface
), y
, h
);
346 static inline void vmsvga_update_rect(struct vmsvga_state_s
*s
,
347 int x
, int y
, int w
, int h
)
349 DisplaySurface
*surface
= qemu_console_surface(s
->vga
.con
);
357 if (!vmsvga_verify_rect(surface
, __func__
, x
, y
, w
, h
)) {
358 /* go for a fullscreen update as fallback */
361 w
= surface_width(surface
);
362 h
= surface_height(surface
);
365 bypl
= surface_stride(surface
);
366 width
= surface_bytes_per_pixel(surface
) * w
;
367 start
= surface_bytes_per_pixel(surface
) * x
+ bypl
* y
;
368 src
= s
->vga
.vram_ptr
+ start
;
369 dst
= surface_data(surface
) + start
;
371 for (line
= h
; line
> 0; line
--, src
+= bypl
, dst
+= bypl
) {
372 memcpy(dst
, src
, width
);
374 dpy_gfx_update(s
->vga
.con
, x
, y
, w
, h
);
377 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s
*s
,
378 int x
, int y
, int w
, int h
)
380 struct vmsvga_rect_s
*rect
= &s
->redraw_fifo
[s
->redraw_fifo_last
++];
382 s
->redraw_fifo_last
&= REDRAW_FIFO_LEN
- 1;
389 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s
*s
)
391 struct vmsvga_rect_s
*rect
;
393 if (s
->invalidated
) {
394 s
->redraw_fifo_first
= s
->redraw_fifo_last
;
397 /* Overlapping region updates can be optimised out here - if someone
398 * knows a smart algorithm to do that, please share. */
399 while (s
->redraw_fifo_first
!= s
->redraw_fifo_last
) {
400 rect
= &s
->redraw_fifo
[s
->redraw_fifo_first
++];
401 s
->redraw_fifo_first
&= REDRAW_FIFO_LEN
- 1;
402 vmsvga_update_rect(s
, rect
->x
, rect
->y
, rect
->w
, rect
->h
);
407 static inline int vmsvga_copy_rect(struct vmsvga_state_s
*s
,
408 int x0
, int y0
, int x1
, int y1
, int w
, int h
)
410 DisplaySurface
*surface
= qemu_console_surface(s
->vga
.con
);
411 uint8_t *vram
= s
->vga
.vram_ptr
;
412 int bypl
= surface_stride(surface
);
413 int bypp
= surface_bytes_per_pixel(surface
);
414 int width
= bypp
* w
;
418 if (!vmsvga_verify_rect(surface
, "vmsvga_copy_rect/src", x0
, y0
, w
, h
)) {
421 if (!vmsvga_verify_rect(surface
, "vmsvga_copy_rect/dst", x1
, y1
, w
, h
)) {
426 ptr
[0] = vram
+ bypp
* x0
+ bypl
* (y0
+ h
- 1);
427 ptr
[1] = vram
+ bypp
* x1
+ bypl
* (y1
+ h
- 1);
428 for (; line
> 0; line
--, ptr
[0] -= bypl
, ptr
[1] -= bypl
) {
429 memmove(ptr
[1], ptr
[0], width
);
432 ptr
[0] = vram
+ bypp
* x0
+ bypl
* y0
;
433 ptr
[1] = vram
+ bypp
* x1
+ bypl
* y1
;
434 for (; line
> 0; line
--, ptr
[0] += bypl
, ptr
[1] += bypl
) {
435 memmove(ptr
[1], ptr
[0], width
);
439 vmsvga_update_rect_delayed(s
, x1
, y1
, w
, h
);
445 static inline int vmsvga_fill_rect(struct vmsvga_state_s
*s
,
446 uint32_t c
, int x
, int y
, int w
, int h
)
448 DisplaySurface
*surface
= qemu_console_surface(s
->vga
.con
);
449 int bypl
= surface_stride(surface
);
450 int width
= surface_bytes_per_pixel(surface
) * w
;
458 if (!vmsvga_verify_rect(surface
, __func__
, x
, y
, w
, h
)) {
467 fst
= s
->vga
.vram_ptr
+ surface_bytes_per_pixel(surface
) * x
+ bypl
* y
;
472 for (column
= width
; column
> 0; column
--) {
474 if (src
- col
== surface_bytes_per_pixel(surface
)) {
479 for (; line
> 0; line
--) {
481 memcpy(dst
, fst
, width
);
485 vmsvga_update_rect_delayed(s
, x
, y
, w
, h
);
490 struct vmsvga_cursor_definition_s
{
498 uint32_t image
[4096];
501 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
502 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
504 #ifdef HW_MOUSE_ACCEL
505 static inline void vmsvga_cursor_define(struct vmsvga_state_s
*s
,
506 struct vmsvga_cursor_definition_s
*c
)
511 qc
= cursor_alloc(c
->width
, c
->height
);
512 qc
->hot_x
= c
->hot_x
;
513 qc
->hot_y
= c
->hot_y
;
516 cursor_set_mono(qc
, 0xffffff, 0x000000, (void *)c
->image
,
519 cursor_print_ascii_art(qc
, "vmware/mono");
523 /* fill alpha channel from mask, set color to zero */
524 cursor_set_mono(qc
, 0x000000, 0x000000, (void *)c
->mask
,
526 /* add in rgb values */
527 pixels
= c
->width
* c
->height
;
528 for (i
= 0; i
< pixels
; i
++) {
529 qc
->data
[i
] |= c
->image
[i
] & 0xffffff;
532 cursor_print_ascii_art(qc
, "vmware/32bit");
536 fprintf(stderr
, "%s: unhandled bpp %d, using fallback cursor\n",
539 qc
= cursor_builtin_left_ptr();
542 dpy_cursor_define(s
->vga
.con
, qc
);
547 static inline int vmsvga_fifo_length(struct vmsvga_state_s
*s
)
551 if (!s
->config
|| !s
->enable
) {
555 s
->fifo_min
= le32_to_cpu(s
->fifo
[SVGA_FIFO_MIN
]);
556 s
->fifo_max
= le32_to_cpu(s
->fifo
[SVGA_FIFO_MAX
]);
557 s
->fifo_next
= le32_to_cpu(s
->fifo
[SVGA_FIFO_NEXT
]);
558 s
->fifo_stop
= le32_to_cpu(s
->fifo
[SVGA_FIFO_STOP
]);
560 /* Check range and alignment. */
561 if ((s
->fifo_min
| s
->fifo_max
| s
->fifo_next
| s
->fifo_stop
) & 3) {
564 if (s
->fifo_min
< sizeof(uint32_t) * 4) {
567 if (s
->fifo_max
> SVGA_FIFO_SIZE
||
568 s
->fifo_min
>= SVGA_FIFO_SIZE
||
569 s
->fifo_stop
>= SVGA_FIFO_SIZE
||
570 s
->fifo_next
>= SVGA_FIFO_SIZE
) {
573 if (s
->fifo_max
< s
->fifo_min
+ 10 * KiB
) {
577 num
= s
->fifo_next
- s
->fifo_stop
;
579 num
+= s
->fifo_max
- s
->fifo_min
;
584 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s
*s
)
586 uint32_t cmd
= s
->fifo
[s
->fifo_stop
>> 2];
589 if (s
->fifo_stop
>= s
->fifo_max
) {
590 s
->fifo_stop
= s
->fifo_min
;
592 s
->fifo
[SVGA_FIFO_STOP
] = cpu_to_le32(s
->fifo_stop
);
596 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s
*s
)
598 return le32_to_cpu(vmsvga_fifo_read_raw(s
));
601 static void vmsvga_fifo_run(struct vmsvga_state_s
*s
)
603 uint32_t cmd
, colour
;
604 int args
, len
, maxloop
= 1024;
605 int x
, y
, dx
, dy
, width
, height
;
606 struct vmsvga_cursor_definition_s cursor
;
609 len
= vmsvga_fifo_length(s
);
610 while (len
> 0 && --maxloop
> 0) {
611 /* May need to go back to the start of the command if incomplete */
612 cmd_start
= s
->fifo_stop
;
614 switch (cmd
= vmsvga_fifo_read(s
)) {
615 case SVGA_CMD_UPDATE
:
616 case SVGA_CMD_UPDATE_VERBOSE
:
622 x
= vmsvga_fifo_read(s
);
623 y
= vmsvga_fifo_read(s
);
624 width
= vmsvga_fifo_read(s
);
625 height
= vmsvga_fifo_read(s
);
626 vmsvga_update_rect_delayed(s
, x
, y
, width
, height
);
629 case SVGA_CMD_RECT_FILL
:
635 colour
= vmsvga_fifo_read(s
);
636 x
= vmsvga_fifo_read(s
);
637 y
= vmsvga_fifo_read(s
);
638 width
= vmsvga_fifo_read(s
);
639 height
= vmsvga_fifo_read(s
);
641 if (vmsvga_fill_rect(s
, colour
, x
, y
, width
, height
) == 0) {
648 case SVGA_CMD_RECT_COPY
:
654 x
= vmsvga_fifo_read(s
);
655 y
= vmsvga_fifo_read(s
);
656 dx
= vmsvga_fifo_read(s
);
657 dy
= vmsvga_fifo_read(s
);
658 width
= vmsvga_fifo_read(s
);
659 height
= vmsvga_fifo_read(s
);
661 if (vmsvga_copy_rect(s
, x
, y
, dx
, dy
, width
, height
) == 0) {
668 case SVGA_CMD_DEFINE_CURSOR
:
674 cursor
.id
= vmsvga_fifo_read(s
);
675 cursor
.hot_x
= vmsvga_fifo_read(s
);
676 cursor
.hot_y
= vmsvga_fifo_read(s
);
677 cursor
.width
= x
= vmsvga_fifo_read(s
);
678 cursor
.height
= y
= vmsvga_fifo_read(s
);
680 cursor
.bpp
= vmsvga_fifo_read(s
);
682 args
= SVGA_BITMAP_SIZE(x
, y
) + SVGA_PIXMAP_SIZE(x
, y
, cursor
.bpp
);
683 if (cursor
.width
> 256
684 || cursor
.height
> 256
686 || SVGA_BITMAP_SIZE(x
, y
) > ARRAY_SIZE(cursor
.mask
)
687 || SVGA_PIXMAP_SIZE(x
, y
, cursor
.bpp
)
688 > ARRAY_SIZE(cursor
.image
)) {
697 for (args
= 0; args
< SVGA_BITMAP_SIZE(x
, y
); args
++) {
698 cursor
.mask
[args
] = vmsvga_fifo_read_raw(s
);
700 for (args
= 0; args
< SVGA_PIXMAP_SIZE(x
, y
, cursor
.bpp
); args
++) {
701 cursor
.image
[args
] = vmsvga_fifo_read_raw(s
);
703 #ifdef HW_MOUSE_ACCEL
704 vmsvga_cursor_define(s
, &cursor
);
712 * Other commands that we at least know the number of arguments
713 * for so we can avoid FIFO desync if driver uses them illegally.
715 case SVGA_CMD_DEFINE_ALPHA_CURSOR
:
723 x
= vmsvga_fifo_read(s
);
724 y
= vmsvga_fifo_read(s
);
727 case SVGA_CMD_RECT_ROP_FILL
:
730 case SVGA_CMD_RECT_ROP_COPY
:
733 case SVGA_CMD_DRAW_GLYPH_CLIPPED
:
740 args
= 7 + (vmsvga_fifo_read(s
) >> 2);
742 case SVGA_CMD_SURFACE_ALPHA_BLEND
:
747 * Other commands that are not listed as depending on any
748 * CAPABILITIES bits, but are not described in the README either.
750 case SVGA_CMD_SURFACE_FILL
:
751 case SVGA_CMD_SURFACE_COPY
:
752 case SVGA_CMD_FRONT_ROP_FILL
:
754 case SVGA_CMD_INVALID_CMD
:
767 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
772 s
->fifo_stop
= cmd_start
;
773 s
->fifo
[SVGA_FIFO_STOP
] = cpu_to_le32(s
->fifo_stop
);
781 static uint32_t vmsvga_index_read(void *opaque
, uint32_t address
)
783 struct vmsvga_state_s
*s
= opaque
;
788 static void vmsvga_index_write(void *opaque
, uint32_t address
, uint32_t index
)
790 struct vmsvga_state_s
*s
= opaque
;
795 static uint32_t vmsvga_value_read(void *opaque
, uint32_t address
)
798 struct vmsvga_state_s
*s
= opaque
;
799 DisplaySurface
*surface
= qemu_console_surface(s
->vga
.con
);
808 case SVGA_REG_ENABLE
:
813 ret
= s
->new_width
? s
->new_width
: surface_width(surface
);
816 case SVGA_REG_HEIGHT
:
817 ret
= s
->new_height
? s
->new_height
: surface_height(surface
);
820 case SVGA_REG_MAX_WIDTH
:
821 ret
= SVGA_MAX_WIDTH
;
824 case SVGA_REG_MAX_HEIGHT
:
825 ret
= SVGA_MAX_HEIGHT
;
829 ret
= (s
->new_depth
== 32) ? 24 : s
->new_depth
;
832 case SVGA_REG_BITS_PER_PIXEL
:
833 case SVGA_REG_HOST_BITS_PER_PIXEL
:
837 case SVGA_REG_PSEUDOCOLOR
:
841 case SVGA_REG_RED_MASK
:
842 pf
= qemu_default_pixelformat(s
->new_depth
);
846 case SVGA_REG_GREEN_MASK
:
847 pf
= qemu_default_pixelformat(s
->new_depth
);
851 case SVGA_REG_BLUE_MASK
:
852 pf
= qemu_default_pixelformat(s
->new_depth
);
856 case SVGA_REG_BYTES_PER_LINE
:
858 ret
= (s
->new_depth
* s
->new_width
) / 8;
860 ret
= surface_stride(surface
);
864 case SVGA_REG_FB_START
: {
865 struct pci_vmsvga_state_s
*pci_vmsvga
866 = container_of(s
, struct pci_vmsvga_state_s
, chip
);
867 ret
= pci_get_bar_addr(PCI_DEVICE(pci_vmsvga
), 1);
871 case SVGA_REG_FB_OFFSET
:
875 case SVGA_REG_VRAM_SIZE
:
876 ret
= s
->vga
.vram_size
; /* No physical VRAM besides the framebuffer */
879 case SVGA_REG_FB_SIZE
:
880 ret
= s
->vga
.vram_size
;
883 case SVGA_REG_CAPABILITIES
:
884 caps
= SVGA_CAP_NONE
;
886 caps
|= SVGA_CAP_RECT_COPY
;
889 caps
|= SVGA_CAP_RECT_FILL
;
891 #ifdef HW_MOUSE_ACCEL
892 if (dpy_cursor_define_supported(s
->vga
.con
)) {
893 caps
|= SVGA_CAP_CURSOR
| SVGA_CAP_CURSOR_BYPASS_2
|
894 SVGA_CAP_CURSOR_BYPASS
;
900 case SVGA_REG_MEM_START
: {
901 struct pci_vmsvga_state_s
*pci_vmsvga
902 = container_of(s
, struct pci_vmsvga_state_s
, chip
);
903 ret
= pci_get_bar_addr(PCI_DEVICE(pci_vmsvga
), 2);
907 case SVGA_REG_MEM_SIZE
:
911 case SVGA_REG_CONFIG_DONE
:
920 case SVGA_REG_GUEST_ID
:
924 case SVGA_REG_CURSOR_ID
:
928 case SVGA_REG_CURSOR_X
:
932 case SVGA_REG_CURSOR_Y
:
936 case SVGA_REG_CURSOR_ON
:
940 case SVGA_REG_SCRATCH_SIZE
:
941 ret
= s
->scratch_size
;
944 case SVGA_REG_MEM_REGS
:
945 case SVGA_REG_NUM_DISPLAYS
:
946 case SVGA_REG_PITCHLOCK
:
947 case SVGA_PALETTE_BASE
... SVGA_PALETTE_END
:
952 if (s
->index
>= SVGA_SCRATCH_BASE
&&
953 s
->index
< SVGA_SCRATCH_BASE
+ s
->scratch_size
) {
954 ret
= s
->scratch
[s
->index
- SVGA_SCRATCH_BASE
];
957 qemu_log_mask(LOG_GUEST_ERROR
,
958 "%s: Bad register %02x\n", __func__
, s
->index
);
963 if (s
->index
>= SVGA_SCRATCH_BASE
) {
964 trace_vmware_scratch_read(s
->index
, ret
);
965 } else if (s
->index
>= SVGA_PALETTE_BASE
) {
966 trace_vmware_palette_read(s
->index
, ret
);
968 trace_vmware_value_read(s
->index
, ret
);
973 static void vmsvga_value_write(void *opaque
, uint32_t address
, uint32_t value
)
975 struct vmsvga_state_s
*s
= opaque
;
977 if (s
->index
>= SVGA_SCRATCH_BASE
) {
978 trace_vmware_scratch_write(s
->index
, value
);
979 } else if (s
->index
>= SVGA_PALETTE_BASE
) {
980 trace_vmware_palette_write(s
->index
, value
);
982 trace_vmware_value_write(s
->index
, value
);
986 if (value
== SVGA_ID_2
|| value
== SVGA_ID_1
|| value
== SVGA_ID_0
) {
991 case SVGA_REG_ENABLE
:
994 s
->vga
.hw_ops
->invalidate(&s
->vga
);
995 if (s
->enable
&& s
->config
) {
996 vga_dirty_log_stop(&s
->vga
);
998 vga_dirty_log_start(&s
->vga
);
1002 case SVGA_REG_WIDTH
:
1003 if (value
<= SVGA_MAX_WIDTH
) {
1004 s
->new_width
= value
;
1007 qemu_log_mask(LOG_GUEST_ERROR
,
1008 "%s: Bad width: %i\n", __func__
, value
);
1012 case SVGA_REG_HEIGHT
:
1013 if (value
<= SVGA_MAX_HEIGHT
) {
1014 s
->new_height
= value
;
1017 qemu_log_mask(LOG_GUEST_ERROR
,
1018 "%s: Bad height: %i\n", __func__
, value
);
1022 case SVGA_REG_BITS_PER_PIXEL
:
1024 qemu_log_mask(LOG_GUEST_ERROR
,
1025 "%s: Bad bits per pixel: %i bits\n", __func__
, value
);
1031 case SVGA_REG_CONFIG_DONE
:
1033 s
->fifo
= (uint32_t *) s
->fifo_ptr
;
1034 vga_dirty_log_stop(&s
->vga
);
1036 s
->config
= !!value
;
1041 vmsvga_fifo_run(s
); /* Or should we just wait for update_display? */
1044 case SVGA_REG_GUEST_ID
:
1047 if (value
>= GUEST_OS_BASE
&& value
< GUEST_OS_BASE
+
1048 ARRAY_SIZE(vmsvga_guest_id
)) {
1049 printf("%s: guest runs %s.\n", __func__
,
1050 vmsvga_guest_id
[value
- GUEST_OS_BASE
]);
1055 case SVGA_REG_CURSOR_ID
:
1056 s
->cursor
.id
= value
;
1059 case SVGA_REG_CURSOR_X
:
1060 s
->cursor
.x
= value
;
1063 case SVGA_REG_CURSOR_Y
:
1064 s
->cursor
.y
= value
;
1067 case SVGA_REG_CURSOR_ON
:
1068 s
->cursor
.on
|= (value
== SVGA_CURSOR_ON_SHOW
);
1069 s
->cursor
.on
&= (value
!= SVGA_CURSOR_ON_HIDE
);
1070 #ifdef HW_MOUSE_ACCEL
1071 if (value
<= SVGA_CURSOR_ON_SHOW
) {
1072 dpy_mouse_set(s
->vga
.con
, s
->cursor
.x
, s
->cursor
.y
, s
->cursor
.on
);
1077 case SVGA_REG_DEPTH
:
1078 case SVGA_REG_MEM_REGS
:
1079 case SVGA_REG_NUM_DISPLAYS
:
1080 case SVGA_REG_PITCHLOCK
:
1081 case SVGA_PALETTE_BASE
... SVGA_PALETTE_END
:
1085 if (s
->index
>= SVGA_SCRATCH_BASE
&&
1086 s
->index
< SVGA_SCRATCH_BASE
+ s
->scratch_size
) {
1087 s
->scratch
[s
->index
- SVGA_SCRATCH_BASE
] = value
;
1090 qemu_log_mask(LOG_GUEST_ERROR
,
1091 "%s: Bad register %02x\n", __func__
, s
->index
);
1095 static uint32_t vmsvga_bios_read(void *opaque
, uint32_t address
)
1097 printf("%s: what are we supposed to return?\n", __func__
);
1101 static void vmsvga_bios_write(void *opaque
, uint32_t address
, uint32_t data
)
1103 printf("%s: what are we supposed to do with (%08x)?\n", __func__
, data
);
1106 static inline void vmsvga_check_size(struct vmsvga_state_s
*s
)
1108 DisplaySurface
*surface
= qemu_console_surface(s
->vga
.con
);
1110 if (s
->new_width
!= surface_width(surface
) ||
1111 s
->new_height
!= surface_height(surface
) ||
1112 s
->new_depth
!= surface_bits_per_pixel(surface
)) {
1113 int stride
= (s
->new_depth
* s
->new_width
) / 8;
1114 pixman_format_code_t format
=
1115 qemu_default_pixman_format(s
->new_depth
, true);
1116 trace_vmware_setmode(s
->new_width
, s
->new_height
, s
->new_depth
);
1117 surface
= qemu_create_displaysurface_from(s
->new_width
, s
->new_height
,
1120 dpy_gfx_replace_surface(s
->vga
.con
, surface
);
1125 static void vmsvga_update_display(void *opaque
)
1127 struct vmsvga_state_s
*s
= opaque
;
1129 if (!s
->enable
|| !s
->config
) {
1130 /* in standard vga mode */
1131 s
->vga
.hw_ops
->gfx_update(&s
->vga
);
1135 vmsvga_check_size(s
);
1138 vmsvga_update_rect_flush(s
);
1140 if (s
->invalidated
) {
1142 dpy_gfx_update_full(s
->vga
.con
);
1146 static void vmsvga_reset(DeviceState
*dev
)
1148 struct pci_vmsvga_state_s
*pci
= VMWARE_SVGA(dev
);
1149 struct vmsvga_state_s
*s
= &pci
->chip
;
1154 s
->svgaid
= SVGA_ID
;
1156 s
->redraw_fifo_first
= 0;
1157 s
->redraw_fifo_last
= 0;
1160 vga_dirty_log_start(&s
->vga
);
1163 static void vmsvga_invalidate_display(void *opaque
)
1165 struct vmsvga_state_s
*s
= opaque
;
1167 s
->vga
.hw_ops
->invalidate(&s
->vga
);
1174 static void vmsvga_text_update(void *opaque
, console_ch_t
*chardata
)
1176 struct vmsvga_state_s
*s
= opaque
;
1178 if (s
->vga
.hw_ops
->text_update
) {
1179 s
->vga
.hw_ops
->text_update(&s
->vga
, chardata
);
1183 static int vmsvga_post_load(void *opaque
, int version_id
)
1185 struct vmsvga_state_s
*s
= opaque
;
1189 s
->fifo
= (uint32_t *) s
->fifo_ptr
;
1194 static const VMStateDescription vmstate_vmware_vga_internal
= {
1195 .name
= "vmware_vga_internal",
1197 .minimum_version_id
= 0,
1198 .post_load
= vmsvga_post_load
,
1199 .fields
= (VMStateField
[]) {
1200 VMSTATE_INT32_EQUAL(new_depth
, struct vmsvga_state_s
, NULL
),
1201 VMSTATE_INT32(enable
, struct vmsvga_state_s
),
1202 VMSTATE_INT32(config
, struct vmsvga_state_s
),
1203 VMSTATE_INT32(cursor
.id
, struct vmsvga_state_s
),
1204 VMSTATE_INT32(cursor
.x
, struct vmsvga_state_s
),
1205 VMSTATE_INT32(cursor
.y
, struct vmsvga_state_s
),
1206 VMSTATE_INT32(cursor
.on
, struct vmsvga_state_s
),
1207 VMSTATE_INT32(index
, struct vmsvga_state_s
),
1208 VMSTATE_VARRAY_INT32(scratch
, struct vmsvga_state_s
,
1209 scratch_size
, 0, vmstate_info_uint32
, uint32_t),
1210 VMSTATE_INT32(new_width
, struct vmsvga_state_s
),
1211 VMSTATE_INT32(new_height
, struct vmsvga_state_s
),
1212 VMSTATE_UINT32(guest
, struct vmsvga_state_s
),
1213 VMSTATE_UINT32(svgaid
, struct vmsvga_state_s
),
1214 VMSTATE_INT32(syncing
, struct vmsvga_state_s
),
1215 VMSTATE_UNUSED(4), /* was fb_size */
1216 VMSTATE_END_OF_LIST()
1220 static const VMStateDescription vmstate_vmware_vga
= {
1221 .name
= "vmware_vga",
1223 .minimum_version_id
= 0,
1224 .fields
= (VMStateField
[]) {
1225 VMSTATE_PCI_DEVICE(parent_obj
, struct pci_vmsvga_state_s
),
1226 VMSTATE_STRUCT(chip
, struct pci_vmsvga_state_s
, 0,
1227 vmstate_vmware_vga_internal
, struct vmsvga_state_s
),
1228 VMSTATE_END_OF_LIST()
1232 static const GraphicHwOps vmsvga_ops
= {
1233 .invalidate
= vmsvga_invalidate_display
,
1234 .gfx_update
= vmsvga_update_display
,
1235 .text_update
= vmsvga_text_update
,
1238 static void vmsvga_init(DeviceState
*dev
, struct vmsvga_state_s
*s
,
1239 MemoryRegion
*address_space
, MemoryRegion
*io
)
1241 s
->scratch_size
= SVGA_SCRATCH_SIZE
;
1242 s
->scratch
= g_malloc(s
->scratch_size
* 4);
1244 s
->vga
.con
= graphic_console_init(dev
, 0, &vmsvga_ops
, s
);
1246 s
->fifo_size
= SVGA_FIFO_SIZE
;
1247 memory_region_init_ram(&s
->fifo_ram
, NULL
, "vmsvga.fifo", s
->fifo_size
,
1249 s
->fifo_ptr
= memory_region_get_ram_ptr(&s
->fifo_ram
);
1251 vga_common_init(&s
->vga
, OBJECT(dev
));
1252 vga_init(&s
->vga
, OBJECT(dev
), address_space
, io
, true);
1253 vmstate_register(NULL
, 0, &vmstate_vga_common
, &s
->vga
);
1257 static uint64_t vmsvga_io_read(void *opaque
, hwaddr addr
, unsigned size
)
1259 struct vmsvga_state_s
*s
= opaque
;
1262 case SVGA_IO_MUL
* SVGA_INDEX_PORT
: return vmsvga_index_read(s
, addr
);
1263 case SVGA_IO_MUL
* SVGA_VALUE_PORT
: return vmsvga_value_read(s
, addr
);
1264 case SVGA_IO_MUL
* SVGA_BIOS_PORT
: return vmsvga_bios_read(s
, addr
);
1265 default: return -1u;
1269 static void vmsvga_io_write(void *opaque
, hwaddr addr
,
1270 uint64_t data
, unsigned size
)
1272 struct vmsvga_state_s
*s
= opaque
;
1275 case SVGA_IO_MUL
* SVGA_INDEX_PORT
:
1276 vmsvga_index_write(s
, addr
, data
);
1278 case SVGA_IO_MUL
* SVGA_VALUE_PORT
:
1279 vmsvga_value_write(s
, addr
, data
);
1281 case SVGA_IO_MUL
* SVGA_BIOS_PORT
:
1282 vmsvga_bios_write(s
, addr
, data
);
1287 static const MemoryRegionOps vmsvga_io_ops
= {
1288 .read
= vmsvga_io_read
,
1289 .write
= vmsvga_io_write
,
1290 .endianness
= DEVICE_LITTLE_ENDIAN
,
1292 .min_access_size
= 4,
1293 .max_access_size
= 4,
1301 static void pci_vmsvga_realize(PCIDevice
*dev
, Error
**errp
)
1303 struct pci_vmsvga_state_s
*s
= VMWARE_SVGA(dev
);
1305 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x08;
1306 dev
->config
[PCI_LATENCY_TIMER
] = 0x40;
1307 dev
->config
[PCI_INTERRUPT_LINE
] = 0xff; /* End */
1309 memory_region_init_io(&s
->io_bar
, NULL
, &vmsvga_io_ops
, &s
->chip
,
1311 memory_region_set_flush_coalesced(&s
->io_bar
);
1312 pci_register_bar(dev
, 0, PCI_BASE_ADDRESS_SPACE_IO
, &s
->io_bar
);
1314 vmsvga_init(DEVICE(dev
), &s
->chip
,
1315 pci_address_space(dev
), pci_address_space_io(dev
));
1317 pci_register_bar(dev
, 1, PCI_BASE_ADDRESS_MEM_PREFETCH
,
1319 pci_register_bar(dev
, 2, PCI_BASE_ADDRESS_MEM_PREFETCH
,
1323 static Property vga_vmware_properties
[] = {
1324 DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s
,
1325 chip
.vga
.vram_size_mb
, 16),
1326 DEFINE_PROP_BOOL("global-vmstate", struct pci_vmsvga_state_s
,
1327 chip
.vga
.global_vmstate
, false),
1328 DEFINE_PROP_END_OF_LIST(),
1331 static void vmsvga_class_init(ObjectClass
*klass
, void *data
)
1333 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1334 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1336 k
->realize
= pci_vmsvga_realize
;
1337 k
->romfile
= "vgabios-vmware.bin";
1338 k
->vendor_id
= PCI_VENDOR_ID_VMWARE
;
1339 k
->device_id
= SVGA_PCI_DEVICE_ID
;
1340 k
->class_id
= PCI_CLASS_DISPLAY_VGA
;
1341 k
->subsystem_vendor_id
= PCI_VENDOR_ID_VMWARE
;
1342 k
->subsystem_id
= SVGA_PCI_DEVICE_ID
;
1343 dc
->reset
= vmsvga_reset
;
1344 dc
->vmsd
= &vmstate_vmware_vga
;
1345 device_class_set_props(dc
, vga_vmware_properties
);
1346 dc
->hotpluggable
= false;
1347 set_bit(DEVICE_CATEGORY_DISPLAY
, dc
->categories
);
1350 static const TypeInfo vmsvga_info
= {
1351 .name
= TYPE_VMWARE_SVGA
,
1352 .parent
= TYPE_PCI_DEVICE
,
1353 .instance_size
= sizeof(struct pci_vmsvga_state_s
),
1354 .class_init
= vmsvga_class_init
,
1355 .interfaces
= (InterfaceInfo
[]) {
1356 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
1361 static void vmsvga_register_types(void)
1363 type_register_static(&vmsvga_info
);
1366 type_init(vmsvga_register_types
)