hw/display/xlnx_dp.c

   1 /*
   2  * xlnx_dp.c
   3  *
   4  *  Copyright (C) 2015 : GreenSocs Ltd
   5  *      http://www.greensocs.com/ , email: info@greensocs.com
   6  *
   7  *  Developed by :
   8  *  Frederic Konrad   <fred.konrad@greensocs.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation, either version 2 of the License, or
  13  * (at your option)any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along
  21  * with this program; if not, see <http://www.gnu.org/licenses/>.
  22  *
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qapi/error.h"
  27 #include "qemu/log.h"
  28 #include "hw/display/xlnx_dp.h"
  29
  30 #ifndef DEBUG_DP
  31 #define DEBUG_DP 0
  32 #endif
  33
  34 #define DPRINTF(fmt, ...) do {                                                 \
  35     if (DEBUG_DP) {                                                            \
  36         qemu_log("xlnx_dp: " fmt , ## __VA_ARGS__);                            \
  37     }                                                                          \
  38 } while (0)
  39
  40 /*
  41  * Register offset for DP.
  42  */
  43 #define DP_LINK_BW_SET                      (0x0000 >> 2)
  44 #define DP_LANE_COUNT_SET                   (0x0004 >> 2)
  45 #define DP_ENHANCED_FRAME_EN                (0x0008 >> 2)
  46 #define DP_TRAINING_PATTERN_SET             (0x000C >> 2)
  47 #define DP_LINK_QUAL_PATTERN_SET            (0x0010 >> 2)
  48 #define DP_SCRAMBLING_DISABLE               (0x0014 >> 2)
  49 #define DP_DOWNSPREAD_CTRL                  (0x0018 >> 2)
  50 #define DP_SOFTWARE_RESET                   (0x001C >> 2)
  51 #define DP_TRANSMITTER_ENABLE               (0x0080 >> 2)
  52 #define DP_MAIN_STREAM_ENABLE               (0x0084 >> 2)
  53 #define DP_FORCE_SCRAMBLER_RESET            (0x00C0 >> 2)
  54 #define DP_VERSION_REGISTER                 (0x00F8 >> 2)
  55 #define DP_CORE_ID                          (0x00FC >> 2)
  56
  57 #define DP_AUX_COMMAND_REGISTER             (0x0100 >> 2)
  58 #define AUX_ADDR_ONLY_MASK                  (0x1000)
  59 #define AUX_COMMAND_MASK                    (0x0F00)
  60 #define AUX_COMMAND_SHIFT                   (8)
  61 #define AUX_COMMAND_NBYTES                  (0x000F)
  62
  63 #define DP_AUX_WRITE_FIFO                   (0x0104 >> 2)
  64 #define DP_AUX_ADDRESS                      (0x0108 >> 2)
  65 #define DP_AUX_CLOCK_DIVIDER                (0x010C >> 2)
  66 #define DP_TX_USER_FIFO_OVERFLOW            (0x0110 >> 2)
  67 #define DP_INTERRUPT_SIGNAL_STATE           (0x0130 >> 2)
  68 #define DP_AUX_REPLY_DATA                   (0x0134 >> 2)
  69 #define DP_AUX_REPLY_CODE                   (0x0138 >> 2)
  70 #define DP_AUX_REPLY_COUNT                  (0x013C >> 2)
  71 #define DP_REPLY_DATA_COUNT                 (0x0148 >> 2)
  72 #define DP_REPLY_STATUS                     (0x014C >> 2)
  73 #define DP_HPD_DURATION                     (0x0150 >> 2)
  74 #define DP_MAIN_STREAM_HTOTAL               (0x0180 >> 2)
  75 #define DP_MAIN_STREAM_VTOTAL               (0x0184 >> 2)
  76 #define DP_MAIN_STREAM_POLARITY             (0x0188 >> 2)
  77 #define DP_MAIN_STREAM_HSWIDTH              (0x018C >> 2)
  78 #define DP_MAIN_STREAM_VSWIDTH              (0x0190 >> 2)
  79 #define DP_MAIN_STREAM_HRES                 (0x0194 >> 2)
  80 #define DP_MAIN_STREAM_VRES                 (0x0198 >> 2)
  81 #define DP_MAIN_STREAM_HSTART               (0x019C >> 2)
  82 #define DP_MAIN_STREAM_VSTART               (0x01A0 >> 2)
  83 #define DP_MAIN_STREAM_MISC0                (0x01A4 >> 2)
  84 #define DP_MAIN_STREAM_MISC1                (0x01A8 >> 2)
  85 #define DP_MAIN_STREAM_M_VID                (0x01AC >> 2)
  86 #define DP_MSA_TRANSFER_UNIT_SIZE           (0x01B0 >> 2)
  87 #define DP_MAIN_STREAM_N_VID                (0x01B4 >> 2)
  88 #define DP_USER_DATA_COUNT_PER_LANE         (0x01BC >> 2)
  89 #define DP_MIN_BYTES_PER_TU                 (0x01C4 >> 2)
  90 #define DP_FRAC_BYTES_PER_TU                (0x01C8 >> 2)
  91 #define DP_INIT_WAIT                        (0x01CC >> 2)
  92 #define DP_PHY_RESET                        (0x0200 >> 2)
  93 #define DP_PHY_VOLTAGE_DIFF_LANE_0          (0x0220 >> 2)
  94 #define DP_PHY_VOLTAGE_DIFF_LANE_1          (0x0224 >> 2)
  95 #define DP_TRANSMIT_PRBS7                   (0x0230 >> 2)
  96 #define DP_PHY_CLOCK_SELECT                 (0x0234 >> 2)
  97 #define DP_TX_PHY_POWER_DOWN                (0x0238 >> 2)
  98 #define DP_PHY_PRECURSOR_LANE_0             (0x023C >> 2)
  99 #define DP_PHY_PRECURSOR_LANE_1             (0x0240 >> 2)
 100 #define DP_PHY_POSTCURSOR_LANE_0            (0x024C >> 2)
 101 #define DP_PHY_POSTCURSOR_LANE_1            (0x0250 >> 2)
 102 #define DP_PHY_STATUS                       (0x0280 >> 2)
 103
 104 #define DP_TX_AUDIO_CONTROL                 (0x0300 >> 2)
 105 #define DP_TX_AUD_CTRL                      (1)
 106
 107 #define DP_TX_AUDIO_CHANNELS                (0x0304 >> 2)
 108 #define DP_TX_AUDIO_INFO_DATA(n)            ((0x0308 + 4 * n) >> 2)
 109 #define DP_TX_M_AUD                         (0x0328 >> 2)
 110 #define DP_TX_N_AUD                         (0x032C >> 2)
 111 #define DP_TX_AUDIO_EXT_DATA(n)             ((0x0330 + 4 * n) >> 2)
 112 #define DP_INT_STATUS                       (0x03A0 >> 2)
 113 #define DP_INT_MASK                         (0x03A4 >> 2)
 114 #define DP_INT_EN                           (0x03A8 >> 2)
 115 #define DP_INT_DS                           (0x03AC >> 2)
 116
 117 /*
 118  * Registers offset for Audio Video Buffer configuration.
 119  */
 120 #define V_BLEND_OFFSET                      (0xA000)
 121 #define V_BLEND_BG_CLR_0                    (0x0000 >> 2)
 122 #define V_BLEND_BG_CLR_1                    (0x0004 >> 2)
 123 #define V_BLEND_BG_CLR_2                    (0x0008 >> 2)
 124 #define V_BLEND_SET_GLOBAL_ALPHA_REG        (0x000C >> 2)
 125 #define V_BLEND_OUTPUT_VID_FORMAT           (0x0014 >> 2)
 126 #define V_BLEND_LAYER0_CONTROL              (0x0018 >> 2)
 127 #define V_BLEND_LAYER1_CONTROL              (0x001C >> 2)
 128
 129 #define V_BLEND_RGB2YCBCR_COEFF(n)          ((0x0020 + 4 * n) >> 2)
 130 #define V_BLEND_IN1CSC_COEFF(n)             ((0x0044 + 4 * n) >> 2)
 131
 132 #define V_BLEND_LUMA_IN1CSC_OFFSET          (0x0068 >> 2)
 133 #define V_BLEND_CR_IN1CSC_OFFSET            (0x006C >> 2)
 134 #define V_BLEND_CB_IN1CSC_OFFSET            (0x0070 >> 2)
 135 #define V_BLEND_LUMA_OUTCSC_OFFSET          (0x0074 >> 2)
 136 #define V_BLEND_CR_OUTCSC_OFFSET            (0x0078 >> 2)
 137 #define V_BLEND_CB_OUTCSC_OFFSET            (0x007C >> 2)
 138
 139 #define V_BLEND_IN2CSC_COEFF(n)             ((0x0080 + 4 * n) >> 2)
 140
 141 #define V_BLEND_LUMA_IN2CSC_OFFSET          (0x00A4 >> 2)
 142 #define V_BLEND_CR_IN2CSC_OFFSET            (0x00A8 >> 2)
 143 #define V_BLEND_CB_IN2CSC_OFFSET            (0x00AC >> 2)
 144 #define V_BLEND_CHROMA_KEY_ENABLE           (0x01D0 >> 2)
 145 #define V_BLEND_CHROMA_KEY_COMP1            (0x01D4 >> 2)
 146 #define V_BLEND_CHROMA_KEY_COMP2            (0x01D8 >> 2)
 147 #define V_BLEND_CHROMA_KEY_COMP3            (0x01DC >> 2)
 148
 149 /*
 150  * Registers offset for Audio Video Buffer configuration.
 151  */
 152 #define AV_BUF_MANAGER_OFFSET               (0xB000)
 153 #define AV_BUF_FORMAT                       (0x0000 >> 2)
 154 #define AV_BUF_NON_LIVE_LATENCY             (0x0008 >> 2)
 155 #define AV_CHBUF0                           (0x0010 >> 2)
 156 #define AV_CHBUF1                           (0x0014 >> 2)
 157 #define AV_CHBUF2                           (0x0018 >> 2)
 158 #define AV_CHBUF3                           (0x001C >> 2)
 159 #define AV_CHBUF4                           (0x0020 >> 2)
 160 #define AV_CHBUF5                           (0x0024 >> 2)
 161 #define AV_BUF_STC_CONTROL                  (0x002C >> 2)
 162 #define AV_BUF_STC_INIT_VALUE0              (0x0030 >> 2)
 163 #define AV_BUF_STC_INIT_VALUE1              (0x0034 >> 2)
 164 #define AV_BUF_STC_ADJ                      (0x0038 >> 2)
 165 #define AV_BUF_STC_VIDEO_VSYNC_TS_REG0      (0x003C >> 2)
 166 #define AV_BUF_STC_VIDEO_VSYNC_TS_REG1      (0x0040 >> 2)
 167 #define AV_BUF_STC_EXT_VSYNC_TS_REG0        (0x0044 >> 2)
 168 #define AV_BUF_STC_EXT_VSYNC_TS_REG1        (0x0048 >> 2)
 169 #define AV_BUF_STC_CUSTOM_EVENT_TS_REG0     (0x004C >> 2)
 170 #define AV_BUF_STC_CUSTOM_EVENT_TS_REG1     (0x0050 >> 2)
 171 #define AV_BUF_STC_CUSTOM_EVENT2_TS_REG0    (0x0054 >> 2)
 172 #define AV_BUF_STC_CUSTOM_EVENT2_TS_REG1    (0x0058 >> 2)
 173 #define AV_BUF_STC_SNAPSHOT0                (0x0060 >> 2)
 174 #define AV_BUF_STC_SNAPSHOT1                (0x0064 >> 2)
 175 #define AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT    (0x0070 >> 2)
 176 #define AV_BUF_HCOUNT_VCOUNT_INT0           (0x0074 >> 2)
 177 #define AV_BUF_HCOUNT_VCOUNT_INT1           (0x0078 >> 2)
 178 #define AV_BUF_DITHER_CONFIG                (0x007C >> 2)
 179 #define AV_BUF_DITHER_CONFIG_MAX            (0x008C >> 2)
 180 #define AV_BUF_DITHER_CONFIG_MIN            (0x0090 >> 2)
 181 #define AV_BUF_PATTERN_GEN_SELECT           (0x0100 >> 2)
 182 #define AV_BUF_AUD_VID_CLK_SOURCE           (0x0120 >> 2)
 183 #define AV_BUF_SRST_REG                     (0x0124 >> 2)
 184 #define AV_BUF_AUDIO_RDY_INTERVAL           (0x0128 >> 2)
 185 #define AV_BUF_AUDIO_CH_CONFIG              (0x012C >> 2)
 186
 187 #define AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(n)((0x0200 + 4 * n) >> 2)
 188
 189 #define AV_BUF_VIDEO_COMP_SCALE_FACTOR(n)   ((0x020C + 4 * n) >> 2)
 190
 191 #define AV_BUF_LIVE_VIDEO_COMP_SF(n)        ((0x0218 + 4 * n) >> 2)
 192
 193 #define AV_BUF_LIVE_VID_CONFIG              (0x0224 >> 2)
 194
 195 #define AV_BUF_LIVE_GFX_COMP_SF(n)          ((0x0228 + 4 * n) >> 2)
 196
 197 #define AV_BUF_LIVE_GFX_CONFIG              (0x0234 >> 2)
 198
 199 #define AUDIO_MIXER_REGISTER_OFFSET         (0xC000)
 200 #define AUDIO_MIXER_VOLUME_CONTROL          (0x0000 >> 2)
 201 #define AUDIO_MIXER_META_DATA               (0x0004 >> 2)
 202 #define AUD_CH_STATUS_REG(n)                ((0x0008 + 4 * n) >> 2)
 203 #define AUD_CH_A_DATA_REG(n)                ((0x0020 + 4 * n) >> 2)
 204 #define AUD_CH_B_DATA_REG(n)                ((0x0038 + 4 * n) >> 2)
 205
 206 #define DP_AUDIO_DMA_CHANNEL(n)             (4 + n)
 207 #define DP_GRAPHIC_DMA_CHANNEL              (3)
 208 #define DP_VIDEO_DMA_CHANNEL                (0)
 209
 210 enum DPGraphicFmt {
 211     DP_GRAPHIC_RGBA8888 = 0 << 8,
 212     DP_GRAPHIC_ABGR8888 = 1 << 8,
 213     DP_GRAPHIC_RGB888 = 2 << 8,
 214     DP_GRAPHIC_BGR888 = 3 << 8,
 215     DP_GRAPHIC_RGBA5551 = 4 << 8,
 216     DP_GRAPHIC_RGBA4444 = 5 << 8,
 217     DP_GRAPHIC_RGB565 = 6 << 8,
 218     DP_GRAPHIC_8BPP = 7 << 8,
 219     DP_GRAPHIC_4BPP = 8 << 8,
 220     DP_GRAPHIC_2BPP = 9 << 8,
 221     DP_GRAPHIC_1BPP = 10 << 8,
 222     DP_GRAPHIC_MASK = 0xF << 8
 223 };
 224
 225 enum DPVideoFmt {
 226     DP_NL_VID_CB_Y0_CR_Y1 = 0,
 227     DP_NL_VID_CR_Y0_CB_Y1 = 1,
 228     DP_NL_VID_Y0_CR_Y1_CB = 2,
 229     DP_NL_VID_Y0_CB_Y1_CR = 3,
 230     DP_NL_VID_YV16 = 4,
 231     DP_NL_VID_YV24 = 5,
 232     DP_NL_VID_YV16CL = 6,
 233     DP_NL_VID_MONO = 7,
 234     DP_NL_VID_YV16CL2 = 8,
 235     DP_NL_VID_YUV444 = 9,
 236     DP_NL_VID_RGB888 = 10,
 237     DP_NL_VID_RGBA8880 = 11,
 238     DP_NL_VID_RGB888_10BPC = 12,
 239     DP_NL_VID_YUV444_10BPC = 13,
 240     DP_NL_VID_YV16CL2_10BPC = 14,
 241     DP_NL_VID_YV16CL_10BPC = 15,
 242     DP_NL_VID_YV16_10BPC = 16,
 243     DP_NL_VID_YV24_10BPC = 17,
 244     DP_NL_VID_Y_ONLY_10BPC = 18,
 245     DP_NL_VID_YV16_420 = 19,
 246     DP_NL_VID_YV16CL_420 = 20,
 247     DP_NL_VID_YV16CL2_420 = 21,
 248     DP_NL_VID_YV16_420_10BPC = 22,
 249     DP_NL_VID_YV16CL_420_10BPC = 23,
 250     DP_NL_VID_YV16CL2_420_10BPC = 24,
 251     DP_NL_VID_FMT_MASK = 0x1F
 252 };
 253
 254 typedef enum DPGraphicFmt DPGraphicFmt;
 255 typedef enum DPVideoFmt DPVideoFmt;
 256
 257 static const VMStateDescription vmstate_dp = {
 258     .name = TYPE_XLNX_DP,
 259     .version_id = 1,
 260     .fields = (VMStateField[]){
 261         VMSTATE_UINT32_ARRAY(core_registers, XlnxDPState,
 262                              DP_CORE_REG_ARRAY_SIZE),
 263         VMSTATE_UINT32_ARRAY(avbufm_registers, XlnxDPState,
 264                              DP_AVBUF_REG_ARRAY_SIZE),
 265         VMSTATE_UINT32_ARRAY(vblend_registers, XlnxDPState,
 266                              DP_VBLEND_REG_ARRAY_SIZE),
 267         VMSTATE_UINT32_ARRAY(audio_registers, XlnxDPState,
 268                              DP_AUDIO_REG_ARRAY_SIZE),
 269         VMSTATE_END_OF_LIST()
 270     }
 271 };
 272
 273 static void xlnx_dp_update_irq(XlnxDPState *s);
 274
 275 static uint64_t xlnx_dp_audio_read(void *opaque, hwaddr offset, unsigned size)
 276 {
 277     XlnxDPState *s = XLNX_DP(opaque);
 278
 279     offset = offset >> 2;
 280     return s->audio_registers[offset];
 281 }
 282
 283 static void xlnx_dp_audio_write(void *opaque, hwaddr offset, uint64_t value,
 284                                 unsigned size)
 285 {
 286     XlnxDPState *s = XLNX_DP(opaque);
 287
 288     offset = offset >> 2;
 289
 290     switch (offset) {
 291     case AUDIO_MIXER_META_DATA:
 292         s->audio_registers[offset] = value & 0x00000001;
 293         break;
 294     default:
 295         s->audio_registers[offset] = value;
 296         break;
 297     }
 298 }
 299
 300 static const MemoryRegionOps audio_ops = {
 301     .read = xlnx_dp_audio_read,
 302     .write = xlnx_dp_audio_write,
 303     .endianness = DEVICE_NATIVE_ENDIAN,
 304 };
 305
 306 static inline uint32_t xlnx_dp_audio_get_volume(XlnxDPState *s,
 307                                                 uint8_t channel)
 308 {
 309     switch (channel) {
 310     case 0:
 311         return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 0, 16);
 312     case 1:
 313         return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 16,
 314                                                                          16);
 315     default:
 316         return 0;
 317     }
 318 }
 319
 320 static inline void xlnx_dp_audio_activate(XlnxDPState *s)
 321 {
 322     bool activated = ((s->core_registers[DP_TX_AUDIO_CONTROL]
 323                    & DP_TX_AUD_CTRL) != 0);
 324     AUD_set_active_out(s->amixer_output_stream, activated);
 325     xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(0),
 326                                       &s->audio_buffer_0);
 327     xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(1),
 328                                       &s->audio_buffer_1);
 329 }
 330
 331 static inline void xlnx_dp_audio_mix_buffer(XlnxDPState *s)
 332 {
 333     /*
 334      * Audio packets are signed and have this shape:
 335      * | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 |
 336      * | R3 | L3 | R2 | L2 | R1 | L1 | R0 | L0 |
 337      *
 338      * Output audio is 16bits saturated.
 339      */
 340     int i;
 341
 342     if ((s->audio_data_available[0]) && (xlnx_dp_audio_get_volume(s, 0))) {
 343         for (i = 0; i < s->audio_data_available[0] / 2; i++) {
 344             s->temp_buffer[i] = (int64_t)(s->audio_buffer_0[i])
 345                               * xlnx_dp_audio_get_volume(s, 0) / 8192;
 346         }
 347         s->byte_left = s->audio_data_available[0];
 348     } else {
 349         memset(s->temp_buffer, 0, s->audio_data_available[1] / 2);
 350     }
 351
 352     if ((s->audio_data_available[1]) && (xlnx_dp_audio_get_volume(s, 1))) {
 353         if ((s->audio_data_available[0] == 0)
 354         || (s->audio_data_available[1] == s->audio_data_available[0])) {
 355             for (i = 0; i < s->audio_data_available[1] / 2; i++) {
 356                 s->temp_buffer[i] += (int64_t)(s->audio_buffer_1[i])
 357                                    * xlnx_dp_audio_get_volume(s, 1) / 8192;
 358             }
 359             s->byte_left = s->audio_data_available[1];
 360         }
 361     }
 362
 363     for (i = 0; i < s->byte_left / 2; i++) {
 364         s->out_buffer[i] = MAX(-32767, MIN(s->temp_buffer[i], 32767));
 365     }
 366
 367     s->data_ptr = 0;
 368 }
 369
 370 static void xlnx_dp_audio_callback(void *opaque, int avail)
 371 {
 372     /*
 373      * Get some data from the DPDMA and compute these datas.
 374      * Then wait for QEMU's audio subsystem to call this callback.
 375      */
 376     XlnxDPState *s = XLNX_DP(opaque);
 377     size_t written = 0;
 378
 379     /* If there are already some data don't get more data. */
 380     if (s->byte_left == 0) {
 381         s->audio_data_available[0] = xlnx_dpdma_start_operation(s->dpdma, 4,
 382                                                                   true);
 383         s->audio_data_available[1] = xlnx_dpdma_start_operation(s->dpdma, 5,
 384                                                                   true);
 385         xlnx_dp_audio_mix_buffer(s);
 386     }
 387
 388     /* Send the buffer through the audio. */
 389     if (s->byte_left <= MAX_QEMU_BUFFER_SIZE) {
 390         if (s->byte_left != 0) {
 391             written = AUD_write(s->amixer_output_stream,
 392                                 &s->out_buffer[s->data_ptr], s->byte_left);
 393         } else {
 394             /*
 395              * There is nothing to play.. We don't have any data! Fill the
 396              * buffer with zero's and send it.
 397              */
 398             written = 0;
 399             memset(s->out_buffer, 0, 1024);
 400             AUD_write(s->amixer_output_stream, s->out_buffer, 1024);
 401         }
 402     } else {
 403         written = AUD_write(s->amixer_output_stream,
 404                             &s->out_buffer[s->data_ptr], MAX_QEMU_BUFFER_SIZE);
 405     }
 406     s->byte_left -= written;
 407     s->data_ptr += written;
 408 }
 409
 410 /*
 411  * AUX channel related function.
 412  */
 413 static void xlnx_dp_aux_clear_rx_fifo(XlnxDPState *s)
 414 {
 415     fifo8_reset(&s->rx_fifo);
 416 }
 417
 418 static void xlnx_dp_aux_push_rx_fifo(XlnxDPState *s, uint8_t *buf, size_t len)
 419 {
 420     DPRINTF("Push %u data in rx_fifo\n", (unsigned)len);
 421     fifo8_push_all(&s->rx_fifo, buf, len);
 422 }
 423
 424 static uint8_t xlnx_dp_aux_pop_rx_fifo(XlnxDPState *s)
 425 {
 426     uint8_t ret;
 427
 428     if (fifo8_is_empty(&s->rx_fifo)) {
 429         DPRINTF("rx_fifo underflow..\n");
 430         abort();
 431     }
 432     ret = fifo8_pop(&s->rx_fifo);
 433     DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret);
 434     return ret;
 435 }
 436
 437 static void xlnx_dp_aux_clear_tx_fifo(XlnxDPState *s)
 438 {
 439     fifo8_reset(&s->tx_fifo);
 440 }
 441
 442 static void xlnx_dp_aux_push_tx_fifo(XlnxDPState *s, uint8_t *buf, size_t len)
 443 {
 444     DPRINTF("Push %u data in tx_fifo\n", (unsigned)len);
 445     fifo8_push_all(&s->tx_fifo, buf, len);
 446 }
 447
 448 static uint8_t xlnx_dp_aux_pop_tx_fifo(XlnxDPState *s)
 449 {
 450     uint8_t ret;
 451
 452     if (fifo8_is_empty(&s->tx_fifo)) {
 453         DPRINTF("tx_fifo underflow..\n");
 454         abort();
 455     }
 456     ret = fifo8_pop(&s->tx_fifo);
 457     DPRINTF("pop 0x%2.2X from tx_fifo.\n", ret);
 458     return ret;
 459 }
 460
 461 static uint32_t xlnx_dp_aux_get_address(XlnxDPState *s)
 462 {
 463     return s->core_registers[DP_AUX_ADDRESS];
 464 }
 465
 466 /*
 467  * Get command from the register.
 468  */
 469 static void xlnx_dp_aux_set_command(XlnxDPState *s, uint32_t value)
 470 {
 471     bool address_only = (value & AUX_ADDR_ONLY_MASK) != 0;
 472     AUXCommand cmd = (value & AUX_COMMAND_MASK) >> AUX_COMMAND_SHIFT;
 473     uint8_t nbytes = (value & AUX_COMMAND_NBYTES) + 1;
 474     uint8_t buf[16];
 475     int i;
 476
 477     /*
 478      * When an address_only command is executed nothing happen to the fifo, so
 479      * just make nbytes = 0.
 480      */
 481     if (address_only) {
 482         nbytes = 0;
 483     }
 484
 485     switch (cmd) {
 486     case READ_AUX:
 487     case READ_I2C:
 488     case READ_I2C_MOT:
 489         s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd,
 490                                                xlnx_dp_aux_get_address(s),
 491                                                nbytes, buf);
 492         s->core_registers[DP_REPLY_DATA_COUNT] = nbytes;
 493
 494         if (s->core_registers[DP_AUX_REPLY_CODE] == AUX_I2C_ACK) {
 495             xlnx_dp_aux_push_rx_fifo(s, buf, nbytes);
 496         }
 497         break;
 498     case WRITE_AUX:
 499     case WRITE_I2C:
 500     case WRITE_I2C_MOT:
 501         for (i = 0; i < nbytes; i++) {
 502             buf[i] = xlnx_dp_aux_pop_tx_fifo(s);
 503         }
 504         s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd,
 505                                                xlnx_dp_aux_get_address(s),
 506                                                nbytes, buf);
 507         xlnx_dp_aux_clear_tx_fifo(s);
 508         break;
 509     case WRITE_I2C_STATUS:
 510         qemu_log_mask(LOG_UNIMP, "xlnx_dp: Write i2c status not implemented\n");
 511         break;
 512     default:
 513         abort();
 514     }
 515
 516     s->core_registers[DP_INTERRUPT_SIGNAL_STATE] |= 0x04;
 517 }
 518
 519 static void xlnx_dp_set_dpdma(const Object *obj, const char *name, Object *val,
 520                               Error **errp)
 521 {
 522     XlnxDPState *s = XLNX_DP(obj);
 523     if (s->console) {
 524         DisplaySurface *surface = qemu_console_surface(s->console);
 525         XlnxDPDMAState *dma = XLNX_DPDMA(val);
 526         xlnx_dpdma_set_host_data_location(dma, DP_GRAPHIC_DMA_CHANNEL,
 527                                           surface_data(surface));
 528     }
 529 }
 530
 531 static inline uint8_t xlnx_dp_global_alpha_value(XlnxDPState *s)
 532 {
 533     return (s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x1FE) >> 1;
 534 }
 535
 536 static inline bool xlnx_dp_global_alpha_enabled(XlnxDPState *s)
 537 {
 538     /*
 539      * If the alpha is totally opaque (255) we consider the alpha is disabled to
 540      * reduce CPU consumption.
 541      */
 542     return ((xlnx_dp_global_alpha_value(s) != 0xFF) &&
 543            ((s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x01) != 0));
 544 }
 545
 546 static void xlnx_dp_recreate_surface(XlnxDPState *s)
 547 {
 548     /*
 549      * Two possibilities, if blending is enabled the console displays
 550      * bout_plane, if not g_plane is displayed.
 551      */
 552     uint16_t width = s->core_registers[DP_MAIN_STREAM_HRES];
 553     uint16_t height = s->core_registers[DP_MAIN_STREAM_VRES];
 554     DisplaySurface *current_console_surface = qemu_console_surface(s->console);
 555
 556     if ((width != 0) && (height != 0)) {
 557         /*
 558          * As dpy_gfx_replace_surface calls qemu_free_displaysurface on the
 559          * surface we need to be careful and don't free the surface associated
 560          * to the console or double free will happen.
 561          */
 562         if (s->bout_plane.surface != current_console_surface) {
 563             qemu_free_displaysurface(s->bout_plane.surface);
 564         }
 565         if (s->v_plane.surface != current_console_surface) {
 566             qemu_free_displaysurface(s->v_plane.surface);
 567         }
 568         if (s->g_plane.surface != current_console_surface) {
 569             qemu_free_displaysurface(s->g_plane.surface);
 570         }
 571
 572         s->g_plane.surface
 573                 = qemu_create_displaysurface_from(width, height,
 574                                                   s->g_plane.format, 0, NULL);
 575         s->v_plane.surface
 576                 = qemu_create_displaysurface_from(width, height,
 577                                                   s->v_plane.format, 0, NULL);
 578         if (xlnx_dp_global_alpha_enabled(s)) {
 579             s->bout_plane.surface =
 580                             qemu_create_displaysurface_from(width,
 581                                                             height,
 582                                                             s->g_plane.format,
 583                                                             0, NULL);
 584             dpy_gfx_replace_surface(s->console, s->bout_plane.surface);
 585         } else {
 586             s->bout_plane.surface = NULL;
 587             dpy_gfx_replace_surface(s->console, s->g_plane.surface);
 588         }
 589
 590         xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL,
 591                                             surface_data(s->g_plane.surface));
 592         xlnx_dpdma_set_host_data_location(s->dpdma, DP_VIDEO_DMA_CHANNEL,
 593                                             surface_data(s->v_plane.surface));
 594     }
 595 }
 596
 597 /*
 598  * Change the graphic format of the surface.
 599  */
 600 static void xlnx_dp_change_graphic_fmt(XlnxDPState *s)
 601 {
 602     switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK) {
 603     case DP_GRAPHIC_RGBA8888:
 604         s->g_plane.format = PIXMAN_r8g8b8a8;
 605         break;
 606     case DP_GRAPHIC_ABGR8888:
 607         s->g_plane.format = PIXMAN_a8b8g8r8;
 608         break;
 609     case DP_GRAPHIC_RGB565:
 610         s->g_plane.format = PIXMAN_r5g6b5;
 611         break;
 612     case DP_GRAPHIC_RGB888:
 613         s->g_plane.format = PIXMAN_r8g8b8;
 614         break;
 615     case DP_GRAPHIC_BGR888:
 616         s->g_plane.format = PIXMAN_b8g8r8;
 617         break;
 618     default:
 619         DPRINTF("error: unsupported graphic format %u.\n",
 620                 s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK);
 621         abort();
 622     }
 623
 624     switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK) {
 625     case 0:
 626         s->v_plane.format = PIXMAN_x8b8g8r8;
 627         break;
 628     case DP_NL_VID_Y0_CB_Y1_CR:
 629         s->v_plane.format = PIXMAN_yuy2;
 630         break;
 631     case DP_NL_VID_RGBA8880:
 632         s->v_plane.format = PIXMAN_x8b8g8r8;
 633         break;
 634     default:
 635         DPRINTF("error: unsupported video format %u.\n",
 636                 s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK);
 637         abort();
 638     }
 639
 640     xlnx_dp_recreate_surface(s);
 641 }
 642
 643 static void xlnx_dp_update_irq(XlnxDPState *s)
 644 {
 645     uint32_t flags;
 646
 647     flags = s->core_registers[DP_INT_STATUS] & ~s->core_registers[DP_INT_MASK];
 648     DPRINTF("update IRQ value = %" PRIx32 "\n", flags);
 649     qemu_set_irq(s->irq, flags != 0);
 650 }
 651
 652 static uint64_t xlnx_dp_read(void *opaque, hwaddr offset, unsigned size)
 653 {
 654     XlnxDPState *s = XLNX_DP(opaque);
 655     uint64_t ret = 0;
 656
 657     offset = offset >> 2;
 658
 659     switch (offset) {
 660     case DP_TX_USER_FIFO_OVERFLOW:
 661         /* This register is cleared after a read */
 662         ret = s->core_registers[DP_TX_USER_FIFO_OVERFLOW];
 663         s->core_registers[DP_TX_USER_FIFO_OVERFLOW] = 0;
 664         break;
 665     case DP_AUX_REPLY_DATA:
 666         ret = xlnx_dp_aux_pop_rx_fifo(s);
 667         break;
 668     case DP_INTERRUPT_SIGNAL_STATE:
 669         /*
 670          * XXX: Not sure it is the right thing to do actually.
 671          * The register is not written by the device driver so it's stuck
 672          * to 0x04.
 673          */
 674         ret = s->core_registers[DP_INTERRUPT_SIGNAL_STATE];
 675         s->core_registers[DP_INTERRUPT_SIGNAL_STATE] &= ~0x04;
 676         break;
 677     case DP_AUX_WRITE_FIFO:
 678     case DP_TX_AUDIO_INFO_DATA(0):
 679     case DP_TX_AUDIO_INFO_DATA(1):
 680     case DP_TX_AUDIO_INFO_DATA(2):
 681     case DP_TX_AUDIO_INFO_DATA(3):
 682     case DP_TX_AUDIO_INFO_DATA(4):
 683     case DP_TX_AUDIO_INFO_DATA(5):
 684     case DP_TX_AUDIO_INFO_DATA(6):
 685     case DP_TX_AUDIO_INFO_DATA(7):
 686     case DP_TX_AUDIO_EXT_DATA(0):
 687     case DP_TX_AUDIO_EXT_DATA(1):
 688     case DP_TX_AUDIO_EXT_DATA(2):
 689     case DP_TX_AUDIO_EXT_DATA(3):
 690     case DP_TX_AUDIO_EXT_DATA(4):
 691     case DP_TX_AUDIO_EXT_DATA(5):
 692     case DP_TX_AUDIO_EXT_DATA(6):
 693     case DP_TX_AUDIO_EXT_DATA(7):
 694     case DP_TX_AUDIO_EXT_DATA(8):
 695         /* write only registers */
 696         ret = 0;
 697         break;
 698     default:
 699         assert(offset <= (0x3AC >> 2));
 700         ret = s->core_registers[offset];
 701         break;
 702     }
 703
 704     DPRINTF("core read @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset << 2, ret);
 705     return ret;
 706 }
 707
 708 static void xlnx_dp_write(void *opaque, hwaddr offset, uint64_t value,
 709                           unsigned size)
 710 {
 711     XlnxDPState *s = XLNX_DP(opaque);
 712
 713     DPRINTF("core write @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset, value);
 714
 715     offset = offset >> 2;
 716
 717     switch (offset) {
 718     /*
 719      * Only special write case are handled.
 720      */
 721     case DP_LINK_BW_SET:
 722         s->core_registers[offset] = value & 0x000000FF;
 723         break;
 724     case DP_LANE_COUNT_SET:
 725     case DP_MAIN_STREAM_MISC0:
 726         s->core_registers[offset] = value & 0x0000000F;
 727         break;
 728     case DP_TRAINING_PATTERN_SET:
 729     case DP_LINK_QUAL_PATTERN_SET:
 730     case DP_MAIN_STREAM_POLARITY:
 731     case DP_PHY_VOLTAGE_DIFF_LANE_0:
 732     case DP_PHY_VOLTAGE_DIFF_LANE_1:
 733         s->core_registers[offset] = value & 0x00000003;
 734         break;
 735     case DP_ENHANCED_FRAME_EN:
 736     case DP_SCRAMBLING_DISABLE:
 737     case DP_DOWNSPREAD_CTRL:
 738     case DP_MAIN_STREAM_ENABLE:
 739     case DP_TRANSMIT_PRBS7:
 740         s->core_registers[offset] = value & 0x00000001;
 741         break;
 742     case DP_PHY_CLOCK_SELECT:
 743         s->core_registers[offset] = value & 0x00000007;
 744         break;
 745     case DP_SOFTWARE_RESET:
 746         /*
 747          * No need to update this bit as it's read '0'.
 748          */
 749         /*
 750          * TODO: reset IP.
 751          */
 752         break;
 753     case DP_TRANSMITTER_ENABLE:
 754         s->core_registers[offset] = value & 0x01;
 755         break;
 756     case DP_FORCE_SCRAMBLER_RESET:
 757         /*
 758          * No need to update this bit as it's read '0'.
 759          */
 760         /*
 761          * TODO: force a scrambler reset??
 762          */
 763         break;
 764     case DP_AUX_COMMAND_REGISTER:
 765         s->core_registers[offset] = value & 0x00001F0F;
 766         xlnx_dp_aux_set_command(s, s->core_registers[offset]);
 767         break;
 768     case DP_MAIN_STREAM_HTOTAL:
 769     case DP_MAIN_STREAM_VTOTAL:
 770     case DP_MAIN_STREAM_HSTART:
 771     case DP_MAIN_STREAM_VSTART:
 772         s->core_registers[offset] = value & 0x0000FFFF;
 773         break;
 774     case DP_MAIN_STREAM_HRES:
 775     case DP_MAIN_STREAM_VRES:
 776         s->core_registers[offset] = value & 0x0000FFFF;
 777         xlnx_dp_recreate_surface(s);
 778         break;
 779     case DP_MAIN_STREAM_HSWIDTH:
 780     case DP_MAIN_STREAM_VSWIDTH:
 781         s->core_registers[offset] = value & 0x00007FFF;
 782         break;
 783     case DP_MAIN_STREAM_MISC1:
 784         s->core_registers[offset] = value & 0x00000086;
 785         break;
 786     case DP_MAIN_STREAM_M_VID:
 787     case DP_MAIN_STREAM_N_VID:
 788         s->core_registers[offset] = value & 0x00FFFFFF;
 789         break;
 790     case DP_MSA_TRANSFER_UNIT_SIZE:
 791     case DP_MIN_BYTES_PER_TU:
 792     case DP_INIT_WAIT:
 793         s->core_registers[offset] = value & 0x00000007;
 794         break;
 795     case DP_USER_DATA_COUNT_PER_LANE:
 796         s->core_registers[offset] = value & 0x0003FFFF;
 797         break;
 798     case DP_FRAC_BYTES_PER_TU:
 799         s->core_registers[offset] = value & 0x000003FF;
 800         break;
 801     case DP_PHY_RESET:
 802         s->core_registers[offset] = value & 0x00010003;
 803         /*
 804          * TODO: Reset something?
 805          */
 806         break;
 807     case DP_TX_PHY_POWER_DOWN:
 808         s->core_registers[offset] = value & 0x0000000F;
 809         /*
 810          * TODO: Power down things?
 811          */
 812         break;
 813     case DP_AUX_WRITE_FIFO: {
 814         uint8_t c = value;
 815         xlnx_dp_aux_push_tx_fifo(s, &c, 1);
 816         break;
 817     }
 818     case DP_AUX_CLOCK_DIVIDER:
 819         break;
 820     case DP_AUX_REPLY_COUNT:
 821         /*
 822          * Writing to this register clear the counter.
 823          */
 824         s->core_registers[offset] = 0x00000000;
 825         break;
 826     case DP_AUX_ADDRESS:
 827         s->core_registers[offset] = value & 0x000FFFFF;
 828         break;
 829     case DP_VERSION_REGISTER:
 830     case DP_CORE_ID:
 831     case DP_TX_USER_FIFO_OVERFLOW:
 832     case DP_AUX_REPLY_DATA:
 833     case DP_AUX_REPLY_CODE:
 834     case DP_REPLY_DATA_COUNT:
 835     case DP_REPLY_STATUS:
 836     case DP_HPD_DURATION:
 837         /*
 838          * Write to read only location..
 839          */
 840         break;
 841     case DP_TX_AUDIO_CONTROL:
 842         s->core_registers[offset] = value & 0x00000001;
 843         xlnx_dp_audio_activate(s);
 844         break;
 845     case DP_TX_AUDIO_CHANNELS:
 846         s->core_registers[offset] = value & 0x00000007;
 847         xlnx_dp_audio_activate(s);
 848         break;
 849     case DP_INT_STATUS:
 850         s->core_registers[DP_INT_STATUS] &= ~value;
 851         xlnx_dp_update_irq(s);
 852         break;
 853     case DP_INT_EN:
 854         s->core_registers[DP_INT_MASK] &= ~value;
 855         xlnx_dp_update_irq(s);
 856         break;
 857     case DP_INT_DS:
 858         s->core_registers[DP_INT_MASK] |= ~value;
 859         xlnx_dp_update_irq(s);
 860         break;
 861     default:
 862         assert(offset <= (0x504C >> 2));
 863         s->core_registers[offset] = value;
 864         break;
 865     }
 866 }
 867
 868 static const MemoryRegionOps dp_ops = {
 869     .read = xlnx_dp_read,
 870     .write = xlnx_dp_write,
 871     .endianness = DEVICE_NATIVE_ENDIAN,
 872     .valid = {
 873         .min_access_size = 4,
 874         .max_access_size = 4,
 875     },
 876     .impl = {
 877         .min_access_size = 4,
 878         .max_access_size = 4,
 879     },
 880 };
 881
 882 /*
 883  * This is to handle Read/Write to the Video Blender.
 884  */
 885 static void xlnx_dp_vblend_write(void *opaque, hwaddr offset,
 886                                  uint64_t value, unsigned size)
 887 {
 888     XlnxDPState *s = XLNX_DP(opaque);
 889     bool alpha_was_enabled;
 890
 891     DPRINTF("vblend: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
 892                                                                (uint32_t)value);
 893     offset = offset >> 2;
 894
 895     switch (offset) {
 896     case V_BLEND_BG_CLR_0:
 897     case V_BLEND_BG_CLR_1:
 898     case V_BLEND_BG_CLR_2:
 899         s->vblend_registers[offset] = value & 0x00000FFF;
 900         break;
 901     case V_BLEND_SET_GLOBAL_ALPHA_REG:
 902         /*
 903          * A write to this register can enable or disable blending. Thus we need
 904          * to recreate the surfaces.
 905          */
 906         alpha_was_enabled = xlnx_dp_global_alpha_enabled(s);
 907         s->vblend_registers[offset] = value & 0x000001FF;
 908         if (xlnx_dp_global_alpha_enabled(s) != alpha_was_enabled) {
 909             xlnx_dp_recreate_surface(s);
 910         }
 911         break;
 912     case V_BLEND_OUTPUT_VID_FORMAT:
 913         s->vblend_registers[offset] = value & 0x00000017;
 914         break;
 915     case V_BLEND_LAYER0_CONTROL:
 916     case V_BLEND_LAYER1_CONTROL:
 917         s->vblend_registers[offset] = value & 0x00000103;
 918         break;
 919     case V_BLEND_RGB2YCBCR_COEFF(0):
 920     case V_BLEND_RGB2YCBCR_COEFF(1):
 921     case V_BLEND_RGB2YCBCR_COEFF(2):
 922     case V_BLEND_RGB2YCBCR_COEFF(3):
 923     case V_BLEND_RGB2YCBCR_COEFF(4):
 924     case V_BLEND_RGB2YCBCR_COEFF(5):
 925     case V_BLEND_RGB2YCBCR_COEFF(6):
 926     case V_BLEND_RGB2YCBCR_COEFF(7):
 927     case V_BLEND_RGB2YCBCR_COEFF(8):
 928     case V_BLEND_IN1CSC_COEFF(0):
 929     case V_BLEND_IN1CSC_COEFF(1):
 930     case V_BLEND_IN1CSC_COEFF(2):
 931     case V_BLEND_IN1CSC_COEFF(3):
 932     case V_BLEND_IN1CSC_COEFF(4):
 933     case V_BLEND_IN1CSC_COEFF(5):
 934     case V_BLEND_IN1CSC_COEFF(6):
 935     case V_BLEND_IN1CSC_COEFF(7):
 936     case V_BLEND_IN1CSC_COEFF(8):
 937     case V_BLEND_IN2CSC_COEFF(0):
 938     case V_BLEND_IN2CSC_COEFF(1):
 939     case V_BLEND_IN2CSC_COEFF(2):
 940     case V_BLEND_IN2CSC_COEFF(3):
 941     case V_BLEND_IN2CSC_COEFF(4):
 942     case V_BLEND_IN2CSC_COEFF(5):
 943     case V_BLEND_IN2CSC_COEFF(6):
 944     case V_BLEND_IN2CSC_COEFF(7):
 945     case V_BLEND_IN2CSC_COEFF(8):
 946         s->vblend_registers[offset] = value & 0x0000FFFF;
 947         break;
 948     case V_BLEND_LUMA_IN1CSC_OFFSET:
 949     case V_BLEND_CR_IN1CSC_OFFSET:
 950     case V_BLEND_CB_IN1CSC_OFFSET:
 951     case V_BLEND_LUMA_IN2CSC_OFFSET:
 952     case V_BLEND_CR_IN2CSC_OFFSET:
 953     case V_BLEND_CB_IN2CSC_OFFSET:
 954     case V_BLEND_LUMA_OUTCSC_OFFSET:
 955     case V_BLEND_CR_OUTCSC_OFFSET:
 956     case V_BLEND_CB_OUTCSC_OFFSET:
 957         s->vblend_registers[offset] = value & 0x3FFF7FFF;
 958         break;
 959     case V_BLEND_CHROMA_KEY_ENABLE:
 960         s->vblend_registers[offset] = value & 0x00000003;
 961         break;
 962     case V_BLEND_CHROMA_KEY_COMP1:
 963     case V_BLEND_CHROMA_KEY_COMP2:
 964     case V_BLEND_CHROMA_KEY_COMP3:
 965         s->vblend_registers[offset] = value & 0x0FFF0FFF;
 966         break;
 967     default:
 968         s->vblend_registers[offset] = value;
 969         break;
 970     }
 971 }
 972
 973 static uint64_t xlnx_dp_vblend_read(void *opaque, hwaddr offset,
 974                                     unsigned size)
 975 {
 976     XlnxDPState *s = XLNX_DP(opaque);
 977
 978     DPRINTF("vblend: read @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
 979             s->vblend_registers[offset >> 2]);
 980     return s->vblend_registers[offset >> 2];
 981 }
 982
 983 static const MemoryRegionOps vblend_ops = {
 984     .read = xlnx_dp_vblend_read,
 985     .write = xlnx_dp_vblend_write,
 986     .endianness = DEVICE_NATIVE_ENDIAN,
 987     .valid = {
 988         .min_access_size = 4,
 989         .max_access_size = 4,
 990     },
 991     .impl = {
 992         .min_access_size = 4,
 993         .max_access_size = 4,
 994     },
 995 };
 996
 997 /*
 998  * This is to handle Read/Write to the Audio Video buffer manager.
 999  */
1000 static void xlnx_dp_avbufm_write(void *opaque, hwaddr offset, uint64_t value,
1001                                  unsigned size)
1002 {
1003     XlnxDPState *s = XLNX_DP(opaque);
1004
1005     DPRINTF("avbufm: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
1006                                                                (uint32_t)value);
1007     offset = offset >> 2;
1008
1009     switch (offset) {
1010     case AV_BUF_FORMAT:
1011         s->avbufm_registers[offset] = value & 0x00000FFF;
1012         xlnx_dp_change_graphic_fmt(s);
1013         break;
1014     case AV_CHBUF0:
1015     case AV_CHBUF1:
1016     case AV_CHBUF2:
1017     case AV_CHBUF3:
1018     case AV_CHBUF4:
1019     case AV_CHBUF5:
1020         s->avbufm_registers[offset] = value & 0x0000007F;
1021         break;
1022     case AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT:
1023         s->avbufm_registers[offset] = value & 0x0000007F;
1024         break;
1025     case AV_BUF_DITHER_CONFIG:
1026         s->avbufm_registers[offset] = value & 0x000007FF;
1027         break;
1028     case AV_BUF_DITHER_CONFIG_MAX:
1029     case AV_BUF_DITHER_CONFIG_MIN:
1030         s->avbufm_registers[offset] = value & 0x00000FFF;
1031         break;
1032     case AV_BUF_PATTERN_GEN_SELECT:
1033         s->avbufm_registers[offset] = value & 0xFFFFFF03;
1034         break;
1035     case AV_BUF_AUD_VID_CLK_SOURCE:
1036         s->avbufm_registers[offset] = value & 0x00000007;
1037         break;
1038     case AV_BUF_SRST_REG:
1039         s->avbufm_registers[offset] = value & 0x00000002;
1040         break;
1041     case AV_BUF_AUDIO_CH_CONFIG:
1042         s->avbufm_registers[offset] = value & 0x00000003;
1043         break;
1044     case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0):
1045     case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1):
1046     case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2):
1047     case AV_BUF_VIDEO_COMP_SCALE_FACTOR(0):
1048     case AV_BUF_VIDEO_COMP_SCALE_FACTOR(1):
1049     case AV_BUF_VIDEO_COMP_SCALE_FACTOR(2):
1050         s->avbufm_registers[offset] = value & 0x0000FFFF;
1051         break;
1052     case AV_BUF_LIVE_VIDEO_COMP_SF(0):
1053     case AV_BUF_LIVE_VIDEO_COMP_SF(1):
1054     case AV_BUF_LIVE_VIDEO_COMP_SF(2):
1055     case AV_BUF_LIVE_VID_CONFIG:
1056     case AV_BUF_LIVE_GFX_COMP_SF(0):
1057     case AV_BUF_LIVE_GFX_COMP_SF(1):
1058     case AV_BUF_LIVE_GFX_COMP_SF(2):
1059     case AV_BUF_LIVE_GFX_CONFIG:
1060     case AV_BUF_NON_LIVE_LATENCY:
1061     case AV_BUF_STC_CONTROL:
1062     case AV_BUF_STC_INIT_VALUE0:
1063     case AV_BUF_STC_INIT_VALUE1:
1064     case AV_BUF_STC_ADJ:
1065     case AV_BUF_STC_VIDEO_VSYNC_TS_REG0:
1066     case AV_BUF_STC_VIDEO_VSYNC_TS_REG1:
1067     case AV_BUF_STC_EXT_VSYNC_TS_REG0:
1068     case AV_BUF_STC_EXT_VSYNC_TS_REG1:
1069     case AV_BUF_STC_CUSTOM_EVENT_TS_REG0:
1070     case AV_BUF_STC_CUSTOM_EVENT_TS_REG1:
1071     case AV_BUF_STC_CUSTOM_EVENT2_TS_REG0:
1072     case AV_BUF_STC_CUSTOM_EVENT2_TS_REG1:
1073     case AV_BUF_STC_SNAPSHOT0:
1074     case AV_BUF_STC_SNAPSHOT1:
1075     case AV_BUF_HCOUNT_VCOUNT_INT0:
1076     case AV_BUF_HCOUNT_VCOUNT_INT1:
1077         qemu_log_mask(LOG_UNIMP, "avbufm: unimplemented register 0x%04"
1078                                  PRIx64 "\n",
1079                       offset << 2);
1080         break;
1081     default:
1082         s->avbufm_registers[offset] = value;
1083         break;
1084     }
1085 }
1086
1087 static uint64_t xlnx_dp_avbufm_read(void *opaque, hwaddr offset,
1088                                     unsigned size)
1089 {
1090     XlnxDPState *s = XLNX_DP(opaque);
1091
1092     offset = offset >> 2;
1093     return s->avbufm_registers[offset];
1094 }
1095
1096 static const MemoryRegionOps avbufm_ops = {
1097     .read = xlnx_dp_avbufm_read,
1098     .write = xlnx_dp_avbufm_write,
1099     .endianness = DEVICE_NATIVE_ENDIAN,
1100     .valid = {
1101         .min_access_size = 4,
1102         .max_access_size = 4,
1103     },
1104     .impl = {
1105         .min_access_size = 4,
1106         .max_access_size = 4,
1107     },
1108 };
1109
1110 /*
1111  * This is a global alpha blending using pixman.
1112  * Both graphic and video planes are multiplied with the global alpha
1113  * coefficient and added.
1114  */
1115 static inline void xlnx_dp_blend_surface(XlnxDPState *s)
1116 {
1117     pixman_fixed_t alpha1[] = { pixman_double_to_fixed(1),
1118                                 pixman_double_to_fixed(1),
1119                                 pixman_double_to_fixed(1.0) };
1120     pixman_fixed_t alpha2[] = { pixman_double_to_fixed(1),
1121                                 pixman_double_to_fixed(1),
1122                                 pixman_double_to_fixed(1.0) };
1123
1124     if ((surface_width(s->g_plane.surface)
1125          != surface_width(s->v_plane.surface)) ||
1126         (surface_height(s->g_plane.surface)
1127          != surface_height(s->v_plane.surface))) {
1128         return;
1129     }
1130
1131     alpha1[2] = pixman_double_to_fixed((double)(xlnx_dp_global_alpha_value(s))
1132                                        / 256.0);
1133     alpha2[2] = pixman_double_to_fixed((255.0
1134                                     - (double)xlnx_dp_global_alpha_value(s))
1135                                        / 256.0);
1136
1137     pixman_image_set_filter(s->g_plane.surface->image,
1138                             PIXMAN_FILTER_CONVOLUTION, alpha1, 3);
1139     pixman_image_composite(PIXMAN_OP_SRC, s->g_plane.surface->image, 0,
1140                            s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0,
1141                            surface_width(s->g_plane.surface),
1142                            surface_height(s->g_plane.surface));
1143     pixman_image_set_filter(s->v_plane.surface->image,
1144                             PIXMAN_FILTER_CONVOLUTION, alpha2, 3);
1145     pixman_image_composite(PIXMAN_OP_ADD, s->v_plane.surface->image, 0,
1146                            s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0,
1147                            surface_width(s->g_plane.surface),
1148                            surface_height(s->g_plane.surface));
1149 }
1150
1151 static void xlnx_dp_update_display(void *opaque)
1152 {
1153     XlnxDPState *s = XLNX_DP(opaque);
1154
1155     if ((s->core_registers[DP_TRANSMITTER_ENABLE] & 0x01) == 0) {
1156         return;
1157     }
1158
1159     s->core_registers[DP_INT_STATUS] |= (1 << 13);
1160     xlnx_dp_update_irq(s);
1161
1162     xlnx_dpdma_trigger_vsync_irq(s->dpdma);
1163
1164     /*
1165      * Trigger the DMA channel.
1166      */
1167     if (!xlnx_dpdma_start_operation(s->dpdma, 3, false)) {
1168         /*
1169          * An error occurred don't do anything with the data..
1170          * Trigger an underflow interrupt.
1171          */
1172         s->core_registers[DP_INT_STATUS] |= (1 << 21);
1173         xlnx_dp_update_irq(s);
1174         return;
1175     }
1176
1177     if (xlnx_dp_global_alpha_enabled(s)) {
1178         if (!xlnx_dpdma_start_operation(s->dpdma, 0, false)) {
1179             s->core_registers[DP_INT_STATUS] |= (1 << 21);
1180             xlnx_dp_update_irq(s);
1181             return;
1182         }
1183         xlnx_dp_blend_surface(s);
1184     }
1185
1186     /*
1187      * XXX: We might want to update only what changed.
1188      */
1189     dpy_gfx_update_full(s->console);
1190 }
1191
1192 static const GraphicHwOps xlnx_dp_gfx_ops = {
1193     .gfx_update  = xlnx_dp_update_display,
1194 };
1195
1196 static void xlnx_dp_init(Object *obj)
1197 {
1198     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1199     XlnxDPState *s = XLNX_DP(obj);
1200
1201     memory_region_init(&s->container, obj, TYPE_XLNX_DP, 0xC050);
1202
1203     memory_region_init_io(&s->core_iomem, obj, &dp_ops, s, TYPE_XLNX_DP
1204                           ".core", 0x3AF);
1205     memory_region_add_subregion(&s->container, 0x0000, &s->core_iomem);
1206
1207     memory_region_init_io(&s->vblend_iomem, obj, &vblend_ops, s, TYPE_XLNX_DP
1208                           ".v_blend", 0x1DF);
1209     memory_region_add_subregion(&s->container, 0xA000, &s->vblend_iomem);
1210
1211     memory_region_init_io(&s->avbufm_iomem, obj, &avbufm_ops, s, TYPE_XLNX_DP
1212                           ".av_buffer_manager", 0x238);
1213     memory_region_add_subregion(&s->container, 0xB000, &s->avbufm_iomem);
1214
1215     memory_region_init_io(&s->audio_iomem, obj, &audio_ops, s, TYPE_XLNX_DP
1216                           ".audio", sizeof(s->audio_registers));
1217     memory_region_add_subregion(&s->container, 0xC000, &s->audio_iomem);
1218
1219     sysbus_init_mmio(sbd, &s->container);
1220     sysbus_init_irq(sbd, &s->irq);
1221
1222     object_property_add_link(obj, "dpdma", TYPE_XLNX_DPDMA,
1223                              (Object **) &s->dpdma,
1224                              xlnx_dp_set_dpdma,
1225                              OBJ_PROP_LINK_STRONG,
1226                              &error_abort);
1227
1228     /*
1229      * Initialize AUX Bus.
1230      */
1231     s->aux_bus = aux_init_bus(DEVICE(obj), "aux");
1232
1233     /*
1234      * Initialize DPCD and EDID..
1235      */
1236     s->dpcd = DPCD(aux_create_slave(s->aux_bus, "dpcd"));
1237     object_property_add_child(OBJECT(s), "dpcd", OBJECT(s->dpcd), NULL);
1238
1239     s->edid = I2CDDC(qdev_create(BUS(aux_get_i2c_bus(s->aux_bus)), "i2c-ddc"));
1240     i2c_set_slave_address(I2C_SLAVE(s->edid), 0x50);
1241     object_property_add_child(OBJECT(s), "edid", OBJECT(s->edid), NULL);
1242
1243     fifo8_create(&s->rx_fifo, 16);
1244     fifo8_create(&s->tx_fifo, 16);
1245 }
1246
1247 static void xlnx_dp_realize(DeviceState *dev, Error **errp)
1248 {
1249     XlnxDPState *s = XLNX_DP(dev);
1250     DisplaySurface *surface;
1251     struct audsettings as;
1252
1253     qdev_init_nofail(DEVICE(s->dpcd));
1254     aux_map_slave(AUX_SLAVE(s->dpcd), 0x0000);
1255
1256     s->console = graphic_console_init(dev, 0, &xlnx_dp_gfx_ops, s);
1257     surface = qemu_console_surface(s->console);
1258     xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL,
1259                                       surface_data(surface));
1260
1261     as.freq = 44100;
1262     as.nchannels = 2;
1263     as.fmt = AUDIO_FORMAT_S16;
1264     as.endianness = 0;
1265
1266     AUD_register_card("xlnx_dp.audio", &s->aud_card);
1267
1268     s->amixer_output_stream = AUD_open_out(&s->aud_card,
1269                                            s->amixer_output_stream,
1270                                            "xlnx_dp.audio.out",
1271                                            s,
1272                                            xlnx_dp_audio_callback,
1273                                            &as);
1274     AUD_set_volume_out(s->amixer_output_stream, 0, 255, 255);
1275     xlnx_dp_audio_activate(s);
1276 }
1277
1278 static void xlnx_dp_reset(DeviceState *dev)
1279 {
1280     XlnxDPState *s = XLNX_DP(dev);
1281
1282     memset(s->core_registers, 0, sizeof(s->core_registers));
1283     s->core_registers[DP_VERSION_REGISTER] = 0x04010000;
1284     s->core_registers[DP_CORE_ID] = 0x01020000;
1285     s->core_registers[DP_REPLY_STATUS] = 0x00000010;
1286     s->core_registers[DP_MSA_TRANSFER_UNIT_SIZE] = 0x00000040;
1287     s->core_registers[DP_INIT_WAIT] = 0x00000020;
1288     s->core_registers[DP_PHY_RESET] = 0x00010003;
1289     s->core_registers[DP_INT_MASK] = 0xFFFFF03F;
1290     s->core_registers[DP_PHY_STATUS] = 0x00000043;
1291     s->core_registers[DP_INTERRUPT_SIGNAL_STATE] = 0x00000001;
1292
1293     s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(0)] = 0x00001000;
1294     s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(4)] = 0x00001000;
1295     s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(8)] = 0x00001000;
1296     s->vblend_registers[V_BLEND_IN1CSC_COEFF(0)] = 0x00001000;
1297     s->vblend_registers[V_BLEND_IN1CSC_COEFF(4)] = 0x00001000;
1298     s->vblend_registers[V_BLEND_IN1CSC_COEFF(8)] = 0x00001000;
1299     s->vblend_registers[V_BLEND_IN2CSC_COEFF(0)] = 0x00001000;
1300     s->vblend_registers[V_BLEND_IN2CSC_COEFF(4)] = 0x00001000;
1301     s->vblend_registers[V_BLEND_IN2CSC_COEFF(8)] = 0x00001000;
1302
1303     s->avbufm_registers[AV_BUF_NON_LIVE_LATENCY] = 0x00000180;
1304     s->avbufm_registers[AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT] = 0x00000008;
1305     s->avbufm_registers[AV_BUF_DITHER_CONFIG_MAX] = 0x00000FFF;
1306     s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0)] = 0x00010101;
1307     s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1)] = 0x00010101;
1308     s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2)] = 0x00010101;
1309     s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(0)] = 0x00010101;
1310     s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(1)] = 0x00010101;
1311     s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(2)] = 0x00010101;
1312     s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(0)] = 0x00010101;
1313     s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(1)] = 0x00010101;
1314     s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(2)] = 0x00010101;
1315     s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(0)] = 0x00010101;
1316     s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(1)] = 0x00010101;
1317     s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(2)] = 0x00010101;
1318
1319     memset(s->audio_registers, 0, sizeof(s->audio_registers));
1320     s->byte_left = 0;
1321
1322     xlnx_dp_aux_clear_rx_fifo(s);
1323     xlnx_dp_change_graphic_fmt(s);
1324     xlnx_dp_update_irq(s);
1325 }
1326
1327 static void xlnx_dp_class_init(ObjectClass *oc, void *data)
1328 {
1329     DeviceClass *dc = DEVICE_CLASS(oc);
1330
1331     dc->realize = xlnx_dp_realize;
1332     dc->vmsd = &vmstate_dp;
1333     dc->reset = xlnx_dp_reset;
1334 }
1335
1336 static const TypeInfo xlnx_dp_info = {
1337     .name          = TYPE_XLNX_DP,
1338     .parent        = TYPE_SYS_BUS_DEVICE,
1339     .instance_size = sizeof(XlnxDPState),
1340     .instance_init = xlnx_dp_init,
1341     .class_init    = xlnx_dp_class_init,
1342 };
1343
1344 static void xlnx_dp_register_types(void)
1345 {
1346     type_register_static(&xlnx_dp_info);
1347 }
1348
1349 type_init(xlnx_dp_register_types)