hw/dma/i8257.c

   1 /*
   2  * QEMU DMA emulation
   3  *
   4  * Copyright (c) 2003-2004 Vassili Karpov (malc)
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "hw/hw.h"
  26 #include "hw/isa/isa.h"
  27 #include "qemu/main-loop.h"
  28 #include "trace.h"
  29
  30 #define TYPE_I8257 "i8257"
  31 #define I8257(obj) \
  32     OBJECT_CHECK(I8257State, (obj), TYPE_I8257)
  33
  34 /* #define DEBUG_DMA */
  35
  36 #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__)
  37 #ifdef DEBUG_DMA
  38 #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__)
  39 #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__)
  40 #else
  41 #define linfo(...)
  42 #define ldebug(...)
  43 #endif
  44
  45 typedef struct I8257Regs {
  46     int now[2];
  47     uint16_t base[2];
  48     uint8_t mode;
  49     uint8_t page;
  50     uint8_t pageh;
  51     uint8_t dack;
  52     uint8_t eop;
  53     DMA_transfer_handler transfer_handler;
  54     void *opaque;
  55 } I8257Regs;
  56
  57 #define ADDR 0
  58 #define COUNT 1
  59
  60 typedef struct I8257State {
  61     ISADevice parent_obj;
  62
  63     int32_t base;
  64     int32_t page_base;
  65     int32_t pageh_base;
  66     int32_t dshift;
  67
  68     uint8_t status;
  69     uint8_t command;
  70     uint8_t mask;
  71     uint8_t flip_flop;
  72     I8257Regs regs[4];
  73     MemoryRegion channel_io;
  74     MemoryRegion cont_io;
  75
  76     QEMUBH *dma_bh;
  77     bool dma_bh_scheduled;
  78     int running;
  79 } I8257State;
  80
  81 static I8257State *dma_controllers[2];
  82
  83 enum {
  84     CMD_MEMORY_TO_MEMORY = 0x01,
  85     CMD_FIXED_ADDRESS    = 0x02,
  86     CMD_BLOCK_CONTROLLER = 0x04,
  87     CMD_COMPRESSED_TIME  = 0x08,
  88     CMD_CYCLIC_PRIORITY  = 0x10,
  89     CMD_EXTENDED_WRITE   = 0x20,
  90     CMD_LOW_DREQ         = 0x40,
  91     CMD_LOW_DACK         = 0x80,
  92     CMD_NOT_SUPPORTED    = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS
  93     | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE
  94     | CMD_LOW_DREQ | CMD_LOW_DACK
  95
  96 };
  97
  98 static void i8257_dma_run(void *opaque);
  99
 100 static const int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
 101
 102 static void i8257_write_page(void *opaque, uint32_t nport, uint32_t data)
 103 {
 104     I8257State *d = opaque;
 105     int ichan;
 106
 107     ichan = channels[nport & 7];
 108     if (-1 == ichan) {
 109         dolog ("invalid channel %#x %#x\n", nport, data);
 110         return;
 111     }
 112     d->regs[ichan].page = data;
 113 }
 114
 115 static void i8257_write_pageh(void *opaque, uint32_t nport, uint32_t data)
 116 {
 117     I8257State *d = opaque;
 118     int ichan;
 119
 120     ichan = channels[nport & 7];
 121     if (-1 == ichan) {
 122         dolog ("invalid channel %#x %#x\n", nport, data);
 123         return;
 124     }
 125     d->regs[ichan].pageh = data;
 126 }
 127
 128 static uint32_t i8257_read_page(void *opaque, uint32_t nport)
 129 {
 130     I8257State *d = opaque;
 131     int ichan;
 132
 133     ichan = channels[nport & 7];
 134     if (-1 == ichan) {
 135         dolog ("invalid channel read %#x\n", nport);
 136         return 0;
 137     }
 138     return d->regs[ichan].page;
 139 }
 140
 141 static uint32_t i8257_read_pageh(void *opaque, uint32_t nport)
 142 {
 143     I8257State *d = opaque;
 144     int ichan;
 145
 146     ichan = channels[nport & 7];
 147     if (-1 == ichan) {
 148         dolog ("invalid channel read %#x\n", nport);
 149         return 0;
 150     }
 151     return d->regs[ichan].pageh;
 152 }
 153
 154 static inline void i8257_init_chan(I8257State *d, int ichan)
 155 {
 156     I8257Regs *r;
 157
 158     r = d->regs + ichan;
 159     r->now[ADDR] = r->base[ADDR] << d->dshift;
 160     r->now[COUNT] = 0;
 161 }
 162
 163 static inline int i8257_getff(I8257State *d)
 164 {
 165     int ff;
 166
 167     ff = d->flip_flop;
 168     d->flip_flop = !ff;
 169     return ff;
 170 }
 171
 172 static uint64_t i8257_read_chan(void *opaque, hwaddr nport, unsigned size)
 173 {
 174     I8257State *d = opaque;
 175     int ichan, nreg, iport, ff, val, dir;
 176     I8257Regs *r;
 177
 178     iport = (nport >> d->dshift) & 0x0f;
 179     ichan = iport >> 1;
 180     nreg = iport & 1;
 181     r = d->regs + ichan;
 182
 183     dir = ((r->mode >> 5) & 1) ? -1 : 1;
 184     ff = i8257_getff(d);
 185     if (nreg)
 186         val = (r->base[COUNT] << d->dshift) - r->now[COUNT];
 187     else
 188         val = r->now[ADDR] + r->now[COUNT] * dir;
 189
 190     ldebug ("read_chan %#x -> %d\n", iport, val);
 191     return (val >> (d->dshift + (ff << 3))) & 0xff;
 192 }
 193
 194 static void i8257_write_chan(void *opaque, hwaddr nport, uint64_t data,
 195                              unsigned int size)
 196 {
 197     I8257State *d = opaque;
 198     int iport, ichan, nreg;
 199     I8257Regs *r;
 200
 201     iport = (nport >> d->dshift) & 0x0f;
 202     ichan = iport >> 1;
 203     nreg = iport & 1;
 204     r = d->regs + ichan;
 205     if (i8257_getff(d)) {
 206         r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00);
 207         i8257_init_chan(d, ichan);
 208     } else {
 209         r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff);
 210     }
 211 }
 212
 213 static void i8257_write_cont(void *opaque, hwaddr nport, uint64_t data,
 214                              unsigned int size)
 215 {
 216     I8257State *d = opaque;
 217     int iport, ichan = 0;
 218
 219     iport = (nport >> d->dshift) & 0x0f;
 220     switch (iport) {
 221     case 0x00:                  /* command */
 222         if ((data != 0) && (data & CMD_NOT_SUPPORTED)) {
 223             dolog("command %"PRIx64" not supported\n", data);
 224             return;
 225         }
 226         d->command = data;
 227         break;
 228
 229     case 0x01:
 230         ichan = data & 3;
 231         if (data & 4) {
 232             d->status |= 1 << (ichan + 4);
 233         }
 234         else {
 235             d->status &= ~(1 << (ichan + 4));
 236         }
 237         d->status &= ~(1 << ichan);
 238         i8257_dma_run(d);
 239         break;
 240
 241     case 0x02:                  /* single mask */
 242         if (data & 4)
 243             d->mask |= 1 << (data & 3);
 244         else
 245             d->mask &= ~(1 << (data & 3));
 246         i8257_dma_run(d);
 247         break;
 248
 249     case 0x03:                  /* mode */
 250         {
 251             ichan = data & 3;
 252 #ifdef DEBUG_DMA
 253             {
 254                 int op, ai, dir, opmode;
 255                 op = (data >> 2) & 3;
 256                 ai = (data >> 4) & 1;
 257                 dir = (data >> 5) & 1;
 258                 opmode = (data >> 6) & 3;
 259
 260                 linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
 261                        ichan, op, ai, dir, opmode);
 262             }
 263 #endif
 264             d->regs[ichan].mode = data;
 265             break;
 266         }
 267
 268     case 0x04:                  /* clear flip flop */
 269         d->flip_flop = 0;
 270         break;
 271
 272     case 0x05:                  /* reset */
 273         d->flip_flop = 0;
 274         d->mask = ~0;
 275         d->status = 0;
 276         d->command = 0;
 277         break;
 278
 279     case 0x06:                  /* clear mask for all channels */
 280         d->mask = 0;
 281         i8257_dma_run(d);
 282         break;
 283
 284     case 0x07:                  /* write mask for all channels */
 285         d->mask = data;
 286         i8257_dma_run(d);
 287         break;
 288
 289     default:
 290         dolog ("unknown iport %#x\n", iport);
 291         break;
 292     }
 293
 294 #ifdef DEBUG_DMA
 295     if (0xc != iport) {
 296         linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n",
 297                nport, ichan, data);
 298     }
 299 #endif
 300 }
 301
 302 static uint64_t i8257_read_cont(void *opaque, hwaddr nport, unsigned size)
 303 {
 304     I8257State *d = opaque;
 305     int iport, val;
 306
 307     iport = (nport >> d->dshift) & 0x0f;
 308     switch (iport) {
 309     case 0x00:                  /* status */
 310         val = d->status;
 311         d->status &= 0xf0;
 312         break;
 313     case 0x01:                  /* mask */
 314         val = d->mask;
 315         break;
 316     default:
 317         val = 0;
 318         break;
 319     }
 320
 321     ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val);
 322     return val;
 323 }
 324
 325 int DMA_get_channel_mode (int nchan)
 326 {
 327     return dma_controllers[nchan > 3]->regs[nchan & 3].mode;
 328 }
 329
 330 void DMA_hold_DREQ (int nchan)
 331 {
 332     int ncont, ichan;
 333
 334     ncont = nchan > 3;
 335     ichan = nchan & 3;
 336     linfo ("held cont=%d chan=%d\n", ncont, ichan);
 337     dma_controllers[ncont]->status |= 1 << (ichan + 4);
 338     i8257_dma_run(dma_controllers[ncont]);
 339 }
 340
 341 void DMA_release_DREQ (int nchan)
 342 {
 343     int ncont, ichan;
 344
 345     ncont = nchan > 3;
 346     ichan = nchan & 3;
 347     linfo ("released cont=%d chan=%d\n", ncont, ichan);
 348     dma_controllers[ncont]->status &= ~(1 << (ichan + 4));
 349     i8257_dma_run(dma_controllers[ncont]);
 350 }
 351
 352 static void i8257_channel_run(I8257State *d, int ichan)
 353 {
 354     int ncont = d->dshift;
 355     int n;
 356     I8257Regs *r = &d->regs[ichan];
 357 #ifdef DEBUG_DMA
 358     int dir, opmode;
 359
 360     dir = (r->mode >> 5) & 1;
 361     opmode = (r->mode >> 6) & 3;
 362
 363     if (dir) {
 364         dolog ("DMA in address decrement mode\n");
 365     }
 366     if (opmode != 1) {
 367         dolog ("DMA not in single mode select %#x\n", opmode);
 368     }
 369 #endif
 370
 371     n = r->transfer_handler (r->opaque, ichan + (ncont << 2),
 372                              r->now[COUNT], (r->base[COUNT] + 1) << ncont);
 373     r->now[COUNT] = n;
 374     ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont);
 375 }
 376
 377 static void i8257_dma_run(void *opaque)
 378 {
 379     I8257State *d = opaque;
 380     int ichan;
 381     int rearm = 0;
 382
 383     if (d->running) {
 384         rearm = 1;
 385         goto out;
 386     } else {
 387         d->running = 1;
 388     }
 389
 390     for (ichan = 0; ichan < 4; ichan++) {
 391         int mask;
 392
 393         mask = 1 << ichan;
 394
 395         if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) {
 396             i8257_channel_run(d, ichan);
 397             rearm = 1;
 398         }
 399     }
 400
 401     d->running = 0;
 402 out:
 403     if (rearm) {
 404         qemu_bh_schedule_idle(d->dma_bh);
 405         d->dma_bh_scheduled = true;
 406     }
 407 }
 408
 409 void DMA_register_channel (int nchan,
 410                            DMA_transfer_handler transfer_handler,
 411                            void *opaque)
 412 {
 413     I8257Regs *r;
 414     int ichan, ncont;
 415
 416     ncont = nchan > 3;
 417     ichan = nchan & 3;
 418
 419     r = dma_controllers[ncont]->regs + ichan;
 420     r->transfer_handler = transfer_handler;
 421     r->opaque = opaque;
 422 }
 423
 424 int DMA_read_memory (int nchan, void *buf, int pos, int len)
 425 {
 426     I8257Regs *r = &dma_controllers[nchan > 3]->regs[nchan & 3];
 427     hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
 428
 429     if (r->mode & 0x20) {
 430         int i;
 431         uint8_t *p = buf;
 432
 433         cpu_physical_memory_read (addr - pos - len, buf, len);
 434         /* What about 16bit transfers? */
 435         for (i = 0; i < len >> 1; i++) {
 436             uint8_t b = p[len - i - 1];
 437             p[i] = b;
 438         }
 439     }
 440     else
 441         cpu_physical_memory_read (addr + pos, buf, len);
 442
 443     return len;
 444 }
 445
 446 int DMA_write_memory (int nchan, void *buf, int pos, int len)
 447 {
 448     I8257Regs *r = &dma_controllers[nchan > 3]->regs[nchan & 3];
 449     hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
 450
 451     if (r->mode & 0x20) {
 452         int i;
 453         uint8_t *p = buf;
 454
 455         cpu_physical_memory_write (addr - pos - len, buf, len);
 456         /* What about 16bit transfers? */
 457         for (i = 0; i < len; i++) {
 458             uint8_t b = p[len - i - 1];
 459             p[i] = b;
 460         }
 461     }
 462     else
 463         cpu_physical_memory_write (addr + pos, buf, len);
 464
 465     return len;
 466 }
 467
 468 /* request the emulator to transfer a new DMA memory block ASAP (even
 469  * if the idle bottom half would not have exited the iothread yet).
 470  */
 471 void DMA_schedule(void)
 472 {
 473     if (dma_controllers[0]->dma_bh_scheduled ||
 474         dma_controllers[1]->dma_bh_scheduled) {
 475         qemu_notify_event();
 476     }
 477 }
 478
 479 static void i8257_reset(DeviceState *dev)
 480 {
 481     I8257State *d = I8257(dev);
 482     i8257_write_cont(d, (0x05 << d->dshift), 0, 1);
 483 }
 484
 485 static int i8257_phony_handler(void *opaque, int nchan, int dma_pos,
 486                                int dma_len)
 487 {
 488     trace_i8257_unregistered_dma(nchan, dma_pos, dma_len);
 489     return dma_pos;
 490 }
 491
 492
 493 static const MemoryRegionOps channel_io_ops = {
 494     .read = i8257_read_chan,
 495     .write = i8257_write_chan,
 496     .endianness = DEVICE_NATIVE_ENDIAN,
 497     .impl = {
 498         .min_access_size = 1,
 499         .max_access_size = 1,
 500     },
 501 };
 502
 503 /* IOport from page_base */
 504 static const MemoryRegionPortio page_portio_list[] = {
 505     { 0x01, 3, 1, .write = i8257_write_page, .read = i8257_read_page, },
 506     { 0x07, 1, 1, .write = i8257_write_page, .read = i8257_read_page, },
 507     PORTIO_END_OF_LIST(),
 508 };
 509
 510 /* IOport from pageh_base */
 511 static const MemoryRegionPortio pageh_portio_list[] = {
 512     { 0x01, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, },
 513     { 0x07, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, },
 514     PORTIO_END_OF_LIST(),
 515 };
 516
 517 static const MemoryRegionOps cont_io_ops = {
 518     .read = i8257_read_cont,
 519     .write = i8257_write_cont,
 520     .endianness = DEVICE_NATIVE_ENDIAN,
 521     .impl = {
 522         .min_access_size = 1,
 523         .max_access_size = 1,
 524     },
 525 };
 526
 527 static const VMStateDescription vmstate_i8257_regs = {
 528     .name = "dma_regs",
 529     .version_id = 1,
 530     .minimum_version_id = 1,
 531     .fields = (VMStateField[]) {
 532         VMSTATE_INT32_ARRAY(now, I8257Regs, 2),
 533         VMSTATE_UINT16_ARRAY(base, I8257Regs, 2),
 534         VMSTATE_UINT8(mode, I8257Regs),
 535         VMSTATE_UINT8(page, I8257Regs),
 536         VMSTATE_UINT8(pageh, I8257Regs),
 537         VMSTATE_UINT8(dack, I8257Regs),
 538         VMSTATE_UINT8(eop, I8257Regs),
 539         VMSTATE_END_OF_LIST()
 540     }
 541 };
 542
 543 static int i8257_post_load(void *opaque, int version_id)
 544 {
 545     I8257State *d = opaque;
 546     i8257_dma_run(d);
 547
 548     return 0;
 549 }
 550
 551 static const VMStateDescription vmstate_i8257 = {
 552     .name = "dma",
 553     .version_id = 1,
 554     .minimum_version_id = 1,
 555     .post_load = i8257_post_load,
 556     .fields = (VMStateField[]) {
 557         VMSTATE_UINT8(command, I8257State),
 558         VMSTATE_UINT8(mask, I8257State),
 559         VMSTATE_UINT8(flip_flop, I8257State),
 560         VMSTATE_INT32(dshift, I8257State),
 561         VMSTATE_STRUCT_ARRAY(regs, I8257State, 4, 1, vmstate_i8257_regs,
 562                              I8257Regs),
 563         VMSTATE_END_OF_LIST()
 564     }
 565 };
 566
 567 static void i8257_realize(DeviceState *dev, Error **errp)
 568 {
 569     ISADevice *isa = ISA_DEVICE(dev);
 570     I8257State *d = I8257(dev);
 571     int i;
 572
 573     memory_region_init_io(&d->channel_io, NULL, &channel_io_ops, d,
 574                           "dma-chan", 8 << d->dshift);
 575     memory_region_add_subregion(isa_address_space_io(isa),
 576                                 d->base, &d->channel_io);
 577
 578     isa_register_portio_list(isa, d->page_base, page_portio_list, d,
 579                              "dma-page");
 580     if (d->pageh_base >= 0) {
 581         isa_register_portio_list(isa, d->pageh_base, pageh_portio_list, d,
 582                                  "dma-pageh");
 583     }
 584
 585     memory_region_init_io(&d->cont_io, OBJECT(isa), &cont_io_ops, d,
 586                           "dma-cont", 8 << d->dshift);
 587     memory_region_add_subregion(isa_address_space_io(isa),
 588                                 d->base + (8 << d->dshift), &d->cont_io);
 589
 590     for (i = 0; i < ARRAY_SIZE(d->regs); ++i) {
 591         d->regs[i].transfer_handler = i8257_phony_handler;
 592     }
 593
 594     d->dma_bh = qemu_bh_new(i8257_dma_run, d);
 595 }
 596
 597 static Property i8257_properties[] = {
 598     DEFINE_PROP_INT32("base", I8257State, base, 0x00),
 599     DEFINE_PROP_INT32("page-base", I8257State, page_base, 0x80),
 600     DEFINE_PROP_INT32("pageh-base", I8257State, pageh_base, 0x480),
 601     DEFINE_PROP_INT32("dshift", I8257State, dshift, 0),
 602     DEFINE_PROP_END_OF_LIST()
 603 };
 604
 605 static void i8257_class_init(ObjectClass *klass, void *data)
 606 {
 607     DeviceClass *dc = DEVICE_CLASS(klass);
 608
 609     dc->realize = i8257_realize;
 610     dc->reset = i8257_reset;
 611     dc->vmsd = &vmstate_i8257;
 612     dc->props = i8257_properties;
 613 }
 614
 615 static const TypeInfo i8257_info = {
 616     .name = TYPE_I8257,
 617     .parent = TYPE_ISA_DEVICE,
 618     .instance_size = sizeof(I8257State),
 619     .class_init = i8257_class_init,
 620 };
 621
 622 static void i8257_register_types(void)
 623 {
 624     type_register_static(&i8257_info);
 625 }
 626
 627 type_init(i8257_register_types)
 628
 629 void DMA_init(ISABus *bus, int high_page_enable)
 630 {
 631     ISADevice *isa1, *isa2;
 632     DeviceState *d;
 633
 634     isa1 = isa_create(bus, TYPE_I8257);
 635     d = DEVICE(isa1);
 636     qdev_prop_set_int32(d, "base", 0x00);
 637     qdev_prop_set_int32(d, "page-base", 0x80);
 638     qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x480 : -1);
 639     qdev_prop_set_int32(d, "dshift", 0);
 640     qdev_init_nofail(d);
 641     dma_controllers[0] = I8257(d);
 642
 643     isa2 = isa_create(bus, TYPE_I8257);
 644     d = DEVICE(isa2);
 645     qdev_prop_set_int32(d, "base", 0xc0);
 646     qdev_prop_set_int32(d, "page-base", 0x88);
 647     qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x488 : -1);
 648     qdev_prop_set_int32(d, "dshift", 1);
 649     qdev_init_nofail(d);
 650     dma_controllers[1] = I8257(d);
 651 }