4 * Copyright (c) 2003-2004 Vassili Karpov (malc)
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "qemu/osdep.h"
26 #include "hw/isa/isa.h"
27 #include "qemu/main-loop.h"
30 /* #define DEBUG_DMA */
32 #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__)
34 #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__)
35 #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__)
41 typedef struct I8257Regs
{
49 DMA_transfer_handler transfer_handler
;
56 typedef struct I8257State
{
63 MemoryRegion channel_io
;
67 bool dma_bh_scheduled
;
71 static I8257State dma_controllers
[2];
74 CMD_MEMORY_TO_MEMORY
= 0x01,
75 CMD_FIXED_ADDRESS
= 0x02,
76 CMD_BLOCK_CONTROLLER
= 0x04,
77 CMD_COMPRESSED_TIME
= 0x08,
78 CMD_CYCLIC_PRIORITY
= 0x10,
79 CMD_EXTENDED_WRITE
= 0x20,
82 CMD_NOT_SUPPORTED
= CMD_MEMORY_TO_MEMORY
| CMD_FIXED_ADDRESS
83 | CMD_COMPRESSED_TIME
| CMD_CYCLIC_PRIORITY
| CMD_EXTENDED_WRITE
84 | CMD_LOW_DREQ
| CMD_LOW_DACK
88 static void i8257_dma_run(void *opaque
);
90 static int channels
[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
92 static void i8257_write_page(void *opaque
, uint32_t nport
, uint32_t data
)
94 I8257State
*d
= opaque
;
97 ichan
= channels
[nport
& 7];
99 dolog ("invalid channel %#x %#x\n", nport
, data
);
102 d
->regs
[ichan
].page
= data
;
105 static void i8257_write_pageh(void *opaque
, uint32_t nport
, uint32_t data
)
107 I8257State
*d
= opaque
;
110 ichan
= channels
[nport
& 7];
112 dolog ("invalid channel %#x %#x\n", nport
, data
);
115 d
->regs
[ichan
].pageh
= data
;
118 static uint32_t i8257_read_page(void *opaque
, uint32_t nport
)
120 I8257State
*d
= opaque
;
123 ichan
= channels
[nport
& 7];
125 dolog ("invalid channel read %#x\n", nport
);
128 return d
->regs
[ichan
].page
;
131 static uint32_t i8257_read_pageh(void *opaque
, uint32_t nport
)
133 I8257State
*d
= opaque
;
136 ichan
= channels
[nport
& 7];
138 dolog ("invalid channel read %#x\n", nport
);
141 return d
->regs
[ichan
].pageh
;
144 static inline void i8257_init_chan(I8257State
*d
, int ichan
)
149 r
->now
[ADDR
] = r
->base
[ADDR
] << d
->dshift
;
153 static inline int i8257_getff(I8257State
*d
)
162 static uint64_t i8257_read_chan(void *opaque
, hwaddr nport
, unsigned size
)
164 I8257State
*d
= opaque
;
165 int ichan
, nreg
, iport
, ff
, val
, dir
;
168 iport
= (nport
>> d
->dshift
) & 0x0f;
173 dir
= ((r
->mode
>> 5) & 1) ? -1 : 1;
176 val
= (r
->base
[COUNT
] << d
->dshift
) - r
->now
[COUNT
];
178 val
= r
->now
[ADDR
] + r
->now
[COUNT
] * dir
;
180 ldebug ("read_chan %#x -> %d\n", iport
, val
);
181 return (val
>> (d
->dshift
+ (ff
<< 3))) & 0xff;
184 static void i8257_write_chan(void *opaque
, hwaddr nport
, uint64_t data
,
187 I8257State
*d
= opaque
;
188 int iport
, ichan
, nreg
;
191 iport
= (nport
>> d
->dshift
) & 0x0f;
195 if (i8257_getff(d
)) {
196 r
->base
[nreg
] = (r
->base
[nreg
] & 0xff) | ((data
<< 8) & 0xff00);
197 i8257_init_chan(d
, ichan
);
199 r
->base
[nreg
] = (r
->base
[nreg
] & 0xff00) | (data
& 0xff);
203 static void i8257_write_cont(void *opaque
, hwaddr nport
, uint64_t data
,
206 I8257State
*d
= opaque
;
207 int iport
, ichan
= 0;
209 iport
= (nport
>> d
->dshift
) & 0x0f;
211 case 0x00: /* command */
212 if ((data
!= 0) && (data
& CMD_NOT_SUPPORTED
)) {
213 dolog("command %"PRIx64
" not supported\n", data
);
222 d
->status
|= 1 << (ichan
+ 4);
225 d
->status
&= ~(1 << (ichan
+ 4));
227 d
->status
&= ~(1 << ichan
);
231 case 0x02: /* single mask */
233 d
->mask
|= 1 << (data
& 3);
235 d
->mask
&= ~(1 << (data
& 3));
239 case 0x03: /* mode */
244 int op
, ai
, dir
, opmode
;
245 op
= (data
>> 2) & 3;
246 ai
= (data
>> 4) & 1;
247 dir
= (data
>> 5) & 1;
248 opmode
= (data
>> 6) & 3;
250 linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
251 ichan
, op
, ai
, dir
, opmode
);
254 d
->regs
[ichan
].mode
= data
;
258 case 0x04: /* clear flip flop */
262 case 0x05: /* reset */
269 case 0x06: /* clear mask for all channels */
274 case 0x07: /* write mask for all channels */
280 dolog ("unknown iport %#x\n", iport
);
286 linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n",
292 static uint64_t i8257_read_cont(void *opaque
, hwaddr nport
, unsigned size
)
294 I8257State
*d
= opaque
;
297 iport
= (nport
>> d
->dshift
) & 0x0f;
299 case 0x00: /* status */
303 case 0x01: /* mask */
311 ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport
, iport
, val
);
315 int DMA_get_channel_mode (int nchan
)
317 return dma_controllers
[nchan
> 3].regs
[nchan
& 3].mode
;
320 void DMA_hold_DREQ (int nchan
)
326 linfo ("held cont=%d chan=%d\n", ncont
, ichan
);
327 dma_controllers
[ncont
].status
|= 1 << (ichan
+ 4);
328 i8257_dma_run(&dma_controllers
[ncont
]);
331 void DMA_release_DREQ (int nchan
)
337 linfo ("released cont=%d chan=%d\n", ncont
, ichan
);
338 dma_controllers
[ncont
].status
&= ~(1 << (ichan
+ 4));
339 i8257_dma_run(&dma_controllers
[ncont
]);
342 static void i8257_channel_run(I8257State
*d
, int ichan
)
344 int ncont
= d
->dshift
;
346 I8257Regs
*r
= &d
->regs
[ichan
];
350 dir
= (r
->mode
>> 5) & 1;
351 opmode
= (r
->mode
>> 6) & 3;
354 dolog ("DMA in address decrement mode\n");
357 dolog ("DMA not in single mode select %#x\n", opmode
);
361 n
= r
->transfer_handler (r
->opaque
, ichan
+ (ncont
<< 2),
362 r
->now
[COUNT
], (r
->base
[COUNT
] + 1) << ncont
);
364 ldebug ("dma_pos %d size %d\n", n
, (r
->base
[COUNT
] + 1) << ncont
);
367 static void i8257_dma_run(void *opaque
)
369 I8257State
*d
= opaque
;
380 for (ichan
= 0; ichan
< 4; ichan
++) {
385 if ((0 == (d
->mask
& mask
)) && (0 != (d
->status
& (mask
<< 4)))) {
386 i8257_channel_run(d
, ichan
);
394 qemu_bh_schedule_idle(d
->dma_bh
);
395 d
->dma_bh_scheduled
= true;
399 void DMA_register_channel (int nchan
,
400 DMA_transfer_handler transfer_handler
,
409 r
= dma_controllers
[ncont
].regs
+ ichan
;
410 r
->transfer_handler
= transfer_handler
;
414 int DMA_read_memory (int nchan
, void *buf
, int pos
, int len
)
416 I8257Regs
*r
= &dma_controllers
[nchan
> 3].regs
[nchan
& 3];
417 hwaddr addr
= ((r
->pageh
& 0x7f) << 24) | (r
->page
<< 16) | r
->now
[ADDR
];
419 if (r
->mode
& 0x20) {
423 cpu_physical_memory_read (addr
- pos
- len
, buf
, len
);
424 /* What about 16bit transfers? */
425 for (i
= 0; i
< len
>> 1; i
++) {
426 uint8_t b
= p
[len
- i
- 1];
431 cpu_physical_memory_read (addr
+ pos
, buf
, len
);
436 int DMA_write_memory (int nchan
, void *buf
, int pos
, int len
)
438 I8257Regs
*r
= &dma_controllers
[nchan
> 3].regs
[nchan
& 3];
439 hwaddr addr
= ((r
->pageh
& 0x7f) << 24) | (r
->page
<< 16) | r
->now
[ADDR
];
441 if (r
->mode
& 0x20) {
445 cpu_physical_memory_write (addr
- pos
- len
, buf
, len
);
446 /* What about 16bit transfers? */
447 for (i
= 0; i
< len
; i
++) {
448 uint8_t b
= p
[len
- i
- 1];
453 cpu_physical_memory_write (addr
+ pos
, buf
, len
);
458 /* request the emulator to transfer a new DMA memory block ASAP (even
459 * if the idle bottom half would not have exited the iothread yet).
461 void DMA_schedule(void)
463 if (dma_controllers
[0].dma_bh_scheduled
||
464 dma_controllers
[1].dma_bh_scheduled
) {
469 static void i8257_reset(void *opaque
)
471 I8257State
*d
= opaque
;
472 i8257_write_cont(d
, (0x05 << d
->dshift
), 0, 1);
475 static int i8257_phony_handler(void *opaque
, int nchan
, int dma_pos
,
478 trace_i8257_unregistered_dma(nchan
, dma_pos
, dma_len
);
483 static const MemoryRegionOps channel_io_ops
= {
484 .read
= i8257_read_chan
,
485 .write
= i8257_write_chan
,
486 .endianness
= DEVICE_NATIVE_ENDIAN
,
488 .min_access_size
= 1,
489 .max_access_size
= 1,
493 /* IOport from page_base */
494 static const MemoryRegionPortio page_portio_list
[] = {
495 { 0x01, 3, 1, .write
= i8257_write_page
, .read
= i8257_read_page
, },
496 { 0x07, 1, 1, .write
= i8257_write_page
, .read
= i8257_read_page
, },
497 PORTIO_END_OF_LIST(),
500 /* IOport from pageh_base */
501 static const MemoryRegionPortio pageh_portio_list
[] = {
502 { 0x01, 3, 1, .write
= i8257_write_pageh
, .read
= i8257_read_pageh
, },
503 { 0x07, 3, 1, .write
= i8257_write_pageh
, .read
= i8257_read_pageh
, },
504 PORTIO_END_OF_LIST(),
507 static const MemoryRegionOps cont_io_ops
= {
508 .read
= i8257_read_cont
,
509 .write
= i8257_write_cont
,
510 .endianness
= DEVICE_NATIVE_ENDIAN
,
512 .min_access_size
= 1,
513 .max_access_size
= 1,
517 /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
518 static void dma_init2(I8257State
*d
, int base
, int dshift
,
519 int page_base
, int pageh_base
)
525 memory_region_init_io(&d
->channel_io
, NULL
, &channel_io_ops
, d
,
526 "dma-chan", 8 << d
->dshift
);
527 memory_region_add_subregion(isa_address_space_io(NULL
),
528 base
, &d
->channel_io
);
530 isa_register_portio_list(NULL
, page_base
, page_portio_list
, d
,
532 if (pageh_base
>= 0) {
533 isa_register_portio_list(NULL
, pageh_base
, pageh_portio_list
, d
,
537 memory_region_init_io(&d
->cont_io
, NULL
, &cont_io_ops
, d
, "dma-cont",
539 memory_region_add_subregion(isa_address_space_io(NULL
),
540 base
+ (8 << d
->dshift
), &d
->cont_io
);
542 qemu_register_reset(i8257_reset
, d
);
544 for (i
= 0; i
< ARRAY_SIZE (d
->regs
); ++i
) {
545 d
->regs
[i
].transfer_handler
= i8257_phony_handler
;
548 d
->dma_bh
= qemu_bh_new(i8257_dma_run
, d
);
551 static const VMStateDescription vmstate_i8257_regs
= {
554 .minimum_version_id
= 1,
555 .fields
= (VMStateField
[]) {
556 VMSTATE_INT32_ARRAY(now
, I8257Regs
, 2),
557 VMSTATE_UINT16_ARRAY(base
, I8257Regs
, 2),
558 VMSTATE_UINT8(mode
, I8257Regs
),
559 VMSTATE_UINT8(page
, I8257Regs
),
560 VMSTATE_UINT8(pageh
, I8257Regs
),
561 VMSTATE_UINT8(dack
, I8257Regs
),
562 VMSTATE_UINT8(eop
, I8257Regs
),
563 VMSTATE_END_OF_LIST()
567 static int i8257_post_load(void *opaque
, int version_id
)
569 I8257State
*d
= opaque
;
575 static const VMStateDescription vmstate_dma
= {
578 .minimum_version_id
= 1,
579 .post_load
= i8257_post_load
,
580 .fields
= (VMStateField
[]) {
581 VMSTATE_UINT8(command
, I8257State
),
582 VMSTATE_UINT8(mask
, I8257State
),
583 VMSTATE_UINT8(flip_flop
, I8257State
),
584 VMSTATE_INT32(dshift
, I8257State
),
585 VMSTATE_STRUCT_ARRAY(regs
, I8257State
, 4, 1, vmstate_i8257_regs
,
587 VMSTATE_END_OF_LIST()
591 void DMA_init(ISABus
*bus
, int high_page_enable
)
593 dma_init2(&dma_controllers
[0], 0x00, 0, 0x80, high_page_enable
? 0x480 : -1);
594 dma_init2(&dma_controllers
[1], 0xc0, 1, 0x88, high_page_enable
? 0x488 : -1);
595 vmstate_register (NULL
, 0, &vmstate_dma
, &dma_controllers
[0]);
596 vmstate_register (NULL
, 1, &vmstate_dma
, &dma_controllers
[1]);