4 * Copyright (c) 2003-2004 Vassili Karpov (malc)
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "hw/isa/isa.h"
27 #include "hw/qdev-properties.h"
28 #include "migration/vmstate.h"
29 #include "hw/dma/i8257.h"
30 #include "qemu/main-loop.h"
31 #include "qemu/module.h"
36 OBJECT_CHECK(I8257State, (obj), TYPE_I8257)
38 /* #define DEBUG_DMA */
40 #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__)
42 #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__)
43 #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__)
53 CMD_MEMORY_TO_MEMORY
= 0x01,
54 CMD_FIXED_ADDRESS
= 0x02,
55 CMD_BLOCK_CONTROLLER
= 0x04,
56 CMD_COMPRESSED_TIME
= 0x08,
57 CMD_CYCLIC_PRIORITY
= 0x10,
58 CMD_EXTENDED_WRITE
= 0x20,
61 CMD_NOT_SUPPORTED
= CMD_MEMORY_TO_MEMORY
| CMD_FIXED_ADDRESS
62 | CMD_COMPRESSED_TIME
| CMD_CYCLIC_PRIORITY
| CMD_EXTENDED_WRITE
63 | CMD_LOW_DREQ
| CMD_LOW_DACK
67 static void i8257_dma_run(void *opaque
);
69 static const int channels
[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
71 static void i8257_write_page(void *opaque
, uint32_t nport
, uint32_t data
)
73 I8257State
*d
= opaque
;
76 ichan
= channels
[nport
& 7];
78 dolog ("invalid channel %#x %#x\n", nport
, data
);
81 d
->regs
[ichan
].page
= data
;
84 static void i8257_write_pageh(void *opaque
, uint32_t nport
, uint32_t data
)
86 I8257State
*d
= opaque
;
89 ichan
= channels
[nport
& 7];
91 dolog ("invalid channel %#x %#x\n", nport
, data
);
94 d
->regs
[ichan
].pageh
= data
;
97 static uint32_t i8257_read_page(void *opaque
, uint32_t nport
)
99 I8257State
*d
= opaque
;
102 ichan
= channels
[nport
& 7];
104 dolog ("invalid channel read %#x\n", nport
);
107 return d
->regs
[ichan
].page
;
110 static uint32_t i8257_read_pageh(void *opaque
, uint32_t nport
)
112 I8257State
*d
= opaque
;
115 ichan
= channels
[nport
& 7];
117 dolog ("invalid channel read %#x\n", nport
);
120 return d
->regs
[ichan
].pageh
;
123 static inline void i8257_init_chan(I8257State
*d
, int ichan
)
128 r
->now
[ADDR
] = r
->base
[ADDR
] << d
->dshift
;
132 static inline int i8257_getff(I8257State
*d
)
141 static uint64_t i8257_read_chan(void *opaque
, hwaddr nport
, unsigned size
)
143 I8257State
*d
= opaque
;
144 int ichan
, nreg
, iport
, ff
, val
, dir
;
147 iport
= (nport
>> d
->dshift
) & 0x0f;
152 dir
= ((r
->mode
>> 5) & 1) ? -1 : 1;
155 val
= (r
->base
[COUNT
] << d
->dshift
) - r
->now
[COUNT
];
157 val
= r
->now
[ADDR
] + r
->now
[COUNT
] * dir
;
159 ldebug ("read_chan %#x -> %d\n", iport
, val
);
160 return (val
>> (d
->dshift
+ (ff
<< 3))) & 0xff;
163 static void i8257_write_chan(void *opaque
, hwaddr nport
, uint64_t data
,
166 I8257State
*d
= opaque
;
167 int iport
, ichan
, nreg
;
170 iport
= (nport
>> d
->dshift
) & 0x0f;
174 if (i8257_getff(d
)) {
175 r
->base
[nreg
] = (r
->base
[nreg
] & 0xff) | ((data
<< 8) & 0xff00);
176 i8257_init_chan(d
, ichan
);
178 r
->base
[nreg
] = (r
->base
[nreg
] & 0xff00) | (data
& 0xff);
182 static void i8257_write_cont(void *opaque
, hwaddr nport
, uint64_t data
,
185 I8257State
*d
= opaque
;
186 int iport
, ichan
= 0;
188 iport
= (nport
>> d
->dshift
) & 0x0f;
190 case 0x00: /* command */
191 if ((data
!= 0) && (data
& CMD_NOT_SUPPORTED
)) {
192 qemu_log_mask(LOG_UNIMP
, "%s: cmd 0x%02"PRIx64
" not supported\n",
202 d
->status
|= 1 << (ichan
+ 4);
205 d
->status
&= ~(1 << (ichan
+ 4));
207 d
->status
&= ~(1 << ichan
);
211 case 0x02: /* single mask */
213 d
->mask
|= 1 << (data
& 3);
215 d
->mask
&= ~(1 << (data
& 3));
219 case 0x03: /* mode */
224 int op
, ai
, dir
, opmode
;
225 op
= (data
>> 2) & 3;
226 ai
= (data
>> 4) & 1;
227 dir
= (data
>> 5) & 1;
228 opmode
= (data
>> 6) & 3;
230 linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
231 ichan
, op
, ai
, dir
, opmode
);
234 d
->regs
[ichan
].mode
= data
;
238 case 0x04: /* clear flip flop */
242 case 0x05: /* reset */
249 case 0x06: /* clear mask for all channels */
254 case 0x07: /* write mask for all channels */
260 dolog ("unknown iport %#x\n", iport
);
266 linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n",
272 static uint64_t i8257_read_cont(void *opaque
, hwaddr nport
, unsigned size
)
274 I8257State
*d
= opaque
;
277 iport
= (nport
>> d
->dshift
) & 0x0f;
279 case 0x00: /* status */
283 case 0x01: /* mask */
291 ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport
, iport
, val
);
295 static bool i8257_dma_has_autoinitialization(IsaDma
*obj
, int nchan
)
297 I8257State
*d
= I8257(obj
);
298 return (d
->regs
[nchan
& 3].mode
>> 4) & 1;
301 static void i8257_dma_hold_DREQ(IsaDma
*obj
, int nchan
)
303 I8257State
*d
= I8257(obj
);
307 d
->status
|= 1 << (ichan
+ 4);
311 static void i8257_dma_release_DREQ(IsaDma
*obj
, int nchan
)
313 I8257State
*d
= I8257(obj
);
317 d
->status
&= ~(1 << (ichan
+ 4));
321 static void i8257_channel_run(I8257State
*d
, int ichan
)
323 int ncont
= d
->dshift
;
325 I8257Regs
*r
= &d
->regs
[ichan
];
329 dir
= (r
->mode
>> 5) & 1;
330 opmode
= (r
->mode
>> 6) & 3;
333 dolog ("DMA in address decrement mode\n");
336 dolog ("DMA not in single mode select %#x\n", opmode
);
340 n
= r
->transfer_handler (r
->opaque
, ichan
+ (ncont
<< 2),
341 r
->now
[COUNT
], (r
->base
[COUNT
] + 1) << ncont
);
343 ldebug ("dma_pos %d size %d\n", n
, (r
->base
[COUNT
] + 1) << ncont
);
344 if (n
== (r
->base
[COUNT
] + 1) << ncont
) {
345 ldebug("transfer done\n");
346 d
->status
|= (1 << ichan
);
350 static void i8257_dma_run(void *opaque
)
352 I8257State
*d
= opaque
;
363 for (ichan
= 0; ichan
< 4; ichan
++) {
368 if ((0 == (d
->mask
& mask
)) && (0 != (d
->status
& (mask
<< 4)))) {
369 i8257_channel_run(d
, ichan
);
377 qemu_bh_schedule_idle(d
->dma_bh
);
378 d
->dma_bh_scheduled
= true;
382 static void i8257_dma_register_channel(IsaDma
*obj
, int nchan
,
383 IsaDmaTransferHandler transfer_handler
,
386 I8257State
*d
= I8257(obj
);
393 r
->transfer_handler
= transfer_handler
;
397 static bool i8257_is_verify_transfer(I8257Regs
*r
)
399 return (r
->mode
& 0x0c) == 0;
402 static int i8257_dma_read_memory(IsaDma
*obj
, int nchan
, void *buf
, int pos
,
405 I8257State
*d
= I8257(obj
);
406 I8257Regs
*r
= &d
->regs
[nchan
& 3];
407 hwaddr addr
= ((r
->pageh
& 0x7f) << 24) | (r
->page
<< 16) | r
->now
[ADDR
];
409 if (i8257_is_verify_transfer(r
)) {
413 if (r
->mode
& 0x20) {
417 cpu_physical_memory_read (addr
- pos
- len
, buf
, len
);
418 /* What about 16bit transfers? */
419 for (i
= 0; i
< len
>> 1; i
++) {
420 uint8_t b
= p
[len
- i
- 1];
425 cpu_physical_memory_read (addr
+ pos
, buf
, len
);
430 static int i8257_dma_write_memory(IsaDma
*obj
, int nchan
, void *buf
, int pos
,
433 I8257State
*s
= I8257(obj
);
434 I8257Regs
*r
= &s
->regs
[nchan
& 3];
435 hwaddr addr
= ((r
->pageh
& 0x7f) << 24) | (r
->page
<< 16) | r
->now
[ADDR
];
437 if (i8257_is_verify_transfer(r
)) {
441 if (r
->mode
& 0x20) {
445 cpu_physical_memory_write (addr
- pos
- len
, buf
, len
);
446 /* What about 16bit transfers? */
447 for (i
= 0; i
< len
; i
++) {
448 uint8_t b
= p
[len
- i
- 1];
453 cpu_physical_memory_write (addr
+ pos
, buf
, len
);
458 /* request the emulator to transfer a new DMA memory block ASAP (even
459 * if the idle bottom half would not have exited the iothread yet).
461 static void i8257_dma_schedule(IsaDma
*obj
)
463 I8257State
*d
= I8257(obj
);
464 if (d
->dma_bh_scheduled
) {
469 static void i8257_reset(DeviceState
*dev
)
471 I8257State
*d
= I8257(dev
);
472 i8257_write_cont(d
, (0x05 << d
->dshift
), 0, 1);
475 static int i8257_phony_handler(void *opaque
, int nchan
, int dma_pos
,
478 trace_i8257_unregistered_dma(nchan
, dma_pos
, dma_len
);
483 static const MemoryRegionOps channel_io_ops
= {
484 .read
= i8257_read_chan
,
485 .write
= i8257_write_chan
,
486 .endianness
= DEVICE_NATIVE_ENDIAN
,
488 .min_access_size
= 1,
489 .max_access_size
= 1,
493 /* IOport from page_base */
494 static const MemoryRegionPortio page_portio_list
[] = {
495 { 0x01, 3, 1, .write
= i8257_write_page
, .read
= i8257_read_page
, },
496 { 0x07, 1, 1, .write
= i8257_write_page
, .read
= i8257_read_page
, },
497 PORTIO_END_OF_LIST(),
500 /* IOport from pageh_base */
501 static const MemoryRegionPortio pageh_portio_list
[] = {
502 { 0x01, 3, 1, .write
= i8257_write_pageh
, .read
= i8257_read_pageh
, },
503 { 0x07, 3, 1, .write
= i8257_write_pageh
, .read
= i8257_read_pageh
, },
504 PORTIO_END_OF_LIST(),
507 static const MemoryRegionOps cont_io_ops
= {
508 .read
= i8257_read_cont
,
509 .write
= i8257_write_cont
,
510 .endianness
= DEVICE_NATIVE_ENDIAN
,
512 .min_access_size
= 1,
513 .max_access_size
= 1,
517 static const VMStateDescription vmstate_i8257_regs
= {
520 .minimum_version_id
= 1,
521 .fields
= (VMStateField
[]) {
522 VMSTATE_INT32_ARRAY(now
, I8257Regs
, 2),
523 VMSTATE_UINT16_ARRAY(base
, I8257Regs
, 2),
524 VMSTATE_UINT8(mode
, I8257Regs
),
525 VMSTATE_UINT8(page
, I8257Regs
),
526 VMSTATE_UINT8(pageh
, I8257Regs
),
527 VMSTATE_UINT8(dack
, I8257Regs
),
528 VMSTATE_UINT8(eop
, I8257Regs
),
529 VMSTATE_END_OF_LIST()
533 static int i8257_post_load(void *opaque
, int version_id
)
535 I8257State
*d
= opaque
;
541 static const VMStateDescription vmstate_i8257
= {
544 .minimum_version_id
= 1,
545 .post_load
= i8257_post_load
,
546 .fields
= (VMStateField
[]) {
547 VMSTATE_UINT8(command
, I8257State
),
548 VMSTATE_UINT8(mask
, I8257State
),
549 VMSTATE_UINT8(flip_flop
, I8257State
),
550 VMSTATE_INT32(dshift
, I8257State
),
551 VMSTATE_STRUCT_ARRAY(regs
, I8257State
, 4, 1, vmstate_i8257_regs
,
553 VMSTATE_END_OF_LIST()
557 static void i8257_realize(DeviceState
*dev
, Error
**errp
)
559 ISADevice
*isa
= ISA_DEVICE(dev
);
560 I8257State
*d
= I8257(dev
);
563 memory_region_init_io(&d
->channel_io
, OBJECT(dev
), &channel_io_ops
, d
,
564 "dma-chan", 8 << d
->dshift
);
565 memory_region_add_subregion(isa_address_space_io(isa
),
566 d
->base
, &d
->channel_io
);
568 isa_register_portio_list(isa
, &d
->portio_page
,
569 d
->page_base
, page_portio_list
, d
,
571 if (d
->pageh_base
>= 0) {
572 isa_register_portio_list(isa
, &d
->portio_pageh
,
573 d
->pageh_base
, pageh_portio_list
, d
,
577 memory_region_init_io(&d
->cont_io
, OBJECT(isa
), &cont_io_ops
, d
,
578 "dma-cont", 8 << d
->dshift
);
579 memory_region_add_subregion(isa_address_space_io(isa
),
580 d
->base
+ (8 << d
->dshift
), &d
->cont_io
);
582 for (i
= 0; i
< ARRAY_SIZE(d
->regs
); ++i
) {
583 d
->regs
[i
].transfer_handler
= i8257_phony_handler
;
586 d
->dma_bh
= qemu_bh_new(i8257_dma_run
, d
);
589 static Property i8257_properties
[] = {
590 DEFINE_PROP_INT32("base", I8257State
, base
, 0x00),
591 DEFINE_PROP_INT32("page-base", I8257State
, page_base
, 0x80),
592 DEFINE_PROP_INT32("pageh-base", I8257State
, pageh_base
, 0x480),
593 DEFINE_PROP_INT32("dshift", I8257State
, dshift
, 0),
594 DEFINE_PROP_END_OF_LIST()
597 static void i8257_class_init(ObjectClass
*klass
, void *data
)
599 DeviceClass
*dc
= DEVICE_CLASS(klass
);
600 IsaDmaClass
*idc
= ISADMA_CLASS(klass
);
602 dc
->realize
= i8257_realize
;
603 dc
->reset
= i8257_reset
;
604 dc
->vmsd
= &vmstate_i8257
;
605 device_class_set_props(dc
, i8257_properties
);
607 idc
->has_autoinitialization
= i8257_dma_has_autoinitialization
;
608 idc
->read_memory
= i8257_dma_read_memory
;
609 idc
->write_memory
= i8257_dma_write_memory
;
610 idc
->hold_DREQ
= i8257_dma_hold_DREQ
;
611 idc
->release_DREQ
= i8257_dma_release_DREQ
;
612 idc
->schedule
= i8257_dma_schedule
;
613 idc
->register_channel
= i8257_dma_register_channel
;
614 /* Reason: needs to be wired up by isa_bus_dma() to work */
615 dc
->user_creatable
= false;
618 static const TypeInfo i8257_info
= {
620 .parent
= TYPE_ISA_DEVICE
,
621 .instance_size
= sizeof(I8257State
),
622 .class_init
= i8257_class_init
,
623 .interfaces
= (InterfaceInfo
[]) {
629 static void i8257_register_types(void)
631 type_register_static(&i8257_info
);
634 type_init(i8257_register_types
)
636 void i8257_dma_init(ISABus
*bus
, bool high_page_enable
)
638 ISADevice
*isa1
, *isa2
;
641 isa1
= isa_create(bus
, TYPE_I8257
);
643 qdev_prop_set_int32(d
, "base", 0x00);
644 qdev_prop_set_int32(d
, "page-base", 0x80);
645 qdev_prop_set_int32(d
, "pageh-base", high_page_enable
? 0x480 : -1);
646 qdev_prop_set_int32(d
, "dshift", 0);
649 isa2
= isa_create(bus
, TYPE_I8257
);
651 qdev_prop_set_int32(d
, "base", 0xc0);
652 qdev_prop_set_int32(d
, "page-base", 0x88);
653 qdev_prop_set_int32(d
, "pageh-base", high_page_enable
? 0x488 : -1);
654 qdev_prop_set_int32(d
, "dshift", 1);
657 isa_bus_dma(bus
, ISADMA(isa1
), ISADMA(isa2
));