hw/dma/xlnx-zdma.c

   1 /*
   2  * QEMU model of the ZynqMP generic DMA
   3  *
   4  * Copyright (c) 2014 Xilinx Inc.
   5  * Copyright (c) 2018 FEIMTECH AB
   6  *
   7  * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>,
   8  *            Francisco Iglesias <francisco.iglesias@feimtech.se>
   9  *
  10  * Permission is hereby granted, free of charge, to any person obtaining a copy
  11  * of this software and associated documentation files (the "Software"), to deal
  12  * in the Software without restriction, including without limitation the rights
  13  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14  * copies of the Software, and to permit persons to whom the Software is
  15  * furnished to do so, subject to the following conditions:
  16  *
  17  * The above copyright notice and this permission notice shall be included in
  18  * all copies or substantial portions of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  25  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  26  * THE SOFTWARE.
  27  */
  28
  29 #include "qemu/osdep.h"
  30 #include "hw/dma/xlnx-zdma.h"
  31 #include "hw/irq.h"
  32 #include "hw/qdev-properties.h"
  33 #include "migration/vmstate.h"
  34 #include "qemu/bitops.h"
  35 #include "qemu/log.h"
  36 #include "qemu/module.h"
  37 #include "qapi/error.h"
  38
  39 #ifndef XLNX_ZDMA_ERR_DEBUG
  40 #define XLNX_ZDMA_ERR_DEBUG 0
  41 #endif
  42
  43 REG32(ZDMA_ERR_CTRL, 0x0)
  44     FIELD(ZDMA_ERR_CTRL, APB_ERR_RES, 0, 1)
  45 REG32(ZDMA_CH_ISR, 0x100)
  46     FIELD(ZDMA_CH_ISR, DMA_PAUSE, 11, 1)
  47     FIELD(ZDMA_CH_ISR, DMA_DONE, 10, 1)
  48     FIELD(ZDMA_CH_ISR, AXI_WR_DATA, 9, 1)
  49     FIELD(ZDMA_CH_ISR, AXI_RD_DATA, 8, 1)
  50     FIELD(ZDMA_CH_ISR, AXI_RD_DST_DSCR, 7, 1)
  51     FIELD(ZDMA_CH_ISR, AXI_RD_SRC_DSCR, 6, 1)
  52     FIELD(ZDMA_CH_ISR, IRQ_DST_ACCT_ERR, 5, 1)
  53     FIELD(ZDMA_CH_ISR, IRQ_SRC_ACCT_ERR, 4, 1)
  54     FIELD(ZDMA_CH_ISR, BYTE_CNT_OVRFL, 3, 1)
  55     FIELD(ZDMA_CH_ISR, DST_DSCR_DONE, 2, 1)
  56     FIELD(ZDMA_CH_ISR, SRC_DSCR_DONE, 1, 1)
  57     FIELD(ZDMA_CH_ISR, INV_APB, 0, 1)
  58 REG32(ZDMA_CH_IMR, 0x104)
  59     FIELD(ZDMA_CH_IMR, DMA_PAUSE, 11, 1)
  60     FIELD(ZDMA_CH_IMR, DMA_DONE, 10, 1)
  61     FIELD(ZDMA_CH_IMR, AXI_WR_DATA, 9, 1)
  62     FIELD(ZDMA_CH_IMR, AXI_RD_DATA, 8, 1)
  63     FIELD(ZDMA_CH_IMR, AXI_RD_DST_DSCR, 7, 1)
  64     FIELD(ZDMA_CH_IMR, AXI_RD_SRC_DSCR, 6, 1)
  65     FIELD(ZDMA_CH_IMR, IRQ_DST_ACCT_ERR, 5, 1)
  66     FIELD(ZDMA_CH_IMR, IRQ_SRC_ACCT_ERR, 4, 1)
  67     FIELD(ZDMA_CH_IMR, BYTE_CNT_OVRFL, 3, 1)
  68     FIELD(ZDMA_CH_IMR, DST_DSCR_DONE, 2, 1)
  69     FIELD(ZDMA_CH_IMR, SRC_DSCR_DONE, 1, 1)
  70     FIELD(ZDMA_CH_IMR, INV_APB, 0, 1)
  71 REG32(ZDMA_CH_IEN, 0x108)
  72     FIELD(ZDMA_CH_IEN, DMA_PAUSE, 11, 1)
  73     FIELD(ZDMA_CH_IEN, DMA_DONE, 10, 1)
  74     FIELD(ZDMA_CH_IEN, AXI_WR_DATA, 9, 1)
  75     FIELD(ZDMA_CH_IEN, AXI_RD_DATA, 8, 1)
  76     FIELD(ZDMA_CH_IEN, AXI_RD_DST_DSCR, 7, 1)
  77     FIELD(ZDMA_CH_IEN, AXI_RD_SRC_DSCR, 6, 1)
  78     FIELD(ZDMA_CH_IEN, IRQ_DST_ACCT_ERR, 5, 1)
  79     FIELD(ZDMA_CH_IEN, IRQ_SRC_ACCT_ERR, 4, 1)
  80     FIELD(ZDMA_CH_IEN, BYTE_CNT_OVRFL, 3, 1)
  81     FIELD(ZDMA_CH_IEN, DST_DSCR_DONE, 2, 1)
  82     FIELD(ZDMA_CH_IEN, SRC_DSCR_DONE, 1, 1)
  83     FIELD(ZDMA_CH_IEN, INV_APB, 0, 1)
  84 REG32(ZDMA_CH_IDS, 0x10c)
  85     FIELD(ZDMA_CH_IDS, DMA_PAUSE, 11, 1)
  86     FIELD(ZDMA_CH_IDS, DMA_DONE, 10, 1)
  87     FIELD(ZDMA_CH_IDS, AXI_WR_DATA, 9, 1)
  88     FIELD(ZDMA_CH_IDS, AXI_RD_DATA, 8, 1)
  89     FIELD(ZDMA_CH_IDS, AXI_RD_DST_DSCR, 7, 1)
  90     FIELD(ZDMA_CH_IDS, AXI_RD_SRC_DSCR, 6, 1)
  91     FIELD(ZDMA_CH_IDS, IRQ_DST_ACCT_ERR, 5, 1)
  92     FIELD(ZDMA_CH_IDS, IRQ_SRC_ACCT_ERR, 4, 1)
  93     FIELD(ZDMA_CH_IDS, BYTE_CNT_OVRFL, 3, 1)
  94     FIELD(ZDMA_CH_IDS, DST_DSCR_DONE, 2, 1)
  95     FIELD(ZDMA_CH_IDS, SRC_DSCR_DONE, 1, 1)
  96     FIELD(ZDMA_CH_IDS, INV_APB, 0, 1)
  97 REG32(ZDMA_CH_CTRL0, 0x110)
  98     FIELD(ZDMA_CH_CTRL0, OVR_FETCH, 7, 1)
  99     FIELD(ZDMA_CH_CTRL0, POINT_TYPE, 6, 1)
 100     FIELD(ZDMA_CH_CTRL0, MODE, 4, 2)
 101     FIELD(ZDMA_CH_CTRL0, RATE_CTRL, 3, 1)
 102     FIELD(ZDMA_CH_CTRL0, CONT_ADDR, 2, 1)
 103     FIELD(ZDMA_CH_CTRL0, CONT, 1, 1)
 104 REG32(ZDMA_CH_CTRL1, 0x114)
 105     FIELD(ZDMA_CH_CTRL1, DST_ISSUE, 5, 5)
 106     FIELD(ZDMA_CH_CTRL1, SRC_ISSUE, 0, 5)
 107 REG32(ZDMA_CH_FCI, 0x118)
 108     FIELD(ZDMA_CH_FCI, PROG_CELL_CNT, 2, 2)
 109     FIELD(ZDMA_CH_FCI, SIDE, 1, 1)
 110     FIELD(ZDMA_CH_FCI, EN, 0, 1)
 111 REG32(ZDMA_CH_STATUS, 0x11c)
 112     FIELD(ZDMA_CH_STATUS, STATE, 0, 2)
 113 REG32(ZDMA_CH_DATA_ATTR, 0x120)
 114     FIELD(ZDMA_CH_DATA_ATTR, ARBURST, 26, 2)
 115     FIELD(ZDMA_CH_DATA_ATTR, ARCACHE, 22, 4)
 116     FIELD(ZDMA_CH_DATA_ATTR, ARQOS, 18, 4)
 117     FIELD(ZDMA_CH_DATA_ATTR, ARLEN, 14, 4)
 118     FIELD(ZDMA_CH_DATA_ATTR, AWBURST, 12, 2)
 119     FIELD(ZDMA_CH_DATA_ATTR, AWCACHE, 8, 4)
 120     FIELD(ZDMA_CH_DATA_ATTR, AWQOS, 4, 4)
 121     FIELD(ZDMA_CH_DATA_ATTR, AWLEN, 0, 4)
 122 REG32(ZDMA_CH_DSCR_ATTR, 0x124)
 123     FIELD(ZDMA_CH_DSCR_ATTR, AXCOHRNT, 8, 1)
 124     FIELD(ZDMA_CH_DSCR_ATTR, AXCACHE, 4, 4)
 125     FIELD(ZDMA_CH_DSCR_ATTR, AXQOS, 0, 4)
 126 REG32(ZDMA_CH_SRC_DSCR_WORD0, 0x128)
 127 REG32(ZDMA_CH_SRC_DSCR_WORD1, 0x12c)
 128     FIELD(ZDMA_CH_SRC_DSCR_WORD1, MSB, 0, 17)
 129 REG32(ZDMA_CH_SRC_DSCR_WORD2, 0x130)
 130     FIELD(ZDMA_CH_SRC_DSCR_WORD2, SIZE, 0, 30)
 131 REG32(ZDMA_CH_SRC_DSCR_WORD3, 0x134)
 132     FIELD(ZDMA_CH_SRC_DSCR_WORD3, CMD, 3, 2)
 133     FIELD(ZDMA_CH_SRC_DSCR_WORD3, INTR, 2, 1)
 134     FIELD(ZDMA_CH_SRC_DSCR_WORD3, TYPE, 1, 1)
 135     FIELD(ZDMA_CH_SRC_DSCR_WORD3, COHRNT, 0, 1)
 136 REG32(ZDMA_CH_DST_DSCR_WORD0, 0x138)
 137 REG32(ZDMA_CH_DST_DSCR_WORD1, 0x13c)
 138     FIELD(ZDMA_CH_DST_DSCR_WORD1, MSB, 0, 17)
 139 REG32(ZDMA_CH_DST_DSCR_WORD2, 0x140)
 140     FIELD(ZDMA_CH_DST_DSCR_WORD2, SIZE, 0, 30)
 141 REG32(ZDMA_CH_DST_DSCR_WORD3, 0x144)
 142     FIELD(ZDMA_CH_DST_DSCR_WORD3, INTR, 2, 1)
 143     FIELD(ZDMA_CH_DST_DSCR_WORD3, TYPE, 1, 1)
 144     FIELD(ZDMA_CH_DST_DSCR_WORD3, COHRNT, 0, 1)
 145 REG32(ZDMA_CH_WR_ONLY_WORD0, 0x148)
 146 REG32(ZDMA_CH_WR_ONLY_WORD1, 0x14c)
 147 REG32(ZDMA_CH_WR_ONLY_WORD2, 0x150)
 148 REG32(ZDMA_CH_WR_ONLY_WORD3, 0x154)
 149 REG32(ZDMA_CH_SRC_START_LSB, 0x158)
 150 REG32(ZDMA_CH_SRC_START_MSB, 0x15c)
 151     FIELD(ZDMA_CH_SRC_START_MSB, ADDR, 0, 17)
 152 REG32(ZDMA_CH_DST_START_LSB, 0x160)
 153 REG32(ZDMA_CH_DST_START_MSB, 0x164)
 154     FIELD(ZDMA_CH_DST_START_MSB, ADDR, 0, 17)
 155 REG32(ZDMA_CH_RATE_CTRL, 0x18c)
 156     FIELD(ZDMA_CH_RATE_CTRL, CNT, 0, 12)
 157 REG32(ZDMA_CH_SRC_CUR_PYLD_LSB, 0x168)
 158 REG32(ZDMA_CH_SRC_CUR_PYLD_MSB, 0x16c)
 159     FIELD(ZDMA_CH_SRC_CUR_PYLD_MSB, ADDR, 0, 17)
 160 REG32(ZDMA_CH_DST_CUR_PYLD_LSB, 0x170)
 161 REG32(ZDMA_CH_DST_CUR_PYLD_MSB, 0x174)
 162     FIELD(ZDMA_CH_DST_CUR_PYLD_MSB, ADDR, 0, 17)
 163 REG32(ZDMA_CH_SRC_CUR_DSCR_LSB, 0x178)
 164 REG32(ZDMA_CH_SRC_CUR_DSCR_MSB, 0x17c)
 165     FIELD(ZDMA_CH_SRC_CUR_DSCR_MSB, ADDR, 0, 17)
 166 REG32(ZDMA_CH_DST_CUR_DSCR_LSB, 0x180)
 167 REG32(ZDMA_CH_DST_CUR_DSCR_MSB, 0x184)
 168     FIELD(ZDMA_CH_DST_CUR_DSCR_MSB, ADDR, 0, 17)
 169 REG32(ZDMA_CH_TOTAL_BYTE, 0x188)
 170 REG32(ZDMA_CH_RATE_CNTL, 0x18c)
 171     FIELD(ZDMA_CH_RATE_CNTL, CNT, 0, 12)
 172 REG32(ZDMA_CH_IRQ_SRC_ACCT, 0x190)
 173     FIELD(ZDMA_CH_IRQ_SRC_ACCT, CNT, 0, 8)
 174 REG32(ZDMA_CH_IRQ_DST_ACCT, 0x194)
 175     FIELD(ZDMA_CH_IRQ_DST_ACCT, CNT, 0, 8)
 176 REG32(ZDMA_CH_DBG0, 0x198)
 177     FIELD(ZDMA_CH_DBG0, CMN_BUF_FREE, 0, 9)
 178 REG32(ZDMA_CH_DBG1, 0x19c)
 179     FIELD(ZDMA_CH_DBG1, CMN_BUF_OCC, 0, 9)
 180 REG32(ZDMA_CH_CTRL2, 0x200)
 181     FIELD(ZDMA_CH_CTRL2, EN, 0, 1)
 182
 183 enum {
 184     PT_REG = 0,
 185     PT_MEM = 1,
 186 };
 187
 188 enum {
 189     CMD_HALT = 1,
 190     CMD_STOP = 2,
 191 };
 192
 193 enum {
 194     RW_MODE_RW = 0,
 195     RW_MODE_WO = 1,
 196     RW_MODE_RO = 2,
 197 };
 198
 199 enum {
 200     DTYPE_LINEAR = 0,
 201     DTYPE_LINKED = 1,
 202 };
 203
 204 enum {
 205     AXI_BURST_FIXED = 0,
 206     AXI_BURST_INCR  = 1,
 207 };
 208
 209 static void zdma_ch_imr_update_irq(XlnxZDMA *s)
 210 {
 211     bool pending;
 212
 213     pending = s->regs[R_ZDMA_CH_ISR] & ~s->regs[R_ZDMA_CH_IMR];
 214
 215     qemu_set_irq(s->irq_zdma_ch_imr, pending);
 216 }
 217
 218 static void zdma_ch_isr_postw(RegisterInfo *reg, uint64_t val64)
 219 {
 220     XlnxZDMA *s = XLNX_ZDMA(reg->opaque);
 221     zdma_ch_imr_update_irq(s);
 222 }
 223
 224 static uint64_t zdma_ch_ien_prew(RegisterInfo *reg, uint64_t val64)
 225 {
 226     XlnxZDMA *s = XLNX_ZDMA(reg->opaque);
 227     uint32_t val = val64;
 228
 229     s->regs[R_ZDMA_CH_IMR] &= ~val;
 230     zdma_ch_imr_update_irq(s);
 231     return 0;
 232 }
 233
 234 static uint64_t zdma_ch_ids_prew(RegisterInfo *reg, uint64_t val64)
 235 {
 236     XlnxZDMA *s = XLNX_ZDMA(reg->opaque);
 237     uint32_t val = val64;
 238
 239     s->regs[R_ZDMA_CH_IMR] |= val;
 240     zdma_ch_imr_update_irq(s);
 241     return 0;
 242 }
 243
 244 static void zdma_set_state(XlnxZDMA *s, XlnxZDMAState state)
 245 {
 246     s->state = state;
 247     ARRAY_FIELD_DP32(s->regs, ZDMA_CH_STATUS, STATE, state);
 248
 249     /* Signal error if we have an error condition.  */
 250     if (s->error) {
 251         ARRAY_FIELD_DP32(s->regs, ZDMA_CH_STATUS, STATE, 3);
 252     }
 253 }
 254
 255 static void zdma_src_done(XlnxZDMA *s)
 256 {
 257     unsigned int cnt;
 258     cnt = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_SRC_ACCT, CNT);
 259     cnt++;
 260     ARRAY_FIELD_DP32(s->regs, ZDMA_CH_IRQ_SRC_ACCT, CNT, cnt);
 261     ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, SRC_DSCR_DONE, true);
 262
 263     /* Did we overflow?  */
 264     if (cnt != ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_SRC_ACCT, CNT)) {
 265         ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, IRQ_SRC_ACCT_ERR, true);
 266     }
 267     zdma_ch_imr_update_irq(s);
 268 }
 269
 270 static void zdma_dst_done(XlnxZDMA *s)
 271 {
 272     unsigned int cnt;
 273     cnt = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_DST_ACCT, CNT);
 274     cnt++;
 275     ARRAY_FIELD_DP32(s->regs, ZDMA_CH_IRQ_DST_ACCT, CNT, cnt);
 276     ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DST_DSCR_DONE, true);
 277
 278     /* Did we overflow?  */
 279     if (cnt != ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_DST_ACCT, CNT)) {
 280         ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, IRQ_DST_ACCT_ERR, true);
 281     }
 282     zdma_ch_imr_update_irq(s);
 283 }
 284
 285 static uint64_t zdma_get_regaddr64(XlnxZDMA *s, unsigned int basereg)
 286 {
 287     uint64_t addr;
 288
 289     addr = s->regs[basereg + 1];
 290     addr <<= 32;
 291     addr |= s->regs[basereg];
 292
 293     return addr;
 294 }
 295
 296 static void zdma_put_regaddr64(XlnxZDMA *s, unsigned int basereg, uint64_t addr)
 297 {
 298     s->regs[basereg] = addr;
 299     s->regs[basereg + 1] = addr >> 32;
 300 }
 301
 302 static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
 303 {
 304     /* ZDMA descriptors must be aligned to their own size.  */
 305     if (addr % sizeof(XlnxZDMADescr)) {
 306         qemu_log_mask(LOG_GUEST_ERROR,
 307                       "zdma: unaligned descriptor at %" PRIx64,
 308                       addr);
 309         memset(buf, 0x0, sizeof(XlnxZDMADescr));
 310         s->error = true;
 311         return false;
 312     }
 313
 314     address_space_read(s->dma_as, addr, s->attr, buf, sizeof(XlnxZDMADescr));
 315     return true;
 316 }
 317
 318 static void zdma_load_src_descriptor(XlnxZDMA *s)
 319 {
 320     uint64_t src_addr;
 321     unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE);
 322
 323     if (ptype == PT_REG) {
 324         memcpy(&s->dsc_src, &s->regs[R_ZDMA_CH_SRC_DSCR_WORD0],
 325                sizeof(s->dsc_src));
 326         return;
 327     }
 328
 329     src_addr = zdma_get_regaddr64(s, R_ZDMA_CH_SRC_CUR_DSCR_LSB);
 330
 331     if (!zdma_load_descriptor(s, src_addr, &s->dsc_src)) {
 332         ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, AXI_RD_SRC_DSCR, true);
 333     }
 334 }
 335
 336 static void zdma_load_dst_descriptor(XlnxZDMA *s)
 337 {
 338     uint64_t dst_addr;
 339     unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE);
 340
 341     if (ptype == PT_REG) {
 342         memcpy(&s->dsc_dst, &s->regs[R_ZDMA_CH_DST_DSCR_WORD0],
 343                sizeof(s->dsc_dst));
 344         return;
 345     }
 346
 347     dst_addr = zdma_get_regaddr64(s, R_ZDMA_CH_DST_CUR_DSCR_LSB);
 348
 349     if (!zdma_load_descriptor(s, dst_addr, &s->dsc_dst)) {
 350         ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, AXI_RD_DST_DSCR, true);
 351     }
 352 }
 353
 354 static uint64_t zdma_update_descr_addr(XlnxZDMA *s, bool type,
 355                                        unsigned int basereg)
 356 {
 357     uint64_t addr, next;
 358
 359     if (type == DTYPE_LINEAR) {
 360         next = zdma_get_regaddr64(s, basereg);
 361         next += sizeof(s->dsc_dst);
 362         zdma_put_regaddr64(s, basereg, next);
 363     } else {
 364         addr = zdma_get_regaddr64(s, basereg);
 365         addr += sizeof(s->dsc_dst);
 366         address_space_read(s->dma_as, addr, s->attr, &next, 8);
 367         zdma_put_regaddr64(s, basereg, next);
 368     }
 369     return next;
 370 }
 371
 372 static void zdma_write_dst(XlnxZDMA *s, uint8_t *buf, uint32_t len)
 373 {
 374     uint32_t dst_size, dlen;
 375     bool dst_intr;
 376     unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE);
 377     unsigned int rw_mode = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, MODE);
 378     unsigned int burst_type = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_DATA_ATTR,
 379                                                AWBURST);
 380
 381     /* FIXED burst types are only supported in simple dma mode.  */
 382     if (ptype != PT_REG) {
 383         burst_type = AXI_BURST_INCR;
 384     }
 385
 386     while (len) {
 387         dst_size = FIELD_EX32(s->dsc_dst.words[2], ZDMA_CH_DST_DSCR_WORD2,
 388                               SIZE);
 389         if (dst_size == 0 && ptype == PT_MEM) {
 390             uint64_t next;
 391             bool dst_type = FIELD_EX32(s->dsc_dst.words[3],
 392                                        ZDMA_CH_DST_DSCR_WORD3,
 393                                        TYPE);
 394
 395             next = zdma_update_descr_addr(s, dst_type,
 396                                           R_ZDMA_CH_DST_CUR_DSCR_LSB);
 397             zdma_load_descriptor(s, next, &s->dsc_dst);
 398             dst_size = FIELD_EX32(s->dsc_dst.words[2], ZDMA_CH_DST_DSCR_WORD2,
 399                                   SIZE);
 400         }
 401
 402         /* Match what hardware does by ignoring the dst_size and only using
 403          * the src size for Simple register mode.  */
 404         if (ptype == PT_REG && rw_mode != RW_MODE_WO) {
 405             dst_size = len;
 406         }
 407
 408         dst_intr = FIELD_EX32(s->dsc_dst.words[3], ZDMA_CH_DST_DSCR_WORD3,
 409                               INTR);
 410
 411         dlen = len > dst_size ? dst_size : len;
 412         if (burst_type == AXI_BURST_FIXED) {
 413             if (dlen > (s->cfg.bus_width / 8)) {
 414                 dlen = s->cfg.bus_width / 8;
 415             }
 416         }
 417
 418         address_space_write(s->dma_as, s->dsc_dst.addr, s->attr, buf, dlen);
 419         if (burst_type == AXI_BURST_INCR) {
 420             s->dsc_dst.addr += dlen;
 421         }
 422         dst_size -= dlen;
 423         buf += dlen;
 424         len -= dlen;
 425
 426         if (dst_size == 0 && dst_intr) {
 427             zdma_dst_done(s);
 428         }
 429
 430         /* Write back to buffered descriptor.  */
 431         s->dsc_dst.words[2] = FIELD_DP32(s->dsc_dst.words[2],
 432                                          ZDMA_CH_DST_DSCR_WORD2,
 433                                          SIZE,
 434                                          dst_size);
 435     }
 436 }
 437
 438 static void zdma_process_descr(XlnxZDMA *s)
 439 {
 440     uint64_t src_addr;
 441     uint32_t src_size, len;
 442     unsigned int src_cmd;
 443     bool src_intr, src_type;
 444     unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE);
 445     unsigned int rw_mode = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, MODE);
 446     unsigned int burst_type = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_DATA_ATTR,
 447                                                ARBURST);
 448
 449     src_addr = s->dsc_src.addr;
 450     src_size = FIELD_EX32(s->dsc_src.words[2], ZDMA_CH_SRC_DSCR_WORD2, SIZE);
 451     src_cmd = FIELD_EX32(s->dsc_src.words[3], ZDMA_CH_SRC_DSCR_WORD3, CMD);
 452     src_type = FIELD_EX32(s->dsc_src.words[3], ZDMA_CH_SRC_DSCR_WORD3, TYPE);
 453     src_intr = FIELD_EX32(s->dsc_src.words[3], ZDMA_CH_SRC_DSCR_WORD3, INTR);
 454
 455     /* FIXED burst types and non-rw modes are only supported in
 456      * simple dma mode.
 457      */
 458     if (ptype != PT_REG) {
 459         if (rw_mode != RW_MODE_RW) {
 460             qemu_log_mask(LOG_GUEST_ERROR,
 461                           "zDMA: rw-mode=%d but not simple DMA mode.\n",
 462                           rw_mode);
 463         }
 464         if (burst_type != AXI_BURST_INCR) {
 465             qemu_log_mask(LOG_GUEST_ERROR,
 466                           "zDMA: burst_type=%d but not simple DMA mode.\n",
 467                           burst_type);
 468         }
 469         burst_type = AXI_BURST_INCR;
 470         rw_mode = RW_MODE_RW;
 471     }
 472
 473     if (rw_mode == RW_MODE_WO) {
 474         /* In Simple DMA Write-Only, we need to push DST size bytes
 475          * regardless of what SRC size is set to.  */
 476         src_size = FIELD_EX32(s->dsc_dst.words[2], ZDMA_CH_DST_DSCR_WORD2,
 477                               SIZE);
 478         memcpy(s->buf, &s->regs[R_ZDMA_CH_WR_ONLY_WORD0], s->cfg.bus_width / 8);
 479     }
 480
 481     while (src_size) {
 482         len = src_size > ARRAY_SIZE(s->buf) ? ARRAY_SIZE(s->buf) : src_size;
 483         if (burst_type == AXI_BURST_FIXED) {
 484             if (len > (s->cfg.bus_width / 8)) {
 485                 len = s->cfg.bus_width / 8;
 486             }
 487         }
 488
 489         if (rw_mode == RW_MODE_WO) {
 490             if (len > s->cfg.bus_width / 8) {
 491                 len = s->cfg.bus_width / 8;
 492             }
 493         } else {
 494             address_space_read(s->dma_as, src_addr, s->attr, s->buf, len);
 495             if (burst_type == AXI_BURST_INCR) {
 496                 src_addr += len;
 497             }
 498         }
 499
 500         if (rw_mode != RW_MODE_RO) {
 501             zdma_write_dst(s, s->buf, len);
 502         }
 503
 504         s->regs[R_ZDMA_CH_TOTAL_BYTE] += len;
 505         src_size -= len;
 506     }
 507
 508     ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DMA_DONE, true);
 509
 510     if (src_intr) {
 511         zdma_src_done(s);
 512     }
 513
 514     /* Load next descriptor.  */
 515     if (ptype == PT_REG || src_cmd == CMD_STOP) {
 516         ARRAY_FIELD_DP32(s->regs, ZDMA_CH_CTRL2, EN, 0);
 517         zdma_set_state(s, DISABLED);
 518         return;
 519     }
 520
 521     if (src_cmd == CMD_HALT) {
 522         zdma_set_state(s, PAUSED);
 523         ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DMA_PAUSE, 1);
 524         zdma_ch_imr_update_irq(s);
 525         return;
 526     }
 527
 528     zdma_update_descr_addr(s, src_type, R_ZDMA_CH_SRC_CUR_DSCR_LSB);
 529 }
 530
 531 static void zdma_run(XlnxZDMA *s)
 532 {
 533     while (s->state == ENABLED && !s->error) {
 534         zdma_load_src_descriptor(s);
 535
 536         if (s->error) {
 537             zdma_set_state(s, DISABLED);
 538         } else {
 539             zdma_process_descr(s);
 540         }
 541     }
 542
 543     zdma_ch_imr_update_irq(s);
 544 }
 545
 546 static void zdma_update_descr_addr_from_start(XlnxZDMA *s)
 547 {
 548     uint64_t src_addr, dst_addr;
 549
 550     src_addr = zdma_get_regaddr64(s, R_ZDMA_CH_SRC_START_LSB);
 551     zdma_put_regaddr64(s, R_ZDMA_CH_SRC_CUR_DSCR_LSB, src_addr);
 552     dst_addr = zdma_get_regaddr64(s, R_ZDMA_CH_DST_START_LSB);
 553     zdma_put_regaddr64(s, R_ZDMA_CH_DST_CUR_DSCR_LSB, dst_addr);
 554     zdma_load_dst_descriptor(s);
 555 }
 556
 557 static void zdma_ch_ctrlx_postw(RegisterInfo *reg, uint64_t val64)
 558 {
 559     XlnxZDMA *s = XLNX_ZDMA(reg->opaque);
 560
 561     if (ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL2, EN)) {
 562         s->error = false;
 563
 564         if (s->state == PAUSED &&
 565             ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, CONT)) {
 566             if (ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, CONT_ADDR) == 1) {
 567                 zdma_update_descr_addr_from_start(s);
 568             } else {
 569                 bool src_type = FIELD_EX32(s->dsc_src.words[3],
 570                                        ZDMA_CH_SRC_DSCR_WORD3, TYPE);
 571                 zdma_update_descr_addr(s, src_type,
 572                                           R_ZDMA_CH_SRC_CUR_DSCR_LSB);
 573             }
 574             ARRAY_FIELD_DP32(s->regs, ZDMA_CH_CTRL0, CONT, false);
 575             zdma_set_state(s, ENABLED);
 576         } else if (s->state == DISABLED) {
 577             zdma_update_descr_addr_from_start(s);
 578             zdma_set_state(s, ENABLED);
 579         }
 580     } else {
 581         /* Leave Paused state?  */
 582         if (s->state == PAUSED &&
 583             ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, CONT)) {
 584             zdma_set_state(s, DISABLED);
 585         }
 586     }
 587
 588     zdma_run(s);
 589 }
 590
 591 static RegisterAccessInfo zdma_regs_info[] = {
 592     {   .name = "ZDMA_ERR_CTRL",  .addr = A_ZDMA_ERR_CTRL,
 593         .rsvd = 0xfffffffe,
 594     },{ .name = "ZDMA_CH_ISR",  .addr = A_ZDMA_CH_ISR,
 595         .rsvd = 0xfffff000,
 596         .w1c = 0xfff,
 597         .post_write = zdma_ch_isr_postw,
 598     },{ .name = "ZDMA_CH_IMR",  .addr = A_ZDMA_CH_IMR,
 599         .reset = 0xfff,
 600         .rsvd = 0xfffff000,
 601         .ro = 0xfff,
 602     },{ .name = "ZDMA_CH_IEN",  .addr = A_ZDMA_CH_IEN,
 603         .rsvd = 0xfffff000,
 604         .pre_write = zdma_ch_ien_prew,
 605     },{ .name = "ZDMA_CH_IDS",  .addr = A_ZDMA_CH_IDS,
 606         .rsvd = 0xfffff000,
 607         .pre_write = zdma_ch_ids_prew,
 608     },{ .name = "ZDMA_CH_CTRL0",  .addr = A_ZDMA_CH_CTRL0,
 609         .reset = 0x80,
 610         .rsvd = 0xffffff01,
 611         .post_write = zdma_ch_ctrlx_postw,
 612     },{ .name = "ZDMA_CH_CTRL1",  .addr = A_ZDMA_CH_CTRL1,
 613         .reset = 0x3ff,
 614         .rsvd = 0xfffffc00,
 615     },{ .name = "ZDMA_CH_FCI",  .addr = A_ZDMA_CH_FCI,
 616         .rsvd = 0xffffffc0,
 617     },{ .name = "ZDMA_CH_STATUS",  .addr = A_ZDMA_CH_STATUS,
 618         .rsvd = 0xfffffffc,
 619         .ro = 0x3,
 620     },{ .name = "ZDMA_CH_DATA_ATTR",  .addr = A_ZDMA_CH_DATA_ATTR,
 621         .reset = 0x483d20f,
 622         .rsvd = 0xf0000000,
 623     },{ .name = "ZDMA_CH_DSCR_ATTR",  .addr = A_ZDMA_CH_DSCR_ATTR,
 624         .rsvd = 0xfffffe00,
 625     },{ .name = "ZDMA_CH_SRC_DSCR_WORD0",  .addr = A_ZDMA_CH_SRC_DSCR_WORD0,
 626     },{ .name = "ZDMA_CH_SRC_DSCR_WORD1",  .addr = A_ZDMA_CH_SRC_DSCR_WORD1,
 627         .rsvd = 0xfffe0000,
 628     },{ .name = "ZDMA_CH_SRC_DSCR_WORD2",  .addr = A_ZDMA_CH_SRC_DSCR_WORD2,
 629         .rsvd = 0xc0000000,
 630     },{ .name = "ZDMA_CH_SRC_DSCR_WORD3",  .addr = A_ZDMA_CH_SRC_DSCR_WORD3,
 631         .rsvd = 0xffffffe0,
 632     },{ .name = "ZDMA_CH_DST_DSCR_WORD0",  .addr = A_ZDMA_CH_DST_DSCR_WORD0,
 633     },{ .name = "ZDMA_CH_DST_DSCR_WORD1",  .addr = A_ZDMA_CH_DST_DSCR_WORD1,
 634         .rsvd = 0xfffe0000,
 635     },{ .name = "ZDMA_CH_DST_DSCR_WORD2",  .addr = A_ZDMA_CH_DST_DSCR_WORD2,
 636         .rsvd = 0xc0000000,
 637     },{ .name = "ZDMA_CH_DST_DSCR_WORD3",  .addr = A_ZDMA_CH_DST_DSCR_WORD3,
 638         .rsvd = 0xfffffffa,
 639     },{ .name = "ZDMA_CH_WR_ONLY_WORD0",  .addr = A_ZDMA_CH_WR_ONLY_WORD0,
 640     },{ .name = "ZDMA_CH_WR_ONLY_WORD1",  .addr = A_ZDMA_CH_WR_ONLY_WORD1,
 641     },{ .name = "ZDMA_CH_WR_ONLY_WORD2",  .addr = A_ZDMA_CH_WR_ONLY_WORD2,
 642     },{ .name = "ZDMA_CH_WR_ONLY_WORD3",  .addr = A_ZDMA_CH_WR_ONLY_WORD3,
 643     },{ .name = "ZDMA_CH_SRC_START_LSB",  .addr = A_ZDMA_CH_SRC_START_LSB,
 644     },{ .name = "ZDMA_CH_SRC_START_MSB",  .addr = A_ZDMA_CH_SRC_START_MSB,
 645         .rsvd = 0xfffe0000,
 646     },{ .name = "ZDMA_CH_DST_START_LSB",  .addr = A_ZDMA_CH_DST_START_LSB,
 647     },{ .name = "ZDMA_CH_DST_START_MSB",  .addr = A_ZDMA_CH_DST_START_MSB,
 648         .rsvd = 0xfffe0000,
 649     },{ .name = "ZDMA_CH_SRC_CUR_PYLD_LSB",  .addr = A_ZDMA_CH_SRC_CUR_PYLD_LSB,
 650         .ro = 0xffffffff,
 651     },{ .name = "ZDMA_CH_SRC_CUR_PYLD_MSB",  .addr = A_ZDMA_CH_SRC_CUR_PYLD_MSB,
 652         .rsvd = 0xfffe0000,
 653         .ro = 0x1ffff,
 654     },{ .name = "ZDMA_CH_DST_CUR_PYLD_LSB",  .addr = A_ZDMA_CH_DST_CUR_PYLD_LSB,
 655         .ro = 0xffffffff,
 656     },{ .name = "ZDMA_CH_DST_CUR_PYLD_MSB",  .addr = A_ZDMA_CH_DST_CUR_PYLD_MSB,
 657         .rsvd = 0xfffe0000,
 658         .ro = 0x1ffff,
 659     },{ .name = "ZDMA_CH_SRC_CUR_DSCR_LSB",  .addr = A_ZDMA_CH_SRC_CUR_DSCR_LSB,
 660         .ro = 0xffffffff,
 661     },{ .name = "ZDMA_CH_SRC_CUR_DSCR_MSB",  .addr = A_ZDMA_CH_SRC_CUR_DSCR_MSB,
 662         .rsvd = 0xfffe0000,
 663         .ro = 0x1ffff,
 664     },{ .name = "ZDMA_CH_DST_CUR_DSCR_LSB",  .addr = A_ZDMA_CH_DST_CUR_DSCR_LSB,
 665         .ro = 0xffffffff,
 666     },{ .name = "ZDMA_CH_DST_CUR_DSCR_MSB",  .addr = A_ZDMA_CH_DST_CUR_DSCR_MSB,
 667         .rsvd = 0xfffe0000,
 668         .ro = 0x1ffff,
 669     },{ .name = "ZDMA_CH_TOTAL_BYTE",  .addr = A_ZDMA_CH_TOTAL_BYTE,
 670         .w1c = 0xffffffff,
 671     },{ .name = "ZDMA_CH_RATE_CNTL",  .addr = A_ZDMA_CH_RATE_CNTL,
 672         .rsvd = 0xfffff000,
 673     },{ .name = "ZDMA_CH_IRQ_SRC_ACCT",  .addr = A_ZDMA_CH_IRQ_SRC_ACCT,
 674         .rsvd = 0xffffff00,
 675         .ro = 0xff,
 676         .cor = 0xff,
 677     },{ .name = "ZDMA_CH_IRQ_DST_ACCT",  .addr = A_ZDMA_CH_IRQ_DST_ACCT,
 678         .rsvd = 0xffffff00,
 679         .ro = 0xff,
 680         .cor = 0xff,
 681     },{ .name = "ZDMA_CH_DBG0",  .addr = A_ZDMA_CH_DBG0,
 682         .rsvd = 0xfffffe00,
 683         .ro = 0x1ff,
 684     },{ .name = "ZDMA_CH_DBG1",  .addr = A_ZDMA_CH_DBG1,
 685         .rsvd = 0xfffffe00,
 686         .ro = 0x1ff,
 687     },{ .name = "ZDMA_CH_CTRL2",  .addr = A_ZDMA_CH_CTRL2,
 688         .rsvd = 0xfffffffe,
 689         .post_write = zdma_ch_ctrlx_postw,
 690     }
 691 };
 692
 693 static void zdma_reset(DeviceState *dev)
 694 {
 695     XlnxZDMA *s = XLNX_ZDMA(dev);
 696     unsigned int i;
 697
 698     for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
 699         register_reset(&s->regs_info[i]);
 700     }
 701
 702     zdma_ch_imr_update_irq(s);
 703 }
 704
 705 static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size)
 706 {
 707     XlnxZDMA *s = XLNX_ZDMA(opaque);
 708     RegisterInfo *r = &s->regs_info[addr / 4];
 709
 710     if (!r->data) {
 711         gchar *path = object_get_canonical_path(OBJECT(s));
 712         qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
 713                  path,
 714                  addr);
 715         g_free(path);
 716         ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
 717         zdma_ch_imr_update_irq(s);
 718         return 0;
 719     }
 720     return register_read(r, ~0, NULL, false);
 721 }
 722
 723 static void zdma_write(void *opaque, hwaddr addr, uint64_t value,
 724                       unsigned size)
 725 {
 726     XlnxZDMA *s = XLNX_ZDMA(opaque);
 727     RegisterInfo *r = &s->regs_info[addr / 4];
 728
 729     if (!r->data) {
 730         gchar *path = object_get_canonical_path(OBJECT(s));
 731         qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
 732                  path,
 733                  addr, value);
 734         g_free(path);
 735         ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
 736         zdma_ch_imr_update_irq(s);
 737         return;
 738     }
 739     register_write(r, value, ~0, NULL, false);
 740 }
 741
 742 static const MemoryRegionOps zdma_ops = {
 743     .read = zdma_read,
 744     .write = zdma_write,
 745     .endianness = DEVICE_LITTLE_ENDIAN,
 746     .valid = {
 747         .min_access_size = 4,
 748         .max_access_size = 4,
 749     },
 750 };
 751
 752 static void zdma_realize(DeviceState *dev, Error **errp)
 753 {
 754     XlnxZDMA *s = XLNX_ZDMA(dev);
 755     unsigned int i;
 756
 757     for (i = 0; i < ARRAY_SIZE(zdma_regs_info); ++i) {
 758         RegisterInfo *r = &s->regs_info[zdma_regs_info[i].addr / 4];
 759
 760         *r = (RegisterInfo) {
 761             .data = (uint8_t *)&s->regs[
 762                     zdma_regs_info[i].addr / 4],
 763             .data_size = sizeof(uint32_t),
 764             .access = &zdma_regs_info[i],
 765             .opaque = s,
 766         };
 767     }
 768
 769     if (s->dma_mr) {
 770         s->dma_as = g_malloc0(sizeof(AddressSpace));
 771         address_space_init(s->dma_as, s->dma_mr, NULL);
 772     } else {
 773         s->dma_as = &address_space_memory;
 774     }
 775     s->attr = MEMTXATTRS_UNSPECIFIED;
 776 }
 777
 778 static void zdma_init(Object *obj)
 779 {
 780     XlnxZDMA *s = XLNX_ZDMA(obj);
 781     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 782
 783     memory_region_init_io(&s->iomem, obj, &zdma_ops, s,
 784                           TYPE_XLNX_ZDMA, ZDMA_R_MAX * 4);
 785     sysbus_init_mmio(sbd, &s->iomem);
 786     sysbus_init_irq(sbd, &s->irq_zdma_ch_imr);
 787
 788     object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
 789                              (Object **)&s->dma_mr,
 790                              qdev_prop_allow_set_link_before_realize,
 791                              OBJ_PROP_LINK_STRONG,
 792                              &error_abort);
 793 }
 794
 795 static const VMStateDescription vmstate_zdma = {
 796     .name = TYPE_XLNX_ZDMA,
 797     .version_id = 1,
 798     .minimum_version_id = 1,
 799     .minimum_version_id_old = 1,
 800     .fields = (VMStateField[]) {
 801         VMSTATE_UINT32_ARRAY(regs, XlnxZDMA, ZDMA_R_MAX),
 802         VMSTATE_UINT32(state, XlnxZDMA),
 803         VMSTATE_UINT32_ARRAY(dsc_src.words, XlnxZDMA, 4),
 804         VMSTATE_UINT32_ARRAY(dsc_dst.words, XlnxZDMA, 4),
 805         VMSTATE_END_OF_LIST(),
 806     }
 807 };
 808
 809 static Property zdma_props[] = {
 810     DEFINE_PROP_UINT32("bus-width", XlnxZDMA, cfg.bus_width, 64),
 811     DEFINE_PROP_END_OF_LIST(),
 812 };
 813
 814 static void zdma_class_init(ObjectClass *klass, void *data)
 815 {
 816     DeviceClass *dc = DEVICE_CLASS(klass);
 817
 818     dc->reset = zdma_reset;
 819     dc->realize = zdma_realize;
 820     device_class_set_props(dc, zdma_props);
 821     dc->vmsd = &vmstate_zdma;
 822 }
 823
 824 static const TypeInfo zdma_info = {
 825     .name          = TYPE_XLNX_ZDMA,
 826     .parent        = TYPE_SYS_BUS_DEVICE,
 827     .instance_size = sizeof(XlnxZDMA),
 828     .class_init    = zdma_class_init,
 829     .instance_init = zdma_init,
 830 };
 831
 832 static void zdma_register_types(void)
 833 {
 834     type_register_static(&zdma_info);
 835 }
 836
 837 type_init(zdma_register_types)