2 * QEMU i8255x (PRO100) emulation
4 * Copyright (c) 2006-2007 Stefan Weil
6 * Portions of the code are copies from grub / etherboot eepro100.c
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
22 * Tested features (i82559):
23 * PXE boot (i386) no valid link
24 * Linux networking (i386) ok
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
36 #if defined(TARGET_I386)
37 # warning "PXE boot still not working!"
40 #include <stddef.h> /* offsetof */
45 #include "eeprom93xx.h"
47 /* Common declarations for all PCI devices. */
49 #define PCI_CONFIG_8(offset, value) \
50 (pci_conf[offset] = (value))
51 #define PCI_CONFIG_16(offset, value) \
52 (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
53 #define PCI_CONFIG_32(offset, value) \
54 (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
58 /* Debug EEPRO100 card. */
59 //~ #define DEBUG_EEPRO100
62 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
64 #define logout(fmt, ...) ((void)0)
67 /* Set flags to 0 to disable debug output. */
68 #define INT 1 /* interrupt related actions */
69 #define MDI 1 /* mdi related actions */
72 #define EEPROM 1 /* eeprom related actions */
74 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
76 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
78 #define MAX_ETH_FRAME_SIZE 1514
80 /* This driver supports several different devices which are declared here. */
81 #define i82550 0x82550
82 #define i82551 0x82551
83 #define i82557A 0x82557a
84 #define i82557B 0x82557b
85 #define i82557C 0x82557c
86 #define i82558A 0x82558a
87 #define i82558B 0x82558b
88 #define i82559A 0x82559a
89 #define i82559B 0x82559b
90 #define i82559C 0x82559c
91 #define i82559ER 0x82559e
92 #define i82562 0x82562
94 /* Use 64 word EEPROM. TODO: could be a runtime option. */
95 #define EEPROM_SIZE 64
97 #define PCI_MEM_SIZE (4 * KiB)
98 #define PCI_IO_SIZE 64
99 #define PCI_FLASH_SIZE (128 * KiB)
101 #define BIT(n) (1 << (n))
102 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
104 /* The SCB accepts the following controls for the Tx and Rx units: */
105 #define CU_NOP 0x0000 /* No operation. */
106 #define CU_START 0x0010 /* CU start. */
107 #define CU_RESUME 0x0020 /* CU resume. */
108 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
109 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
110 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
111 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
112 #define CU_SRESUME 0x00a0 /* CU static resume. */
114 #define RU_NOP 0x0000
115 #define RX_START 0x0001
116 #define RX_RESUME 0x0002
117 #define RX_ABORT 0x0004
118 #define RX_ADDR_LOAD 0x0006
119 #define RX_RESUMENR 0x0007
120 #define INT_MASK 0x0100
121 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
123 /* Offsets to the various registers.
124 All accesses need not be longword aligned. */
125 enum speedo_offsets
{
128 SCBCmd
= 2, /* Rx/Command Unit command and status. */
130 SCBPointer
= 4, /* General purpose pointer. */
131 SCBPort
= 8, /* Misc. commands and operands. */
132 SCBflash
= 12, SCBeeprom
= 14, /* EEPROM and flash memory control. */
133 SCBCtrlMDI
= 16, /* MDI interface control. */
134 SCBEarlyRx
= 20, /* Early receive byte count. */
138 /* A speedo3 transmit buffer descriptor with two buffers... */
142 uint32_t link
; /* void * */
143 uint32_t tx_desc_addr
; /* transmit buffer decsriptor array address. */
144 uint16_t tcb_bytes
; /* transmit command block byte count (in lower 14 bits */
145 uint8_t tx_threshold
; /* transmit threshold */
146 uint8_t tbd_count
; /* TBD number */
147 //~ /* This constitutes two "TBD" entries: hdr and data */
148 //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
149 //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
150 //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
151 //~ int32_t tx_buf_size1; /* Length of Tx data. */
154 /* Receive frame descriptor. */
158 uint32_t link
; /* struct RxFD * */
159 uint32_t rx_buf_addr
; /* void * */
162 char packet
[MAX_ETH_FRAME_SIZE
+ 4];
166 uint32_t tx_good_frames
, tx_max_collisions
, tx_late_collisions
,
167 tx_underruns
, tx_lost_crs
, tx_deferred
, tx_single_collisions
,
168 tx_multiple_collisions
, tx_total_collisions
;
169 uint32_t rx_good_frames
, rx_crc_errors
, rx_alignment_errors
,
170 rx_resource_errors
, rx_overrun_errors
, rx_cdt_errors
,
171 rx_short_frame_errors
;
172 uint32_t fc_xmt_pause
, fc_rcv_pause
, fc_rcv_unsupported
;
173 uint16_t xmt_tco_frames
, rcv_tco_frames
;
209 uint8_t phys
[6]; /* mac address */
211 uint8_t mult
[8]; /* multicast mask array */
215 uint8_t scb_stat
; /* SCB stat/ack byte */
216 uint8_t int_stat
; /* PCI interrupt status */
217 uint32_t region
[3]; /* PCI region addresses */
219 uint32_t statcounter
[19];
222 uint32_t device
; /* device variant */
224 /* (cu_base + cu_offset) address the next command block in the command block list. */
225 uint32_t cu_base
; /* CU base address */
226 uint32_t cu_offset
; /* CU address offset */
227 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
228 uint32_t ru_base
; /* RU base address */
229 uint32_t ru_offset
; /* RU address offset */
230 uint32_t statsaddr
; /* pointer to eepro100_stats_t */
231 eepro100_stats_t statistics
; /* statistical counters */
236 /* Configuration bytes. */
237 uint8_t configuration
[22];
239 /* Data in mem is always in the byte order of the controller (le). */
240 uint8_t mem
[PCI_MEM_SIZE
];
243 /* Default values for MDI (PHY) registers */
244 static const uint16_t eepro100_mdi_default
[] = {
245 /* MDI Registers 0 - 6, 7 */
246 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
247 /* MDI Registers 8 - 15 */
248 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
249 /* MDI Registers 16 - 31 */
250 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
251 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
254 /* Readonly mask for MDI (PHY) registers */
255 static const uint16_t eepro100_mdi_mask
[] = {
256 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
257 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
258 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
259 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
262 #define POLYNOMIAL 0x04c11db6
266 static int compute_mcast_idx(const uint8_t * ep
)
273 for (i
= 0; i
< 6; i
++) {
275 for (j
= 0; j
< 8; j
++) {
276 carry
= ((crc
& 0x80000000L
) ? 1 : 0) ^ (b
& 0x01);
280 crc
= ((crc
^ POLYNOMIAL
) | carry
);
287 #if defined(DEBUG_EEPRO100)
288 static const char *nic_dump(const uint8_t * buf
, unsigned size
)
290 static char dump
[3 * 16 + 1];
296 p
+= sprintf(p
, " %02x", *buf
++);
300 #endif /* DEBUG_EEPRO100 */
303 stat_ack_not_ours
= 0x00,
304 stat_ack_sw_gen
= 0x04,
306 stat_ack_cu_idle
= 0x20,
307 stat_ack_frame_rx
= 0x40,
308 stat_ack_cu_cmd_done
= 0x80,
309 stat_ack_not_present
= 0xFF,
310 stat_ack_rx
= (stat_ack_sw_gen
| stat_ack_rnr
| stat_ack_frame_rx
),
311 stat_ack_tx
= (stat_ack_cu_idle
| stat_ack_cu_cmd_done
),
314 static void disable_interrupt(EEPRO100State
* s
)
317 TRACE(INT
, logout("interrupt disabled\n"));
318 qemu_irq_lower(s
->dev
.irq
[0]);
323 static void enable_interrupt(EEPRO100State
* s
)
326 TRACE(INT
, logout("interrupt enabled\n"));
327 qemu_irq_raise(s
->dev
.irq
[0]);
332 static void eepro100_acknowledge(EEPRO100State
* s
)
334 s
->scb_stat
&= ~s
->mem
[SCBAck
];
335 s
->mem
[SCBAck
] = s
->scb_stat
;
336 if (s
->scb_stat
== 0) {
337 disable_interrupt(s
);
341 static void eepro100_interrupt(EEPRO100State
* s
, uint8_t stat
)
343 uint8_t mask
= ~s
->mem
[SCBIntmask
];
344 s
->mem
[SCBAck
] |= stat
;
345 stat
= s
->scb_stat
= s
->mem
[SCBAck
];
346 stat
&= (mask
| 0x0f);
347 //~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
348 if (stat
&& (mask
& 0x01)) {
349 /* SCB mask and SCB Bit M do not disable interrupt. */
351 } else if (s
->int_stat
) {
352 disable_interrupt(s
);
356 static void eepro100_cx_interrupt(EEPRO100State
* s
)
358 /* CU completed action command. */
359 /* Transmit not ok (82557 only, not in emulation). */
360 eepro100_interrupt(s
, 0x80);
363 static void eepro100_cna_interrupt(EEPRO100State
* s
)
365 /* CU left the active state. */
366 eepro100_interrupt(s
, 0x20);
369 static void eepro100_fr_interrupt(EEPRO100State
* s
)
371 /* RU received a complete frame. */
372 eepro100_interrupt(s
, 0x40);
376 static void eepro100_rnr_interrupt(EEPRO100State
* s
)
378 /* RU is not ready. */
379 eepro100_interrupt(s
, 0x10);
383 static void eepro100_mdi_interrupt(EEPRO100State
* s
)
385 /* MDI completed read or write cycle. */
386 eepro100_interrupt(s
, 0x08);
389 static void eepro100_swi_interrupt(EEPRO100State
* s
)
391 /* Software has requested an interrupt. */
392 eepro100_interrupt(s
, 0x04);
396 static void eepro100_fcp_interrupt(EEPRO100State
* s
)
398 /* Flow control pause interrupt (82558 and later). */
399 eepro100_interrupt(s
, 0x01);
403 static void pci_reset(EEPRO100State
* s
)
405 uint32_t device
= s
->device
;
406 uint8_t *pci_conf
= s
->dev
.config
;
408 TRACE(OTHER
, logout("%p\n", s
));
411 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_INTEL
);
412 /* PCI Device ID depends on device and is set below. */
414 PCI_CONFIG_16(PCI_COMMAND
, 0x0000);
416 PCI_CONFIG_16(PCI_STATUS
, 0x2800);
417 /* PCI Revision ID */
418 PCI_CONFIG_8(PCI_REVISION_ID
, 0x08);
420 PCI_CONFIG_8(0x09, 0x00);
421 pci_config_set_class(pci_conf
, PCI_CLASS_NETWORK_ETHERNET
);
422 /* PCI Cache Line Size */
423 /* check cache line size!!! */
424 //~ PCI_CONFIG_8(0x0c, 0x00);
425 /* PCI Latency Timer */
426 PCI_CONFIG_8(0x0d, 0x20); // latency timer = 32 clocks
427 /* PCI Header Type */
428 /* BIST (built-in self test) */
429 #if defined(TARGET_I386)
430 // !!! workaround for buggy bios
431 //~ #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0
434 /* PCI Base Address Registers */
435 /* CSR Memory Mapped Base Address */
436 PCI_CONFIG_32(PCI_BASE_ADDRESS_0
,
437 PCI_ADDRESS_SPACE_MEM
| PCI_ADDRESS_SPACE_MEM_PREFETCH
);
438 /* CSR I/O Mapped Base Address */
439 PCI_CONFIG_32(PCI_BASE_ADDRESS_1
, PCI_ADDRESS_SPACE_IO
);
441 /* Flash Memory Mapped Base Address */
442 PCI_CONFIG_32(PCI_BASE_ADDRESS_2
, 0xfffe0000 | PCI_ADDRESS_SPACE_MEM
);
445 /* Expansion ROM Base Address (depends on boot disable!!!) */
446 PCI_CONFIG_32(0x30, 0x00000000);
447 /* Capability Pointer */
448 PCI_CONFIG_8(0x34, 0xdc);
451 PCI_CONFIG_8(0x3d, 1); // interrupt pin 0
453 PCI_CONFIG_8(0x3e, 0x08);
454 /* Maximum Latency */
455 PCI_CONFIG_8(0x3f, 0x18);
456 /* Power Management Capabilities / Next Item Pointer / Capability ID */
457 PCI_CONFIG_32(0xdc, 0x7e210001);
461 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82551IT
);
462 PCI_CONFIG_8(PCI_REVISION_ID
, 0x0f);
465 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
466 PCI_CONFIG_8(PCI_REVISION_ID
, 0x02);
469 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
470 PCI_CONFIG_8(PCI_REVISION_ID
, 0x03);
473 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
474 PCI_CONFIG_16(PCI_STATUS
, 0x2810);
475 PCI_CONFIG_8(PCI_REVISION_ID
, 0x05);
478 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
479 PCI_CONFIG_16(PCI_STATUS
, 0x2810);
480 //~ PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
483 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82551IT
);
484 PCI_CONFIG_16(PCI_STATUS
, 0x2810);
485 PCI_CONFIG_8(PCI_REVISION_ID
, 0x09);
487 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1029);
488 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1030); /* 82559 InBusiness 10/100 */
490 logout("Device %X is undefined!\n", device
);
493 if (device
== i82557C
|| device
== i82558B
|| device
== i82559C
) {
494 logout("Get device id and revision from EEPROM!!!\n");
498 static void nic_selective_reset(EEPRO100State
* s
)
501 uint16_t *eeprom_contents
= eeprom93xx_data(s
->eeprom
);
502 //~ eeprom93xx_reset(s->eeprom);
503 memcpy(eeprom_contents
, s
->macaddr
, 6);
504 eeprom_contents
[0xa] = 0x4000;
505 if (s
->device
== i82557B
|| s
->device
== i82557C
)
506 eeprom_contents
[5] = 0x0100;
508 for (i
= 0; i
< EEPROM_SIZE
- 1; i
++) {
509 sum
+= eeprom_contents
[i
];
511 eeprom_contents
[EEPROM_SIZE
- 1] = 0xbaba - sum
;
512 TRACE(EEPROM
, logout("checksum=0x%04x\n", eeprom_contents
[EEPROM_SIZE
- 1]));
514 memset(s
->mem
, 0, sizeof(s
->mem
));
515 uint32_t val
= BIT(21);
516 memcpy(&s
->mem
[SCBCtrlMDI
], &val
, sizeof(val
));
518 assert(sizeof(s
->mdimem
) == sizeof(eepro100_mdi_default
));
519 memcpy(&s
->mdimem
[0], &eepro100_mdi_default
[0], sizeof(s
->mdimem
));
522 static void nic_reset(void *opaque
)
524 EEPRO100State
*s
= opaque
;
525 TRACE(OTHER
, logout("%p\n", s
));
526 nic_selective_reset(s
);
529 #if defined(DEBUG_EEPRO100)
530 static const char * const reg
[PCI_IO_SIZE
/ 4] = {
534 "EEPROM/Flash Control",
536 "Receive DMA Byte Count",
538 "General Status/Control"
541 static char *regname(uint32_t addr
)
544 if (addr
< PCI_IO_SIZE
) {
545 const char *r
= reg
[addr
/ 4];
547 snprintf(buf
, sizeof(buf
), "%s+%u", r
, addr
% 4);
549 snprintf(buf
, sizeof(buf
), "0x%02x", addr
);
552 snprintf(buf
, sizeof(buf
), "??? 0x%08x", addr
);
556 #endif /* DEBUG_EEPRO100 */
559 static uint16_t eepro100_read_status(EEPRO100State
* s
)
561 uint16_t val
= s
->status
;
562 TRACE(OTHER
, logout("val=0x%04x\n", val
));
566 static void eepro100_write_status(EEPRO100State
* s
, uint16_t val
)
568 TRACE(OTHER
, logout("val=0x%04x\n", val
));
573 /*****************************************************************************
577 ****************************************************************************/
580 static uint16_t eepro100_read_command(EEPRO100State
* s
)
582 uint16_t val
= 0xffff;
583 //~ TRACE(OTHER, logout("val=0x%04x\n", val));
588 static bool device_supports_eTxCB(EEPRO100State
* s
)
590 return (s
->device
!= i82557B
&& s
->device
!= i82557C
);
593 /* Commands that can be put in a command list entry. */
598 CmdMulticastList
= 3,
600 CmdTDR
= 5, /* load microcode */
604 /* And some extra flags: */
605 CmdSuspend
= 0x4000, /* Suspend after completion. */
606 CmdIntr
= 0x2000, /* Interrupt after completion. */
607 CmdTxFlex
= 0x0008, /* Use "Flexible mode" for CmdTx command. */
610 static cu_state_t
get_cu_state(EEPRO100State
* s
)
612 return ((s
->mem
[SCBStatus
] >> 6) & 0x03);
615 static void set_cu_state(EEPRO100State
* s
, cu_state_t state
)
617 s
->mem
[SCBStatus
] = (s
->mem
[SCBStatus
] & 0x3f) + (state
<< 6);
620 static ru_state_t
get_ru_state(EEPRO100State
* s
)
622 return ((s
->mem
[SCBStatus
] >> 2) & 0x0f);
625 static void set_ru_state(EEPRO100State
* s
, ru_state_t state
)
627 s
->mem
[SCBStatus
] = (s
->mem
[SCBStatus
] & 0xc3) + (state
<< 2);
630 static void dump_statistics(EEPRO100State
* s
)
632 /* Dump statistical data. Most data is never changed by the emulation
633 * and always 0, so we first just copy the whole block and then those
634 * values which really matter.
635 * Number of data should check configuration!!!
637 cpu_physical_memory_write(s
->statsaddr
, (uint8_t *) & s
->statistics
, 64);
638 stl_phys(s
->statsaddr
+ 0, s
->statistics
.tx_good_frames
);
639 stl_phys(s
->statsaddr
+ 36, s
->statistics
.rx_good_frames
);
640 stl_phys(s
->statsaddr
+ 48, s
->statistics
.rx_resource_errors
);
641 stl_phys(s
->statsaddr
+ 60, s
->statistics
.rx_short_frame_errors
);
642 //~ stw_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
643 //~ stw_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
644 //~ missing("CU dump statistical counters");
647 static void eepro100_cu_command(EEPRO100State
* s
, uint8_t val
)
656 if (get_cu_state(s
) != cu_idle
) {
657 /* Intel documentation says that CU must be idle for the CU
658 * start command. Intel driver for Linux also starts the CU
659 * from suspended state. */
660 logout("CU state is %u, should be %u\n", get_cu_state(s
), cu_idle
);
661 //~ assert(!"wrong CU state");
663 set_cu_state(s
, cu_active
);
664 s
->cu_offset
= s
->pointer
;
666 cb_address
= s
->cu_base
+ s
->cu_offset
;
667 cpu_physical_memory_read(cb_address
, (uint8_t *) & tx
, sizeof(tx
));
668 uint16_t status
= le16_to_cpu(tx
.status
);
669 uint16_t command
= le16_to_cpu(tx
.command
);
671 ("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
672 val
, status
, command
, tx
.link
);
673 bool bit_el
= ((command
& 0x8000) != 0);
674 bool bit_s
= ((command
& 0x4000) != 0);
675 bool bit_i
= ((command
& 0x2000) != 0);
676 bool bit_nc
= ((command
& 0x0010) != 0);
678 //~ bool bit_sf = ((command & 0x0008) != 0);
679 uint16_t cmd
= command
& 0x0007;
680 s
->cu_offset
= le32_to_cpu(tx
.link
);
686 cpu_physical_memory_read(cb_address
+ 8, &s
->macaddr
[0], 6);
687 TRACE(OTHER
, logout("macaddr: %s\n", nic_dump(&s
->macaddr
[0], 6)));
690 cpu_physical_memory_read(cb_address
+ 8, &s
->configuration
[0],
691 sizeof(s
->configuration
));
692 TRACE(OTHER
, logout("configuration: %s\n", nic_dump(&s
->configuration
[0], 16)));
694 case CmdMulticastList
:
695 //~ missing("multicast list");
699 uint32_t tbd_array
= le32_to_cpu(tx
.tx_desc_addr
);
700 uint16_t tcb_bytes
= (le16_to_cpu(tx
.tcb_bytes
) & 0x3fff);
702 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
703 tbd_array
, tcb_bytes
, tx
.tbd_count
));
706 missing("CmdTx: NC = 0");
711 if (tcb_bytes
> 2600) {
712 logout("TCB byte count too large, using 2600\n");
715 /* Next assertion fails for local configuration. */
716 //~ assert((tcb_bytes > 0) || (tbd_array != 0xffffffff));
717 if (!((tcb_bytes
> 0) || (tbd_array
!= 0xffffffff))) {
719 ("illegal values of TBD array address and TCB byte count!\n");
721 // sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes
724 uint32_t tbd_address
= cb_address
+ 0x10;
725 assert(tcb_bytes
<= sizeof(buf
));
726 while (size
< tcb_bytes
) {
727 uint32_t tx_buffer_address
= ldl_phys(tbd_address
);
728 uint16_t tx_buffer_size
= lduw_phys(tbd_address
+ 4);
729 //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
732 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
733 tx_buffer_address
, tx_buffer_size
));
734 tx_buffer_size
= MIN(tx_buffer_size
, sizeof(buf
) - size
);
735 cpu_physical_memory_read(tx_buffer_address
, &buf
[size
],
737 size
+= tx_buffer_size
;
739 if (tbd_array
== 0xffffffff) {
740 /* Simplified mode. Was already handled by code above. */
743 uint8_t tbd_count
= 0;
744 if (device_supports_eTxCB(s
) && !(s
->configuration
[6] & BIT(4))) {
745 /* Extended Flexible TCB. */
746 for (; tbd_count
< 2; tbd_count
++) {
747 uint32_t tx_buffer_address
= ldl_phys(tbd_address
);
748 uint16_t tx_buffer_size
= lduw_phys(tbd_address
+ 4);
749 uint16_t tx_buffer_el
= lduw_phys(tbd_address
+ 6);
752 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
753 tx_buffer_address
, tx_buffer_size
));
754 tx_buffer_size
= MIN(tx_buffer_size
, sizeof(buf
) - size
);
755 cpu_physical_memory_read(tx_buffer_address
, &buf
[size
],
757 size
+= tx_buffer_size
;
758 if (tx_buffer_el
& 1) {
763 tbd_address
= tbd_array
;
764 for (; tbd_count
< tx
.tbd_count
; tbd_count
++) {
765 uint32_t tx_buffer_address
= ldl_phys(tbd_address
);
766 uint16_t tx_buffer_size
= lduw_phys(tbd_address
+ 4);
767 uint16_t tx_buffer_el
= lduw_phys(tbd_address
+ 6);
770 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
771 tx_buffer_address
, tx_buffer_size
));
772 tx_buffer_size
= MIN(tx_buffer_size
, sizeof(buf
) - size
);
773 cpu_physical_memory_read(tx_buffer_address
, &buf
[size
],
775 size
+= tx_buffer_size
;
776 if (tx_buffer_el
& 1) {
781 TRACE(RXTX
, logout("%p sending frame, len=%d,%s\n", s
, size
, nic_dump(buf
, size
)));
782 qemu_send_packet(s
->vc
, buf
, size
);
783 s
->statistics
.tx_good_frames
++;
784 /* Transmit with bad status would raise an CX/TNO interrupt.
785 * (82557 only). Emulation never has bad status. */
786 //~ eepro100_cx_interrupt(s);
789 TRACE(OTHER
, logout("load microcode\n"));
790 /* Starting with offset 8, the command contains
791 * 64 dwords microcode which we just ignore here. */
794 missing("undefined command");
798 /* Write new status. */
799 stw_phys(cb_address
, status
| 0x8000 | (success
? 0x2000 : 0));
801 /* CU completed action. */
802 eepro100_cx_interrupt(s
);
805 /* CU becomes idle. Terminate command loop. */
806 set_cu_state(s
, cu_idle
);
807 eepro100_cna_interrupt(s
);
809 /* CU becomes suspended. */
810 set_cu_state(s
, cu_suspended
);
811 eepro100_cna_interrupt(s
);
813 /* More entries in list. */
814 TRACE(OTHER
, logout("CU list with at least one more entry\n"));
817 TRACE(OTHER
, logout("CU list empty\n"));
818 /* List is empty. Now CU is idle or suspended. */
821 if (get_cu_state(s
) != cu_suspended
) {
822 logout("bad CU resume from CU state %u\n", get_cu_state(s
));
823 /* Workaround for bad Linux eepro100 driver which resumes
824 * from idle state. */
825 //~ missing("cu resume");
826 set_cu_state(s
, cu_suspended
);
828 if (get_cu_state(s
) == cu_suspended
) {
829 TRACE(OTHER
, logout("CU resuming\n"));
830 set_cu_state(s
, cu_active
);
835 /* Load dump counters address. */
836 s
->statsaddr
= s
->pointer
;
837 TRACE(OTHER
, logout("val=0x%02x (status address)\n", val
));
840 /* Dump statistical counters. */
841 TRACE(OTHER
, logout("val=0x%02x (dump stats)\n", val
));
846 TRACE(OTHER
, logout("val=0x%02x (CU base address)\n", val
));
847 s
->cu_base
= s
->pointer
;
850 /* Dump and reset statistical counters. */
851 TRACE(OTHER
, logout("val=0x%02x (dump stats and reset)\n", val
));
853 memset(&s
->statistics
, 0, sizeof(s
->statistics
));
856 /* CU static resume. */
857 missing("CU static resume");
860 missing("Undefined CU command");
864 static void eepro100_ru_command(EEPRO100State
* s
, uint8_t val
)
872 if (get_ru_state(s
) != ru_idle
) {
873 logout("RU state is %u, should be %u\n", get_ru_state(s
), ru_idle
);
874 //~ assert(!"wrong RU state");
876 set_ru_state(s
, ru_ready
);
877 s
->ru_offset
= s
->pointer
;
878 TRACE(OTHER
, logout("val=0x%02x (rx start)\n", val
));
882 if (get_ru_state(s
) != ru_suspended
) {
883 logout("RU state is %u, should be %u\n", get_ru_state(s
),
885 //~ assert(!"wrong RU state");
887 set_ru_state(s
, ru_ready
);
891 TRACE(OTHER
, logout("val=0x%02x (RU base address)\n", val
));
892 s
->ru_base
= s
->pointer
;
895 logout("val=0x%02x (undefined RU command)\n", val
);
896 missing("Undefined SU command");
900 static void eepro100_write_command(EEPRO100State
* s
, uint8_t val
)
902 eepro100_ru_command(s
, val
& 0x0f);
903 eepro100_cu_command(s
, val
& 0xf0);
905 TRACE(OTHER
, logout("val=0x%02x\n", val
));
907 /* Clear command byte after command was accepted. */
911 /*****************************************************************************
915 ****************************************************************************/
917 #define EEPROM_CS 0x02
918 #define EEPROM_SK 0x01
919 #define EEPROM_DI 0x04
920 #define EEPROM_DO 0x08
922 static uint16_t eepro100_read_eeprom(EEPRO100State
* s
)
925 memcpy(&val
, &s
->mem
[SCBeeprom
], sizeof(val
));
926 if (eeprom93xx_read(s
->eeprom
)) {
931 TRACE(EEPROM
, logout("val=0x%04x\n", val
));
935 static void eepro100_write_eeprom(eeprom_t
* eeprom
, uint8_t val
)
937 TRACE(EEPROM
, logout("val=0x%02x\n", val
));
939 /* mask unwriteable bits */
940 //~ val = SET_MASKED(val, 0x31, eeprom->value);
942 int eecs
= ((val
& EEPROM_CS
) != 0);
943 int eesk
= ((val
& EEPROM_SK
) != 0);
944 int eedi
= ((val
& EEPROM_DI
) != 0);
945 eeprom93xx_write(eeprom
, eecs
, eesk
, eedi
);
948 static void eepro100_write_pointer(EEPRO100State
* s
, uint32_t val
)
950 s
->pointer
= le32_to_cpu(val
);
951 TRACE(OTHER
, logout("val=0x%08x\n", val
));
954 /*****************************************************************************
958 ****************************************************************************/
960 #if defined(DEBUG_EEPRO100)
961 static const char * const mdi_op_name
[] = {
968 static const char * const mdi_reg_name
[] = {
971 "PHY Identification (Word 1)",
972 "PHY Identification (Word 2)",
973 "Auto-Negotiation Advertisement",
974 "Auto-Negotiation Link Partner Ability",
975 "Auto-Negotiation Expansion"
978 static const char *reg2name(uint8_t reg
)
980 static char buffer
[10];
981 const char *p
= buffer
;
982 if (reg
< ARRAY_SIZE(mdi_reg_name
)) {
983 p
= mdi_reg_name
[reg
];
985 snprintf(buffer
, sizeof(buffer
), "reg=0x%02x", reg
);
989 #endif /* DEBUG_EEPRO100 */
991 static uint32_t eepro100_read_mdi(EEPRO100State
* s
)
994 memcpy(&val
, &s
->mem
[0x10], sizeof(val
));
996 #ifdef DEBUG_EEPRO100
997 uint8_t raiseint
= (val
& BIT(29)) >> 29;
998 uint8_t opcode
= (val
& BITS(27, 26)) >> 26;
999 uint8_t phy
= (val
& BITS(25, 21)) >> 21;
1000 uint8_t reg
= (val
& BITS(20, 16)) >> 16;
1001 uint16_t data
= (val
& BITS(15, 0));
1003 /* Emulation takes no time to finish MDI transaction. */
1005 TRACE(MDI
, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1006 val
, raiseint
, mdi_op_name
[opcode
], phy
,
1007 reg2name(reg
), data
));
1011 static void eepro100_write_mdi(EEPRO100State
* s
, uint32_t val
)
1013 uint8_t raiseint
= (val
& BIT(29)) >> 29;
1014 uint8_t opcode
= (val
& BITS(27, 26)) >> 26;
1015 uint8_t phy
= (val
& BITS(25, 21)) >> 21;
1016 uint8_t reg
= (val
& BITS(20, 16)) >> 16;
1017 uint16_t data
= (val
& BITS(15, 0));
1018 TRACE(MDI
, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1019 val
, raiseint
, mdi_op_name
[opcode
], phy
, reg2name(reg
), data
));
1021 /* Unsupported PHY address. */
1022 //~ logout("phy must be 1 but is %u\n", phy);
1024 } else if (opcode
!= 1 && opcode
!= 2) {
1025 /* Unsupported opcode. */
1026 logout("opcode must be 1 or 2 but is %u\n", opcode
);
1028 } else if (reg
> 6) {
1029 /* Unsupported register. */
1030 logout("register must be 0...6 but is %u\n", reg
);
1033 TRACE(MDI
, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1034 val
, raiseint
, mdi_op_name
[opcode
], phy
,
1035 reg2name(reg
), data
));
1039 case 0: /* Control Register */
1040 if (data
& 0x8000) {
1041 /* Reset status and control registers to default. */
1042 s
->mdimem
[0] = eepro100_mdi_default
[0];
1043 s
->mdimem
[1] = eepro100_mdi_default
[1];
1044 data
= s
->mdimem
[reg
];
1046 /* Restart Auto Configuration = Normal Operation */
1050 case 1: /* Status Register */
1051 missing("not writable");
1052 data
= s
->mdimem
[reg
];
1054 case 2: /* PHY Identification Register (Word 1) */
1055 case 3: /* PHY Identification Register (Word 2) */
1056 missing("not implemented");
1058 case 4: /* Auto-Negotiation Advertisement Register */
1059 case 5: /* Auto-Negotiation Link Partner Ability Register */
1061 case 6: /* Auto-Negotiation Expansion Register */
1063 missing("not implemented");
1065 s
->mdimem
[reg
] = data
;
1066 } else if (opcode
== 2) {
1069 case 0: /* Control Register */
1070 if (data
& 0x8000) {
1071 /* Reset status and control registers to default. */
1072 s
->mdimem
[0] = eepro100_mdi_default
[0];
1073 s
->mdimem
[1] = eepro100_mdi_default
[1];
1076 case 1: /* Status Register */
1077 s
->mdimem
[reg
] |= 0x0020;
1079 case 2: /* PHY Identification Register (Word 1) */
1080 case 3: /* PHY Identification Register (Word 2) */
1081 case 4: /* Auto-Negotiation Advertisement Register */
1083 case 5: /* Auto-Negotiation Link Partner Ability Register */
1084 s
->mdimem
[reg
] = 0x41fe;
1086 case 6: /* Auto-Negotiation Expansion Register */
1087 s
->mdimem
[reg
] = 0x0001;
1090 data
= s
->mdimem
[reg
];
1092 /* Emulation takes no time to finish MDI transaction.
1093 * Set MDI bit in SCB status register. */
1094 s
->mem
[SCBAck
] |= 0x08;
1097 eepro100_mdi_interrupt(s
);
1100 val
= (val
& 0xffff0000) + data
;
1101 memcpy(&s
->mem
[0x10], &val
, sizeof(val
));
1104 /*****************************************************************************
1108 ****************************************************************************/
1110 #define PORT_SOFTWARE_RESET 0
1111 #define PORT_SELFTEST 1
1112 #define PORT_SELECTIVE_RESET 2
1114 #define PORT_SELECTION_MASK 3
1117 uint32_t st_sign
; /* Self Test Signature */
1118 uint32_t st_result
; /* Self Test Results */
1119 } eepro100_selftest_t
;
1121 static uint32_t eepro100_read_port(EEPRO100State
* s
)
1126 static void eepro100_write_port(EEPRO100State
* s
, uint32_t val
)
1128 val
= le32_to_cpu(val
);
1129 uint32_t address
= (val
& ~PORT_SELECTION_MASK
);
1130 uint8_t selection
= (val
& PORT_SELECTION_MASK
);
1131 switch (selection
) {
1132 case PORT_SOFTWARE_RESET
:
1136 TRACE(OTHER
, logout("selftest address=0x%08x\n", address
));
1137 eepro100_selftest_t data
;
1138 cpu_physical_memory_read(address
, (uint8_t *) & data
, sizeof(data
));
1139 data
.st_sign
= 0xffffffff;
1141 cpu_physical_memory_write(address
, (uint8_t *) & data
, sizeof(data
));
1143 case PORT_SELECTIVE_RESET
:
1144 TRACE(OTHER
, logout("selective reset, selftest address=0x%08x\n", address
));
1145 nic_selective_reset(s
);
1148 logout("val=0x%08x\n", val
);
1149 missing("unknown port selection");
1153 /*****************************************************************************
1155 * General hardware emulation.
1157 ****************************************************************************/
1159 static uint8_t eepro100_read1(EEPRO100State
* s
, uint32_t addr
)
1162 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1163 memcpy(&val
, &s
->mem
[addr
], sizeof(val
));
1168 //~ val = eepro100_read_status(s);
1169 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1172 //~ val = eepro100_read_status(s);
1173 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1176 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1177 //~ val = eepro100_read_command(s);
1180 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1183 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1186 val
= eepro100_read_eeprom(s
);
1188 case 0x1b: /* PMDR (power management driver register) */
1190 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1192 case 0x1d: /* general status register */
1193 /* 100 Mbps full duplex, valid link */
1195 TRACE(OTHER
, logout("addr=General Status val=%02x\n", val
));
1198 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1199 missing("unknown byte read");
1204 static uint16_t eepro100_read2(EEPRO100State
* s
, uint32_t addr
)
1207 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1208 memcpy(&val
, &s
->mem
[addr
], sizeof(val
));
1213 //~ val = eepro100_read_status(s);
1215 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1218 val
= eepro100_read_eeprom(s
);
1219 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1222 logout("addr=%s val=0x%04x\n", regname(addr
), val
);
1223 missing("unknown word read");
1228 static uint32_t eepro100_read4(EEPRO100State
* s
, uint32_t addr
)
1231 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1232 memcpy(&val
, &s
->mem
[addr
], sizeof(val
));
1237 //~ val = eepro100_read_status(s);
1238 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1241 //~ val = eepro100_read_pointer(s);
1242 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1245 val
= eepro100_read_port(s
);
1246 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1249 val
= eepro100_read_mdi(s
);
1252 logout("addr=%s val=0x%08x\n", regname(addr
), val
);
1253 missing("unknown longword read");
1258 static void eepro100_write1(EEPRO100State
* s
, uint32_t addr
, uint8_t val
)
1260 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1261 memcpy(&s
->mem
[addr
], &val
, sizeof(val
));
1264 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1268 //~ eepro100_write_status(s, val);
1271 eepro100_acknowledge(s
);
1274 eepro100_write_command(s
, val
);
1278 eepro100_swi_interrupt(s
);
1280 eepro100_interrupt(s
, 0);
1283 case SCBFlow
: /* does not exist on 82557 */
1287 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1290 eepro100_write_eeprom(s
->eeprom
, val
);
1293 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1294 missing("unknown byte write");
1298 static void eepro100_write2(EEPRO100State
* s
, uint32_t addr
, uint16_t val
)
1300 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1301 memcpy(&s
->mem
[addr
], &val
, sizeof(val
));
1304 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1308 //~ eepro100_write_status(s, val);
1309 eepro100_acknowledge(s
);
1312 eepro100_write_command(s
, val
);
1313 eepro100_write1(s
, SCBIntmask
, val
>> 8);
1316 eepro100_write_eeprom(s
->eeprom
, val
);
1319 logout("addr=%s val=0x%04x\n", regname(addr
), val
);
1320 missing("unknown word write");
1324 static void eepro100_write4(EEPRO100State
* s
, uint32_t addr
, uint32_t val
)
1326 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1327 memcpy(&s
->mem
[addr
], &val
, sizeof(val
));
1332 eepro100_write_pointer(s
, val
);
1335 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1336 eepro100_write_port(s
, val
);
1339 eepro100_write_mdi(s
, val
);
1342 logout("addr=%s val=0x%08x\n", regname(addr
), val
);
1343 missing("unknown longword write");
1347 /*****************************************************************************
1351 ****************************************************************************/
1353 static uint32_t ioport_read1(void *opaque
, uint32_t addr
)
1355 EEPRO100State
*s
= opaque
;
1356 //~ logout("addr=%s\n", regname(addr));
1357 return eepro100_read1(s
, addr
- s
->region
[1]);
1360 static uint32_t ioport_read2(void *opaque
, uint32_t addr
)
1362 EEPRO100State
*s
= opaque
;
1363 return eepro100_read2(s
, addr
- s
->region
[1]);
1366 static uint32_t ioport_read4(void *opaque
, uint32_t addr
)
1368 EEPRO100State
*s
= opaque
;
1369 return eepro100_read4(s
, addr
- s
->region
[1]);
1372 static void ioport_write1(void *opaque
, uint32_t addr
, uint32_t val
)
1374 EEPRO100State
*s
= opaque
;
1375 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1376 eepro100_write1(s
, addr
- s
->region
[1], val
);
1379 static void ioport_write2(void *opaque
, uint32_t addr
, uint32_t val
)
1381 EEPRO100State
*s
= opaque
;
1382 eepro100_write2(s
, addr
- s
->region
[1], val
);
1385 static void ioport_write4(void *opaque
, uint32_t addr
, uint32_t val
)
1387 EEPRO100State
*s
= opaque
;
1388 eepro100_write4(s
, addr
- s
->region
[1], val
);
1391 /***********************************************************/
1392 /* PCI EEPRO100 definitions */
1394 static void pci_map(PCIDevice
* pci_dev
, int region_num
,
1395 uint32_t addr
, uint32_t size
, int type
)
1397 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1399 TRACE(OTHER
, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
1400 region_num
, addr
, size
, type
));
1402 assert(region_num
== 1);
1403 register_ioport_write(addr
, size
, 1, ioport_write1
, s
);
1404 register_ioport_read(addr
, size
, 1, ioport_read1
, s
);
1405 register_ioport_write(addr
, size
, 2, ioport_write2
, s
);
1406 register_ioport_read(addr
, size
, 2, ioport_read2
, s
);
1407 register_ioport_write(addr
, size
, 4, ioport_write4
, s
);
1408 register_ioport_read(addr
, size
, 4, ioport_read4
, s
);
1410 s
->region
[region_num
] = addr
;
1413 /*****************************************************************************
1415 * Memory mapped I/O.
1417 ****************************************************************************/
1419 static void pci_mmio_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1421 EEPRO100State
*s
= opaque
;
1422 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1423 eepro100_write1(s
, addr
, val
);
1426 static void pci_mmio_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1428 EEPRO100State
*s
= opaque
;
1429 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1430 eepro100_write2(s
, addr
, val
);
1433 static void pci_mmio_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1435 EEPRO100State
*s
= opaque
;
1436 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1437 eepro100_write4(s
, addr
, val
);
1440 static uint32_t pci_mmio_readb(void *opaque
, target_phys_addr_t addr
)
1442 EEPRO100State
*s
= opaque
;
1443 //~ logout("addr=%s\n", regname(addr));
1444 return eepro100_read1(s
, addr
);
1447 static uint32_t pci_mmio_readw(void *opaque
, target_phys_addr_t addr
)
1449 EEPRO100State
*s
= opaque
;
1450 //~ logout("addr=%s\n", regname(addr));
1451 return eepro100_read2(s
, addr
);
1454 static uint32_t pci_mmio_readl(void *opaque
, target_phys_addr_t addr
)
1456 EEPRO100State
*s
= opaque
;
1457 //~ logout("addr=%s\n", regname(addr));
1458 return eepro100_read4(s
, addr
);
1461 static CPUWriteMemoryFunc
* const pci_mmio_write
[] = {
1467 static CPUReadMemoryFunc
* const pci_mmio_read
[] = {
1473 static void pci_mmio_map(PCIDevice
* pci_dev
, int region_num
,
1474 uint32_t addr
, uint32_t size
, int type
)
1476 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1478 TRACE(OTHER
, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
1479 region_num
, addr
, size
, type
));
1481 if (region_num
== 0) {
1482 /* Map control / status registers. */
1483 cpu_register_physical_memory(addr
, size
, s
->mmio_index
);
1484 s
->region
[region_num
] = addr
;
1488 static int nic_can_receive(VLANClientState
*vc
)
1490 EEPRO100State
*s
= vc
->opaque
;
1491 TRACE(RXTX
, logout("%p\n", s
));
1492 return get_ru_state(s
) == ru_ready
;
1493 //~ return !eepro100_buffer_full(s);
1496 static ssize_t
nic_receive(VLANClientState
*vc
, const uint8_t * buf
, size_t size
)
1499 * - Magic packets should set bit 30 in power management driver register.
1500 * - Interesting packets should set bit 29 in power management driver register.
1502 EEPRO100State
*s
= vc
->opaque
;
1503 uint16_t rfd_status
= 0xa000;
1504 static const uint8_t broadcast_macaddr
[6] =
1505 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1507 /* TODO: check multiple IA bit. */
1508 if (s
->configuration
[20] & BIT(6)) {
1509 missing("Multiple IA bit");
1513 if (s
->configuration
[8] & 0x80) {
1514 /* CSMA is disabled. */
1515 logout("%p received while CSMA is disabled\n", s
);
1517 } else if (size
< 64 && (s
->configuration
[7] & 1)) {
1518 /* Short frame and configuration byte 7/0 (discard short receive) set:
1519 * Short frame is discarded */
1520 logout("%p received short frame (%zu byte)\n", s
, size
);
1521 s
->statistics
.rx_short_frame_errors
++;
1523 } else if ((size
> MAX_ETH_FRAME_SIZE
+ 4) && !(s
->configuration
[18] & 8)) {
1524 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1525 * Long frames are discarded. */
1526 logout("%p received long frame (%zu byte), ignored\n", s
, size
);
1528 } else if (memcmp(buf
, s
->macaddr
, 6) == 0) { // !!!
1529 /* Frame matches individual address. */
1530 /* TODO: check configuration byte 15/4 (ignore U/L). */
1531 TRACE(RXTX
, logout("%p received frame for me, len=%zu\n", s
, size
));
1532 } else if (memcmp(buf
, broadcast_macaddr
, 6) == 0) {
1533 /* Broadcast frame. */
1534 TRACE(RXTX
, logout("%p received broadcast, len=%zu\n", s
, size
));
1535 rfd_status
|= 0x0002;
1536 } else if (buf
[0] & 0x01) { // !!!
1537 /* Multicast frame. */
1538 TRACE(RXTX
, logout("%p received multicast, len=%zu\n", s
, size
));
1539 /* TODO: check multicast all bit. */
1540 if (s
->configuration
[21] & BIT(3)) {
1541 missing("Multicast All bit");
1543 int mcast_idx
= compute_mcast_idx(buf
);
1544 if (!(s
->mult
[mcast_idx
>> 3] & (1 << (mcast_idx
& 7)))) {
1547 rfd_status
|= 0x0002;
1548 } else if (s
->configuration
[15] & 1) {
1549 /* Promiscuous: receive all. */
1550 TRACE(RXTX
, logout("%p received frame in promiscuous mode, len=%zu\n", s
, size
));
1551 rfd_status
|= 0x0004;
1553 TRACE(RXTX
, logout("%p received frame, ignored, len=%zu,%s\n", s
, size
,
1554 nic_dump(buf
, size
)));
1558 if (get_ru_state(s
) != ru_ready
) {
1559 /* No resources available. */
1560 logout("no resources, state=%u\n", get_ru_state(s
));
1561 s
->statistics
.rx_resource_errors
++;
1562 //~ assert(!"no resources");
1566 //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
1568 cpu_physical_memory_read(s
->ru_base
+ s
->ru_offset
, (uint8_t *) & rx
,
1569 offsetof(eepro100_rx_t
, packet
));
1570 uint16_t rfd_command
= le16_to_cpu(rx
.command
);
1571 uint16_t rfd_size
= le16_to_cpu(rx
.size
);
1573 if (size
> rfd_size
) {
1574 logout("Receive buffer (%" PRId16
" bytes) too small for data "
1575 "(%zu bytes); data truncated\n", rfd_size
, size
);
1579 rfd_status
|= 0x0080;
1581 TRACE(OTHER
, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1582 rfd_command
, rx
.link
, rx
.rx_buf_addr
, rfd_size
));
1583 stw_phys(s
->ru_base
+ s
->ru_offset
+ offsetof(eepro100_rx_t
, status
),
1585 stw_phys(s
->ru_base
+ s
->ru_offset
+ offsetof(eepro100_rx_t
, count
), size
);
1586 /* Early receive interrupt not supported. */
1587 //~ eepro100_er_interrupt(s);
1588 /* Receive CRC Transfer not supported. */
1589 if (s
->configuration
[18] & 4) {
1590 missing("Receive CRC Transfer");
1593 /* TODO: check stripping enable bit. */
1594 //~ assert(!(s->configuration[17] & 1));
1595 cpu_physical_memory_write(s
->ru_base
+ s
->ru_offset
+
1596 offsetof(eepro100_rx_t
, packet
), buf
, size
);
1597 s
->statistics
.rx_good_frames
++;
1598 eepro100_fr_interrupt(s
);
1599 s
->ru_offset
= le32_to_cpu(rx
.link
);
1600 if (rfd_command
& 0x8000) {
1601 /* EL bit is set, so this was the last frame. */
1602 logout("receive: Running out of frames\n");
1603 set_ru_state(s
, ru_suspended
);
1605 if (rfd_command
& 0x4000) {
1607 set_ru_state(s
, ru_suspended
);
1612 static int nic_load(QEMUFile
* f
, void *opaque
, int version_id
)
1614 EEPRO100State
*s
= opaque
;
1621 if (version_id
>= 3) {
1622 ret
= pci_device_load(&s
->dev
, f
);
1627 if (version_id
>= 2) {
1628 qemu_get_8s(f
, &s
->rxcr
);
1633 qemu_get_8s(f
, &s
->cmd
);
1634 qemu_get_be32s(f
, &s
->start
);
1635 qemu_get_be32s(f
, &s
->stop
);
1636 qemu_get_8s(f
, &s
->boundary
);
1637 qemu_get_8s(f
, &s
->tsr
);
1638 qemu_get_8s(f
, &s
->tpsr
);
1639 qemu_get_be16s(f
, &s
->tcnt
);
1640 qemu_get_be16s(f
, &s
->rcnt
);
1641 qemu_get_be32s(f
, &s
->rsar
);
1642 qemu_get_8s(f
, &s
->rsr
);
1643 qemu_get_8s(f
, &s
->isr
);
1644 qemu_get_8s(f
, &s
->dcfg
);
1645 qemu_get_8s(f
, &s
->imr
);
1646 qemu_get_buffer(f
, s
->phys
, 6);
1647 qemu_get_8s(f
, &s
->curpag
);
1648 qemu_get_buffer(f
, s
->mult
, 8);
1649 qemu_get_buffer(f
, s
->mem
, sizeof(s
->mem
));
1651 /* Restore all members of struct between scv_stat and mem. */
1652 qemu_get_8s(f
, &s
->scb_stat
);
1653 qemu_get_8s(f
, &s
->int_stat
);
1654 for (i
= 0; i
< 3; i
++) {
1655 qemu_get_be32s(f
, &s
->region
[i
]);
1657 qemu_get_buffer(f
, s
->macaddr
, 6);
1658 for (i
= 0; i
< 19; i
++) {
1659 qemu_get_be32s(f
, &s
->statcounter
[i
]);
1661 for (i
= 0; i
< 32; i
++) {
1662 qemu_get_be16s(f
, &s
->mdimem
[i
]);
1664 /* The eeprom should be saved and restored by its own routines. */
1665 qemu_get_be32s(f
, &s
->device
);
1666 qemu_get_be32s(f
, &s
->pointer
);
1667 qemu_get_be32s(f
, &s
->cu_base
);
1668 qemu_get_be32s(f
, &s
->cu_offset
);
1669 qemu_get_be32s(f
, &s
->ru_base
);
1670 qemu_get_be32s(f
, &s
->ru_offset
);
1671 qemu_get_be32s(f
, &s
->statsaddr
);
1672 /* Restore epro100_stats_t statistics. */
1673 qemu_get_be32s(f
, &s
->statistics
.tx_good_frames
);
1674 qemu_get_be32s(f
, &s
->statistics
.tx_max_collisions
);
1675 qemu_get_be32s(f
, &s
->statistics
.tx_late_collisions
);
1676 qemu_get_be32s(f
, &s
->statistics
.tx_underruns
);
1677 qemu_get_be32s(f
, &s
->statistics
.tx_lost_crs
);
1678 qemu_get_be32s(f
, &s
->statistics
.tx_deferred
);
1679 qemu_get_be32s(f
, &s
->statistics
.tx_single_collisions
);
1680 qemu_get_be32s(f
, &s
->statistics
.tx_multiple_collisions
);
1681 qemu_get_be32s(f
, &s
->statistics
.tx_total_collisions
);
1682 qemu_get_be32s(f
, &s
->statistics
.rx_good_frames
);
1683 qemu_get_be32s(f
, &s
->statistics
.rx_crc_errors
);
1684 qemu_get_be32s(f
, &s
->statistics
.rx_alignment_errors
);
1685 qemu_get_be32s(f
, &s
->statistics
.rx_resource_errors
);
1686 qemu_get_be32s(f
, &s
->statistics
.rx_overrun_errors
);
1687 qemu_get_be32s(f
, &s
->statistics
.rx_cdt_errors
);
1688 qemu_get_be32s(f
, &s
->statistics
.rx_short_frame_errors
);
1689 qemu_get_be32s(f
, &s
->statistics
.fc_xmt_pause
);
1690 qemu_get_be32s(f
, &s
->statistics
.fc_rcv_pause
);
1691 qemu_get_be32s(f
, &s
->statistics
.fc_rcv_unsupported
);
1692 qemu_get_be16s(f
, &s
->statistics
.xmt_tco_frames
);
1693 qemu_get_be16s(f
, &s
->statistics
.rcv_tco_frames
);
1694 qemu_get_be32s(f
, &s
->statistics
.complete
);
1696 qemu_get_be16s(f
, &s
->status
);
1699 /* Configuration bytes. */
1700 qemu_get_buffer(f
, s
->configuration
, sizeof(s
->configuration
));
1705 static void nic_save(QEMUFile
* f
, void *opaque
)
1707 EEPRO100State
*s
= opaque
;
1710 pci_device_save(&s
->dev
, f
);
1712 qemu_put_8s(f
, &s
->rxcr
);
1714 qemu_put_8s(f
, &s
->cmd
);
1715 qemu_put_be32s(f
, &s
->start
);
1716 qemu_put_be32s(f
, &s
->stop
);
1717 qemu_put_8s(f
, &s
->boundary
);
1718 qemu_put_8s(f
, &s
->tsr
);
1719 qemu_put_8s(f
, &s
->tpsr
);
1720 qemu_put_be16s(f
, &s
->tcnt
);
1721 qemu_put_be16s(f
, &s
->rcnt
);
1722 qemu_put_be32s(f
, &s
->rsar
);
1723 qemu_put_8s(f
, &s
->rsr
);
1724 qemu_put_8s(f
, &s
->isr
);
1725 qemu_put_8s(f
, &s
->dcfg
);
1726 qemu_put_8s(f
, &s
->imr
);
1727 qemu_put_buffer(f
, s
->phys
, 6);
1728 qemu_put_8s(f
, &s
->curpag
);
1729 qemu_put_buffer(f
, s
->mult
, 8);
1730 qemu_put_buffer(f
, s
->mem
, sizeof(s
->mem
));
1732 /* Save all members of struct between scv_stat and mem. */
1733 qemu_put_8s(f
, &s
->scb_stat
);
1734 qemu_put_8s(f
, &s
->int_stat
);
1735 for (i
= 0; i
< 3; i
++) {
1736 qemu_put_be32s(f
, &s
->region
[i
]);
1738 qemu_put_buffer(f
, s
->macaddr
, 6);
1739 for (i
= 0; i
< 19; i
++) {
1740 qemu_put_be32s(f
, &s
->statcounter
[i
]);
1742 for (i
= 0; i
< 32; i
++) {
1743 qemu_put_be16s(f
, &s
->mdimem
[i
]);
1745 /* The eeprom should be saved and restored by its own routines. */
1746 qemu_put_be32s(f
, &s
->device
);
1747 qemu_put_be32s(f
, &s
->pointer
);
1748 qemu_put_be32s(f
, &s
->cu_base
);
1749 qemu_put_be32s(f
, &s
->cu_offset
);
1750 qemu_put_be32s(f
, &s
->ru_base
);
1751 qemu_put_be32s(f
, &s
->ru_offset
);
1752 qemu_put_be32s(f
, &s
->statsaddr
);
1753 /* Save epro100_stats_t statistics. */
1754 qemu_put_be32s(f
, &s
->statistics
.tx_good_frames
);
1755 qemu_put_be32s(f
, &s
->statistics
.tx_max_collisions
);
1756 qemu_put_be32s(f
, &s
->statistics
.tx_late_collisions
);
1757 qemu_put_be32s(f
, &s
->statistics
.tx_underruns
);
1758 qemu_put_be32s(f
, &s
->statistics
.tx_lost_crs
);
1759 qemu_put_be32s(f
, &s
->statistics
.tx_deferred
);
1760 qemu_put_be32s(f
, &s
->statistics
.tx_single_collisions
);
1761 qemu_put_be32s(f
, &s
->statistics
.tx_multiple_collisions
);
1762 qemu_put_be32s(f
, &s
->statistics
.tx_total_collisions
);
1763 qemu_put_be32s(f
, &s
->statistics
.rx_good_frames
);
1764 qemu_put_be32s(f
, &s
->statistics
.rx_crc_errors
);
1765 qemu_put_be32s(f
, &s
->statistics
.rx_alignment_errors
);
1766 qemu_put_be32s(f
, &s
->statistics
.rx_resource_errors
);
1767 qemu_put_be32s(f
, &s
->statistics
.rx_overrun_errors
);
1768 qemu_put_be32s(f
, &s
->statistics
.rx_cdt_errors
);
1769 qemu_put_be32s(f
, &s
->statistics
.rx_short_frame_errors
);
1770 qemu_put_be32s(f
, &s
->statistics
.fc_xmt_pause
);
1771 qemu_put_be32s(f
, &s
->statistics
.fc_rcv_pause
);
1772 qemu_put_be32s(f
, &s
->statistics
.fc_rcv_unsupported
);
1773 qemu_put_be16s(f
, &s
->statistics
.xmt_tco_frames
);
1774 qemu_put_be16s(f
, &s
->statistics
.rcv_tco_frames
);
1775 qemu_put_be32s(f
, &s
->statistics
.complete
);
1777 qemu_put_be16s(f
, &s
->status
);
1780 /* Configuration bytes. */
1781 qemu_put_buffer(f
, s
->configuration
, sizeof(s
->configuration
));
1784 static void nic_cleanup(VLANClientState
*vc
)
1786 EEPRO100State
*s
= vc
->opaque
;
1788 unregister_savevm(vc
->model
, s
);
1790 eeprom93xx_free(s
->eeprom
);
1793 static int pci_nic_uninit(PCIDevice
*pci_dev
)
1795 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1797 cpu_unregister_io_memory(s
->mmio_index
);
1802 static int nic_init(PCIDevice
*pci_dev
, uint32_t device
)
1804 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1806 TRACE(OTHER
, logout("\n"));
1812 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1813 * i82559 and later support 64 or 256 word EEPROM. */
1814 s
->eeprom
= eeprom93xx_new(EEPROM_SIZE
);
1816 /* Handler for memory-mapped I/O */
1818 cpu_register_io_memory(pci_mmio_read
, pci_mmio_write
, s
);
1820 pci_register_bar(&s
->dev
, 0, PCI_MEM_SIZE
,
1821 PCI_ADDRESS_SPACE_MEM
|
1822 PCI_ADDRESS_SPACE_MEM_PREFETCH
, pci_mmio_map
);
1823 pci_register_bar(&s
->dev
, 1, PCI_IO_SIZE
, PCI_ADDRESS_SPACE_IO
,
1825 pci_register_bar(&s
->dev
, 2, PCI_FLASH_SIZE
, PCI_ADDRESS_SPACE_MEM
,
1828 qdev_get_macaddr(&s
->dev
.qdev
, s
->macaddr
);
1829 logout("macaddr: %s\n", nic_dump(&s
->macaddr
[0], 6));
1830 assert(s
->region
[1] == 0);
1834 s
->vc
= qdev_get_vlan_client(&s
->dev
.qdev
,
1835 nic_can_receive
, nic_receive
, NULL
,
1838 qemu_format_nic_info_str(s
->vc
, s
->macaddr
);
1839 TRACE(OTHER
, logout("%s\n", s
->vc
->info_str
));
1841 qemu_register_reset(nic_reset
, s
);
1843 register_savevm(s
->vc
->model
, -1, 3, nic_save
, nic_load
, s
);
1847 static int pci_i82550_init(PCIDevice
*pci_dev
)
1849 return nic_init(pci_dev
, i82550
);
1852 static int pci_i82551_init(PCIDevice
*pci_dev
)
1854 return nic_init(pci_dev
, i82551
);
1857 static int pci_i82557a_init(PCIDevice
*pci_dev
)
1859 return nic_init(pci_dev
, i82557A
);
1862 static int pci_i82557b_init(PCIDevice
*pci_dev
)
1864 return nic_init(pci_dev
, i82557B
);
1867 static int pci_i82557c_init(PCIDevice
*pci_dev
)
1869 return nic_init(pci_dev
, i82557C
);
1872 static int pci_i82558a_init(PCIDevice
*pci_dev
)
1874 return nic_init(pci_dev
, i82558A
);
1877 static int pci_i82558b_init(PCIDevice
*pci_dev
)
1879 return nic_init(pci_dev
, i82558B
);
1882 static int pci_i82559a_init(PCIDevice
*pci_dev
)
1884 return nic_init(pci_dev
, i82559A
);
1887 static int pci_i82559b_init(PCIDevice
*pci_dev
)
1889 return nic_init(pci_dev
, i82559B
);
1892 static int pci_i82559c_init(PCIDevice
*pci_dev
)
1894 return nic_init(pci_dev
, i82559C
);
1897 static int pci_i82559er_init(PCIDevice
*pci_dev
)
1899 return nic_init(pci_dev
, i82559ER
);
1902 static int pci_i82562_init(PCIDevice
*pci_dev
)
1904 return nic_init(pci_dev
, i82562
);
1907 static PCIDeviceInfo eepro100_info
[] = {
1909 .qdev
.name
= "i82550",
1910 .qdev
.size
= sizeof(EEPRO100State
),
1911 .init
= pci_i82550_init
,
1913 .qdev
.name
= "i82551",
1914 .qdev
.size
= sizeof(EEPRO100State
),
1915 .init
= pci_i82551_init
,
1916 .exit
= pci_nic_uninit
,
1918 .qdev
.name
= "i82557a",
1919 .qdev
.size
= sizeof(EEPRO100State
),
1920 .init
= pci_i82557a_init
,
1922 .qdev
.name
= "i82557b",
1923 .qdev
.size
= sizeof(EEPRO100State
),
1924 .init
= pci_i82557b_init
,
1925 .exit
= pci_nic_uninit
,
1927 .qdev
.name
= "i82557c",
1928 .qdev
.size
= sizeof(EEPRO100State
),
1929 .init
= pci_i82557c_init
,
1931 .qdev
.name
= "i82558a",
1932 .qdev
.size
= sizeof(EEPRO100State
),
1933 .init
= pci_i82558a_init
,
1935 .qdev
.name
= "i82558b",
1936 .qdev
.size
= sizeof(EEPRO100State
),
1937 .init
= pci_i82558b_init
,
1939 .qdev
.name
= "i82559a",
1940 .qdev
.size
= sizeof(EEPRO100State
),
1941 .init
= pci_i82559a_init
,
1943 .qdev
.name
= "i82559b",
1944 .qdev
.size
= sizeof(EEPRO100State
),
1945 .init
= pci_i82559b_init
,
1947 .qdev
.name
= "i82559c",
1948 .qdev
.size
= sizeof(EEPRO100State
),
1949 .init
= pci_i82559c_init
,
1951 .qdev
.name
= "i82559er",
1952 .qdev
.size
= sizeof(EEPRO100State
),
1953 .init
= pci_i82559er_init
,
1954 .exit
= pci_nic_uninit
,
1956 .qdev
.name
= "i82562",
1957 .qdev
.size
= sizeof(EEPRO100State
),
1958 .init
= pci_i82562_init
,
1964 static void eepro100_register_devices(void)
1966 pci_qdev_register_many(eepro100_info
);
1969 device_init(eepro100_register_devices
)