2 * QEMU i8255x (PRO100) emulation
4 * Copyright (c) 2006-2007 Stefan Weil
6 * Portions of the code are copies from grub / etherboot eepro100.c
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
22 * Tested features (i82559):
23 * PXE boot (i386) no valid link
24 * Linux networking (i386) ok
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
36 #if defined(TARGET_I386)
37 # warning "PXE boot still not working!"
40 #include <stddef.h> /* offsetof */
45 #include "eeprom93xx.h"
47 /* Common declarations for all PCI devices. */
49 #define PCI_CONFIG_8(offset, value) \
50 (pci_conf[offset] = (value))
51 #define PCI_CONFIG_16(offset, value) \
52 (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
53 #define PCI_CONFIG_32(offset, value) \
54 (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
58 /* Debug EEPRO100 card. */
59 //~ #define DEBUG_EEPRO100
62 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
64 #define logout(fmt, ...) ((void)0)
67 /* Set flags to 0 to disable debug output. */
68 #define INT 1 /* interrupt related actions */
69 #define MDI 1 /* mdi related actions */
72 #define EEPROM 1 /* eeprom related actions */
74 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
76 #define missing(text) assert(!"feature is missing in this emulation: " text)
78 #define MAX_ETH_FRAME_SIZE 1514
80 /* This driver supports several different devices which are declared here. */
81 #define i82551 0x82551
82 #define i82557B 0x82557b
83 #define i82557C 0x82557c
84 #define i82558B 0x82558b
85 #define i82559C 0x82559c
86 #define i82559ER 0x82559e
87 #define i82562 0x82562
89 /* Use 64 word EEPROM. TODO: could be a runtime option. */
90 #define EEPROM_SIZE 64
92 #define PCI_MEM_SIZE (4 * KiB)
93 #define PCI_IO_SIZE 64
94 #define PCI_FLASH_SIZE (128 * KiB)
96 #define BIT(n) (1 << (n))
97 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
99 /* The SCB accepts the following controls for the Tx and Rx units: */
100 #define CU_NOP 0x0000 /* No operation. */
101 #define CU_START 0x0010 /* CU start. */
102 #define CU_RESUME 0x0020 /* CU resume. */
103 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
104 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
105 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
106 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
107 #define CU_SRESUME 0x00a0 /* CU static resume. */
109 #define RU_NOP 0x0000
110 #define RX_START 0x0001
111 #define RX_RESUME 0x0002
112 #define RX_ABORT 0x0004
113 #define RX_ADDR_LOAD 0x0006
114 #define RX_RESUMENR 0x0007
115 #define INT_MASK 0x0100
116 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
118 /* Offsets to the various registers.
119 All accesses need not be longword aligned. */
120 enum speedo_offsets
{
123 SCBCmd
= 2, /* Rx/Command Unit command and status. */
125 SCBPointer
= 4, /* General purpose pointer. */
126 SCBPort
= 8, /* Misc. commands and operands. */
127 SCBflash
= 12, SCBeeprom
= 14, /* EEPROM and flash memory control. */
128 SCBCtrlMDI
= 16, /* MDI interface control. */
129 SCBEarlyRx
= 20, /* Early receive byte count. */
133 /* A speedo3 transmit buffer descriptor with two buffers... */
137 uint32_t link
; /* void * */
138 uint32_t tx_desc_addr
; /* transmit buffer decsriptor array address. */
139 uint16_t tcb_bytes
; /* transmit command block byte count (in lower 14 bits */
140 uint8_t tx_threshold
; /* transmit threshold */
141 uint8_t tbd_count
; /* TBD number */
142 //~ /* This constitutes two "TBD" entries: hdr and data */
143 //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
144 //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
145 //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
146 //~ int32_t tx_buf_size1; /* Length of Tx data. */
149 /* Receive frame descriptor. */
153 uint32_t link
; /* struct RxFD * */
154 uint32_t rx_buf_addr
; /* void * */
157 char packet
[MAX_ETH_FRAME_SIZE
+ 4];
161 uint32_t tx_good_frames
, tx_max_collisions
, tx_late_collisions
,
162 tx_underruns
, tx_lost_crs
, tx_deferred
, tx_single_collisions
,
163 tx_multiple_collisions
, tx_total_collisions
;
164 uint32_t rx_good_frames
, rx_crc_errors
, rx_alignment_errors
,
165 rx_resource_errors
, rx_overrun_errors
, rx_cdt_errors
,
166 rx_short_frame_errors
;
167 uint32_t fc_xmt_pause
, fc_rcv_pause
, fc_rcv_unsupported
;
168 uint16_t xmt_tco_frames
, rcv_tco_frames
;
204 uint8_t phys
[6]; /* mac address */
206 uint8_t mult
[8]; /* multicast mask array */
210 uint8_t scb_stat
; /* SCB stat/ack byte */
211 uint8_t int_stat
; /* PCI interrupt status */
212 uint32_t region
[3]; /* PCI region addresses */
214 uint32_t statcounter
[19];
217 uint32_t device
; /* device variant */
219 /* (cu_base + cu_offset) address the next command block in the command block list. */
220 uint32_t cu_base
; /* CU base address */
221 uint32_t cu_offset
; /* CU address offset */
222 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
223 uint32_t ru_base
; /* RU base address */
224 uint32_t ru_offset
; /* RU address offset */
225 uint32_t statsaddr
; /* pointer to eepro100_stats_t */
226 eepro100_stats_t statistics
; /* statistical counters */
231 /* Configuration bytes. */
232 uint8_t configuration
[22];
234 /* Data in mem is always in the byte order of the controller (le). */
235 uint8_t mem
[PCI_MEM_SIZE
];
238 /* Default values for MDI (PHY) registers */
239 static const uint16_t eepro100_mdi_default
[] = {
240 /* MDI Registers 0 - 6, 7 */
241 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
242 /* MDI Registers 8 - 15 */
243 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
244 /* MDI Registers 16 - 31 */
245 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
246 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
249 /* Readonly mask for MDI (PHY) registers */
250 static const uint16_t eepro100_mdi_mask
[] = {
251 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
252 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
253 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
254 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
257 #define POLYNOMIAL 0x04c11db6
261 static int compute_mcast_idx(const uint8_t * ep
)
268 for (i
= 0; i
< 6; i
++) {
270 for (j
= 0; j
< 8; j
++) {
271 carry
= ((crc
& 0x80000000L
) ? 1 : 0) ^ (b
& 0x01);
275 crc
= ((crc
^ POLYNOMIAL
) | carry
);
282 #if defined(DEBUG_EEPRO100)
283 static const char *nic_dump(const uint8_t * buf
, unsigned size
)
285 static char dump
[3 * 16 + 1];
291 p
+= sprintf(p
, " %02x", *buf
++);
295 #endif /* DEBUG_EEPRO100 */
298 stat_ack_not_ours
= 0x00,
299 stat_ack_sw_gen
= 0x04,
301 stat_ack_cu_idle
= 0x20,
302 stat_ack_frame_rx
= 0x40,
303 stat_ack_cu_cmd_done
= 0x80,
304 stat_ack_not_present
= 0xFF,
305 stat_ack_rx
= (stat_ack_sw_gen
| stat_ack_rnr
| stat_ack_frame_rx
),
306 stat_ack_tx
= (stat_ack_cu_idle
| stat_ack_cu_cmd_done
),
309 static void disable_interrupt(EEPRO100State
* s
)
312 TRACE(INT
, logout("interrupt disabled\n"));
313 qemu_irq_lower(s
->dev
.irq
[0]);
318 static void enable_interrupt(EEPRO100State
* s
)
321 TRACE(INT
, logout("interrupt enabled\n"));
322 qemu_irq_raise(s
->dev
.irq
[0]);
327 static void eepro100_acknowledge(EEPRO100State
* s
)
329 s
->scb_stat
&= ~s
->mem
[SCBAck
];
330 s
->mem
[SCBAck
] = s
->scb_stat
;
331 if (s
->scb_stat
== 0) {
332 disable_interrupt(s
);
336 static void eepro100_interrupt(EEPRO100State
* s
, uint8_t stat
)
338 uint8_t mask
= ~s
->mem
[SCBIntmask
];
339 s
->mem
[SCBAck
] |= stat
;
340 stat
= s
->scb_stat
= s
->mem
[SCBAck
];
341 stat
&= (mask
| 0x0f);
342 //~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
343 if (stat
&& (mask
& 0x01)) {
344 /* SCB mask and SCB Bit M do not disable interrupt. */
346 } else if (s
->int_stat
) {
347 disable_interrupt(s
);
351 static void eepro100_cx_interrupt(EEPRO100State
* s
)
353 /* CU completed action command. */
354 /* Transmit not ok (82557 only, not in emulation). */
355 eepro100_interrupt(s
, 0x80);
358 static void eepro100_cna_interrupt(EEPRO100State
* s
)
360 /* CU left the active state. */
361 eepro100_interrupt(s
, 0x20);
364 static void eepro100_fr_interrupt(EEPRO100State
* s
)
366 /* RU received a complete frame. */
367 eepro100_interrupt(s
, 0x40);
371 static void eepro100_rnr_interrupt(EEPRO100State
* s
)
373 /* RU is not ready. */
374 eepro100_interrupt(s
, 0x10);
378 static void eepro100_mdi_interrupt(EEPRO100State
* s
)
380 /* MDI completed read or write cycle. */
381 eepro100_interrupt(s
, 0x08);
384 static void eepro100_swi_interrupt(EEPRO100State
* s
)
386 /* Software has requested an interrupt. */
387 eepro100_interrupt(s
, 0x04);
391 static void eepro100_fcp_interrupt(EEPRO100State
* s
)
393 /* Flow control pause interrupt (82558 and later). */
394 eepro100_interrupt(s
, 0x01);
398 static void pci_reset(EEPRO100State
* s
)
400 uint32_t device
= s
->device
;
401 uint8_t *pci_conf
= s
->dev
.config
;
403 TRACE(OTHER
, logout("%p\n", s
));
406 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_INTEL
);
407 /* PCI Device ID depends on device and is set below. */
409 PCI_CONFIG_16(PCI_COMMAND
, 0x0000);
411 PCI_CONFIG_16(PCI_STATUS
, 0x2800);
412 /* PCI Revision ID */
413 PCI_CONFIG_8(PCI_REVISION_ID
, 0x08);
415 PCI_CONFIG_8(0x09, 0x00);
416 pci_config_set_class(pci_conf
, PCI_CLASS_NETWORK_ETHERNET
);
417 /* PCI Cache Line Size */
418 /* check cache line size!!! */
419 //~ PCI_CONFIG_8(0x0c, 0x00);
420 /* PCI Latency Timer */
421 PCI_CONFIG_8(0x0d, 0x20); // latency timer = 32 clocks
422 /* PCI Header Type */
423 /* BIST (built-in self test) */
424 #if defined(TARGET_I386)
425 // !!! workaround for buggy bios
426 //~ #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0
429 /* PCI Base Address Registers */
430 /* CSR Memory Mapped Base Address */
431 PCI_CONFIG_32(PCI_BASE_ADDRESS_0
,
432 PCI_ADDRESS_SPACE_MEM
| PCI_ADDRESS_SPACE_MEM_PREFETCH
);
433 /* CSR I/O Mapped Base Address */
434 PCI_CONFIG_32(PCI_BASE_ADDRESS_1
, PCI_ADDRESS_SPACE_IO
);
436 /* Flash Memory Mapped Base Address */
437 PCI_CONFIG_32(PCI_BASE_ADDRESS_2
, 0xfffe0000 | PCI_ADDRESS_SPACE_MEM
);
440 /* Expansion ROM Base Address (depends on boot disable!!!) */
441 PCI_CONFIG_32(0x30, 0x00000000);
442 /* Capability Pointer */
443 PCI_CONFIG_8(0x34, 0xdc);
446 PCI_CONFIG_8(0x3d, 1); // interrupt pin 0
448 PCI_CONFIG_8(0x3e, 0x08);
449 /* Maximum Latency */
450 PCI_CONFIG_8(0x3f, 0x18);
451 /* Power Management Capabilities / Next Item Pointer / Capability ID */
452 PCI_CONFIG_32(0xdc, 0x7e210001);
456 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82551IT
);
457 PCI_CONFIG_8(PCI_REVISION_ID
, 0x0f);
460 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
461 PCI_CONFIG_8(PCI_REVISION_ID
, 0x02);
464 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
465 PCI_CONFIG_8(PCI_REVISION_ID
, 0x03);
468 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
469 PCI_CONFIG_16(PCI_STATUS
, 0x2810);
470 PCI_CONFIG_8(PCI_REVISION_ID
, 0x05);
473 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
474 PCI_CONFIG_16(PCI_STATUS
, 0x2810);
475 //~ PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
478 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82551IT
);
479 PCI_CONFIG_16(PCI_STATUS
, 0x2810);
480 PCI_CONFIG_8(PCI_REVISION_ID
, 0x09);
482 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1029);
483 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1030); /* 82559 InBusiness 10/100 */
485 logout("Device %X is undefined!\n", device
);
488 if (device
== i82557C
|| device
== i82558B
|| device
== i82559C
) {
489 logout("Get device id and revision from EEPROM!!!\n");
493 static void nic_selective_reset(EEPRO100State
* s
)
496 uint16_t *eeprom_contents
= eeprom93xx_data(s
->eeprom
);
497 //~ eeprom93xx_reset(s->eeprom);
498 memcpy(eeprom_contents
, s
->macaddr
, 6);
499 eeprom_contents
[0xa] = 0x4000;
501 for (i
= 0; i
< EEPROM_SIZE
- 1; i
++) {
502 sum
+= eeprom_contents
[i
];
504 eeprom_contents
[EEPROM_SIZE
- 1] = 0xbaba - sum
;
505 TRACE(EEPROM
, logout("checksum=0x%04x\n", eeprom_contents
[EEPROM_SIZE
- 1]));
507 memset(s
->mem
, 0, sizeof(s
->mem
));
508 uint32_t val
= BIT(21);
509 memcpy(&s
->mem
[SCBCtrlMDI
], &val
, sizeof(val
));
511 assert(sizeof(s
->mdimem
) == sizeof(eepro100_mdi_default
));
512 memcpy(&s
->mdimem
[0], &eepro100_mdi_default
[0], sizeof(s
->mdimem
));
515 static void nic_reset(void *opaque
)
517 EEPRO100State
*s
= opaque
;
518 TRACE(OTHER
, logout("%p\n", s
));
519 nic_selective_reset(s
);
522 #if defined(DEBUG_EEPRO100)
523 static const char * const reg
[PCI_IO_SIZE
/ 4] = {
527 "EEPROM/Flash Control",
529 "Receive DMA Byte Count",
531 "General Status/Control"
534 static char *regname(uint32_t addr
)
537 if (addr
< PCI_IO_SIZE
) {
538 const char *r
= reg
[addr
/ 4];
540 snprintf(buf
, sizeof(buf
), "%s+%u", r
, addr
% 4);
542 snprintf(buf
, sizeof(buf
), "0x%02x", addr
);
545 snprintf(buf
, sizeof(buf
), "??? 0x%08x", addr
);
549 #endif /* DEBUG_EEPRO100 */
552 static uint16_t eepro100_read_status(EEPRO100State
* s
)
554 uint16_t val
= s
->status
;
555 TRACE(OTHER
, logout("val=0x%04x\n", val
));
559 static void eepro100_write_status(EEPRO100State
* s
, uint16_t val
)
561 TRACE(OTHER
, logout("val=0x%04x\n", val
));
566 /*****************************************************************************
570 ****************************************************************************/
573 static uint16_t eepro100_read_command(EEPRO100State
* s
)
575 uint16_t val
= 0xffff;
576 //~ TRACE(OTHER, logout("val=0x%04x\n", val));
581 static bool device_supports_eTxCB(EEPRO100State
* s
)
583 return (s
->device
!= i82557B
&& s
->device
!= i82557C
);
586 /* Commands that can be put in a command list entry. */
591 CmdMulticastList
= 3,
593 CmdTDR
= 5, /* load microcode */
597 /* And some extra flags: */
598 CmdSuspend
= 0x4000, /* Suspend after completion. */
599 CmdIntr
= 0x2000, /* Interrupt after completion. */
600 CmdTxFlex
= 0x0008, /* Use "Flexible mode" for CmdTx command. */
603 static cu_state_t
get_cu_state(EEPRO100State
* s
)
605 return ((s
->mem
[SCBStatus
] >> 6) & 0x03);
608 static void set_cu_state(EEPRO100State
* s
, cu_state_t state
)
610 s
->mem
[SCBStatus
] = (s
->mem
[SCBStatus
] & 0x3f) + (state
<< 6);
613 static ru_state_t
get_ru_state(EEPRO100State
* s
)
615 return ((s
->mem
[SCBStatus
] >> 2) & 0x0f);
618 static void set_ru_state(EEPRO100State
* s
, ru_state_t state
)
620 s
->mem
[SCBStatus
] = (s
->mem
[SCBStatus
] & 0xc3) + (state
<< 2);
623 static void dump_statistics(EEPRO100State
* s
)
625 /* Dump statistical data. Most data is never changed by the emulation
626 * and always 0, so we first just copy the whole block and then those
627 * values which really matter.
628 * Number of data should check configuration!!!
630 cpu_physical_memory_write(s
->statsaddr
, (uint8_t *) & s
->statistics
, 64);
631 stl_phys(s
->statsaddr
+ 0, s
->statistics
.tx_good_frames
);
632 stl_phys(s
->statsaddr
+ 36, s
->statistics
.rx_good_frames
);
633 stl_phys(s
->statsaddr
+ 48, s
->statistics
.rx_resource_errors
);
634 stl_phys(s
->statsaddr
+ 60, s
->statistics
.rx_short_frame_errors
);
635 //~ stw_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
636 //~ stw_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
637 //~ missing("CU dump statistical counters");
640 static void eepro100_cu_command(EEPRO100State
* s
, uint8_t val
)
649 if (get_cu_state(s
) != cu_idle
) {
650 /* Intel documentation says that CU must be idle for the CU
651 * start command. Intel driver for Linux also starts the CU
652 * from suspended state. */
653 logout("CU state is %u, should be %u\n", get_cu_state(s
), cu_idle
);
654 //~ assert(!"wrong CU state");
656 set_cu_state(s
, cu_active
);
657 s
->cu_offset
= s
->pointer
;
659 cb_address
= s
->cu_base
+ s
->cu_offset
;
660 cpu_physical_memory_read(cb_address
, (uint8_t *) & tx
, sizeof(tx
));
661 uint16_t status
= le16_to_cpu(tx
.status
);
662 uint16_t command
= le16_to_cpu(tx
.command
);
664 ("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
665 val
, status
, command
, tx
.link
);
666 bool bit_el
= ((command
& 0x8000) != 0);
667 bool bit_s
= ((command
& 0x4000) != 0);
668 bool bit_i
= ((command
& 0x2000) != 0);
669 bool bit_nc
= ((command
& 0x0010) != 0);
670 //~ bool bit_sf = ((command & 0x0008) != 0);
671 uint16_t cmd
= command
& 0x0007;
672 s
->cu_offset
= le32_to_cpu(tx
.link
);
678 cpu_physical_memory_read(cb_address
+ 8, &s
->macaddr
[0], 6);
679 TRACE(OTHER
, logout("macaddr: %s\n", nic_dump(&s
->macaddr
[0], 6)));
682 cpu_physical_memory_read(cb_address
+ 8, &s
->configuration
[0],
683 sizeof(s
->configuration
));
684 TRACE(OTHER
, logout("configuration: %s\n", nic_dump(&s
->configuration
[0], 16)));
686 case CmdMulticastList
:
687 //~ missing("multicast list");
691 uint32_t tbd_array
= le32_to_cpu(tx
.tx_desc_addr
);
692 uint16_t tcb_bytes
= (le16_to_cpu(tx
.tcb_bytes
) & 0x3fff);
694 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
695 tbd_array
, tcb_bytes
, tx
.tbd_count
));
698 assert(tcb_bytes
<= 2600);
699 /* Next assertion fails for local configuration. */
700 //~ assert((tcb_bytes > 0) || (tbd_array != 0xffffffff));
701 if (!((tcb_bytes
> 0) || (tbd_array
!= 0xffffffff))) {
703 ("illegal values of TBD array address and TCB byte count!\n");
705 // sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes
708 uint32_t tbd_address
= cb_address
+ 0x10;
709 assert(tcb_bytes
<= sizeof(buf
));
710 while (size
< tcb_bytes
) {
711 uint32_t tx_buffer_address
= ldl_phys(tbd_address
);
712 uint16_t tx_buffer_size
= lduw_phys(tbd_address
+ 4);
713 //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
716 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
717 tx_buffer_address
, tx_buffer_size
));
718 tx_buffer_size
= MIN(tx_buffer_size
, sizeof(buf
) - size
);
719 cpu_physical_memory_read(tx_buffer_address
, &buf
[size
],
721 size
+= tx_buffer_size
;
723 if (tbd_array
== 0xffffffff) {
724 /* Simplified mode. Was already handled by code above. */
727 uint8_t tbd_count
= 0;
728 if (device_supports_eTxCB(s
) && !(s
->configuration
[6] & BIT(4))) {
729 /* Extended Flexible TCB. */
730 assert(tcb_bytes
== 0);
731 for (; tbd_count
< 2; tbd_count
++) {
732 uint32_t tx_buffer_address
= ldl_phys(tbd_address
);
733 uint16_t tx_buffer_size
= lduw_phys(tbd_address
+ 4);
734 uint16_t tx_buffer_el
= lduw_phys(tbd_address
+ 6);
737 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
738 tx_buffer_address
, tx_buffer_size
));
739 tx_buffer_size
= MIN(tx_buffer_size
, sizeof(buf
) - size
);
740 cpu_physical_memory_read(tx_buffer_address
, &buf
[size
],
742 size
+= tx_buffer_size
;
743 if (tx_buffer_el
& 1) {
748 tbd_address
= tbd_array
;
749 for (; tbd_count
< tx
.tbd_count
; tbd_count
++) {
750 uint32_t tx_buffer_address
= ldl_phys(tbd_address
);
751 uint16_t tx_buffer_size
= lduw_phys(tbd_address
+ 4);
752 uint16_t tx_buffer_el
= lduw_phys(tbd_address
+ 6);
755 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
756 tx_buffer_address
, tx_buffer_size
));
757 tx_buffer_size
= MIN(tx_buffer_size
, sizeof(buf
) - size
);
758 cpu_physical_memory_read(tx_buffer_address
, &buf
[size
],
760 size
+= tx_buffer_size
;
761 if (tx_buffer_el
& 1) {
766 TRACE(RXTX
, logout("%p sending frame, len=%d,%s\n", s
, size
, nic_dump(buf
, size
)));
767 qemu_send_packet(s
->vc
, buf
, size
);
768 s
->statistics
.tx_good_frames
++;
769 /* Transmit with bad status would raise an CX/TNO interrupt.
770 * (82557 only). Emulation never has bad status. */
771 //~ eepro100_cx_interrupt(s);
774 TRACE(OTHER
, logout("load microcode\n"));
775 /* Starting with offset 8, the command contains
776 * 64 dwords microcode which we just ignore here. */
779 missing("undefined command");
781 /* Write new status (success). */
782 stw_phys(cb_address
, status
| 0x8000 | 0x2000);
784 /* CU completed action. */
785 eepro100_cx_interrupt(s
);
788 /* CU becomes idle. Terminate command loop. */
789 set_cu_state(s
, cu_idle
);
790 eepro100_cna_interrupt(s
);
792 /* CU becomes suspended. */
793 set_cu_state(s
, cu_suspended
);
794 eepro100_cna_interrupt(s
);
796 /* More entries in list. */
797 TRACE(OTHER
, logout("CU list with at least one more entry\n"));
800 TRACE(OTHER
, logout("CU list empty\n"));
801 /* List is empty. Now CU is idle or suspended. */
804 if (get_cu_state(s
) != cu_suspended
) {
805 logout("bad CU resume from CU state %u\n", get_cu_state(s
));
806 /* Workaround for bad Linux eepro100 driver which resumes
807 * from idle state. */
808 //~ missing("cu resume");
809 set_cu_state(s
, cu_suspended
);
811 if (get_cu_state(s
) == cu_suspended
) {
812 TRACE(OTHER
, logout("CU resuming\n"));
813 set_cu_state(s
, cu_active
);
818 /* Load dump counters address. */
819 s
->statsaddr
= s
->pointer
;
820 TRACE(OTHER
, logout("val=0x%02x (status address)\n", val
));
823 /* Dump statistical counters. */
824 TRACE(OTHER
, logout("val=0x%02x (dump stats)\n", val
));
829 TRACE(OTHER
, logout("val=0x%02x (CU base address)\n", val
));
830 s
->cu_base
= s
->pointer
;
833 /* Dump and reset statistical counters. */
834 TRACE(OTHER
, logout("val=0x%02x (dump stats and reset)\n", val
));
836 memset(&s
->statistics
, 0, sizeof(s
->statistics
));
839 /* CU static resume. */
840 missing("CU static resume");
843 missing("Undefined CU command");
847 static void eepro100_ru_command(EEPRO100State
* s
, uint8_t val
)
855 if (get_ru_state(s
) != ru_idle
) {
856 logout("RU state is %u, should be %u\n", get_ru_state(s
), ru_idle
);
857 //~ assert(!"wrong RU state");
859 set_ru_state(s
, ru_ready
);
860 s
->ru_offset
= s
->pointer
;
861 TRACE(OTHER
, logout("val=0x%02x (rx start)\n", val
));
865 if (get_ru_state(s
) != ru_suspended
) {
866 logout("RU state is %u, should be %u\n", get_ru_state(s
),
868 //~ assert(!"wrong RU state");
870 set_ru_state(s
, ru_ready
);
874 TRACE(OTHER
, logout("val=0x%02x (RU base address)\n", val
));
875 s
->ru_base
= s
->pointer
;
878 logout("val=0x%02x (undefined RU command)\n", val
);
879 missing("Undefined SU command");
883 static void eepro100_write_command(EEPRO100State
* s
, uint8_t val
)
885 eepro100_ru_command(s
, val
& 0x0f);
886 eepro100_cu_command(s
, val
& 0xf0);
888 TRACE(OTHER
, logout("val=0x%02x\n", val
));
890 /* Clear command byte after command was accepted. */
894 /*****************************************************************************
898 ****************************************************************************/
900 #define EEPROM_CS 0x02
901 #define EEPROM_SK 0x01
902 #define EEPROM_DI 0x04
903 #define EEPROM_DO 0x08
905 static uint16_t eepro100_read_eeprom(EEPRO100State
* s
)
908 memcpy(&val
, &s
->mem
[SCBeeprom
], sizeof(val
));
909 if (eeprom93xx_read(s
->eeprom
)) {
914 TRACE(EEPROM
, logout("val=0x%04x\n", val
));
918 static void eepro100_write_eeprom(eeprom_t
* eeprom
, uint8_t val
)
920 TRACE(EEPROM
, logout("val=0x%02x\n", val
));
922 /* mask unwriteable bits */
923 //~ val = SET_MASKED(val, 0x31, eeprom->value);
925 int eecs
= ((val
& EEPROM_CS
) != 0);
926 int eesk
= ((val
& EEPROM_SK
) != 0);
927 int eedi
= ((val
& EEPROM_DI
) != 0);
928 eeprom93xx_write(eeprom
, eecs
, eesk
, eedi
);
931 static void eepro100_write_pointer(EEPRO100State
* s
, uint32_t val
)
933 s
->pointer
= le32_to_cpu(val
);
934 TRACE(OTHER
, logout("val=0x%08x\n", val
));
937 /*****************************************************************************
941 ****************************************************************************/
943 #if defined(DEBUG_EEPRO100)
944 static const char * const mdi_op_name
[] = {
951 static const char * const mdi_reg_name
[] = {
954 "PHY Identification (Word 1)",
955 "PHY Identification (Word 2)",
956 "Auto-Negotiation Advertisement",
957 "Auto-Negotiation Link Partner Ability",
958 "Auto-Negotiation Expansion"
961 static const char *reg2name(uint8_t reg
)
963 static char buffer
[10];
964 const char *p
= buffer
;
965 if (reg
< ARRAY_SIZE(mdi_reg_name
)) {
966 p
= mdi_reg_name
[reg
];
968 snprintf(buffer
, sizeof(buffer
), "reg=0x%02x", reg
);
972 #endif /* DEBUG_EEPRO100 */
974 static uint32_t eepro100_read_mdi(EEPRO100State
* s
)
977 memcpy(&val
, &s
->mem
[0x10], sizeof(val
));
979 #ifdef DEBUG_EEPRO100
980 uint8_t raiseint
= (val
& BIT(29)) >> 29;
981 uint8_t opcode
= (val
& BITS(27, 26)) >> 26;
982 uint8_t phy
= (val
& BITS(25, 21)) >> 21;
983 uint8_t reg
= (val
& BITS(20, 16)) >> 16;
984 uint16_t data
= (val
& BITS(15, 0));
986 /* Emulation takes no time to finish MDI transaction. */
988 TRACE(MDI
, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
989 val
, raiseint
, mdi_op_name
[opcode
], phy
,
990 reg2name(reg
), data
));
994 static void eepro100_write_mdi(EEPRO100State
* s
, uint32_t val
)
996 uint8_t raiseint
= (val
& BIT(29)) >> 29;
997 uint8_t opcode
= (val
& BITS(27, 26)) >> 26;
998 uint8_t phy
= (val
& BITS(25, 21)) >> 21;
999 uint8_t reg
= (val
& BITS(20, 16)) >> 16;
1000 uint16_t data
= (val
& BITS(15, 0));
1001 TRACE(MDI
, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1002 val
, raiseint
, mdi_op_name
[opcode
], phy
, reg2name(reg
), data
));
1004 /* Unsupported PHY address. */
1005 //~ logout("phy must be 1 but is %u\n", phy);
1007 } else if (opcode
!= 1 && opcode
!= 2) {
1008 /* Unsupported opcode. */
1009 logout("opcode must be 1 or 2 but is %u\n", opcode
);
1011 } else if (reg
> 6) {
1012 /* Unsupported register. */
1013 logout("register must be 0...6 but is %u\n", reg
);
1016 TRACE(MDI
, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1017 val
, raiseint
, mdi_op_name
[opcode
], phy
,
1018 reg2name(reg
), data
));
1022 case 0: /* Control Register */
1023 if (data
& 0x8000) {
1024 /* Reset status and control registers to default. */
1025 s
->mdimem
[0] = eepro100_mdi_default
[0];
1026 s
->mdimem
[1] = eepro100_mdi_default
[1];
1027 data
= s
->mdimem
[reg
];
1029 /* Restart Auto Configuration = Normal Operation */
1033 case 1: /* Status Register */
1034 missing("not writable");
1035 data
= s
->mdimem
[reg
];
1037 case 2: /* PHY Identification Register (Word 1) */
1038 case 3: /* PHY Identification Register (Word 2) */
1039 missing("not implemented");
1041 case 4: /* Auto-Negotiation Advertisement Register */
1042 case 5: /* Auto-Negotiation Link Partner Ability Register */
1044 case 6: /* Auto-Negotiation Expansion Register */
1046 missing("not implemented");
1048 s
->mdimem
[reg
] = data
;
1049 } else if (opcode
== 2) {
1052 case 0: /* Control Register */
1053 if (data
& 0x8000) {
1054 /* Reset status and control registers to default. */
1055 s
->mdimem
[0] = eepro100_mdi_default
[0];
1056 s
->mdimem
[1] = eepro100_mdi_default
[1];
1059 case 1: /* Status Register */
1060 s
->mdimem
[reg
] |= 0x0020;
1062 case 2: /* PHY Identification Register (Word 1) */
1063 case 3: /* PHY Identification Register (Word 2) */
1064 case 4: /* Auto-Negotiation Advertisement Register */
1066 case 5: /* Auto-Negotiation Link Partner Ability Register */
1067 s
->mdimem
[reg
] = 0x41fe;
1069 case 6: /* Auto-Negotiation Expansion Register */
1070 s
->mdimem
[reg
] = 0x0001;
1073 data
= s
->mdimem
[reg
];
1075 /* Emulation takes no time to finish MDI transaction.
1076 * Set MDI bit in SCB status register. */
1077 s
->mem
[SCBAck
] |= 0x08;
1080 eepro100_mdi_interrupt(s
);
1083 val
= (val
& 0xffff0000) + data
;
1084 memcpy(&s
->mem
[0x10], &val
, sizeof(val
));
1087 /*****************************************************************************
1091 ****************************************************************************/
1093 #define PORT_SOFTWARE_RESET 0
1094 #define PORT_SELFTEST 1
1095 #define PORT_SELECTIVE_RESET 2
1097 #define PORT_SELECTION_MASK 3
1100 uint32_t st_sign
; /* Self Test Signature */
1101 uint32_t st_result
; /* Self Test Results */
1102 } eepro100_selftest_t
;
1104 static uint32_t eepro100_read_port(EEPRO100State
* s
)
1109 static void eepro100_write_port(EEPRO100State
* s
, uint32_t val
)
1111 val
= le32_to_cpu(val
);
1112 uint32_t address
= (val
& ~PORT_SELECTION_MASK
);
1113 uint8_t selection
= (val
& PORT_SELECTION_MASK
);
1114 switch (selection
) {
1115 case PORT_SOFTWARE_RESET
:
1119 TRACE(OTHER
, logout("selftest address=0x%08x\n", address
));
1120 eepro100_selftest_t data
;
1121 cpu_physical_memory_read(address
, (uint8_t *) & data
, sizeof(data
));
1122 data
.st_sign
= 0xffffffff;
1124 cpu_physical_memory_write(address
, (uint8_t *) & data
, sizeof(data
));
1126 case PORT_SELECTIVE_RESET
:
1127 TRACE(OTHER
, logout("selective reset, selftest address=0x%08x\n", address
));
1128 nic_selective_reset(s
);
1131 logout("val=0x%08x\n", val
);
1132 missing("unknown port selection");
1136 /*****************************************************************************
1138 * General hardware emulation.
1140 ****************************************************************************/
1142 static uint8_t eepro100_read1(EEPRO100State
* s
, uint32_t addr
)
1145 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1146 memcpy(&val
, &s
->mem
[addr
], sizeof(val
));
1151 //~ val = eepro100_read_status(s);
1152 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1155 //~ val = eepro100_read_status(s);
1156 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1159 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1160 //~ val = eepro100_read_command(s);
1163 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1166 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1169 val
= eepro100_read_eeprom(s
);
1171 case 0x1b: /* PMDR (power management driver register) */
1173 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1175 case 0x1d: /* general status register */
1176 /* 100 Mbps full duplex, valid link */
1178 TRACE(OTHER
, logout("addr=General Status val=%02x\n", val
));
1181 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1182 missing("unknown byte read");
1187 static uint16_t eepro100_read2(EEPRO100State
* s
, uint32_t addr
)
1190 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1191 memcpy(&val
, &s
->mem
[addr
], sizeof(val
));
1196 //~ val = eepro100_read_status(s);
1197 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1200 val
= eepro100_read_eeprom(s
);
1201 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1204 logout("addr=%s val=0x%04x\n", regname(addr
), val
);
1205 missing("unknown word read");
1210 static uint32_t eepro100_read4(EEPRO100State
* s
, uint32_t addr
)
1213 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1214 memcpy(&val
, &s
->mem
[addr
], sizeof(val
));
1219 //~ val = eepro100_read_status(s);
1220 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1223 //~ val = eepro100_read_pointer(s);
1224 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1227 val
= eepro100_read_port(s
);
1228 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1231 val
= eepro100_read_mdi(s
);
1234 logout("addr=%s val=0x%08x\n", regname(addr
), val
);
1235 missing("unknown longword read");
1240 static void eepro100_write1(EEPRO100State
* s
, uint32_t addr
, uint8_t val
)
1242 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1243 memcpy(&s
->mem
[addr
], &val
, sizeof(val
));
1246 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1250 //~ eepro100_write_status(s, val);
1253 eepro100_acknowledge(s
);
1256 eepro100_write_command(s
, val
);
1260 eepro100_swi_interrupt(s
);
1262 eepro100_interrupt(s
, 0);
1265 case SCBFlow
: /* does not exist on 82557 */
1269 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1272 eepro100_write_eeprom(s
->eeprom
, val
);
1275 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1276 missing("unknown byte write");
1280 static void eepro100_write2(EEPRO100State
* s
, uint32_t addr
, uint16_t val
)
1282 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1283 memcpy(&s
->mem
[addr
], &val
, sizeof(val
));
1286 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1290 //~ eepro100_write_status(s, val);
1291 eepro100_acknowledge(s
);
1294 eepro100_write_command(s
, val
);
1295 eepro100_write1(s
, SCBIntmask
, val
>> 8);
1298 eepro100_write_eeprom(s
->eeprom
, val
);
1301 logout("addr=%s val=0x%04x\n", regname(addr
), val
);
1302 missing("unknown word write");
1306 static void eepro100_write4(EEPRO100State
* s
, uint32_t addr
, uint32_t val
)
1308 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1309 memcpy(&s
->mem
[addr
], &val
, sizeof(val
));
1314 eepro100_write_pointer(s
, val
);
1317 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1318 eepro100_write_port(s
, val
);
1321 eepro100_write_mdi(s
, val
);
1324 logout("addr=%s val=0x%08x\n", regname(addr
), val
);
1325 missing("unknown longword write");
1329 /*****************************************************************************
1333 ****************************************************************************/
1335 static uint32_t ioport_read1(void *opaque
, uint32_t addr
)
1337 EEPRO100State
*s
= opaque
;
1338 //~ logout("addr=%s\n", regname(addr));
1339 return eepro100_read1(s
, addr
- s
->region
[1]);
1342 static uint32_t ioport_read2(void *opaque
, uint32_t addr
)
1344 EEPRO100State
*s
= opaque
;
1345 return eepro100_read2(s
, addr
- s
->region
[1]);
1348 static uint32_t ioport_read4(void *opaque
, uint32_t addr
)
1350 EEPRO100State
*s
= opaque
;
1351 return eepro100_read4(s
, addr
- s
->region
[1]);
1354 static void ioport_write1(void *opaque
, uint32_t addr
, uint32_t val
)
1356 EEPRO100State
*s
= opaque
;
1357 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1358 eepro100_write1(s
, addr
- s
->region
[1], val
);
1361 static void ioport_write2(void *opaque
, uint32_t addr
, uint32_t val
)
1363 EEPRO100State
*s
= opaque
;
1364 eepro100_write2(s
, addr
- s
->region
[1], val
);
1367 static void ioport_write4(void *opaque
, uint32_t addr
, uint32_t val
)
1369 EEPRO100State
*s
= opaque
;
1370 eepro100_write4(s
, addr
- s
->region
[1], val
);
1373 /***********************************************************/
1374 /* PCI EEPRO100 definitions */
1376 static void pci_map(PCIDevice
* pci_dev
, int region_num
,
1377 uint32_t addr
, uint32_t size
, int type
)
1379 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1381 TRACE(OTHER
, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
1382 region_num
, addr
, size
, type
));
1384 assert(region_num
== 1);
1385 register_ioport_write(addr
, size
, 1, ioport_write1
, s
);
1386 register_ioport_read(addr
, size
, 1, ioport_read1
, s
);
1387 register_ioport_write(addr
, size
, 2, ioport_write2
, s
);
1388 register_ioport_read(addr
, size
, 2, ioport_read2
, s
);
1389 register_ioport_write(addr
, size
, 4, ioport_write4
, s
);
1390 register_ioport_read(addr
, size
, 4, ioport_read4
, s
);
1392 s
->region
[region_num
] = addr
;
1395 /*****************************************************************************
1397 * Memory mapped I/O.
1399 ****************************************************************************/
1401 static void pci_mmio_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1403 EEPRO100State
*s
= opaque
;
1404 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1405 eepro100_write1(s
, addr
, val
);
1408 static void pci_mmio_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1410 EEPRO100State
*s
= opaque
;
1411 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1412 eepro100_write2(s
, addr
, val
);
1415 static void pci_mmio_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1417 EEPRO100State
*s
= opaque
;
1418 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1419 eepro100_write4(s
, addr
, val
);
1422 static uint32_t pci_mmio_readb(void *opaque
, target_phys_addr_t addr
)
1424 EEPRO100State
*s
= opaque
;
1425 //~ logout("addr=%s\n", regname(addr));
1426 return eepro100_read1(s
, addr
);
1429 static uint32_t pci_mmio_readw(void *opaque
, target_phys_addr_t addr
)
1431 EEPRO100State
*s
= opaque
;
1432 //~ logout("addr=%s\n", regname(addr));
1433 return eepro100_read2(s
, addr
);
1436 static uint32_t pci_mmio_readl(void *opaque
, target_phys_addr_t addr
)
1438 EEPRO100State
*s
= opaque
;
1439 //~ logout("addr=%s\n", regname(addr));
1440 return eepro100_read4(s
, addr
);
1443 static CPUWriteMemoryFunc
* const pci_mmio_write
[] = {
1449 static CPUReadMemoryFunc
* const pci_mmio_read
[] = {
1455 static void pci_mmio_map(PCIDevice
* pci_dev
, int region_num
,
1456 uint32_t addr
, uint32_t size
, int type
)
1458 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1460 TRACE(OTHER
, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
1461 region_num
, addr
, size
, type
));
1463 if (region_num
== 0) {
1464 /* Map control / status registers. */
1465 cpu_register_physical_memory(addr
, size
, s
->mmio_index
);
1466 s
->region
[region_num
] = addr
;
1470 static int nic_can_receive(VLANClientState
*vc
)
1472 EEPRO100State
*s
= vc
->opaque
;
1473 TRACE(RXTX
, logout("%p\n", s
));
1474 return get_ru_state(s
) == ru_ready
;
1475 //~ return !eepro100_buffer_full(s);
1478 static ssize_t
nic_receive(VLANClientState
*vc
, const uint8_t * buf
, size_t size
)
1481 * - Magic packets should set bit 30 in power management driver register.
1482 * - Interesting packets should set bit 29 in power management driver register.
1484 EEPRO100State
*s
= vc
->opaque
;
1485 uint16_t rfd_status
= 0xa000;
1486 static const uint8_t broadcast_macaddr
[6] =
1487 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1489 /* TODO: check multiple IA bit. */
1490 assert(!(s
->configuration
[20] & BIT(6)));
1492 if (s
->configuration
[8] & 0x80) {
1493 /* CSMA is disabled. */
1494 logout("%p received while CSMA is disabled\n", s
);
1496 } else if (size
< 64 && (s
->configuration
[7] & 1)) {
1497 /* Short frame and configuration byte 7/0 (discard short receive) set:
1498 * Short frame is discarded */
1499 logout("%p received short frame (%d byte)\n", s
, size
);
1500 s
->statistics
.rx_short_frame_errors
++;
1502 } else if ((size
> MAX_ETH_FRAME_SIZE
+ 4) && !(s
->configuration
[18] & 8)) {
1503 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1504 * Long frames are discarded. */
1505 logout("%p received long frame (%d byte), ignored\n", s
, size
);
1507 } else if (memcmp(buf
, s
->macaddr
, 6) == 0) { // !!!
1508 /* Frame matches individual address. */
1509 /* TODO: check configuration byte 15/4 (ignore U/L). */
1510 TRACE(RXTX
, logout("%p received frame for me, len=%d\n", s
, size
));
1511 } else if (memcmp(buf
, broadcast_macaddr
, 6) == 0) {
1512 /* Broadcast frame. */
1513 TRACE(RXTX
, logout("%p received broadcast, len=%d\n", s
, size
));
1514 rfd_status
|= 0x0002;
1515 } else if (buf
[0] & 0x01) { // !!!
1516 /* Multicast frame. */
1517 TRACE(RXTX
, logout("%p received multicast, len=%d\n", s
, size
));
1518 /* TODO: check multicast all bit. */
1519 assert(!(s
->configuration
[21] & BIT(3)));
1520 int mcast_idx
= compute_mcast_idx(buf
);
1521 if (!(s
->mult
[mcast_idx
>> 3] & (1 << (mcast_idx
& 7)))) {
1524 rfd_status
|= 0x0002;
1525 } else if (s
->configuration
[15] & 1) {
1526 /* Promiscuous: receive all. */
1527 TRACE(RXTX
, logout("%p received frame in promiscuous mode, len=%d\n", s
, size
));
1528 rfd_status
|= 0x0004;
1530 TRACE(RXTX
, logout("%p received frame, ignored, len=%d,%s\n", s
, size
,
1531 nic_dump(buf
, size
)));
1535 if (get_ru_state(s
) != ru_ready
) {
1536 /* No resources available. */
1537 logout("no resources, state=%u\n", get_ru_state(s
));
1538 s
->statistics
.rx_resource_errors
++;
1539 //~ assert(!"no resources");
1543 //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
1545 cpu_physical_memory_read(s
->ru_base
+ s
->ru_offset
, (uint8_t *) & rx
,
1546 offsetof(eepro100_rx_t
, packet
));
1547 uint16_t rfd_command
= le16_to_cpu(rx
.command
);
1548 uint16_t rfd_size
= le16_to_cpu(rx
.size
);
1549 assert(size
<= rfd_size
);
1551 rfd_status
|= 0x0080;
1553 TRACE(OTHER
, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1554 rfd_command
, rx
.link
, rx
.rx_buf_addr
, rfd_size
));
1555 stw_phys(s
->ru_base
+ s
->ru_offset
+ offsetof(eepro100_rx_t
, status
),
1557 stw_phys(s
->ru_base
+ s
->ru_offset
+ offsetof(eepro100_rx_t
, count
), size
);
1558 /* Early receive interrupt not supported. */
1559 //~ eepro100_er_interrupt(s);
1560 /* Receive CRC Transfer not supported. */
1561 assert(!(s
->configuration
[18] & 4));
1562 /* TODO: check stripping enable bit. */
1563 //~ assert(!(s->configuration[17] & 1));
1564 cpu_physical_memory_write(s
->ru_base
+ s
->ru_offset
+
1565 offsetof(eepro100_rx_t
, packet
), buf
, size
);
1566 s
->statistics
.rx_good_frames
++;
1567 eepro100_fr_interrupt(s
);
1568 s
->ru_offset
= le32_to_cpu(rx
.link
);
1569 if (rfd_command
& 0x8000) {
1570 /* EL bit is set, so this was the last frame. */
1573 if (rfd_command
& 0x4000) {
1575 set_ru_state(s
, ru_suspended
);
1580 static int nic_load(QEMUFile
* f
, void *opaque
, int version_id
)
1582 EEPRO100State
*s
= opaque
;
1589 if (version_id
>= 3) {
1590 ret
= pci_device_load(&s
->dev
, f
);
1595 if (version_id
>= 2) {
1596 qemu_get_8s(f
, &s
->rxcr
);
1601 qemu_get_8s(f
, &s
->cmd
);
1602 qemu_get_be32s(f
, &s
->start
);
1603 qemu_get_be32s(f
, &s
->stop
);
1604 qemu_get_8s(f
, &s
->boundary
);
1605 qemu_get_8s(f
, &s
->tsr
);
1606 qemu_get_8s(f
, &s
->tpsr
);
1607 qemu_get_be16s(f
, &s
->tcnt
);
1608 qemu_get_be16s(f
, &s
->rcnt
);
1609 qemu_get_be32s(f
, &s
->rsar
);
1610 qemu_get_8s(f
, &s
->rsr
);
1611 qemu_get_8s(f
, &s
->isr
);
1612 qemu_get_8s(f
, &s
->dcfg
);
1613 qemu_get_8s(f
, &s
->imr
);
1614 qemu_get_buffer(f
, s
->phys
, 6);
1615 qemu_get_8s(f
, &s
->curpag
);
1616 qemu_get_buffer(f
, s
->mult
, 8);
1617 qemu_get_buffer(f
, s
->mem
, sizeof(s
->mem
));
1619 /* Restore all members of struct between scv_stat and mem. */
1620 qemu_get_8s(f
, &s
->scb_stat
);
1621 qemu_get_8s(f
, &s
->int_stat
);
1622 for (i
= 0; i
< 3; i
++) {
1623 qemu_get_be32s(f
, &s
->region
[i
]);
1625 qemu_get_buffer(f
, s
->macaddr
, 6);
1626 for (i
= 0; i
< 19; i
++) {
1627 qemu_get_be32s(f
, &s
->statcounter
[i
]);
1629 for (i
= 0; i
< 32; i
++) {
1630 qemu_get_be16s(f
, &s
->mdimem
[i
]);
1632 /* The eeprom should be saved and restored by its own routines. */
1633 qemu_get_be32s(f
, &s
->device
);
1634 qemu_get_be32s(f
, &s
->pointer
);
1635 qemu_get_be32s(f
, &s
->cu_base
);
1636 qemu_get_be32s(f
, &s
->cu_offset
);
1637 qemu_get_be32s(f
, &s
->ru_base
);
1638 qemu_get_be32s(f
, &s
->ru_offset
);
1639 qemu_get_be32s(f
, &s
->statsaddr
);
1640 /* Restore epro100_stats_t statistics. */
1641 qemu_get_be32s(f
, &s
->statistics
.tx_good_frames
);
1642 qemu_get_be32s(f
, &s
->statistics
.tx_max_collisions
);
1643 qemu_get_be32s(f
, &s
->statistics
.tx_late_collisions
);
1644 qemu_get_be32s(f
, &s
->statistics
.tx_underruns
);
1645 qemu_get_be32s(f
, &s
->statistics
.tx_lost_crs
);
1646 qemu_get_be32s(f
, &s
->statistics
.tx_deferred
);
1647 qemu_get_be32s(f
, &s
->statistics
.tx_single_collisions
);
1648 qemu_get_be32s(f
, &s
->statistics
.tx_multiple_collisions
);
1649 qemu_get_be32s(f
, &s
->statistics
.tx_total_collisions
);
1650 qemu_get_be32s(f
, &s
->statistics
.rx_good_frames
);
1651 qemu_get_be32s(f
, &s
->statistics
.rx_crc_errors
);
1652 qemu_get_be32s(f
, &s
->statistics
.rx_alignment_errors
);
1653 qemu_get_be32s(f
, &s
->statistics
.rx_resource_errors
);
1654 qemu_get_be32s(f
, &s
->statistics
.rx_overrun_errors
);
1655 qemu_get_be32s(f
, &s
->statistics
.rx_cdt_errors
);
1656 qemu_get_be32s(f
, &s
->statistics
.rx_short_frame_errors
);
1657 qemu_get_be32s(f
, &s
->statistics
.fc_xmt_pause
);
1658 qemu_get_be32s(f
, &s
->statistics
.fc_rcv_pause
);
1659 qemu_get_be32s(f
, &s
->statistics
.fc_rcv_unsupported
);
1660 qemu_get_be16s(f
, &s
->statistics
.xmt_tco_frames
);
1661 qemu_get_be16s(f
, &s
->statistics
.rcv_tco_frames
);
1662 qemu_get_be32s(f
, &s
->statistics
.complete
);
1664 qemu_get_be16s(f
, &s
->status
);
1667 /* Configuration bytes. */
1668 qemu_get_buffer(f
, s
->configuration
, sizeof(s
->configuration
));
1673 static void nic_save(QEMUFile
* f
, void *opaque
)
1675 EEPRO100State
*s
= opaque
;
1678 pci_device_save(&s
->dev
, f
);
1680 qemu_put_8s(f
, &s
->rxcr
);
1682 qemu_put_8s(f
, &s
->cmd
);
1683 qemu_put_be32s(f
, &s
->start
);
1684 qemu_put_be32s(f
, &s
->stop
);
1685 qemu_put_8s(f
, &s
->boundary
);
1686 qemu_put_8s(f
, &s
->tsr
);
1687 qemu_put_8s(f
, &s
->tpsr
);
1688 qemu_put_be16s(f
, &s
->tcnt
);
1689 qemu_put_be16s(f
, &s
->rcnt
);
1690 qemu_put_be32s(f
, &s
->rsar
);
1691 qemu_put_8s(f
, &s
->rsr
);
1692 qemu_put_8s(f
, &s
->isr
);
1693 qemu_put_8s(f
, &s
->dcfg
);
1694 qemu_put_8s(f
, &s
->imr
);
1695 qemu_put_buffer(f
, s
->phys
, 6);
1696 qemu_put_8s(f
, &s
->curpag
);
1697 qemu_put_buffer(f
, s
->mult
, 8);
1698 qemu_put_buffer(f
, s
->mem
, sizeof(s
->mem
));
1700 /* Save all members of struct between scv_stat and mem. */
1701 qemu_put_8s(f
, &s
->scb_stat
);
1702 qemu_put_8s(f
, &s
->int_stat
);
1703 for (i
= 0; i
< 3; i
++) {
1704 qemu_put_be32s(f
, &s
->region
[i
]);
1706 qemu_put_buffer(f
, s
->macaddr
, 6);
1707 for (i
= 0; i
< 19; i
++) {
1708 qemu_put_be32s(f
, &s
->statcounter
[i
]);
1710 for (i
= 0; i
< 32; i
++) {
1711 qemu_put_be16s(f
, &s
->mdimem
[i
]);
1713 /* The eeprom should be saved and restored by its own routines. */
1714 qemu_put_be32s(f
, &s
->device
);
1715 qemu_put_be32s(f
, &s
->pointer
);
1716 qemu_put_be32s(f
, &s
->cu_base
);
1717 qemu_put_be32s(f
, &s
->cu_offset
);
1718 qemu_put_be32s(f
, &s
->ru_base
);
1719 qemu_put_be32s(f
, &s
->ru_offset
);
1720 qemu_put_be32s(f
, &s
->statsaddr
);
1721 /* Save epro100_stats_t statistics. */
1722 qemu_put_be32s(f
, &s
->statistics
.tx_good_frames
);
1723 qemu_put_be32s(f
, &s
->statistics
.tx_max_collisions
);
1724 qemu_put_be32s(f
, &s
->statistics
.tx_late_collisions
);
1725 qemu_put_be32s(f
, &s
->statistics
.tx_underruns
);
1726 qemu_put_be32s(f
, &s
->statistics
.tx_lost_crs
);
1727 qemu_put_be32s(f
, &s
->statistics
.tx_deferred
);
1728 qemu_put_be32s(f
, &s
->statistics
.tx_single_collisions
);
1729 qemu_put_be32s(f
, &s
->statistics
.tx_multiple_collisions
);
1730 qemu_put_be32s(f
, &s
->statistics
.tx_total_collisions
);
1731 qemu_put_be32s(f
, &s
->statistics
.rx_good_frames
);
1732 qemu_put_be32s(f
, &s
->statistics
.rx_crc_errors
);
1733 qemu_put_be32s(f
, &s
->statistics
.rx_alignment_errors
);
1734 qemu_put_be32s(f
, &s
->statistics
.rx_resource_errors
);
1735 qemu_put_be32s(f
, &s
->statistics
.rx_overrun_errors
);
1736 qemu_put_be32s(f
, &s
->statistics
.rx_cdt_errors
);
1737 qemu_put_be32s(f
, &s
->statistics
.rx_short_frame_errors
);
1738 qemu_put_be32s(f
, &s
->statistics
.fc_xmt_pause
);
1739 qemu_put_be32s(f
, &s
->statistics
.fc_rcv_pause
);
1740 qemu_put_be32s(f
, &s
->statistics
.fc_rcv_unsupported
);
1741 qemu_put_be16s(f
, &s
->statistics
.xmt_tco_frames
);
1742 qemu_put_be16s(f
, &s
->statistics
.rcv_tco_frames
);
1743 qemu_put_be32s(f
, &s
->statistics
.complete
);
1745 qemu_put_be16s(f
, &s
->status
);
1748 /* Configuration bytes. */
1749 qemu_put_buffer(f
, s
->configuration
, sizeof(s
->configuration
));
1752 static void nic_cleanup(VLANClientState
*vc
)
1754 EEPRO100State
*s
= vc
->opaque
;
1756 unregister_savevm(vc
->model
, s
);
1758 eeprom93xx_free(s
->eeprom
);
1761 static int pci_nic_uninit(PCIDevice
*dev
)
1763 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, dev
);
1765 cpu_unregister_io_memory(s
->mmio_index
);
1770 static int nic_init(PCIDevice
*pci_dev
, uint32_t device
)
1772 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1774 TRACE(OTHER
, logout("\n"));
1776 s
->dev
.unregister
= pci_nic_uninit
;
1782 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1783 * i82559 and later support 64 or 256 word EEPROM. */
1784 s
->eeprom
= eeprom93xx_new(EEPROM_SIZE
);
1786 /* Handler for memory-mapped I/O */
1788 cpu_register_io_memory(pci_mmio_read
, pci_mmio_write
, s
);
1790 pci_register_bar(&s
->dev
, 0, PCI_MEM_SIZE
,
1791 PCI_ADDRESS_SPACE_MEM
|
1792 PCI_ADDRESS_SPACE_MEM_PREFETCH
, pci_mmio_map
);
1793 pci_register_bar(&s
->dev
, 1, PCI_IO_SIZE
, PCI_ADDRESS_SPACE_IO
,
1795 pci_register_bar(&s
->dev
, 2, PCI_FLASH_SIZE
, PCI_ADDRESS_SPACE_MEM
,
1798 qdev_get_macaddr(&s
->dev
.qdev
, s
->macaddr
);
1799 logout("macaddr: %s\n", nic_dump(&s
->macaddr
[0], 6));
1800 assert(s
->region
[1] == 0);
1804 s
->vc
= qdev_get_vlan_client(&s
->dev
.qdev
,
1805 nic_can_receive
, nic_receive
, NULL
,
1808 qemu_format_nic_info_str(s
->vc
, s
->macaddr
);
1809 TRACE(OTHER
, logout("%s\n", s
->vc
->info_str
));
1811 qemu_register_reset(nic_reset
, s
);
1813 register_savevm(s
->vc
->model
, -1, 3, nic_save
, nic_load
, s
);
1817 static int pci_i82551_init(PCIDevice
*dev
)
1819 return nic_init(dev
, i82551
);
1822 static int pci_i82557b_init(PCIDevice
*dev
)
1824 return nic_init(dev
, i82557B
);
1827 static int pci_i82559er_init(PCIDevice
*dev
)
1829 return nic_init(dev
, i82559ER
);
1832 static PCIDeviceInfo eepro100_info
[] = {
1834 .qdev
.name
= "i82551",
1835 .qdev
.size
= sizeof(EEPRO100State
),
1836 .init
= pci_i82551_init
,
1838 .qdev
.name
= "i82557b",
1839 .qdev
.size
= sizeof(EEPRO100State
),
1840 .init
= pci_i82557b_init
,
1842 .qdev
.name
= "i82559er",
1843 .qdev
.size
= sizeof(EEPRO100State
),
1844 .init
= pci_i82559er_init
,
1850 static void eepro100_register_devices(void)
1852 pci_qdev_register_many(eepro100_info
);
1855 device_init(eepro100_register_devices
)