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eepro100: Fix initial value for PCI_STATUS
[mirror_qemu.git] / hw / eepro100.c
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (c) 2006-2007 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559):
23 * PXE boot (i386) no valid link
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * non-i386 platforms
28 * Windows networking
29 *
30 * References:
31 *
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
34 */
35
36 #if defined(TARGET_I386)
37 # warning "PXE boot still not working!"
38 #endif
39
40 #include <stddef.h> /* offsetof */
41 #include <stdbool.h>
42 #include "hw.h"
43 #include "loader.h" /* rom_add_option */
44 #include "pci.h"
45 #include "net.h"
46 #include "eeprom93xx.h"
47
48 /* Common declarations for all PCI devices. */
49
50 #define PCI_CONFIG_8(offset, value) \
51 (pci_conf[offset] = (value))
52 #define PCI_CONFIG_16(offset, value) \
53 (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
54 #define PCI_CONFIG_32(offset, value) \
55 (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
56
57 #define KiB 1024
58
59 /* Debug EEPRO100 card. */
60 //~ #define DEBUG_EEPRO100
61
62 #ifdef DEBUG_EEPRO100
63 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
64 #else
65 #define logout(fmt, ...) ((void)0)
66 #endif
67
68 /* Set flags to 0 to disable debug output. */
69 #define INT 1 /* interrupt related actions */
70 #define MDI 1 /* mdi related actions */
71 #define OTHER 1
72 #define RXTX 1
73 #define EEPROM 1 /* eeprom related actions */
74
75 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
76
77 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
78
79 #define MAX_ETH_FRAME_SIZE 1514
80
81 /* This driver supports several different devices which are declared here. */
82 #define i82550 0x82550
83 #define i82551 0x82551
84 #define i82557A 0x82557a
85 #define i82557B 0x82557b
86 #define i82557C 0x82557c
87 #define i82558A 0x82558a
88 #define i82558B 0x82558b
89 #define i82559A 0x82559a
90 #define i82559B 0x82559b
91 #define i82559C 0x82559c
92 #define i82559ER 0x82559e
93 #define i82562 0x82562
94
95 /* Use 64 word EEPROM. TODO: could be a runtime option. */
96 #define EEPROM_SIZE 64
97
98 #define PCI_MEM_SIZE (4 * KiB)
99 #define PCI_IO_SIZE 64
100 #define PCI_FLASH_SIZE (128 * KiB)
101
102 #define BIT(n) (1 << (n))
103 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
104
105 /* The SCB accepts the following controls for the Tx and Rx units: */
106 #define CU_NOP 0x0000 /* No operation. */
107 #define CU_START 0x0010 /* CU start. */
108 #define CU_RESUME 0x0020 /* CU resume. */
109 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
110 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
111 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
112 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
113 #define CU_SRESUME 0x00a0 /* CU static resume. */
114
115 #define RU_NOP 0x0000
116 #define RX_START 0x0001
117 #define RX_RESUME 0x0002
118 #define RX_ABORT 0x0004
119 #define RX_ADDR_LOAD 0x0006
120 #define RX_RESUMENR 0x0007
121 #define INT_MASK 0x0100
122 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
123
124 /* Offsets to the various registers.
125 All accesses need not be longword aligned. */
126 enum speedo_offsets {
127 SCBStatus = 0,
128 SCBAck = 1,
129 SCBCmd = 2, /* Rx/Command Unit command and status. */
130 SCBIntmask = 3,
131 SCBPointer = 4, /* General purpose pointer. */
132 SCBPort = 8, /* Misc. commands and operands. */
133 SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */
134 SCBCtrlMDI = 16, /* MDI interface control. */
135 SCBEarlyRx = 20, /* Early receive byte count. */
136 SCBFlow = 24,
137 };
138
139 /* A speedo3 transmit buffer descriptor with two buffers... */
140 typedef struct {
141 uint16_t status;
142 uint16_t command;
143 uint32_t link; /* void * */
144 uint32_t tx_desc_addr; /* transmit buffer decsriptor array address. */
145 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
146 uint8_t tx_threshold; /* transmit threshold */
147 uint8_t tbd_count; /* TBD number */
148 //~ /* This constitutes two "TBD" entries: hdr and data */
149 //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
150 //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
151 //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
152 //~ int32_t tx_buf_size1; /* Length of Tx data. */
153 } eepro100_tx_t;
154
155 /* Receive frame descriptor. */
156 typedef struct {
157 int16_t status;
158 uint16_t command;
159 uint32_t link; /* struct RxFD * */
160 uint32_t rx_buf_addr; /* void * */
161 uint16_t count;
162 uint16_t size;
163 char packet[MAX_ETH_FRAME_SIZE + 4];
164 } eepro100_rx_t;
165
166 typedef struct {
167 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
168 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
169 tx_multiple_collisions, tx_total_collisions;
170 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
171 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
172 rx_short_frame_errors;
173 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
174 uint16_t xmt_tco_frames, rcv_tco_frames;
175 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
176 uint32_t reserved[4];
177 } eepro100_stats_t;
178
179 typedef enum {
180 cu_idle = 0,
181 cu_suspended = 1,
182 cu_active = 2,
183 cu_lpq_active = 2,
184 cu_hqp_active = 3
185 } cu_state_t;
186
187 typedef enum {
188 ru_idle = 0,
189 ru_suspended = 1,
190 ru_no_resources = 2,
191 ru_ready = 4
192 } ru_state_t;
193
194 typedef struct {
195 PCIDevice dev;
196 uint8_t mult[8]; /* multicast mask array */
197 int mmio_index;
198 NICState *nic;
199 NICConf conf;
200 uint8_t scb_stat; /* SCB stat/ack byte */
201 uint8_t int_stat; /* PCI interrupt status */
202 /* region must not be saved by nic_save. */
203 uint32_t region[3]; /* PCI region addresses */
204 uint16_t mdimem[32];
205 eeprom_t *eeprom;
206 uint32_t device; /* device variant */
207 uint32_t pointer;
208 /* (cu_base + cu_offset) address the next command block in the command block list. */
209 uint32_t cu_base; /* CU base address */
210 uint32_t cu_offset; /* CU address offset */
211 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
212 uint32_t ru_base; /* RU base address */
213 uint32_t ru_offset; /* RU address offset */
214 uint32_t statsaddr; /* pointer to eepro100_stats_t */
215
216 /* Statistical counters. Also used for wake-up packet (i82559). */
217 eepro100_stats_t statistics;
218
219 #if 0
220 uint16_t status;
221 #endif
222
223 /* Configuration bytes. */
224 uint8_t configuration[22];
225
226 /* Data in mem is always in the byte order of the controller (le). */
227 uint8_t mem[PCI_MEM_SIZE];
228 /* vmstate for each particular nic */
229 VMStateDescription *vmstate;
230
231 /* Quasi static device properties (no need to save them). */
232 uint16_t stats_size;
233 bool has_extended_tcb_support;
234 } EEPRO100State;
235
236 /* Default values for MDI (PHY) registers */
237 static const uint16_t eepro100_mdi_default[] = {
238 /* MDI Registers 0 - 6, 7 */
239 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
240 /* MDI Registers 8 - 15 */
241 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
242 /* MDI Registers 16 - 31 */
243 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
244 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
245 };
246
247 /* Readonly mask for MDI (PHY) registers */
248 static const uint16_t eepro100_mdi_mask[] = {
249 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
250 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
251 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
252 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
253 };
254
255 /* XXX: optimize */
256 static void stl_le_phys(target_phys_addr_t addr, uint32_t val)
257 {
258 val = cpu_to_le32(val);
259 cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val));
260 }
261
262 #define POLYNOMIAL 0x04c11db6
263
264 /* From FreeBSD */
265 /* XXX: optimize */
266 static int compute_mcast_idx(const uint8_t * ep)
267 {
268 uint32_t crc;
269 int carry, i, j;
270 uint8_t b;
271
272 crc = 0xffffffff;
273 for (i = 0; i < 6; i++) {
274 b = *ep++;
275 for (j = 0; j < 8; j++) {
276 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
277 crc <<= 1;
278 b >>= 1;
279 if (carry) {
280 crc = ((crc ^ POLYNOMIAL) | carry);
281 }
282 }
283 }
284 return (crc >> 26);
285 }
286
287 #if defined(DEBUG_EEPRO100)
288 static const char *nic_dump(const uint8_t * buf, unsigned size)
289 {
290 static char dump[3 * 16 + 1];
291 char *p = &dump[0];
292 if (size > 16) {
293 size = 16;
294 }
295 while (size-- > 0) {
296 p += sprintf(p, " %02x", *buf++);
297 }
298 return dump;
299 }
300 #endif /* DEBUG_EEPRO100 */
301
302 enum scb_stat_ack {
303 stat_ack_not_ours = 0x00,
304 stat_ack_sw_gen = 0x04,
305 stat_ack_rnr = 0x10,
306 stat_ack_cu_idle = 0x20,
307 stat_ack_frame_rx = 0x40,
308 stat_ack_cu_cmd_done = 0x80,
309 stat_ack_not_present = 0xFF,
310 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
311 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
312 };
313
314 static void disable_interrupt(EEPRO100State * s)
315 {
316 if (s->int_stat) {
317 TRACE(INT, logout("interrupt disabled\n"));
318 qemu_irq_lower(s->dev.irq[0]);
319 s->int_stat = 0;
320 }
321 }
322
323 static void enable_interrupt(EEPRO100State * s)
324 {
325 if (!s->int_stat) {
326 TRACE(INT, logout("interrupt enabled\n"));
327 qemu_irq_raise(s->dev.irq[0]);
328 s->int_stat = 1;
329 }
330 }
331
332 static void eepro100_acknowledge(EEPRO100State * s)
333 {
334 s->scb_stat &= ~s->mem[SCBAck];
335 s->mem[SCBAck] = s->scb_stat;
336 if (s->scb_stat == 0) {
337 disable_interrupt(s);
338 }
339 }
340
341 static void eepro100_interrupt(EEPRO100State * s, uint8_t stat)
342 {
343 uint8_t mask = ~s->mem[SCBIntmask];
344 s->mem[SCBAck] |= stat;
345 stat = s->scb_stat = s->mem[SCBAck];
346 stat &= (mask | 0x0f);
347 //~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
348 if (stat && (mask & 0x01)) {
349 /* SCB mask and SCB Bit M do not disable interrupt. */
350 enable_interrupt(s);
351 } else if (s->int_stat) {
352 disable_interrupt(s);
353 }
354 }
355
356 static void eepro100_cx_interrupt(EEPRO100State * s)
357 {
358 /* CU completed action command. */
359 /* Transmit not ok (82557 only, not in emulation). */
360 eepro100_interrupt(s, 0x80);
361 }
362
363 static void eepro100_cna_interrupt(EEPRO100State * s)
364 {
365 /* CU left the active state. */
366 eepro100_interrupt(s, 0x20);
367 }
368
369 static void eepro100_fr_interrupt(EEPRO100State * s)
370 {
371 /* RU received a complete frame. */
372 eepro100_interrupt(s, 0x40);
373 }
374
375 #if 0
376 static void eepro100_rnr_interrupt(EEPRO100State * s)
377 {
378 /* RU is not ready. */
379 eepro100_interrupt(s, 0x10);
380 }
381 #endif
382
383 static void eepro100_mdi_interrupt(EEPRO100State * s)
384 {
385 /* MDI completed read or write cycle. */
386 eepro100_interrupt(s, 0x08);
387 }
388
389 static void eepro100_swi_interrupt(EEPRO100State * s)
390 {
391 /* Software has requested an interrupt. */
392 eepro100_interrupt(s, 0x04);
393 }
394
395 #if 0
396 static void eepro100_fcp_interrupt(EEPRO100State * s)
397 {
398 /* Flow control pause interrupt (82558 and later). */
399 eepro100_interrupt(s, 0x01);
400 }
401 #endif
402
403 static void pci_reset(EEPRO100State * s)
404 {
405 uint32_t device = s->device;
406 uint8_t *pci_conf = s->dev.config;
407 bool power_management = 1;
408
409 TRACE(OTHER, logout("%p\n", s));
410
411 /* PCI Vendor ID */
412 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
413 /* PCI Device ID depends on device and is set below. */
414 /* PCI Command */
415 /* TODO: this is the default, do not override. */
416 PCI_CONFIG_16(PCI_COMMAND, 0x0000);
417 /* PCI Status */
418 /* TODO: Value at RST# should be 0. */
419 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK);
420 /* PCI Revision ID */
421 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
422 /* TODO: this is the default, do not override. */
423 /* PCI Class Code */
424 PCI_CONFIG_8(PCI_CLASS_PROG, 0x00);
425 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
426 /* PCI Cache Line Size */
427 /* check cache line size!!! */
428 //~ PCI_CONFIG_8(0x0c, 0x00);
429 /* PCI Latency Timer */
430 PCI_CONFIG_8(PCI_LATENCY_TIMER, 0x20); // latency timer = 32 clocks
431 /* PCI Header Type */
432 /* BIST (built-in self test) */
433 #if defined(TARGET_I386)
434 // !!! workaround for buggy bios
435 //~ #define PCI_BASE_ADDRESS_MEM_PREFETCH 0
436 #endif
437 #if 0
438 /* PCI Base Address Registers */
439 /* CSR Memory Mapped Base Address */
440 PCI_CONFIG_32(PCI_BASE_ADDRESS_0,
441 PCI_BASE_ADDRESS_SPACE_MEMORY |
442 PCI_BASE_ADDRESS_MEM_PREFETCH);
443 /* CSR I/O Mapped Base Address */
444 PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_SPACE_IO);
445 #if 0
446 /* Flash Memory Mapped Base Address */
447 PCI_CONFIG_32(PCI_BASE_ADDRESS_2,
448 0xfffe0000 | PCI_BASE_ADDRESS_SPACE_MEMORY);
449 #endif
450 #endif
451 /* Expansion ROM Base Address (depends on boot disable!!!) */
452 /* TODO: not needed, set when BAR is registered */
453 PCI_CONFIG_32(PCI_ROM_ADDRESS, PCI_BASE_ADDRESS_SPACE_MEMORY);
454 /* Capability Pointer */
455 /* TODO: revisions with power_management 1 use this but
456 * do not set new capability list bit in status register. */
457 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0xdc);
458 /* Interrupt Line */
459 /* Interrupt Pin */
460 /* TODO: RST# value should be 0 */
461 PCI_CONFIG_8(PCI_INTERRUPT_PIN, 1); // interrupt pin 0
462 /* Minimum Grant */
463 PCI_CONFIG_8(PCI_MIN_GNT, 0x08);
464 /* Maximum Latency */
465 PCI_CONFIG_8(PCI_MAX_LAT, 0x18);
466
467 switch (device) {
468 case i82550:
469 // TODO: check device id.
470 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
471 /* Revision ID: 0x0c, 0x0d, 0x0e. */
472 PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
473 // TODO: check size of statistical counters.
474 s->stats_size = 80;
475 // TODO: check extended tcb support.
476 s->has_extended_tcb_support = 1;
477 break;
478 case i82551:
479 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
480 /* Revision ID: 0x0f, 0x10. */
481 PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
482 // TODO: check size of statistical counters.
483 s->stats_size = 80;
484 s->has_extended_tcb_support = 1;
485 break;
486 case i82557A:
487 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
488 PCI_CONFIG_8(PCI_REVISION_ID, 0x01);
489 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
490 power_management = 0;
491 break;
492 case i82557B:
493 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
494 PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
495 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
496 power_management = 0;
497 break;
498 case i82557C:
499 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
500 PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
501 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
502 power_management = 0;
503 break;
504 case i82558A:
505 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
506 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
507 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
508 PCI_CONFIG_8(PCI_REVISION_ID, 0x04);
509 s->stats_size = 76;
510 s->has_extended_tcb_support = 1;
511 break;
512 case i82558B:
513 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
514 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
515 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
516 PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
517 s->stats_size = 76;
518 s->has_extended_tcb_support = 1;
519 break;
520 case i82559A:
521 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
522 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
523 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
524 PCI_CONFIG_8(PCI_REVISION_ID, 0x06);
525 s->stats_size = 80;
526 s->has_extended_tcb_support = 1;
527 break;
528 case i82559B:
529 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
530 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
531 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
532 PCI_CONFIG_8(PCI_REVISION_ID, 0x07);
533 s->stats_size = 80;
534 s->has_extended_tcb_support = 1;
535 break;
536 case i82559C:
537 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
538 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
539 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
540 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
541 // TODO: Windows wants revision id 0x0c.
542 PCI_CONFIG_8(PCI_REVISION_ID, 0x0c);
543 #if EEPROM_SIZE > 0
544 PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID, 0x8086);
545 PCI_CONFIG_16(PCI_SUBSYSTEM_ID, 0x0040);
546 #endif
547 s->stats_size = 80;
548 s->has_extended_tcb_support = 1;
549 break;
550 case i82559ER:
551 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
552 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
553 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
554 PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
555 s->stats_size = 80;
556 s->has_extended_tcb_support = 1;
557 break;
558 case i82562:
559 // TODO: check device id.
560 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
561 /* TODO: wrong revision id. */
562 PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
563 s->stats_size = 80;
564 s->has_extended_tcb_support = 1;
565 break;
566 default:
567 logout("Device %X is undefined!\n", device);
568 }
569
570 s->configuration[6] |= BIT(5);
571
572 if (s->stats_size == 80) {
573 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
574 if (s->configuration[6] & BIT(2)) {
575 /* TCO statistical counters. */
576 assert(s->configuration[6] & BIT(5));
577 } else {
578 if (s->configuration[6] & BIT(5)) {
579 /* No extended statistical counters, i82557 compatible. */
580 s->stats_size = 64;
581 } else {
582 /* i82558 compatible. */
583 s->stats_size = 76;
584 }
585 }
586 } else {
587 if (s->configuration[6] & BIT(5)) {
588 /* No extended statistical counters. */
589 s->stats_size = 64;
590 }
591 }
592 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
593
594 if (power_management) {
595 /* Power Management Capabilities */
596 PCI_CONFIG_8(0xdc, 0x01);
597 /* Next Item Pointer */
598 /* Capability ID */
599 PCI_CONFIG_16(0xde, 0x7e21);
600 /* TODO: Power Management Control / Status. */
601 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
602 }
603
604 #if EEPROM_SIZE > 0
605 if (device == i82557C || device == i82558B || device == i82559C) {
606 // TODO: get vendor id from EEPROM for i82557C or later.
607 // TODO: get device id from EEPROM for i82557C or later.
608 // TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
609 // TODO: header type is determined by EEPROM for i82559.
610 // TODO: get subsystem id from EEPROM for i82557C or later.
611 // TODO: get subsystem vendor id from EEPROM for i82557C or later.
612 // TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
613 // TODO: capability pointer depends on EEPROM for i82558.
614 logout("Get device id and revision from EEPROM!!!\n");
615 }
616 #endif /* EEPROM_SIZE > 0 */
617 }
618
619 static void nic_selective_reset(EEPRO100State * s)
620 {
621 size_t i;
622 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
623 //~ eeprom93xx_reset(s->eeprom);
624 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
625 eeprom_contents[0xa] = 0x4000;
626 if (s->device == i82557B || s->device == i82557C)
627 eeprom_contents[5] = 0x0100;
628 uint16_t sum = 0;
629 for (i = 0; i < EEPROM_SIZE - 1; i++) {
630 sum += eeprom_contents[i];
631 }
632 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
633 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
634
635 memset(s->mem, 0, sizeof(s->mem));
636 uint32_t val = BIT(21);
637 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
638
639 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
640 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
641 }
642
643 static void nic_reset(void *opaque)
644 {
645 EEPRO100State *s = opaque;
646 TRACE(OTHER, logout("%p\n", s));
647 nic_selective_reset(s);
648 }
649
650 #if defined(DEBUG_EEPRO100)
651 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
652 "Command/Status",
653 "General Pointer",
654 "Port",
655 "EEPROM/Flash Control",
656 "MDI Control",
657 "Receive DMA Byte Count",
658 "Flow Control",
659 "General Status/Control"
660 };
661
662 static char *regname(uint32_t addr)
663 {
664 static char buf[32];
665 if (addr < PCI_IO_SIZE) {
666 const char *r = e100_reg[addr / 4];
667 if (r != 0) {
668 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
669 } else {
670 snprintf(buf, sizeof(buf), "0x%02x", addr);
671 }
672 } else {
673 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
674 }
675 return buf;
676 }
677 #endif /* DEBUG_EEPRO100 */
678
679 #if 0
680 static uint16_t eepro100_read_status(EEPRO100State * s)
681 {
682 uint16_t val = s->status;
683 TRACE(OTHER, logout("val=0x%04x\n", val));
684 return val;
685 }
686
687 static void eepro100_write_status(EEPRO100State * s, uint16_t val)
688 {
689 TRACE(OTHER, logout("val=0x%04x\n", val));
690 s->status = val;
691 }
692 #endif
693
694 /*****************************************************************************
695 *
696 * Command emulation.
697 *
698 ****************************************************************************/
699
700 #if 0
701 static uint16_t eepro100_read_command(EEPRO100State * s)
702 {
703 uint16_t val = 0xffff;
704 //~ TRACE(OTHER, logout("val=0x%04x\n", val));
705 return val;
706 }
707 #endif
708
709 /* Commands that can be put in a command list entry. */
710 enum commands {
711 CmdNOp = 0,
712 CmdIASetup = 1,
713 CmdConfigure = 2,
714 CmdMulticastList = 3,
715 CmdTx = 4,
716 CmdTDR = 5, /* load microcode */
717 CmdDump = 6,
718 CmdDiagnose = 7,
719
720 /* And some extra flags: */
721 CmdSuspend = 0x4000, /* Suspend after completion. */
722 CmdIntr = 0x2000, /* Interrupt after completion. */
723 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
724 };
725
726 static cu_state_t get_cu_state(EEPRO100State * s)
727 {
728 return ((s->mem[SCBStatus] >> 6) & 0x03);
729 }
730
731 static void set_cu_state(EEPRO100State * s, cu_state_t state)
732 {
733 s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6);
734 }
735
736 static ru_state_t get_ru_state(EEPRO100State * s)
737 {
738 return ((s->mem[SCBStatus] >> 2) & 0x0f);
739 }
740
741 static void set_ru_state(EEPRO100State * s, ru_state_t state)
742 {
743 s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2);
744 }
745
746 static void dump_statistics(EEPRO100State * s)
747 {
748 /* Dump statistical data. Most data is never changed by the emulation
749 * and always 0, so we first just copy the whole block and then those
750 * values which really matter.
751 * Number of data should check configuration!!!
752 */
753 cpu_physical_memory_write(s->statsaddr,
754 (uint8_t *) & s->statistics, s->stats_size);
755 stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
756 stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
757 stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
758 stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
759 //~ stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
760 //~ stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
761 //~ missing("CU dump statistical counters");
762 }
763
764 static void action_command(EEPRO100State *s)
765 {
766 for (;;) {
767 uint32_t cb_address = s->cu_base + s->cu_offset;
768 eepro100_tx_t tx;
769 cpu_physical_memory_read(cb_address, (uint8_t *) & tx, sizeof(tx));
770 uint16_t status = le16_to_cpu(tx.status);
771 uint16_t command = le16_to_cpu(tx.command);
772 logout
773 ("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
774 val, status, command, tx.link);
775 bool bit_el = ((command & 0x8000) != 0);
776 bool bit_s = ((command & 0x4000) != 0);
777 bool bit_i = ((command & 0x2000) != 0);
778 bool bit_nc = ((command & 0x0010) != 0);
779 bool success = true;
780 //~ bool bit_sf = ((command & 0x0008) != 0);
781 uint16_t cmd = command & 0x0007;
782 s->cu_offset = le32_to_cpu(tx.link);
783 switch (cmd) {
784 case CmdNOp:
785 /* Do nothing. */
786 break;
787 case CmdIASetup:
788 cpu_physical_memory_read(cb_address + 8, &s->conf.macaddr.a[0], 6);
789 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6)));
790 break;
791 case CmdConfigure:
792 cpu_physical_memory_read(cb_address + 8, &s->configuration[0],
793 sizeof(s->configuration));
794 TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)));
795 break;
796 case CmdMulticastList:
797 //~ missing("multicast list");
798 break;
799 case CmdTx:
800 (void)0;
801 uint32_t tbd_array = le32_to_cpu(tx.tx_desc_addr);
802 uint16_t tcb_bytes = (le16_to_cpu(tx.tcb_bytes) & 0x3fff);
803 TRACE(RXTX, logout
804 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
805 tbd_array, tcb_bytes, tx.tbd_count));
806
807 if (bit_nc) {
808 missing("CmdTx: NC = 0");
809 success = false;
810 break;
811 }
812 //~ assert(!bit_sf);
813 if (tcb_bytes > 2600) {
814 logout("TCB byte count too large, using 2600\n");
815 tcb_bytes = 2600;
816 }
817 /* Next assertion fails for local configuration. */
818 //~ assert((tcb_bytes > 0) || (tbd_array != 0xffffffff));
819 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
820 logout
821 ("illegal values of TBD array address and TCB byte count!\n");
822 }
823 // sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes
824 uint8_t buf[2600];
825 uint16_t size = 0;
826 uint32_t tbd_address = cb_address + 0x10;
827 assert(tcb_bytes <= sizeof(buf));
828 while (size < tcb_bytes) {
829 uint32_t tx_buffer_address = ldl_phys(tbd_address);
830 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
831 //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
832 tbd_address += 8;
833 TRACE(RXTX, logout
834 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
835 tx_buffer_address, tx_buffer_size));
836 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
837 cpu_physical_memory_read(tx_buffer_address, &buf[size],
838 tx_buffer_size);
839 size += tx_buffer_size;
840 }
841 if (tbd_array == 0xffffffff) {
842 /* Simplified mode. Was already handled by code above. */
843 } else {
844 /* Flexible mode. */
845 uint8_t tbd_count = 0;
846 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
847 /* Extended Flexible TCB. */
848 for (; tbd_count < 2; tbd_count++) {
849 uint32_t tx_buffer_address = ldl_phys(tbd_address);
850 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
851 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
852 tbd_address += 8;
853 TRACE(RXTX, logout
854 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
855 tx_buffer_address, tx_buffer_size));
856 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
857 cpu_physical_memory_read(tx_buffer_address, &buf[size],
858 tx_buffer_size);
859 size += tx_buffer_size;
860 if (tx_buffer_el & 1) {
861 break;
862 }
863 }
864 }
865 tbd_address = tbd_array;
866 for (; tbd_count < tx.tbd_count; tbd_count++) {
867 uint32_t tx_buffer_address = ldl_phys(tbd_address);
868 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
869 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
870 tbd_address += 8;
871 TRACE(RXTX, logout
872 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
873 tx_buffer_address, tx_buffer_size));
874 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
875 cpu_physical_memory_read(tx_buffer_address, &buf[size],
876 tx_buffer_size);
877 size += tx_buffer_size;
878 if (tx_buffer_el & 1) {
879 break;
880 }
881 }
882 }
883 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
884 qemu_send_packet(&s->nic->nc, buf, size);
885 s->statistics.tx_good_frames++;
886 /* Transmit with bad status would raise an CX/TNO interrupt.
887 * (82557 only). Emulation never has bad status. */
888 //~ eepro100_cx_interrupt(s);
889 break;
890 case CmdTDR:
891 TRACE(OTHER, logout("load microcode\n"));
892 /* Starting with offset 8, the command contains
893 * 64 dwords microcode which we just ignore here. */
894 break;
895 default:
896 missing("undefined command");
897 success = false;
898 break;
899 }
900 /* Write new status. */
901 stw_phys(cb_address, status | 0x8000 | (success ? 0x2000 : 0));
902 if (bit_i) {
903 /* CU completed action. */
904 eepro100_cx_interrupt(s);
905 }
906 if (bit_el) {
907 /* CU becomes idle. Terminate command loop. */
908 set_cu_state(s, cu_idle);
909 eepro100_cna_interrupt(s);
910 break;
911 } else if (bit_s) {
912 /* CU becomes suspended. Terminate command loop. */
913 set_cu_state(s, cu_suspended);
914 eepro100_cna_interrupt(s);
915 break;
916 } else {
917 /* More entries in list. */
918 TRACE(OTHER, logout("CU list with at least one more entry\n"));
919 }
920 }
921 TRACE(OTHER, logout("CU list empty\n"));
922 /* List is empty. Now CU is idle or suspended. */
923 }
924
925 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
926 {
927 switch (val) {
928 case CU_NOP:
929 /* No operation. */
930 break;
931 case CU_START:
932 if (get_cu_state(s) != cu_idle) {
933 /* Intel documentation says that CU must be idle for the CU
934 * start command. Intel driver for Linux also starts the CU
935 * from suspended state. */
936 logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle);
937 //~ assert(!"wrong CU state");
938 }
939 set_cu_state(s, cu_active);
940 s->cu_offset = s->pointer;
941 action_command(s);
942 break;
943 case CU_RESUME:
944 if (get_cu_state(s) != cu_suspended) {
945 logout("bad CU resume from CU state %u\n", get_cu_state(s));
946 /* Workaround for bad Linux eepro100 driver which resumes
947 * from idle state. */
948 //~ missing("cu resume");
949 set_cu_state(s, cu_suspended);
950 }
951 if (get_cu_state(s) == cu_suspended) {
952 TRACE(OTHER, logout("CU resuming\n"));
953 set_cu_state(s, cu_active);
954 action_command(s);
955 }
956 break;
957 case CU_STATSADDR:
958 /* Load dump counters address. */
959 s->statsaddr = s->pointer;
960 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
961 break;
962 case CU_SHOWSTATS:
963 /* Dump statistical counters. */
964 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
965 dump_statistics(s);
966 stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
967 break;
968 case CU_CMD_BASE:
969 /* Load CU base. */
970 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
971 s->cu_base = s->pointer;
972 break;
973 case CU_DUMPSTATS:
974 /* Dump and reset statistical counters. */
975 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
976 dump_statistics(s);
977 stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
978 memset(&s->statistics, 0, sizeof(s->statistics));
979 break;
980 case CU_SRESUME:
981 /* CU static resume. */
982 missing("CU static resume");
983 break;
984 default:
985 missing("Undefined CU command");
986 }
987 }
988
989 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
990 {
991 switch (val) {
992 case RU_NOP:
993 /* No operation. */
994 break;
995 case RX_START:
996 /* RU start. */
997 if (get_ru_state(s) != ru_idle) {
998 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
999 //~ assert(!"wrong RU state");
1000 }
1001 set_ru_state(s, ru_ready);
1002 s->ru_offset = s->pointer;
1003 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
1004 break;
1005 case RX_RESUME:
1006 /* Restart RU. */
1007 if (get_ru_state(s) != ru_suspended) {
1008 logout("RU state is %u, should be %u\n", get_ru_state(s),
1009 ru_suspended);
1010 //~ assert(!"wrong RU state");
1011 }
1012 set_ru_state(s, ru_ready);
1013 break;
1014 case RX_ADDR_LOAD:
1015 /* Load RU base. */
1016 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1017 s->ru_base = s->pointer;
1018 break;
1019 default:
1020 logout("val=0x%02x (undefined RU command)\n", val);
1021 missing("Undefined SU command");
1022 }
1023 }
1024
1025 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1026 {
1027 eepro100_ru_command(s, val & 0x0f);
1028 eepro100_cu_command(s, val & 0xf0);
1029 if ((val) == 0) {
1030 TRACE(OTHER, logout("val=0x%02x\n", val));
1031 }
1032 /* Clear command byte after command was accepted. */
1033 s->mem[SCBCmd] = 0;
1034 }
1035
1036 /*****************************************************************************
1037 *
1038 * EEPROM emulation.
1039 *
1040 ****************************************************************************/
1041
1042 #define EEPROM_CS 0x02
1043 #define EEPROM_SK 0x01
1044 #define EEPROM_DI 0x04
1045 #define EEPROM_DO 0x08
1046
1047 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1048 {
1049 uint16_t val;
1050 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
1051 if (eeprom93xx_read(s->eeprom)) {
1052 val |= EEPROM_DO;
1053 } else {
1054 val &= ~EEPROM_DO;
1055 }
1056 TRACE(EEPROM, logout("val=0x%04x\n", val));
1057 return val;
1058 }
1059
1060 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1061 {
1062 TRACE(EEPROM, logout("val=0x%02x\n", val));
1063
1064 /* mask unwriteable bits */
1065 //~ val = SET_MASKED(val, 0x31, eeprom->value);
1066
1067 int eecs = ((val & EEPROM_CS) != 0);
1068 int eesk = ((val & EEPROM_SK) != 0);
1069 int eedi = ((val & EEPROM_DI) != 0);
1070 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1071 }
1072
1073 static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
1074 {
1075 s->pointer = le32_to_cpu(val);
1076 TRACE(OTHER, logout("val=0x%08x\n", val));
1077 }
1078
1079 /*****************************************************************************
1080 *
1081 * MDI emulation.
1082 *
1083 ****************************************************************************/
1084
1085 #if defined(DEBUG_EEPRO100)
1086 static const char * const mdi_op_name[] = {
1087 "opcode 0",
1088 "write",
1089 "read",
1090 "opcode 3"
1091 };
1092
1093 static const char * const mdi_reg_name[] = {
1094 "Control",
1095 "Status",
1096 "PHY Identification (Word 1)",
1097 "PHY Identification (Word 2)",
1098 "Auto-Negotiation Advertisement",
1099 "Auto-Negotiation Link Partner Ability",
1100 "Auto-Negotiation Expansion"
1101 };
1102
1103 static const char *reg2name(uint8_t reg)
1104 {
1105 static char buffer[10];
1106 const char *p = buffer;
1107 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1108 p = mdi_reg_name[reg];
1109 } else {
1110 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1111 }
1112 return p;
1113 }
1114 #endif /* DEBUG_EEPRO100 */
1115
1116 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1117 {
1118 uint32_t val;
1119 memcpy(&val, &s->mem[0x10], sizeof(val));
1120
1121 #ifdef DEBUG_EEPRO100
1122 uint8_t raiseint = (val & BIT(29)) >> 29;
1123 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1124 uint8_t phy = (val & BITS(25, 21)) >> 21;
1125 uint8_t reg = (val & BITS(20, 16)) >> 16;
1126 uint16_t data = (val & BITS(15, 0));
1127 #endif
1128 /* Emulation takes no time to finish MDI transaction. */
1129 val |= BIT(28);
1130 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1131 val, raiseint, mdi_op_name[opcode], phy,
1132 reg2name(reg), data));
1133 return val;
1134 }
1135
1136 static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1137 {
1138 uint8_t raiseint = (val & BIT(29)) >> 29;
1139 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1140 uint8_t phy = (val & BITS(25, 21)) >> 21;
1141 uint8_t reg = (val & BITS(20, 16)) >> 16;
1142 uint16_t data = (val & BITS(15, 0));
1143 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1144 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1145 if (phy != 1) {
1146 /* Unsupported PHY address. */
1147 //~ logout("phy must be 1 but is %u\n", phy);
1148 data = 0;
1149 } else if (opcode != 1 && opcode != 2) {
1150 /* Unsupported opcode. */
1151 logout("opcode must be 1 or 2 but is %u\n", opcode);
1152 data = 0;
1153 } else if (reg > 6) {
1154 /* Unsupported register. */
1155 logout("register must be 0...6 but is %u\n", reg);
1156 data = 0;
1157 } else {
1158 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1159 val, raiseint, mdi_op_name[opcode], phy,
1160 reg2name(reg), data));
1161 if (opcode == 1) {
1162 /* MDI write */
1163 switch (reg) {
1164 case 0: /* Control Register */
1165 if (data & 0x8000) {
1166 /* Reset status and control registers to default. */
1167 s->mdimem[0] = eepro100_mdi_default[0];
1168 s->mdimem[1] = eepro100_mdi_default[1];
1169 data = s->mdimem[reg];
1170 } else {
1171 /* Restart Auto Configuration = Normal Operation */
1172 data &= ~0x0200;
1173 }
1174 break;
1175 case 1: /* Status Register */
1176 missing("not writable");
1177 data = s->mdimem[reg];
1178 break;
1179 case 2: /* PHY Identification Register (Word 1) */
1180 case 3: /* PHY Identification Register (Word 2) */
1181 missing("not implemented");
1182 break;
1183 case 4: /* Auto-Negotiation Advertisement Register */
1184 case 5: /* Auto-Negotiation Link Partner Ability Register */
1185 break;
1186 case 6: /* Auto-Negotiation Expansion Register */
1187 default:
1188 missing("not implemented");
1189 }
1190 s->mdimem[reg] = data;
1191 } else if (opcode == 2) {
1192 /* MDI read */
1193 switch (reg) {
1194 case 0: /* Control Register */
1195 if (data & 0x8000) {
1196 /* Reset status and control registers to default. */
1197 s->mdimem[0] = eepro100_mdi_default[0];
1198 s->mdimem[1] = eepro100_mdi_default[1];
1199 }
1200 break;
1201 case 1: /* Status Register */
1202 s->mdimem[reg] |= 0x0020;
1203 break;
1204 case 2: /* PHY Identification Register (Word 1) */
1205 case 3: /* PHY Identification Register (Word 2) */
1206 case 4: /* Auto-Negotiation Advertisement Register */
1207 break;
1208 case 5: /* Auto-Negotiation Link Partner Ability Register */
1209 s->mdimem[reg] = 0x41fe;
1210 break;
1211 case 6: /* Auto-Negotiation Expansion Register */
1212 s->mdimem[reg] = 0x0001;
1213 break;
1214 }
1215 data = s->mdimem[reg];
1216 }
1217 /* Emulation takes no time to finish MDI transaction.
1218 * Set MDI bit in SCB status register. */
1219 s->mem[SCBAck] |= 0x08;
1220 val |= BIT(28);
1221 if (raiseint) {
1222 eepro100_mdi_interrupt(s);
1223 }
1224 }
1225 val = (val & 0xffff0000) + data;
1226 memcpy(&s->mem[0x10], &val, sizeof(val));
1227 }
1228
1229 /*****************************************************************************
1230 *
1231 * Port emulation.
1232 *
1233 ****************************************************************************/
1234
1235 #define PORT_SOFTWARE_RESET 0
1236 #define PORT_SELFTEST 1
1237 #define PORT_SELECTIVE_RESET 2
1238 #define PORT_DUMP 3
1239 #define PORT_SELECTION_MASK 3
1240
1241 typedef struct {
1242 uint32_t st_sign; /* Self Test Signature */
1243 uint32_t st_result; /* Self Test Results */
1244 } eepro100_selftest_t;
1245
1246 static uint32_t eepro100_read_port(EEPRO100State * s)
1247 {
1248 return 0;
1249 }
1250
1251 static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1252 {
1253 val = le32_to_cpu(val);
1254 uint32_t address = (val & ~PORT_SELECTION_MASK);
1255 uint8_t selection = (val & PORT_SELECTION_MASK);
1256 switch (selection) {
1257 case PORT_SOFTWARE_RESET:
1258 nic_reset(s);
1259 break;
1260 case PORT_SELFTEST:
1261 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1262 eepro100_selftest_t data;
1263 cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1264 data.st_sign = 0xffffffff;
1265 data.st_result = 0;
1266 cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1267 break;
1268 case PORT_SELECTIVE_RESET:
1269 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1270 nic_selective_reset(s);
1271 break;
1272 default:
1273 logout("val=0x%08x\n", val);
1274 missing("unknown port selection");
1275 }
1276 }
1277
1278 /*****************************************************************************
1279 *
1280 * General hardware emulation.
1281 *
1282 ****************************************************************************/
1283
1284 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1285 {
1286 uint8_t val;
1287 if (addr <= sizeof(s->mem) - sizeof(val)) {
1288 memcpy(&val, &s->mem[addr], sizeof(val));
1289 }
1290
1291 switch (addr) {
1292 case SCBStatus:
1293 //~ val = eepro100_read_status(s);
1294 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1295 break;
1296 case SCBAck:
1297 //~ val = eepro100_read_status(s);
1298 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1299 break;
1300 case SCBCmd:
1301 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1302 //~ val = eepro100_read_command(s);
1303 break;
1304 case SCBIntmask:
1305 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1306 break;
1307 case SCBPort + 3:
1308 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1309 break;
1310 case SCBeeprom:
1311 val = eepro100_read_eeprom(s);
1312 break;
1313 case 0x1b: /* PMDR (power management driver register) */
1314 val = 0;
1315 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1316 break;
1317 case 0x1d: /* general status register */
1318 /* 100 Mbps full duplex, valid link */
1319 val = 0x07;
1320 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1321 break;
1322 default:
1323 logout("addr=%s val=0x%02x\n", regname(addr), val);
1324 missing("unknown byte read");
1325 }
1326 return val;
1327 }
1328
1329 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1330 {
1331 uint16_t val;
1332 if (addr <= sizeof(s->mem) - sizeof(val)) {
1333 memcpy(&val, &s->mem[addr], sizeof(val));
1334 }
1335
1336 switch (addr) {
1337 case SCBStatus:
1338 //~ val = eepro100_read_status(s);
1339 case SCBCmd:
1340 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1341 break;
1342 case SCBeeprom:
1343 val = eepro100_read_eeprom(s);
1344 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1345 break;
1346 default:
1347 logout("addr=%s val=0x%04x\n", regname(addr), val);
1348 missing("unknown word read");
1349 }
1350 return val;
1351 }
1352
1353 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1354 {
1355 uint32_t val;
1356 if (addr <= sizeof(s->mem) - sizeof(val)) {
1357 memcpy(&val, &s->mem[addr], sizeof(val));
1358 }
1359
1360 switch (addr) {
1361 case SCBStatus:
1362 //~ val = eepro100_read_status(s);
1363 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1364 break;
1365 case SCBPointer:
1366 //~ val = eepro100_read_pointer(s);
1367 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1368 break;
1369 case SCBPort:
1370 val = eepro100_read_port(s);
1371 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1372 break;
1373 case SCBCtrlMDI:
1374 val = eepro100_read_mdi(s);
1375 break;
1376 default:
1377 logout("addr=%s val=0x%08x\n", regname(addr), val);
1378 missing("unknown longword read");
1379 }
1380 return val;
1381 }
1382
1383 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1384 {
1385 if (addr <= sizeof(s->mem) - sizeof(val)) {
1386 memcpy(&s->mem[addr], &val, sizeof(val));
1387 }
1388
1389 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1390
1391 switch (addr) {
1392 case SCBStatus:
1393 //~ eepro100_write_status(s, val);
1394 break;
1395 case SCBAck:
1396 eepro100_acknowledge(s);
1397 break;
1398 case SCBCmd:
1399 eepro100_write_command(s, val);
1400 break;
1401 case SCBIntmask:
1402 if (val & BIT(1)) {
1403 eepro100_swi_interrupt(s);
1404 }
1405 eepro100_interrupt(s, 0);
1406 break;
1407 case SCBPort + 3:
1408 case SCBFlow: /* does not exist on 82557 */
1409 case SCBFlow + 1:
1410 case SCBFlow + 2:
1411 case SCBFlow + 3:
1412 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1413 break;
1414 case SCBeeprom:
1415 eepro100_write_eeprom(s->eeprom, val);
1416 break;
1417 default:
1418 logout("addr=%s val=0x%02x\n", regname(addr), val);
1419 missing("unknown byte write");
1420 }
1421 }
1422
1423 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1424 {
1425 if (addr <= sizeof(s->mem) - sizeof(val)) {
1426 memcpy(&s->mem[addr], &val, sizeof(val));
1427 }
1428
1429 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1430
1431 switch (addr) {
1432 case SCBStatus:
1433 //~ eepro100_write_status(s, val);
1434 eepro100_acknowledge(s);
1435 break;
1436 case SCBCmd:
1437 eepro100_write_command(s, val);
1438 eepro100_write1(s, SCBIntmask, val >> 8);
1439 break;
1440 case SCBeeprom:
1441 eepro100_write_eeprom(s->eeprom, val);
1442 break;
1443 default:
1444 logout("addr=%s val=0x%04x\n", regname(addr), val);
1445 missing("unknown word write");
1446 }
1447 }
1448
1449 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1450 {
1451 if (addr <= sizeof(s->mem) - sizeof(val)) {
1452 memcpy(&s->mem[addr], &val, sizeof(val));
1453 }
1454
1455 switch (addr) {
1456 case SCBPointer:
1457 eepro100_write_pointer(s, val);
1458 break;
1459 case SCBPort:
1460 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1461 eepro100_write_port(s, val);
1462 break;
1463 case SCBCtrlMDI:
1464 eepro100_write_mdi(s, val);
1465 break;
1466 default:
1467 logout("addr=%s val=0x%08x\n", regname(addr), val);
1468 missing("unknown longword write");
1469 }
1470 }
1471
1472 /*****************************************************************************
1473 *
1474 * Port mapped I/O.
1475 *
1476 ****************************************************************************/
1477
1478 static uint32_t ioport_read1(void *opaque, uint32_t addr)
1479 {
1480 EEPRO100State *s = opaque;
1481 //~ logout("addr=%s\n", regname(addr));
1482 return eepro100_read1(s, addr - s->region[1]);
1483 }
1484
1485 static uint32_t ioport_read2(void *opaque, uint32_t addr)
1486 {
1487 EEPRO100State *s = opaque;
1488 return eepro100_read2(s, addr - s->region[1]);
1489 }
1490
1491 static uint32_t ioport_read4(void *opaque, uint32_t addr)
1492 {
1493 EEPRO100State *s = opaque;
1494 return eepro100_read4(s, addr - s->region[1]);
1495 }
1496
1497 static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1498 {
1499 EEPRO100State *s = opaque;
1500 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1501 eepro100_write1(s, addr - s->region[1], val);
1502 }
1503
1504 static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1505 {
1506 EEPRO100State *s = opaque;
1507 eepro100_write2(s, addr - s->region[1], val);
1508 }
1509
1510 static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1511 {
1512 EEPRO100State *s = opaque;
1513 eepro100_write4(s, addr - s->region[1], val);
1514 }
1515
1516 /***********************************************************/
1517 /* PCI EEPRO100 definitions */
1518
1519 static void pci_map(PCIDevice * pci_dev, int region_num,
1520 pcibus_t addr, pcibus_t size, int type)
1521 {
1522 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1523
1524 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1525 "size=0x%08"FMT_PCIBUS", type=%d\n",
1526 region_num, addr, size, type));
1527
1528 assert(region_num == 1);
1529 register_ioport_write(addr, size, 1, ioport_write1, s);
1530 register_ioport_read(addr, size, 1, ioport_read1, s);
1531 register_ioport_write(addr, size, 2, ioport_write2, s);
1532 register_ioport_read(addr, size, 2, ioport_read2, s);
1533 register_ioport_write(addr, size, 4, ioport_write4, s);
1534 register_ioport_read(addr, size, 4, ioport_read4, s);
1535
1536 s->region[region_num] = addr;
1537 }
1538
1539 /*****************************************************************************
1540 *
1541 * Memory mapped I/O.
1542 *
1543 ****************************************************************************/
1544
1545 static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1546 {
1547 EEPRO100State *s = opaque;
1548 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1549 eepro100_write1(s, addr, val);
1550 }
1551
1552 static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1553 {
1554 EEPRO100State *s = opaque;
1555 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1556 eepro100_write2(s, addr, val);
1557 }
1558
1559 static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1560 {
1561 EEPRO100State *s = opaque;
1562 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1563 eepro100_write4(s, addr, val);
1564 }
1565
1566 static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1567 {
1568 EEPRO100State *s = opaque;
1569 //~ logout("addr=%s\n", regname(addr));
1570 return eepro100_read1(s, addr);
1571 }
1572
1573 static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1574 {
1575 EEPRO100State *s = opaque;
1576 //~ logout("addr=%s\n", regname(addr));
1577 return eepro100_read2(s, addr);
1578 }
1579
1580 static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1581 {
1582 EEPRO100State *s = opaque;
1583 //~ logout("addr=%s\n", regname(addr));
1584 return eepro100_read4(s, addr);
1585 }
1586
1587 static CPUWriteMemoryFunc * const pci_mmio_write[] = {
1588 pci_mmio_writeb,
1589 pci_mmio_writew,
1590 pci_mmio_writel
1591 };
1592
1593 static CPUReadMemoryFunc * const pci_mmio_read[] = {
1594 pci_mmio_readb,
1595 pci_mmio_readw,
1596 pci_mmio_readl
1597 };
1598
1599 static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
1600 pcibus_t addr, pcibus_t size, int type)
1601 {
1602 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1603
1604 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1605 "size=0x%08"FMT_PCIBUS", type=%d\n",
1606 region_num, addr, size, type));
1607
1608 if (region_num == 0) {
1609 /* Map control / status registers. */
1610 cpu_register_physical_memory(addr, size, s->mmio_index);
1611 s->region[region_num] = addr;
1612 }
1613 }
1614
1615 static int nic_can_receive(VLANClientState *nc)
1616 {
1617 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1618 TRACE(RXTX, logout("%p\n", s));
1619 return get_ru_state(s) == ru_ready;
1620 //~ return !eepro100_buffer_full(s);
1621 }
1622
1623 static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
1624 {
1625 /* TODO:
1626 * - Magic packets should set bit 30 in power management driver register.
1627 * - Interesting packets should set bit 29 in power management driver register.
1628 */
1629 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1630 uint16_t rfd_status = 0xa000;
1631 static const uint8_t broadcast_macaddr[6] =
1632 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1633
1634 /* TODO: check multiple IA bit. */
1635 if (s->configuration[20] & BIT(6)) {
1636 missing("Multiple IA bit");
1637 return -1;
1638 }
1639
1640 if (s->configuration[8] & 0x80) {
1641 /* CSMA is disabled. */
1642 logout("%p received while CSMA is disabled\n", s);
1643 return -1;
1644 } else if (size < 64 && (s->configuration[7] & 1)) {
1645 /* Short frame and configuration byte 7/0 (discard short receive) set:
1646 * Short frame is discarded */
1647 logout("%p received short frame (%zu byte)\n", s, size);
1648 s->statistics.rx_short_frame_errors++;
1649 //~ return -1;
1650 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & 8)) {
1651 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1652 * Long frames are discarded. */
1653 logout("%p received long frame (%zu byte), ignored\n", s, size);
1654 return -1;
1655 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { // !!!
1656 /* Frame matches individual address. */
1657 /* TODO: check configuration byte 15/4 (ignore U/L). */
1658 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1659 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1660 /* Broadcast frame. */
1661 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1662 rfd_status |= 0x0002;
1663 } else if (buf[0] & 0x01) { // !!!
1664 /* Multicast frame. */
1665 TRACE(RXTX, logout("%p received multicast, len=%zu\n", s, size));
1666 /* TODO: check multicast all bit. */
1667 if (s->configuration[21] & BIT(3)) {
1668 missing("Multicast All bit");
1669 }
1670 int mcast_idx = compute_mcast_idx(buf);
1671 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) {
1672 return size;
1673 }
1674 rfd_status |= 0x0002;
1675 } else if (s->configuration[15] & 1) {
1676 /* Promiscuous: receive all. */
1677 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1678 rfd_status |= 0x0004;
1679 } else {
1680 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1681 nic_dump(buf, size)));
1682 return size;
1683 }
1684
1685 if (get_ru_state(s) != ru_ready) {
1686 /* No resources available. */
1687 logout("no resources, state=%u\n", get_ru_state(s));
1688 s->statistics.rx_resource_errors++;
1689 //~ assert(!"no resources");
1690 return -1;
1691 }
1692 //~ !!!
1693 //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
1694 eepro100_rx_t rx;
1695 cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
1696 offsetof(eepro100_rx_t, packet));
1697 uint16_t rfd_command = le16_to_cpu(rx.command);
1698 uint16_t rfd_size = le16_to_cpu(rx.size);
1699
1700 if (size > rfd_size) {
1701 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1702 "(%zu bytes); data truncated\n", rfd_size, size);
1703 size = rfd_size;
1704 }
1705 if (size < 64) {
1706 rfd_status |= 0x0080;
1707 }
1708 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1709 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1710 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
1711 rfd_status);
1712 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
1713 /* Early receive interrupt not supported. */
1714 //~ eepro100_er_interrupt(s);
1715 /* Receive CRC Transfer not supported. */
1716 if (s->configuration[18] & 4) {
1717 missing("Receive CRC Transfer");
1718 return -1;
1719 }
1720 /* TODO: check stripping enable bit. */
1721 //~ assert(!(s->configuration[17] & 1));
1722 cpu_physical_memory_write(s->ru_base + s->ru_offset +
1723 offsetof(eepro100_rx_t, packet), buf, size);
1724 s->statistics.rx_good_frames++;
1725 eepro100_fr_interrupt(s);
1726 s->ru_offset = le32_to_cpu(rx.link);
1727 if (rfd_command & 0x8000) {
1728 /* EL bit is set, so this was the last frame. */
1729 logout("receive: Running out of frames\n");
1730 set_ru_state(s, ru_suspended);
1731 }
1732 if (rfd_command & 0x4000) {
1733 /* S bit is set. */
1734 set_ru_state(s, ru_suspended);
1735 }
1736 return size;
1737 }
1738
1739 static const VMStateDescription vmstate_eepro100 = {
1740 .version_id = 3,
1741 .minimum_version_id = 2,
1742 .minimum_version_id_old = 2,
1743 .fields = (VMStateField []) {
1744 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1745 VMSTATE_UNUSED(32),
1746 VMSTATE_BUFFER(mult, EEPRO100State),
1747 VMSTATE_BUFFER(mem, EEPRO100State),
1748 /* Save all members of struct between scb_stat and mem. */
1749 VMSTATE_UINT8(scb_stat, EEPRO100State),
1750 VMSTATE_UINT8(int_stat, EEPRO100State),
1751 VMSTATE_UNUSED(3*4),
1752 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1753 VMSTATE_UNUSED(19*4),
1754 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1755 /* The eeprom should be saved and restored by its own routines. */
1756 VMSTATE_UINT32(device, EEPRO100State),
1757 /* TODO check device. */
1758 VMSTATE_UINT32(pointer, EEPRO100State),
1759 VMSTATE_UINT32(cu_base, EEPRO100State),
1760 VMSTATE_UINT32(cu_offset, EEPRO100State),
1761 VMSTATE_UINT32(ru_base, EEPRO100State),
1762 VMSTATE_UINT32(ru_offset, EEPRO100State),
1763 VMSTATE_UINT32(statsaddr, EEPRO100State),
1764 /* Save eepro100_stats_t statistics. */
1765 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1766 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1767 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1768 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1769 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1770 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1771 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1772 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1773 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1774 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1775 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1776 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1777 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1778 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1779 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1780 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1781 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1782 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1783 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1784 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1785 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1786 #if 0
1787 VMSTATE_UINT16(status, EEPRO100State),
1788 #endif
1789 /* Configuration bytes. */
1790 VMSTATE_BUFFER(configuration, EEPRO100State),
1791 VMSTATE_END_OF_LIST()
1792 }
1793 };
1794
1795 static void nic_cleanup(VLANClientState *nc)
1796 {
1797 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1798
1799 s->nic = NULL;
1800 }
1801
1802 static int pci_nic_uninit(PCIDevice *pci_dev)
1803 {
1804 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1805
1806 cpu_unregister_io_memory(s->mmio_index);
1807 vmstate_unregister(s->vmstate, s);
1808 eeprom93xx_free(s->eeprom);
1809 qemu_del_vlan_client(&s->nic->nc);
1810 return 0;
1811 }
1812
1813 static NetClientInfo net_eepro100_info = {
1814 .type = NET_CLIENT_TYPE_NIC,
1815 .size = sizeof(NICState),
1816 .can_receive = nic_can_receive,
1817 .receive = nic_receive,
1818 .cleanup = nic_cleanup,
1819 };
1820
1821 static int nic_init(PCIDevice *pci_dev, uint32_t device)
1822 {
1823 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1824
1825 TRACE(OTHER, logout("\n"));
1826
1827 s->device = device;
1828
1829 pci_reset(s);
1830
1831 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1832 * i82559 and later support 64 or 256 word EEPROM. */
1833 s->eeprom = eeprom93xx_new(EEPROM_SIZE);
1834
1835 /* Handler for memory-mapped I/O */
1836 s->mmio_index =
1837 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
1838
1839 pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
1840 PCI_BASE_ADDRESS_SPACE_MEMORY |
1841 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map);
1842 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
1843 pci_map);
1844 pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
1845 pci_mmio_map);
1846
1847 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1848 logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6));
1849 assert(s->region[1] == 0);
1850
1851 nic_reset(s);
1852
1853 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1854 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
1855
1856 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1857 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
1858
1859 qemu_register_reset(nic_reset, s);
1860
1861 s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1862 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1863 s->vmstate->name = s->nic->nc.model;
1864 vmstate_register(-1, s->vmstate, s);
1865
1866 if (!pci_dev->qdev.hotplugged) {
1867 static int loaded = 0;
1868 if (!loaded) {
1869 char fname[32];
1870 snprintf(fname, sizeof(fname), "pxe-%s.bin", s->nic->nc.model);
1871 rom_add_option(fname);
1872 loaded = 1;
1873 }
1874 }
1875 return 0;
1876 }
1877
1878 static int pci_i82550_init(PCIDevice *pci_dev)
1879 {
1880 return nic_init(pci_dev, i82550);
1881 }
1882
1883 static int pci_i82551_init(PCIDevice *pci_dev)
1884 {
1885 return nic_init(pci_dev, i82551);
1886 }
1887
1888 static int pci_i82557a_init(PCIDevice *pci_dev)
1889 {
1890 return nic_init(pci_dev, i82557A);
1891 }
1892
1893 static int pci_i82557b_init(PCIDevice *pci_dev)
1894 {
1895 return nic_init(pci_dev, i82557B);
1896 }
1897
1898 static int pci_i82557c_init(PCIDevice *pci_dev)
1899 {
1900 return nic_init(pci_dev, i82557C);
1901 }
1902
1903 static int pci_i82558a_init(PCIDevice *pci_dev)
1904 {
1905 return nic_init(pci_dev, i82558A);
1906 }
1907
1908 static int pci_i82558b_init(PCIDevice *pci_dev)
1909 {
1910 return nic_init(pci_dev, i82558B);
1911 }
1912
1913 static int pci_i82559a_init(PCIDevice *pci_dev)
1914 {
1915 return nic_init(pci_dev, i82559A);
1916 }
1917
1918 static int pci_i82559b_init(PCIDevice *pci_dev)
1919 {
1920 return nic_init(pci_dev, i82559B);
1921 }
1922
1923 static int pci_i82559c_init(PCIDevice *pci_dev)
1924 {
1925 return nic_init(pci_dev, i82559C);
1926 }
1927
1928 static int pci_i82559er_init(PCIDevice *pci_dev)
1929 {
1930 return nic_init(pci_dev, i82559ER);
1931 }
1932
1933 static int pci_i82562_init(PCIDevice *pci_dev)
1934 {
1935 return nic_init(pci_dev, i82562);
1936 }
1937
1938 static PCIDeviceInfo eepro100_info[] = {
1939 {
1940 .qdev.name = "i82550",
1941 .qdev.size = sizeof(EEPRO100State),
1942 .init = pci_i82550_init,
1943 .exit = pci_nic_uninit,
1944 .qdev.props = (Property[]) {
1945 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1946 DEFINE_PROP_END_OF_LIST(),
1947 },
1948 },{
1949 .qdev.name = "i82551",
1950 .qdev.size = sizeof(EEPRO100State),
1951 .init = pci_i82551_init,
1952 .exit = pci_nic_uninit,
1953 .qdev.props = (Property[]) {
1954 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1955 DEFINE_PROP_END_OF_LIST(),
1956 },
1957 },{
1958 .qdev.name = "i82557a",
1959 .qdev.size = sizeof(EEPRO100State),
1960 .init = pci_i82557a_init,
1961 .exit = pci_nic_uninit,
1962 .qdev.props = (Property[]) {
1963 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1964 DEFINE_PROP_END_OF_LIST(),
1965 },
1966 },{
1967 .qdev.name = "i82557b",
1968 .qdev.size = sizeof(EEPRO100State),
1969 .init = pci_i82557b_init,
1970 .exit = pci_nic_uninit,
1971 .qdev.props = (Property[]) {
1972 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1973 DEFINE_PROP_END_OF_LIST(),
1974 },
1975 },{
1976 .qdev.name = "i82557c",
1977 .qdev.size = sizeof(EEPRO100State),
1978 .init = pci_i82557c_init,
1979 .exit = pci_nic_uninit,
1980 .qdev.props = (Property[]) {
1981 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1982 DEFINE_PROP_END_OF_LIST(),
1983 },
1984 },{
1985 .qdev.name = "i82558a",
1986 .qdev.size = sizeof(EEPRO100State),
1987 .init = pci_i82558a_init,
1988 .exit = pci_nic_uninit,
1989 .qdev.props = (Property[]) {
1990 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1991 DEFINE_PROP_END_OF_LIST(),
1992 },
1993 },{
1994 .qdev.name = "i82558b",
1995 .qdev.size = sizeof(EEPRO100State),
1996 .init = pci_i82558b_init,
1997 .exit = pci_nic_uninit,
1998 .qdev.props = (Property[]) {
1999 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2000 DEFINE_PROP_END_OF_LIST(),
2001 },
2002 },{
2003 .qdev.name = "i82559a",
2004 .qdev.size = sizeof(EEPRO100State),
2005 .init = pci_i82559a_init,
2006 .exit = pci_nic_uninit,
2007 .qdev.props = (Property[]) {
2008 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2009 DEFINE_PROP_END_OF_LIST(),
2010 },
2011 },{
2012 .qdev.name = "i82559b",
2013 .qdev.size = sizeof(EEPRO100State),
2014 .init = pci_i82559b_init,
2015 .exit = pci_nic_uninit,
2016 .qdev.props = (Property[]) {
2017 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2018 DEFINE_PROP_END_OF_LIST(),
2019 },
2020 },{
2021 .qdev.name = "i82559c",
2022 .qdev.size = sizeof(EEPRO100State),
2023 .init = pci_i82559c_init,
2024 .exit = pci_nic_uninit,
2025 .qdev.props = (Property[]) {
2026 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2027 DEFINE_PROP_END_OF_LIST(),
2028 },
2029 },{
2030 .qdev.name = "i82559er",
2031 .qdev.size = sizeof(EEPRO100State),
2032 .init = pci_i82559er_init,
2033 .exit = pci_nic_uninit,
2034 .qdev.props = (Property[]) {
2035 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2036 DEFINE_PROP_END_OF_LIST(),
2037 },
2038 },{
2039 .qdev.name = "i82562",
2040 .qdev.size = sizeof(EEPRO100State),
2041 .init = pci_i82562_init,
2042 .exit = pci_nic_uninit,
2043 .qdev.props = (Property[]) {
2044 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2045 DEFINE_PROP_END_OF_LIST(),
2046 },
2047 },{
2048 /* end of list */
2049 }
2050 };
2051
2052 static void eepro100_register_devices(void)
2053 {
2054 pci_qdev_register_many(eepro100_info);
2055 }
2056
2057 device_init(eepro100_register_devices)
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