]> git.proxmox.com Git - mirror_qemu.git/blob - hw/eepro100.c
projects / mirror_qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
eepro100: Remove old unused code
[mirror_qemu.git] / hw / eepro100.c
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (C) 2006-2010 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559):
23 * PXE boot (i386) ok
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * non-i386 platforms
28 * Windows networking
29 *
30 * References:
31 *
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
34 *
35 * TODO:
36 * * PHY emulation should be separated from nic emulation.
37 * Most nic emulations could share the same phy code.
38 * * i82550 is untested. It is programmed like the i82559.
39 * * i82562 is untested. It is programmed like the i82559.
40 * * Power management (i82558 and later) is not implemented.
41 * * Wake-on-LAN is not implemented.
42 */
43
44 #include <stddef.h> /* offsetof */
45 #include <stdbool.h>
46 #include "hw.h"
47 #include "pci.h"
48 #include "net.h"
49 #include "eeprom93xx.h"
50
51 /* Common declarations for all PCI devices. */
52
53 #define PCI_CONFIG_8(offset, value) \
54 (pci_conf[offset] = (value))
55 #define PCI_CONFIG_16(offset, value) \
56 (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
57 #define PCI_CONFIG_32(offset, value) \
58 (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
59
60 #define KiB 1024
61
62 /* Debug EEPRO100 card. */
63 #if 0
64 # define DEBUG_EEPRO100
65 #endif
66
67 #ifdef DEBUG_EEPRO100
68 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
69 #else
70 #define logout(fmt, ...) ((void)0)
71 #endif
72
73 /* Set flags to 0 to disable debug output. */
74 #define INT 1 /* interrupt related actions */
75 #define MDI 1 /* mdi related actions */
76 #define OTHER 1
77 #define RXTX 1
78 #define EEPROM 1 /* eeprom related actions */
79
80 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
81
82 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
83
84 #define MAX_ETH_FRAME_SIZE 1514
85
86 /* This driver supports several different devices which are declared here. */
87 #define i82550 0x82550
88 #define i82551 0x82551
89 #define i82557A 0x82557a
90 #define i82557B 0x82557b
91 #define i82557C 0x82557c
92 #define i82558A 0x82558a
93 #define i82558B 0x82558b
94 #define i82559A 0x82559a
95 #define i82559B 0x82559b
96 #define i82559C 0x82559c
97 #define i82559ER 0x82559e
98 #define i82562 0x82562
99
100 /* Use 64 word EEPROM. TODO: could be a runtime option. */
101 #define EEPROM_SIZE 64
102
103 #define PCI_MEM_SIZE (4 * KiB)
104 #define PCI_IO_SIZE 64
105 #define PCI_FLASH_SIZE (128 * KiB)
106
107 #define BIT(n) (1 << (n))
108 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
109
110 /* The SCB accepts the following controls for the Tx and Rx units: */
111 #define CU_NOP 0x0000 /* No operation. */
112 #define CU_START 0x0010 /* CU start. */
113 #define CU_RESUME 0x0020 /* CU resume. */
114 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
115 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
116 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
117 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
118 #define CU_SRESUME 0x00a0 /* CU static resume. */
119
120 #define RU_NOP 0x0000
121 #define RX_START 0x0001
122 #define RX_RESUME 0x0002
123 #define RX_ABORT 0x0004
124 #define RX_ADDR_LOAD 0x0006
125 #define RX_RESUMENR 0x0007
126 #define INT_MASK 0x0100
127 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
128
129 /* Offsets to the various registers.
130 All accesses need not be longword aligned. */
131 enum speedo_offsets {
132 SCBStatus = 0, /* Status Word. */
133 SCBAck = 1,
134 SCBCmd = 2, /* Rx/Command Unit command and status. */
135 SCBIntmask = 3,
136 SCBPointer = 4, /* General purpose pointer. */
137 SCBPort = 8, /* Misc. commands and operands. */
138 SCBflash = 12, /* Flash memory control. */
139 SCBeeprom = 14, /* EEPROM control. */
140 SCBCtrlMDI = 16, /* MDI interface control. */
141 SCBEarlyRx = 20, /* Early receive byte count. */
142 SCBFlow = 24, /* Flow Control. */
143 SCBpmdr = 27, /* Power Management Driver. */
144 SCBgctrl = 28, /* General Control. */
145 SCBgstat = 29, /* General Status. */
146 };
147
148 /* A speedo3 transmit buffer descriptor with two buffers... */
149 typedef struct {
150 uint16_t status;
151 uint16_t command;
152 uint32_t link; /* void * */
153 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
154 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
155 uint8_t tx_threshold; /* transmit threshold */
156 uint8_t tbd_count; /* TBD number */
157 //~ /* This constitutes two "TBD" entries: hdr and data */
158 //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
159 //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
160 //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
161 //~ int32_t tx_buf_size1; /* Length of Tx data. */
162 } eepro100_tx_t;
163
164 /* Receive frame descriptor. */
165 typedef struct {
166 int16_t status;
167 uint16_t command;
168 uint32_t link; /* struct RxFD * */
169 uint32_t rx_buf_addr; /* void * */
170 uint16_t count;
171 uint16_t size;
172 char packet[MAX_ETH_FRAME_SIZE + 4];
173 } eepro100_rx_t;
174
175 typedef enum {
176 COMMAND_EL = BIT(15),
177 COMMAND_S = BIT(14),
178 COMMAND_I = BIT(13),
179 COMMAND_NC = BIT(4),
180 COMMAND_SF = BIT(3),
181 COMMAND_CMD = BITS(2, 0),
182 } scb_command_bit;
183
184 typedef enum {
185 STATUS_C = BIT(15),
186 STATUS_OK = BIT(13),
187 } scb_status_bit;
188
189 typedef struct {
190 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
191 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
192 tx_multiple_collisions, tx_total_collisions;
193 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
194 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
195 rx_short_frame_errors;
196 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
197 uint16_t xmt_tco_frames, rcv_tco_frames;
198 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
199 uint32_t reserved[4];
200 } eepro100_stats_t;
201
202 typedef enum {
203 cu_idle = 0,
204 cu_suspended = 1,
205 cu_active = 2,
206 cu_lpq_active = 2,
207 cu_hqp_active = 3
208 } cu_state_t;
209
210 typedef enum {
211 ru_idle = 0,
212 ru_suspended = 1,
213 ru_no_resources = 2,
214 ru_ready = 4
215 } ru_state_t;
216
217 typedef struct {
218 PCIDevice dev;
219 uint8_t mult[8]; /* multicast mask array */
220 int mmio_index;
221 NICState *nic;
222 NICConf conf;
223 uint8_t scb_stat; /* SCB stat/ack byte */
224 uint8_t int_stat; /* PCI interrupt status */
225 /* region must not be saved by nic_save. */
226 uint32_t region[3]; /* PCI region addresses */
227 uint16_t mdimem[32];
228 eeprom_t *eeprom;
229 uint32_t device; /* device variant */
230 uint32_t pointer;
231 /* (cu_base + cu_offset) address the next command block in the command block list. */
232 uint32_t cu_base; /* CU base address */
233 uint32_t cu_offset; /* CU address offset */
234 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
235 uint32_t ru_base; /* RU base address */
236 uint32_t ru_offset; /* RU address offset */
237 uint32_t statsaddr; /* pointer to eepro100_stats_t */
238
239 /* Temporary status information (no need to save these values),
240 * used while processing CU commands. */
241 eepro100_tx_t tx; /* transmit buffer descriptor */
242 uint32_t cb_address; /* = cu_base + cu_offset */
243
244 /* Statistical counters. Also used for wake-up packet (i82559). */
245 eepro100_stats_t statistics;
246
247 #if 0
248 uint16_t status;
249 #endif
250
251 /* Configuration bytes. */
252 uint8_t configuration[22];
253
254 /* Data in mem is always in the byte order of the controller (le). */
255 uint8_t mem[PCI_MEM_SIZE];
256 /* vmstate for each particular nic */
257 VMStateDescription *vmstate;
258
259 /* Quasi static device properties (no need to save them). */
260 uint16_t stats_size;
261 bool has_extended_tcb_support;
262 } EEPRO100State;
263
264 /* Word indices in EEPROM. */
265 typedef enum {
266 EEPROM_CNFG_MDIX = 0x03,
267 EEPROM_ID = 0x05,
268 EEPROM_PHY_ID = 0x06,
269 EEPROM_VENDOR_ID = 0x0c,
270 EEPROM_CONFIG_ASF = 0x0d,
271 EEPROM_DEVICE_ID = 0x23,
272 EEPROM_SMBUS_ADDR = 0x90,
273 } EEPROMOffset;
274
275 /* Default values for MDI (PHY) registers */
276 static const uint16_t eepro100_mdi_default[] = {
277 /* MDI Registers 0 - 6, 7 */
278 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
279 /* MDI Registers 8 - 15 */
280 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
281 /* MDI Registers 16 - 31 */
282 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
283 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
284 };
285
286 /* Readonly mask for MDI (PHY) registers */
287 static const uint16_t eepro100_mdi_mask[] = {
288 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
289 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
290 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
291 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
292 };
293
294 /* XXX: optimize */
295 static void stl_le_phys(target_phys_addr_t addr, uint32_t val)
296 {
297 val = cpu_to_le32(val);
298 cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val));
299 }
300
301 #define POLYNOMIAL 0x04c11db6
302
303 /* From FreeBSD */
304 /* XXX: optimize */
305 static unsigned compute_mcast_idx(const uint8_t * ep)
306 {
307 uint32_t crc;
308 int carry, i, j;
309 uint8_t b;
310
311 crc = 0xffffffff;
312 for (i = 0; i < 6; i++) {
313 b = *ep++;
314 for (j = 0; j < 8; j++) {
315 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
316 crc <<= 1;
317 b >>= 1;
318 if (carry) {
319 crc = ((crc ^ POLYNOMIAL) | carry);
320 }
321 }
322 }
323 return (crc & BITS(7, 2)) >> 2;
324 }
325
326 #if defined(DEBUG_EEPRO100)
327 static const char *nic_dump(const uint8_t * buf, unsigned size)
328 {
329 static char dump[3 * 16 + 1];
330 char *p = &dump[0];
331 if (size > 16) {
332 size = 16;
333 }
334 while (size-- > 0) {
335 p += sprintf(p, " %02x", *buf++);
336 }
337 return dump;
338 }
339 #endif /* DEBUG_EEPRO100 */
340
341 enum scb_stat_ack {
342 stat_ack_not_ours = 0x00,
343 stat_ack_sw_gen = 0x04,
344 stat_ack_rnr = 0x10,
345 stat_ack_cu_idle = 0x20,
346 stat_ack_frame_rx = 0x40,
347 stat_ack_cu_cmd_done = 0x80,
348 stat_ack_not_present = 0xFF,
349 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
350 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
351 };
352
353 static void disable_interrupt(EEPRO100State * s)
354 {
355 if (s->int_stat) {
356 TRACE(INT, logout("interrupt disabled\n"));
357 qemu_irq_lower(s->dev.irq[0]);
358 s->int_stat = 0;
359 }
360 }
361
362 static void enable_interrupt(EEPRO100State * s)
363 {
364 if (!s->int_stat) {
365 TRACE(INT, logout("interrupt enabled\n"));
366 qemu_irq_raise(s->dev.irq[0]);
367 s->int_stat = 1;
368 }
369 }
370
371 static void eepro100_acknowledge(EEPRO100State * s)
372 {
373 s->scb_stat &= ~s->mem[SCBAck];
374 s->mem[SCBAck] = s->scb_stat;
375 if (s->scb_stat == 0) {
376 disable_interrupt(s);
377 }
378 }
379
380 static void eepro100_interrupt(EEPRO100State * s, uint8_t stat)
381 {
382 uint8_t mask = ~s->mem[SCBIntmask];
383 s->mem[SCBAck] |= stat;
384 stat = s->scb_stat = s->mem[SCBAck];
385 stat &= (mask | 0x0f);
386 //~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
387 if (stat && (mask & 0x01)) {
388 /* SCB mask and SCB Bit M do not disable interrupt. */
389 enable_interrupt(s);
390 } else if (s->int_stat) {
391 disable_interrupt(s);
392 }
393 }
394
395 static void eepro100_cx_interrupt(EEPRO100State * s)
396 {
397 /* CU completed action command. */
398 /* Transmit not ok (82557 only, not in emulation). */
399 eepro100_interrupt(s, 0x80);
400 }
401
402 static void eepro100_cna_interrupt(EEPRO100State * s)
403 {
404 /* CU left the active state. */
405 eepro100_interrupt(s, 0x20);
406 }
407
408 static void eepro100_fr_interrupt(EEPRO100State * s)
409 {
410 /* RU received a complete frame. */
411 eepro100_interrupt(s, 0x40);
412 }
413
414 #if 0
415 static void eepro100_rnr_interrupt(EEPRO100State * s)
416 {
417 /* RU is not ready. */
418 eepro100_interrupt(s, 0x10);
419 }
420 #endif
421
422 static void eepro100_mdi_interrupt(EEPRO100State * s)
423 {
424 /* MDI completed read or write cycle. */
425 eepro100_interrupt(s, 0x08);
426 }
427
428 static void eepro100_swi_interrupt(EEPRO100State * s)
429 {
430 /* Software has requested an interrupt. */
431 eepro100_interrupt(s, 0x04);
432 }
433
434 #if 0
435 static void eepro100_fcp_interrupt(EEPRO100State * s)
436 {
437 /* Flow control pause interrupt (82558 and later). */
438 eepro100_interrupt(s, 0x01);
439 }
440 #endif
441
442 static void pci_reset(EEPRO100State * s)
443 {
444 uint32_t device = s->device;
445 uint8_t *pci_conf = s->dev.config;
446 bool power_management = 1;
447
448 TRACE(OTHER, logout("%p\n", s));
449
450 /* PCI Vendor ID */
451 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
452 /* PCI Device ID depends on device and is set below. */
453 /* PCI Command */
454 /* TODO: this is the default, do not override. */
455 PCI_CONFIG_16(PCI_COMMAND, 0x0000);
456 /* PCI Status */
457 /* TODO: Value at RST# should be 0. */
458 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK);
459 /* PCI Revision ID */
460 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
461 /* TODO: this is the default, do not override. */
462 /* PCI Class Code */
463 PCI_CONFIG_8(PCI_CLASS_PROG, 0x00);
464 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
465 /* PCI Cache Line Size */
466 /* check cache line size!!! */
467 //~ PCI_CONFIG_8(0x0c, 0x00);
468 /* PCI Latency Timer */
469 PCI_CONFIG_8(PCI_LATENCY_TIMER, 0x20); // latency timer = 32 clocks
470 /* PCI Header Type */
471 /* BIST (built-in self test) */
472 /* Expansion ROM Base Address (depends on boot disable!!!) */
473 /* TODO: not needed, set when BAR is registered */
474 PCI_CONFIG_32(PCI_ROM_ADDRESS, PCI_BASE_ADDRESS_SPACE_MEMORY);
475 /* Capability Pointer */
476 /* TODO: revisions with power_management 1 use this but
477 * do not set new capability list bit in status register. */
478 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0xdc);
479 /* Interrupt Line */
480 /* Interrupt Pin */
481 /* TODO: RST# value should be 0 */
482 PCI_CONFIG_8(PCI_INTERRUPT_PIN, 1); // interrupt pin 0
483 /* Minimum Grant */
484 PCI_CONFIG_8(PCI_MIN_GNT, 0x08);
485 /* Maximum Latency */
486 PCI_CONFIG_8(PCI_MAX_LAT, 0x18);
487
488 switch (device) {
489 case i82550:
490 // TODO: check device id.
491 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
492 /* Revision ID: 0x0c, 0x0d, 0x0e. */
493 PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
494 // TODO: check size of statistical counters.
495 s->stats_size = 80;
496 // TODO: check extended tcb support.
497 s->has_extended_tcb_support = 1;
498 break;
499 case i82551:
500 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
501 /* Revision ID: 0x0f, 0x10. */
502 PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
503 // TODO: check size of statistical counters.
504 s->stats_size = 80;
505 s->has_extended_tcb_support = 1;
506 break;
507 case i82557A:
508 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
509 PCI_CONFIG_8(PCI_REVISION_ID, 0x01);
510 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
511 power_management = 0;
512 break;
513 case i82557B:
514 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
515 PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
516 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
517 power_management = 0;
518 break;
519 case i82557C:
520 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
521 PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
522 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
523 power_management = 0;
524 break;
525 case i82558A:
526 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
527 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
528 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
529 PCI_CONFIG_8(PCI_REVISION_ID, 0x04);
530 s->stats_size = 76;
531 s->has_extended_tcb_support = 1;
532 break;
533 case i82558B:
534 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
535 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
536 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
537 PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
538 s->stats_size = 76;
539 s->has_extended_tcb_support = 1;
540 break;
541 case i82559A:
542 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
543 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
544 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
545 PCI_CONFIG_8(PCI_REVISION_ID, 0x06);
546 s->stats_size = 80;
547 s->has_extended_tcb_support = 1;
548 break;
549 case i82559B:
550 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
551 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
552 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
553 PCI_CONFIG_8(PCI_REVISION_ID, 0x07);
554 s->stats_size = 80;
555 s->has_extended_tcb_support = 1;
556 break;
557 case i82559C:
558 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
559 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
560 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
561 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
562 // TODO: Windows wants revision id 0x0c.
563 PCI_CONFIG_8(PCI_REVISION_ID, 0x0c);
564 #if EEPROM_SIZE > 0
565 PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID, 0x8086);
566 PCI_CONFIG_16(PCI_SUBSYSTEM_ID, 0x0040);
567 #endif
568 s->stats_size = 80;
569 s->has_extended_tcb_support = 1;
570 break;
571 case i82559ER:
572 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
573 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
574 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
575 PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
576 s->stats_size = 80;
577 s->has_extended_tcb_support = 1;
578 break;
579 case i82562:
580 // TODO: check device id.
581 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
582 /* TODO: wrong revision id. */
583 PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
584 s->stats_size = 80;
585 s->has_extended_tcb_support = 1;
586 break;
587 default:
588 logout("Device %X is undefined!\n", device);
589 }
590
591 s->configuration[6] |= BIT(5);
592
593 if (s->stats_size == 80) {
594 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
595 if (s->configuration[6] & BIT(2)) {
596 /* TCO statistical counters. */
597 assert(s->configuration[6] & BIT(5));
598 } else {
599 if (s->configuration[6] & BIT(5)) {
600 /* No extended statistical counters, i82557 compatible. */
601 s->stats_size = 64;
602 } else {
603 /* i82558 compatible. */
604 s->stats_size = 76;
605 }
606 }
607 } else {
608 if (s->configuration[6] & BIT(5)) {
609 /* No extended statistical counters. */
610 s->stats_size = 64;
611 }
612 }
613 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
614
615 if (power_management) {
616 /* Power Management Capabilities */
617 PCI_CONFIG_8(0xdc, 0x01);
618 /* Next Item Pointer */
619 /* Capability ID */
620 PCI_CONFIG_16(0xde, 0x7e21);
621 /* TODO: Power Management Control / Status. */
622 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
623 }
624
625 #if EEPROM_SIZE > 0
626 if (device == i82557C || device == i82558B || device == i82559C) {
627 // TODO: get vendor id from EEPROM for i82557C or later.
628 // TODO: get device id from EEPROM for i82557C or later.
629 // TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
630 // TODO: header type is determined by EEPROM for i82559.
631 // TODO: get subsystem id from EEPROM for i82557C or later.
632 // TODO: get subsystem vendor id from EEPROM for i82557C or later.
633 // TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
634 // TODO: capability pointer depends on EEPROM for i82558.
635 logout("Get device id and revision from EEPROM!!!\n");
636 }
637 #endif /* EEPROM_SIZE > 0 */
638 }
639
640 static void nic_selective_reset(EEPRO100State * s)
641 {
642 size_t i;
643 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
644 //~ eeprom93xx_reset(s->eeprom);
645 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
646 eeprom_contents[EEPROM_ID] = 0x4000;
647 if (s->device == i82557B || s->device == i82557C)
648 eeprom_contents[5] = 0x0100;
649 eeprom_contents[EEPROM_PHY_ID] = 1;
650 uint16_t sum = 0;
651 for (i = 0; i < EEPROM_SIZE - 1; i++) {
652 sum += eeprom_contents[i];
653 }
654 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
655 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
656
657 memset(s->mem, 0, sizeof(s->mem));
658 uint32_t val = BIT(21);
659 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
660
661 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
662 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
663 }
664
665 static void nic_reset(void *opaque)
666 {
667 EEPRO100State *s = opaque;
668 TRACE(OTHER, logout("%p\n", s));
669 /* TODO: Clearing of multicast table for selective reset, too? */
670 memset(&s->mult[0], 0, sizeof(s->mult));
671 nic_selective_reset(s);
672 }
673
674 #if defined(DEBUG_EEPRO100)
675 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
676 "Command/Status",
677 "General Pointer",
678 "Port",
679 "EEPROM/Flash Control",
680 "MDI Control",
681 "Receive DMA Byte Count",
682 "Flow Control",
683 "General Status/Control"
684 };
685
686 static char *regname(uint32_t addr)
687 {
688 static char buf[32];
689 if (addr < PCI_IO_SIZE) {
690 const char *r = e100_reg[addr / 4];
691 if (r != 0) {
692 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
693 } else {
694 snprintf(buf, sizeof(buf), "0x%02x", addr);
695 }
696 } else {
697 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
698 }
699 return buf;
700 }
701 #endif /* DEBUG_EEPRO100 */
702
703 #if 0
704 static uint16_t eepro100_read_status(EEPRO100State * s)
705 {
706 uint16_t val = s->status;
707 TRACE(OTHER, logout("val=0x%04x\n", val));
708 return val;
709 }
710
711 static void eepro100_write_status(EEPRO100State * s, uint16_t val)
712 {
713 TRACE(OTHER, logout("val=0x%04x\n", val));
714 s->status = val;
715 }
716 #endif
717
718 /*****************************************************************************
719 *
720 * Command emulation.
721 *
722 ****************************************************************************/
723
724 #if 0
725 static uint16_t eepro100_read_command(EEPRO100State * s)
726 {
727 uint16_t val = 0xffff;
728 //~ TRACE(OTHER, logout("val=0x%04x\n", val));
729 return val;
730 }
731 #endif
732
733 /* Commands that can be put in a command list entry. */
734 enum commands {
735 CmdNOp = 0,
736 CmdIASetup = 1,
737 CmdConfigure = 2,
738 CmdMulticastList = 3,
739 CmdTx = 4,
740 CmdTDR = 5, /* load microcode */
741 CmdDump = 6,
742 CmdDiagnose = 7,
743
744 /* And some extra flags: */
745 CmdSuspend = 0x4000, /* Suspend after completion. */
746 CmdIntr = 0x2000, /* Interrupt after completion. */
747 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
748 };
749
750 static cu_state_t get_cu_state(EEPRO100State * s)
751 {
752 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
753 }
754
755 static void set_cu_state(EEPRO100State * s, cu_state_t state)
756 {
757 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
758 }
759
760 static ru_state_t get_ru_state(EEPRO100State * s)
761 {
762 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
763 }
764
765 static void set_ru_state(EEPRO100State * s, ru_state_t state)
766 {
767 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
768 }
769
770 static void dump_statistics(EEPRO100State * s)
771 {
772 /* Dump statistical data. Most data is never changed by the emulation
773 * and always 0, so we first just copy the whole block and then those
774 * values which really matter.
775 * Number of data should check configuration!!!
776 */
777 cpu_physical_memory_write(s->statsaddr,
778 (uint8_t *) & s->statistics, s->stats_size);
779 stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
780 stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
781 stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
782 stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
783 //~ stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
784 //~ stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
785 //~ missing("CU dump statistical counters");
786 }
787
788 static void tx_command(EEPRO100State *s)
789 {
790 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
791 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
792 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
793 uint8_t buf[2600];
794 uint16_t size = 0;
795 uint32_t tbd_address = s->cb_address + 0x10;
796 TRACE(RXTX, logout
797 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
798 tbd_array, tcb_bytes, s->tx.tbd_count));
799
800 if (tcb_bytes > 2600) {
801 logout("TCB byte count too large, using 2600\n");
802 tcb_bytes = 2600;
803 }
804 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
805 logout
806 ("illegal values of TBD array address and TCB byte count!\n");
807 }
808 assert(tcb_bytes <= sizeof(buf));
809 while (size < tcb_bytes) {
810 uint32_t tx_buffer_address = ldl_phys(tbd_address);
811 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
812 //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
813 tbd_address += 8;
814 TRACE(RXTX, logout
815 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
816 tx_buffer_address, tx_buffer_size));
817 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
818 cpu_physical_memory_read(tx_buffer_address, &buf[size],
819 tx_buffer_size);
820 size += tx_buffer_size;
821 }
822 if (tbd_array == 0xffffffff) {
823 /* Simplified mode. Was already handled by code above. */
824 } else {
825 /* Flexible mode. */
826 uint8_t tbd_count = 0;
827 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
828 /* Extended Flexible TCB. */
829 for (; tbd_count < 2; tbd_count++) {
830 uint32_t tx_buffer_address = ldl_phys(tbd_address);
831 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
832 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
833 tbd_address += 8;
834 TRACE(RXTX, logout
835 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
836 tx_buffer_address, tx_buffer_size));
837 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
838 cpu_physical_memory_read(tx_buffer_address, &buf[size],
839 tx_buffer_size);
840 size += tx_buffer_size;
841 if (tx_buffer_el & 1) {
842 break;
843 }
844 }
845 }
846 tbd_address = tbd_array;
847 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
848 uint32_t tx_buffer_address = ldl_phys(tbd_address);
849 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
850 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
851 tbd_address += 8;
852 TRACE(RXTX, logout
853 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
854 tx_buffer_address, tx_buffer_size));
855 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
856 cpu_physical_memory_read(tx_buffer_address, &buf[size],
857 tx_buffer_size);
858 size += tx_buffer_size;
859 if (tx_buffer_el & 1) {
860 break;
861 }
862 }
863 }
864 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
865 qemu_send_packet(&s->nic->nc, buf, size);
866 s->statistics.tx_good_frames++;
867 /* Transmit with bad status would raise an CX/TNO interrupt.
868 * (82557 only). Emulation never has bad status. */
869 //~ eepro100_cx_interrupt(s);
870 }
871
872 static void set_multicast_list(EEPRO100State *s)
873 {
874 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
875 uint16_t i;
876 memset(&s->mult[0], 0, sizeof(s->mult));
877 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
878 for (i = 0; i < multicast_count; i += 6) {
879 uint8_t multicast_addr[6];
880 cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6);
881 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
882 unsigned mcast_idx = compute_mcast_idx(multicast_addr);
883 assert(mcast_idx < 64);
884 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
885 }
886 }
887
888 static void action_command(EEPRO100State *s)
889 {
890 for (;;) {
891 s->cb_address = s->cu_base + s->cu_offset;
892 cpu_physical_memory_read(s->cb_address, (uint8_t *)&s->tx, sizeof(s->tx));
893 uint16_t status = le16_to_cpu(s->tx.status);
894 uint16_t command = le16_to_cpu(s->tx.command);
895 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
896 status, command, s->tx.link);
897 bool bit_el = ((command & COMMAND_EL) != 0);
898 bool bit_s = ((command & COMMAND_S) != 0);
899 bool bit_i = ((command & COMMAND_I) != 0);
900 bool bit_nc = ((command & COMMAND_NC) != 0);
901 bool success = true;
902 //~ bool bit_sf = ((command & COMMAND_SF) != 0);
903 uint16_t cmd = command & COMMAND_CMD;
904 s->cu_offset = le32_to_cpu(s->tx.link);
905 switch (cmd) {
906 case CmdNOp:
907 /* Do nothing. */
908 break;
909 case CmdIASetup:
910 cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
911 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
912 break;
913 case CmdConfigure:
914 cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
915 sizeof(s->configuration));
916 TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)));
917 break;
918 case CmdMulticastList:
919 set_multicast_list(s);
920 break;
921 case CmdTx:
922 if (bit_nc) {
923 missing("CmdTx: NC = 0");
924 success = false;
925 break;
926 }
927 tx_command(s);
928 break;
929 case CmdTDR:
930 TRACE(OTHER, logout("load microcode\n"));
931 /* Starting with offset 8, the command contains
932 * 64 dwords microcode which we just ignore here. */
933 break;
934 default:
935 missing("undefined command");
936 success = false;
937 break;
938 }
939 /* Write new status. */
940 stw_phys(s->cb_address, status | STATUS_C | (success ? STATUS_OK : 0));
941 if (bit_i) {
942 /* CU completed action. */
943 eepro100_cx_interrupt(s);
944 }
945 if (bit_el) {
946 /* CU becomes idle. Terminate command loop. */
947 set_cu_state(s, cu_idle);
948 eepro100_cna_interrupt(s);
949 break;
950 } else if (bit_s) {
951 /* CU becomes suspended. Terminate command loop. */
952 set_cu_state(s, cu_suspended);
953 eepro100_cna_interrupt(s);
954 break;
955 } else {
956 /* More entries in list. */
957 TRACE(OTHER, logout("CU list with at least one more entry\n"));
958 }
959 }
960 TRACE(OTHER, logout("CU list empty\n"));
961 /* List is empty. Now CU is idle or suspended. */
962 }
963
964 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
965 {
966 switch (val) {
967 case CU_NOP:
968 /* No operation. */
969 break;
970 case CU_START:
971 if (get_cu_state(s) != cu_idle) {
972 /* Intel documentation says that CU must be idle for the CU
973 * start command. Intel driver for Linux also starts the CU
974 * from suspended state. */
975 logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle);
976 //~ assert(!"wrong CU state");
977 }
978 set_cu_state(s, cu_active);
979 s->cu_offset = s->pointer;
980 action_command(s);
981 break;
982 case CU_RESUME:
983 if (get_cu_state(s) != cu_suspended) {
984 logout("bad CU resume from CU state %u\n", get_cu_state(s));
985 /* Workaround for bad Linux eepro100 driver which resumes
986 * from idle state. */
987 //~ missing("cu resume");
988 set_cu_state(s, cu_suspended);
989 }
990 if (get_cu_state(s) == cu_suspended) {
991 TRACE(OTHER, logout("CU resuming\n"));
992 set_cu_state(s, cu_active);
993 action_command(s);
994 }
995 break;
996 case CU_STATSADDR:
997 /* Load dump counters address. */
998 s->statsaddr = s->pointer;
999 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
1000 break;
1001 case CU_SHOWSTATS:
1002 /* Dump statistical counters. */
1003 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
1004 dump_statistics(s);
1005 stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
1006 break;
1007 case CU_CMD_BASE:
1008 /* Load CU base. */
1009 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
1010 s->cu_base = s->pointer;
1011 break;
1012 case CU_DUMPSTATS:
1013 /* Dump and reset statistical counters. */
1014 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
1015 dump_statistics(s);
1016 stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
1017 memset(&s->statistics, 0, sizeof(s->statistics));
1018 break;
1019 case CU_SRESUME:
1020 /* CU static resume. */
1021 missing("CU static resume");
1022 break;
1023 default:
1024 missing("Undefined CU command");
1025 }
1026 }
1027
1028 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
1029 {
1030 switch (val) {
1031 case RU_NOP:
1032 /* No operation. */
1033 break;
1034 case RX_START:
1035 /* RU start. */
1036 if (get_ru_state(s) != ru_idle) {
1037 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
1038 //~ assert(!"wrong RU state");
1039 }
1040 set_ru_state(s, ru_ready);
1041 s->ru_offset = s->pointer;
1042 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
1043 break;
1044 case RX_RESUME:
1045 /* Restart RU. */
1046 if (get_ru_state(s) != ru_suspended) {
1047 logout("RU state is %u, should be %u\n", get_ru_state(s),
1048 ru_suspended);
1049 //~ assert(!"wrong RU state");
1050 }
1051 set_ru_state(s, ru_ready);
1052 break;
1053 case RX_ADDR_LOAD:
1054 /* Load RU base. */
1055 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1056 s->ru_base = s->pointer;
1057 break;
1058 default:
1059 logout("val=0x%02x (undefined RU command)\n", val);
1060 missing("Undefined SU command");
1061 }
1062 }
1063
1064 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1065 {
1066 eepro100_ru_command(s, val & 0x0f);
1067 eepro100_cu_command(s, val & 0xf0);
1068 if ((val) == 0) {
1069 TRACE(OTHER, logout("val=0x%02x\n", val));
1070 }
1071 /* Clear command byte after command was accepted. */
1072 s->mem[SCBCmd] = 0;
1073 }
1074
1075 /*****************************************************************************
1076 *
1077 * EEPROM emulation.
1078 *
1079 ****************************************************************************/
1080
1081 #define EEPROM_CS 0x02
1082 #define EEPROM_SK 0x01
1083 #define EEPROM_DI 0x04
1084 #define EEPROM_DO 0x08
1085
1086 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1087 {
1088 uint16_t val;
1089 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
1090 if (eeprom93xx_read(s->eeprom)) {
1091 val |= EEPROM_DO;
1092 } else {
1093 val &= ~EEPROM_DO;
1094 }
1095 TRACE(EEPROM, logout("val=0x%04x\n", val));
1096 return val;
1097 }
1098
1099 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1100 {
1101 TRACE(EEPROM, logout("val=0x%02x\n", val));
1102
1103 /* mask unwriteable bits */
1104 //~ val = SET_MASKED(val, 0x31, eeprom->value);
1105
1106 int eecs = ((val & EEPROM_CS) != 0);
1107 int eesk = ((val & EEPROM_SK) != 0);
1108 int eedi = ((val & EEPROM_DI) != 0);
1109 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1110 }
1111
1112 static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
1113 {
1114 s->pointer = le32_to_cpu(val);
1115 TRACE(OTHER, logout("val=0x%08x\n", val));
1116 }
1117
1118 /*****************************************************************************
1119 *
1120 * MDI emulation.
1121 *
1122 ****************************************************************************/
1123
1124 #if defined(DEBUG_EEPRO100)
1125 static const char * const mdi_op_name[] = {
1126 "opcode 0",
1127 "write",
1128 "read",
1129 "opcode 3"
1130 };
1131
1132 static const char * const mdi_reg_name[] = {
1133 "Control",
1134 "Status",
1135 "PHY Identification (Word 1)",
1136 "PHY Identification (Word 2)",
1137 "Auto-Negotiation Advertisement",
1138 "Auto-Negotiation Link Partner Ability",
1139 "Auto-Negotiation Expansion"
1140 };
1141
1142 static const char *reg2name(uint8_t reg)
1143 {
1144 static char buffer[10];
1145 const char *p = buffer;
1146 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1147 p = mdi_reg_name[reg];
1148 } else {
1149 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1150 }
1151 return p;
1152 }
1153 #endif /* DEBUG_EEPRO100 */
1154
1155 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1156 {
1157 uint32_t val;
1158 memcpy(&val, &s->mem[0x10], sizeof(val));
1159
1160 #ifdef DEBUG_EEPRO100
1161 uint8_t raiseint = (val & BIT(29)) >> 29;
1162 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1163 uint8_t phy = (val & BITS(25, 21)) >> 21;
1164 uint8_t reg = (val & BITS(20, 16)) >> 16;
1165 uint16_t data = (val & BITS(15, 0));
1166 #endif
1167 /* Emulation takes no time to finish MDI transaction. */
1168 val |= BIT(28);
1169 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1170 val, raiseint, mdi_op_name[opcode], phy,
1171 reg2name(reg), data));
1172 return val;
1173 }
1174
1175 static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1176 {
1177 uint8_t raiseint = (val & BIT(29)) >> 29;
1178 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1179 uint8_t phy = (val & BITS(25, 21)) >> 21;
1180 uint8_t reg = (val & BITS(20, 16)) >> 16;
1181 uint16_t data = (val & BITS(15, 0));
1182 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1183 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1184 if (phy != 1) {
1185 /* Unsupported PHY address. */
1186 //~ logout("phy must be 1 but is %u\n", phy);
1187 data = 0;
1188 } else if (opcode != 1 && opcode != 2) {
1189 /* Unsupported opcode. */
1190 logout("opcode must be 1 or 2 but is %u\n", opcode);
1191 data = 0;
1192 } else if (reg > 6) {
1193 /* Unsupported register. */
1194 logout("register must be 0...6 but is %u\n", reg);
1195 data = 0;
1196 } else {
1197 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1198 val, raiseint, mdi_op_name[opcode], phy,
1199 reg2name(reg), data));
1200 if (opcode == 1) {
1201 /* MDI write */
1202 switch (reg) {
1203 case 0: /* Control Register */
1204 if (data & 0x8000) {
1205 /* Reset status and control registers to default. */
1206 s->mdimem[0] = eepro100_mdi_default[0];
1207 s->mdimem[1] = eepro100_mdi_default[1];
1208 data = s->mdimem[reg];
1209 } else {
1210 /* Restart Auto Configuration = Normal Operation */
1211 data &= ~0x0200;
1212 }
1213 break;
1214 case 1: /* Status Register */
1215 missing("not writable");
1216 data = s->mdimem[reg];
1217 break;
1218 case 2: /* PHY Identification Register (Word 1) */
1219 case 3: /* PHY Identification Register (Word 2) */
1220 missing("not implemented");
1221 break;
1222 case 4: /* Auto-Negotiation Advertisement Register */
1223 case 5: /* Auto-Negotiation Link Partner Ability Register */
1224 break;
1225 case 6: /* Auto-Negotiation Expansion Register */
1226 default:
1227 missing("not implemented");
1228 }
1229 s->mdimem[reg] = data;
1230 } else if (opcode == 2) {
1231 /* MDI read */
1232 switch (reg) {
1233 case 0: /* Control Register */
1234 if (data & 0x8000) {
1235 /* Reset status and control registers to default. */
1236 s->mdimem[0] = eepro100_mdi_default[0];
1237 s->mdimem[1] = eepro100_mdi_default[1];
1238 }
1239 break;
1240 case 1: /* Status Register */
1241 s->mdimem[reg] |= 0x0020;
1242 break;
1243 case 2: /* PHY Identification Register (Word 1) */
1244 case 3: /* PHY Identification Register (Word 2) */
1245 case 4: /* Auto-Negotiation Advertisement Register */
1246 break;
1247 case 5: /* Auto-Negotiation Link Partner Ability Register */
1248 s->mdimem[reg] = 0x41fe;
1249 break;
1250 case 6: /* Auto-Negotiation Expansion Register */
1251 s->mdimem[reg] = 0x0001;
1252 break;
1253 }
1254 data = s->mdimem[reg];
1255 }
1256 /* Emulation takes no time to finish MDI transaction.
1257 * Set MDI bit in SCB status register. */
1258 s->mem[SCBAck] |= 0x08;
1259 val |= BIT(28);
1260 if (raiseint) {
1261 eepro100_mdi_interrupt(s);
1262 }
1263 }
1264 val = (val & 0xffff0000) + data;
1265 memcpy(&s->mem[0x10], &val, sizeof(val));
1266 }
1267
1268 /*****************************************************************************
1269 *
1270 * Port emulation.
1271 *
1272 ****************************************************************************/
1273
1274 #define PORT_SOFTWARE_RESET 0
1275 #define PORT_SELFTEST 1
1276 #define PORT_SELECTIVE_RESET 2
1277 #define PORT_DUMP 3
1278 #define PORT_SELECTION_MASK 3
1279
1280 typedef struct {
1281 uint32_t st_sign; /* Self Test Signature */
1282 uint32_t st_result; /* Self Test Results */
1283 } eepro100_selftest_t;
1284
1285 static uint32_t eepro100_read_port(EEPRO100State * s)
1286 {
1287 return 0;
1288 }
1289
1290 static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1291 {
1292 val = le32_to_cpu(val);
1293 uint32_t address = (val & ~PORT_SELECTION_MASK);
1294 uint8_t selection = (val & PORT_SELECTION_MASK);
1295 switch (selection) {
1296 case PORT_SOFTWARE_RESET:
1297 nic_reset(s);
1298 break;
1299 case PORT_SELFTEST:
1300 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1301 eepro100_selftest_t data;
1302 cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1303 data.st_sign = 0xffffffff;
1304 data.st_result = 0;
1305 cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1306 break;
1307 case PORT_SELECTIVE_RESET:
1308 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1309 nic_selective_reset(s);
1310 break;
1311 default:
1312 logout("val=0x%08x\n", val);
1313 missing("unknown port selection");
1314 }
1315 }
1316
1317 /*****************************************************************************
1318 *
1319 * General hardware emulation.
1320 *
1321 ****************************************************************************/
1322
1323 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1324 {
1325 uint8_t val;
1326 if (addr <= sizeof(s->mem) - sizeof(val)) {
1327 memcpy(&val, &s->mem[addr], sizeof(val));
1328 }
1329
1330 switch (addr) {
1331 case SCBStatus:
1332 //~ val = eepro100_read_status(s);
1333 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1334 break;
1335 case SCBAck:
1336 //~ val = eepro100_read_status(s);
1337 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1338 break;
1339 case SCBCmd:
1340 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1341 //~ val = eepro100_read_command(s);
1342 break;
1343 case SCBIntmask:
1344 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1345 break;
1346 case SCBPort + 3:
1347 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1348 break;
1349 case SCBeeprom:
1350 val = eepro100_read_eeprom(s);
1351 break;
1352 case SCBpmdr: /* Power Management Driver Register */
1353 val = 0;
1354 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1355 break;
1356 case SCBgstat: /* General Status Register */
1357 /* 100 Mbps full duplex, valid link */
1358 val = 0x07;
1359 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1360 break;
1361 default:
1362 logout("addr=%s val=0x%02x\n", regname(addr), val);
1363 missing("unknown byte read");
1364 }
1365 return val;
1366 }
1367
1368 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1369 {
1370 uint16_t val;
1371 if (addr <= sizeof(s->mem) - sizeof(val)) {
1372 memcpy(&val, &s->mem[addr], sizeof(val));
1373 }
1374
1375 switch (addr) {
1376 case SCBStatus:
1377 //~ val = eepro100_read_status(s);
1378 case SCBCmd:
1379 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1380 break;
1381 case SCBeeprom:
1382 val = eepro100_read_eeprom(s);
1383 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1384 break;
1385 default:
1386 logout("addr=%s val=0x%04x\n", regname(addr), val);
1387 missing("unknown word read");
1388 }
1389 return val;
1390 }
1391
1392 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1393 {
1394 uint32_t val;
1395 if (addr <= sizeof(s->mem) - sizeof(val)) {
1396 memcpy(&val, &s->mem[addr], sizeof(val));
1397 }
1398
1399 switch (addr) {
1400 case SCBStatus:
1401 //~ val = eepro100_read_status(s);
1402 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1403 break;
1404 case SCBPointer:
1405 //~ val = eepro100_read_pointer(s);
1406 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1407 break;
1408 case SCBPort:
1409 val = eepro100_read_port(s);
1410 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1411 break;
1412 case SCBCtrlMDI:
1413 val = eepro100_read_mdi(s);
1414 break;
1415 default:
1416 logout("addr=%s val=0x%08x\n", regname(addr), val);
1417 missing("unknown longword read");
1418 }
1419 return val;
1420 }
1421
1422 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1423 {
1424 if (addr <= sizeof(s->mem) - sizeof(val)) {
1425 memcpy(&s->mem[addr], &val, sizeof(val));
1426 }
1427
1428 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1429
1430 switch (addr) {
1431 case SCBStatus:
1432 //~ eepro100_write_status(s, val);
1433 break;
1434 case SCBAck:
1435 eepro100_acknowledge(s);
1436 break;
1437 case SCBCmd:
1438 eepro100_write_command(s, val);
1439 break;
1440 case SCBIntmask:
1441 if (val & BIT(1)) {
1442 eepro100_swi_interrupt(s);
1443 }
1444 eepro100_interrupt(s, 0);
1445 break;
1446 case SCBPort + 3:
1447 case SCBFlow: /* does not exist on 82557 */
1448 case SCBFlow + 1:
1449 case SCBFlow + 2:
1450 case SCBpmdr: /* does not exist on 82557 */
1451 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1452 break;
1453 case SCBeeprom:
1454 eepro100_write_eeprom(s->eeprom, val);
1455 break;
1456 default:
1457 logout("addr=%s val=0x%02x\n", regname(addr), val);
1458 missing("unknown byte write");
1459 }
1460 }
1461
1462 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1463 {
1464 if (addr <= sizeof(s->mem) - sizeof(val)) {
1465 memcpy(&s->mem[addr], &val, sizeof(val));
1466 }
1467
1468 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1469
1470 switch (addr) {
1471 case SCBStatus:
1472 //~ eepro100_write_status(s, val);
1473 eepro100_acknowledge(s);
1474 break;
1475 case SCBCmd:
1476 eepro100_write_command(s, val);
1477 eepro100_write1(s, SCBIntmask, val >> 8);
1478 break;
1479 case SCBeeprom:
1480 eepro100_write_eeprom(s->eeprom, val);
1481 break;
1482 default:
1483 logout("addr=%s val=0x%04x\n", regname(addr), val);
1484 missing("unknown word write");
1485 }
1486 }
1487
1488 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1489 {
1490 if (addr <= sizeof(s->mem) - sizeof(val)) {
1491 memcpy(&s->mem[addr], &val, sizeof(val));
1492 }
1493
1494 switch (addr) {
1495 case SCBPointer:
1496 eepro100_write_pointer(s, val);
1497 break;
1498 case SCBPort:
1499 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1500 eepro100_write_port(s, val);
1501 break;
1502 case SCBCtrlMDI:
1503 eepro100_write_mdi(s, val);
1504 break;
1505 default:
1506 logout("addr=%s val=0x%08x\n", regname(addr), val);
1507 missing("unknown longword write");
1508 }
1509 }
1510
1511 /*****************************************************************************
1512 *
1513 * Port mapped I/O.
1514 *
1515 ****************************************************************************/
1516
1517 static uint32_t ioport_read1(void *opaque, uint32_t addr)
1518 {
1519 EEPRO100State *s = opaque;
1520 //~ logout("addr=%s\n", regname(addr));
1521 return eepro100_read1(s, addr - s->region[1]);
1522 }
1523
1524 static uint32_t ioport_read2(void *opaque, uint32_t addr)
1525 {
1526 EEPRO100State *s = opaque;
1527 return eepro100_read2(s, addr - s->region[1]);
1528 }
1529
1530 static uint32_t ioport_read4(void *opaque, uint32_t addr)
1531 {
1532 EEPRO100State *s = opaque;
1533 return eepro100_read4(s, addr - s->region[1]);
1534 }
1535
1536 static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1537 {
1538 EEPRO100State *s = opaque;
1539 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1540 eepro100_write1(s, addr - s->region[1], val);
1541 }
1542
1543 static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1544 {
1545 EEPRO100State *s = opaque;
1546 eepro100_write2(s, addr - s->region[1], val);
1547 }
1548
1549 static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1550 {
1551 EEPRO100State *s = opaque;
1552 eepro100_write4(s, addr - s->region[1], val);
1553 }
1554
1555 /***********************************************************/
1556 /* PCI EEPRO100 definitions */
1557
1558 static void pci_map(PCIDevice * pci_dev, int region_num,
1559 pcibus_t addr, pcibus_t size, int type)
1560 {
1561 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1562
1563 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1564 "size=0x%08"FMT_PCIBUS", type=%d\n",
1565 region_num, addr, size, type));
1566
1567 assert(region_num == 1);
1568 register_ioport_write(addr, size, 1, ioport_write1, s);
1569 register_ioport_read(addr, size, 1, ioport_read1, s);
1570 register_ioport_write(addr, size, 2, ioport_write2, s);
1571 register_ioport_read(addr, size, 2, ioport_read2, s);
1572 register_ioport_write(addr, size, 4, ioport_write4, s);
1573 register_ioport_read(addr, size, 4, ioport_read4, s);
1574
1575 s->region[region_num] = addr;
1576 }
1577
1578 /*****************************************************************************
1579 *
1580 * Memory mapped I/O.
1581 *
1582 ****************************************************************************/
1583
1584 static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1585 {
1586 EEPRO100State *s = opaque;
1587 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1588 eepro100_write1(s, addr, val);
1589 }
1590
1591 static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1592 {
1593 EEPRO100State *s = opaque;
1594 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1595 eepro100_write2(s, addr, val);
1596 }
1597
1598 static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1599 {
1600 EEPRO100State *s = opaque;
1601 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1602 eepro100_write4(s, addr, val);
1603 }
1604
1605 static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1606 {
1607 EEPRO100State *s = opaque;
1608 //~ logout("addr=%s\n", regname(addr));
1609 return eepro100_read1(s, addr);
1610 }
1611
1612 static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1613 {
1614 EEPRO100State *s = opaque;
1615 //~ logout("addr=%s\n", regname(addr));
1616 return eepro100_read2(s, addr);
1617 }
1618
1619 static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1620 {
1621 EEPRO100State *s = opaque;
1622 //~ logout("addr=%s\n", regname(addr));
1623 return eepro100_read4(s, addr);
1624 }
1625
1626 static CPUWriteMemoryFunc * const pci_mmio_write[] = {
1627 pci_mmio_writeb,
1628 pci_mmio_writew,
1629 pci_mmio_writel
1630 };
1631
1632 static CPUReadMemoryFunc * const pci_mmio_read[] = {
1633 pci_mmio_readb,
1634 pci_mmio_readw,
1635 pci_mmio_readl
1636 };
1637
1638 static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
1639 pcibus_t addr, pcibus_t size, int type)
1640 {
1641 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1642
1643 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1644 "size=0x%08"FMT_PCIBUS", type=%d\n",
1645 region_num, addr, size, type));
1646
1647 if (region_num == 0) {
1648 /* Map control / status registers. */
1649 cpu_register_physical_memory(addr, size, s->mmio_index);
1650 s->region[region_num] = addr;
1651 }
1652 }
1653
1654 static int nic_can_receive(VLANClientState *nc)
1655 {
1656 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1657 TRACE(RXTX, logout("%p\n", s));
1658 return get_ru_state(s) == ru_ready;
1659 //~ return !eepro100_buffer_full(s);
1660 }
1661
1662 static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
1663 {
1664 /* TODO:
1665 * - Magic packets should set bit 30 in power management driver register.
1666 * - Interesting packets should set bit 29 in power management driver register.
1667 */
1668 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1669 uint16_t rfd_status = 0xa000;
1670 static const uint8_t broadcast_macaddr[6] =
1671 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1672
1673 /* TODO: check multiple IA bit. */
1674 if (s->configuration[20] & BIT(6)) {
1675 missing("Multiple IA bit");
1676 return -1;
1677 }
1678
1679 if (s->configuration[8] & 0x80) {
1680 /* CSMA is disabled. */
1681 logout("%p received while CSMA is disabled\n", s);
1682 return -1;
1683 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
1684 /* Short frame and configuration byte 7/0 (discard short receive) set:
1685 * Short frame is discarded */
1686 logout("%p received short frame (%zu byte)\n", s, size);
1687 s->statistics.rx_short_frame_errors++;
1688 //~ return -1;
1689 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
1690 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1691 * Long frames are discarded. */
1692 logout("%p received long frame (%zu byte), ignored\n", s, size);
1693 return -1;
1694 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { // !!!
1695 /* Frame matches individual address. */
1696 /* TODO: check configuration byte 15/4 (ignore U/L). */
1697 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1698 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1699 /* Broadcast frame. */
1700 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1701 rfd_status |= 0x0002;
1702 } else if (buf[0] & 0x01) {
1703 /* Multicast frame. */
1704 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1705 if (s->configuration[21] & BIT(3)) {
1706 /* Multicast all bit is set, receive all multicast frames. */
1707 } else {
1708 unsigned mcast_idx = compute_mcast_idx(buf);
1709 assert(mcast_idx < 64);
1710 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1711 /* Multicast frame is allowed in hash table. */
1712 } else if (s->configuration[15] & BIT(0)) {
1713 /* Promiscuous: receive all. */
1714 rfd_status |= 0x0004;
1715 } else {
1716 TRACE(RXTX, logout("%p multicast ignored\n", s));
1717 return -1;
1718 }
1719 }
1720 /* TODO: Next not for promiscuous mode? */
1721 rfd_status |= 0x0002;
1722 } else if (s->configuration[15] & BIT(0)) {
1723 /* Promiscuous: receive all. */
1724 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1725 rfd_status |= 0x0004;
1726 } else {
1727 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1728 nic_dump(buf, size)));
1729 return size;
1730 }
1731
1732 if (get_ru_state(s) != ru_ready) {
1733 /* No resources available. */
1734 logout("no resources, state=%u\n", get_ru_state(s));
1735 s->statistics.rx_resource_errors++;
1736 //~ assert(!"no resources");
1737 return -1;
1738 }
1739 //~ !!!
1740 //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
1741 eepro100_rx_t rx;
1742 cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
1743 offsetof(eepro100_rx_t, packet));
1744 uint16_t rfd_command = le16_to_cpu(rx.command);
1745 uint16_t rfd_size = le16_to_cpu(rx.size);
1746
1747 if (size > rfd_size) {
1748 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1749 "(%zu bytes); data truncated\n", rfd_size, size);
1750 size = rfd_size;
1751 }
1752 if (size < 64) {
1753 rfd_status |= 0x0080;
1754 }
1755 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1756 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1757 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
1758 rfd_status);
1759 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
1760 /* Early receive interrupt not supported. */
1761 //~ eepro100_er_interrupt(s);
1762 /* Receive CRC Transfer not supported. */
1763 if (s->configuration[18] & BIT(2)) {
1764 missing("Receive CRC Transfer");
1765 return -1;
1766 }
1767 /* TODO: check stripping enable bit. */
1768 //~ assert(!(s->configuration[17] & BIT(0)));
1769 cpu_physical_memory_write(s->ru_base + s->ru_offset +
1770 offsetof(eepro100_rx_t, packet), buf, size);
1771 s->statistics.rx_good_frames++;
1772 eepro100_fr_interrupt(s);
1773 s->ru_offset = le32_to_cpu(rx.link);
1774 if (rfd_command & COMMAND_EL) {
1775 /* EL bit is set, so this was the last frame. */
1776 logout("receive: Running out of frames\n");
1777 set_ru_state(s, ru_suspended);
1778 }
1779 if (rfd_command & COMMAND_S) {
1780 /* S bit is set. */
1781 set_ru_state(s, ru_suspended);
1782 }
1783 return size;
1784 }
1785
1786 static const VMStateDescription vmstate_eepro100 = {
1787 .version_id = 3,
1788 .minimum_version_id = 2,
1789 .minimum_version_id_old = 2,
1790 .fields = (VMStateField []) {
1791 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1792 VMSTATE_UNUSED(32),
1793 VMSTATE_BUFFER(mult, EEPRO100State),
1794 VMSTATE_BUFFER(mem, EEPRO100State),
1795 /* Save all members of struct between scb_stat and mem. */
1796 VMSTATE_UINT8(scb_stat, EEPRO100State),
1797 VMSTATE_UINT8(int_stat, EEPRO100State),
1798 VMSTATE_UNUSED(3*4),
1799 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1800 VMSTATE_UNUSED(19*4),
1801 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1802 /* The eeprom should be saved and restored by its own routines. */
1803 VMSTATE_UINT32(device, EEPRO100State),
1804 /* TODO check device. */
1805 VMSTATE_UINT32(pointer, EEPRO100State),
1806 VMSTATE_UINT32(cu_base, EEPRO100State),
1807 VMSTATE_UINT32(cu_offset, EEPRO100State),
1808 VMSTATE_UINT32(ru_base, EEPRO100State),
1809 VMSTATE_UINT32(ru_offset, EEPRO100State),
1810 VMSTATE_UINT32(statsaddr, EEPRO100State),
1811 /* Save eepro100_stats_t statistics. */
1812 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1813 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1814 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1815 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1816 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1817 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1818 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1819 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1820 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1821 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1822 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1823 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1824 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1825 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1826 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1827 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1828 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1829 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1830 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1831 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1832 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1833 #if 0
1834 VMSTATE_UINT16(status, EEPRO100State),
1835 #endif
1836 /* Configuration bytes. */
1837 VMSTATE_BUFFER(configuration, EEPRO100State),
1838 VMSTATE_END_OF_LIST()
1839 }
1840 };
1841
1842 static void nic_cleanup(VLANClientState *nc)
1843 {
1844 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1845
1846 s->nic = NULL;
1847 }
1848
1849 static int pci_nic_uninit(PCIDevice *pci_dev)
1850 {
1851 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1852
1853 cpu_unregister_io_memory(s->mmio_index);
1854 vmstate_unregister(s->vmstate, s);
1855 eeprom93xx_free(s->eeprom);
1856 qemu_del_vlan_client(&s->nic->nc);
1857 return 0;
1858 }
1859
1860 static NetClientInfo net_eepro100_info = {
1861 .type = NET_CLIENT_TYPE_NIC,
1862 .size = sizeof(NICState),
1863 .can_receive = nic_can_receive,
1864 .receive = nic_receive,
1865 .cleanup = nic_cleanup,
1866 };
1867
1868 static int nic_init(PCIDevice *pci_dev, uint32_t device)
1869 {
1870 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1871
1872 TRACE(OTHER, logout("\n"));
1873
1874 s->device = device;
1875
1876 pci_reset(s);
1877
1878 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1879 * i82559 and later support 64 or 256 word EEPROM. */
1880 s->eeprom = eeprom93xx_new(EEPROM_SIZE);
1881
1882 /* Handler for memory-mapped I/O */
1883 s->mmio_index =
1884 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
1885
1886 pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
1887 PCI_BASE_ADDRESS_SPACE_MEMORY |
1888 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map);
1889 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
1890 pci_map);
1891 pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
1892 pci_mmio_map);
1893
1894 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1895 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1896 assert(s->region[1] == 0);
1897
1898 nic_reset(s);
1899
1900 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1901 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
1902
1903 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1904 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
1905
1906 qemu_register_reset(nic_reset, s);
1907
1908 s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1909 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1910 s->vmstate->name = s->nic->nc.model;
1911 vmstate_register(-1, s->vmstate, s);
1912
1913 return 0;
1914 }
1915
1916 static int pci_i82550_init(PCIDevice *pci_dev)
1917 {
1918 return nic_init(pci_dev, i82550);
1919 }
1920
1921 static int pci_i82551_init(PCIDevice *pci_dev)
1922 {
1923 return nic_init(pci_dev, i82551);
1924 }
1925
1926 static int pci_i82557a_init(PCIDevice *pci_dev)
1927 {
1928 return nic_init(pci_dev, i82557A);
1929 }
1930
1931 static int pci_i82557b_init(PCIDevice *pci_dev)
1932 {
1933 return nic_init(pci_dev, i82557B);
1934 }
1935
1936 static int pci_i82557c_init(PCIDevice *pci_dev)
1937 {
1938 return nic_init(pci_dev, i82557C);
1939 }
1940
1941 static int pci_i82558a_init(PCIDevice *pci_dev)
1942 {
1943 return nic_init(pci_dev, i82558A);
1944 }
1945
1946 static int pci_i82558b_init(PCIDevice *pci_dev)
1947 {
1948 return nic_init(pci_dev, i82558B);
1949 }
1950
1951 static int pci_i82559a_init(PCIDevice *pci_dev)
1952 {
1953 return nic_init(pci_dev, i82559A);
1954 }
1955
1956 static int pci_i82559b_init(PCIDevice *pci_dev)
1957 {
1958 return nic_init(pci_dev, i82559B);
1959 }
1960
1961 static int pci_i82559c_init(PCIDevice *pci_dev)
1962 {
1963 return nic_init(pci_dev, i82559C);
1964 }
1965
1966 static int pci_i82559er_init(PCIDevice *pci_dev)
1967 {
1968 return nic_init(pci_dev, i82559ER);
1969 }
1970
1971 static int pci_i82562_init(PCIDevice *pci_dev)
1972 {
1973 return nic_init(pci_dev, i82562);
1974 }
1975
1976 static PCIDeviceInfo eepro100_info[] = {
1977 {
1978 .qdev.name = "i82550",
1979 .qdev.desc = "Intel i82550 Ethernet",
1980 .qdev.size = sizeof(EEPRO100State),
1981 .init = pci_i82550_init,
1982 .exit = pci_nic_uninit,
1983 .romfile = "gpxe-eepro100-80861209.rom",
1984 .qdev.props = (Property[]) {
1985 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1986 DEFINE_PROP_END_OF_LIST(),
1987 },
1988 },{
1989 .qdev.name = "i82551",
1990 .qdev.desc = "Intel i82551 Ethernet",
1991 .qdev.size = sizeof(EEPRO100State),
1992 .init = pci_i82551_init,
1993 .exit = pci_nic_uninit,
1994 .romfile = "gpxe-eepro100-80861209.rom",
1995 .qdev.props = (Property[]) {
1996 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1997 DEFINE_PROP_END_OF_LIST(),
1998 },
1999 },{
2000 .qdev.name = "i82557a",
2001 .qdev.desc = "Intel i82557A Ethernet",
2002 .qdev.size = sizeof(EEPRO100State),
2003 .init = pci_i82557a_init,
2004 .exit = pci_nic_uninit,
2005 .romfile = "gpxe-eepro100-80861229.rom",
2006 .qdev.props = (Property[]) {
2007 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2008 DEFINE_PROP_END_OF_LIST(),
2009 },
2010 },{
2011 .qdev.name = "i82557b",
2012 .qdev.desc = "Intel i82557B Ethernet",
2013 .qdev.size = sizeof(EEPRO100State),
2014 .init = pci_i82557b_init,
2015 .exit = pci_nic_uninit,
2016 .romfile = "gpxe-eepro100-80861229.rom",
2017 .qdev.props = (Property[]) {
2018 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2019 DEFINE_PROP_END_OF_LIST(),
2020 },
2021 },{
2022 .qdev.name = "i82557c",
2023 .qdev.desc = "Intel i82557C Ethernet",
2024 .qdev.size = sizeof(EEPRO100State),
2025 .init = pci_i82557c_init,
2026 .exit = pci_nic_uninit,
2027 .romfile = "gpxe-eepro100-80861229.rom",
2028 .qdev.props = (Property[]) {
2029 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2030 DEFINE_PROP_END_OF_LIST(),
2031 },
2032 },{
2033 .qdev.name = "i82558a",
2034 .qdev.desc = "Intel i82558A Ethernet",
2035 .qdev.size = sizeof(EEPRO100State),
2036 .init = pci_i82558a_init,
2037 .exit = pci_nic_uninit,
2038 .romfile = "gpxe-eepro100-80861229.rom",
2039 .qdev.props = (Property[]) {
2040 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2041 DEFINE_PROP_END_OF_LIST(),
2042 },
2043 },{
2044 .qdev.name = "i82558b",
2045 .qdev.desc = "Intel i82558B Ethernet",
2046 .qdev.size = sizeof(EEPRO100State),
2047 .init = pci_i82558b_init,
2048 .exit = pci_nic_uninit,
2049 .romfile = "gpxe-eepro100-80861229.rom",
2050 .qdev.props = (Property[]) {
2051 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2052 DEFINE_PROP_END_OF_LIST(),
2053 },
2054 },{
2055 .qdev.name = "i82559a",
2056 .qdev.desc = "Intel i82559A Ethernet",
2057 .qdev.size = sizeof(EEPRO100State),
2058 .init = pci_i82559a_init,
2059 .exit = pci_nic_uninit,
2060 .romfile = "gpxe-eepro100-80861229.rom",
2061 .qdev.props = (Property[]) {
2062 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2063 DEFINE_PROP_END_OF_LIST(),
2064 },
2065 },{
2066 .qdev.name = "i82559b",
2067 .qdev.desc = "Intel i82559B Ethernet",
2068 .qdev.size = sizeof(EEPRO100State),
2069 .init = pci_i82559b_init,
2070 .exit = pci_nic_uninit,
2071 .romfile = "gpxe-eepro100-80861229.rom",
2072 .qdev.props = (Property[]) {
2073 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2074 DEFINE_PROP_END_OF_LIST(),
2075 },
2076 },{
2077 .qdev.name = "i82559c",
2078 .qdev.desc = "Intel i82559C Ethernet",
2079 .qdev.size = sizeof(EEPRO100State),
2080 .init = pci_i82559c_init,
2081 .exit = pci_nic_uninit,
2082 .romfile = "gpxe-eepro100-80861229.rom",
2083 .qdev.props = (Property[]) {
2084 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2085 DEFINE_PROP_END_OF_LIST(),
2086 },
2087 },{
2088 .qdev.name = "i82559er",
2089 .qdev.desc = "Intel i82559ER Ethernet",
2090 .qdev.size = sizeof(EEPRO100State),
2091 .init = pci_i82559er_init,
2092 .exit = pci_nic_uninit,
2093 .romfile = "gpxe-eepro100-80861209.rom",
2094 .qdev.props = (Property[]) {
2095 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2096 DEFINE_PROP_END_OF_LIST(),
2097 },
2098 },{
2099 .qdev.name = "i82562",
2100 .qdev.desc = "Intel i82562 Ethernet",
2101 .qdev.size = sizeof(EEPRO100State),
2102 .init = pci_i82562_init,
2103 .exit = pci_nic_uninit,
2104 .romfile = "gpxe-eepro100-80861209.rom",
2105 .qdev.props = (Property[]) {
2106 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2107 DEFINE_PROP_END_OF_LIST(),
2108 },
2109 },{
2110 /* end of list */
2111 }
2112 };
2113
2114 static void eepro100_register_devices(void)
2115 {
2116 pci_qdev_register_many(eepro100_info);
2117 }
2118
2119 device_init(eepro100_register_devices)
QEMU mirror