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git.proxmox.com Git - mirror_qemu.git/blob - hw/etraxfs_timer.c
4 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "qemu-timer.h"
32 #define RW_TMR0_DIV 0x00
33 #define R_TMR0_DATA 0x04
34 #define RW_TMR0_CTRL 0x08
35 #define RW_TMR1_DIV 0x10
36 #define R_TMR1_DATA 0x14
37 #define RW_TMR1_CTRL 0x18
39 #define RW_WD_CTRL 0x40
40 #define R_WD_STAT 0x44
41 #define RW_INTR_MASK 0x48
42 #define RW_ACK_INTR 0x4c
44 #define R_MASKED_INTR 0x54
49 target_phys_addr_t base
;
54 ptimer_state
*ptimer_t0
;
55 ptimer_state
*ptimer_t1
;
56 ptimer_state
*ptimer_wd
;
59 /* Control registers. */
62 uint32_t rw_tmr0_ctrl
;
66 uint32_t rw_tmr1_ctrl
;
70 uint32_t rw_intr_mask
;
73 uint32_t r_masked_intr
;
76 static uint32_t timer_rinvalid (void *opaque
, target_phys_addr_t addr
)
78 struct fs_timer_t
*t
= opaque
;
79 CPUState
*env
= t
->env
;
80 cpu_abort(env
, "Unsupported short access. reg=%x pc=%x.\n",
85 static uint32_t timer_readl (void *opaque
, target_phys_addr_t addr
)
87 struct fs_timer_t
*t
= opaque
;
88 D(CPUState
*env
= t
->env
);
91 /* Make addr relative to this instances base. */
97 D(printf ("R_TMR1_DATA\n"));
100 r
= qemu_get_clock(vm_clock
) * 10;
106 r
= t
->r_intr
& t
->rw_intr_mask
;
109 D(printf ("%s %x p=%x\n", __func__
, addr
, env
->pc
));
116 timer_winvalid (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
118 struct fs_timer_t
*t
= opaque
;
119 CPUState
*env
= t
->env
;
120 cpu_abort(env
, "Unsupported short access. reg=%x pc=%x.\n",
124 #define TIMER_SLOWDOWN 1
125 static void update_ctrl(struct fs_timer_t
*t
, int tnum
)
129 unsigned int freq_hz
;
135 ctrl
= t
->rw_tmr0_ctrl
;
136 div
= t
->rw_tmr0_div
;
137 timer
= t
->ptimer_t0
;
139 ctrl
= t
->rw_tmr1_ctrl
;
140 div
= t
->rw_tmr1_div
;
141 timer
= t
->ptimer_t1
;
153 D(printf ("extern or disabled timer clock?\n"));
155 case 4: freq_hz
= 29493000; break;
156 case 5: freq_hz
= 32000000; break;
157 case 6: freq_hz
= 32768000; break;
158 case 7: freq_hz
= 100001000; break;
164 D(printf ("freq_hz=%d div=%d\n", freq_hz
, div
));
165 div
= div
* TIMER_SLOWDOWN
;
168 ptimer_set_freq(timer
, freq_hz
);
169 ptimer_set_limit(timer
, div
, 0);
175 ptimer_set_limit(timer
, div
, 1);
183 ptimer_run(timer
, 0);
191 static void timer_update_irq(struct fs_timer_t
*t
)
193 t
->r_intr
&= ~(t
->rw_ack_intr
);
194 t
->r_masked_intr
= t
->r_intr
& t
->rw_intr_mask
;
196 D(printf("%s: masked_intr=%x\n", __func__
, t
->r_masked_intr
));
197 if (t
->r_masked_intr
)
198 qemu_irq_raise(t
->irq
[0]);
200 qemu_irq_lower(t
->irq
[0]);
203 static void timer0_hit(void *opaque
)
205 struct fs_timer_t
*t
= opaque
;
210 static void timer1_hit(void *opaque
)
212 struct fs_timer_t
*t
= opaque
;
217 static void watchdog_hit(void *opaque
)
219 qemu_system_reset_request();
222 static inline void timer_watchdog_update(struct fs_timer_t
*t
, uint32_t value
)
224 unsigned int wd_en
= t
->rw_wd_ctrl
& (1 << 8);
225 unsigned int wd_key
= t
->rw_wd_ctrl
>> 9;
226 unsigned int wd_cnt
= t
->rw_wd_ctrl
& 511;
227 unsigned int new_key
= value
>> 9 & ((1 << 7) - 1);
228 unsigned int new_cmd
= (value
>> 8) & 1;
230 /* If the watchdog is enabled, they written key must match the
231 complement of the previous. */
232 wd_key
= ~wd_key
& ((1 << 7) - 1);
234 if (wd_en
&& wd_key
!= new_key
)
237 D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
238 wd_en
, new_key
, wd_key
, new_cmd
, wd_cnt
));
240 ptimer_set_freq(t
->ptimer_wd
, 760);
243 ptimer_set_count(t
->ptimer_wd
, wd_cnt
);
245 ptimer_run(t
->ptimer_wd
, 1);
247 ptimer_stop(t
->ptimer_wd
);
249 t
->rw_wd_ctrl
= value
;
253 timer_writel (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
255 struct fs_timer_t
*t
= opaque
;
256 CPUState
*env
= t
->env
;
258 /* Make addr relative to this instances base. */
263 t
->rw_tmr0_div
= value
;
266 D(printf ("RW_TMR0_CTRL=%x\n", value
));
267 t
->rw_tmr0_ctrl
= value
;
271 t
->rw_tmr1_div
= value
;
274 D(printf ("RW_TMR1_CTRL=%x\n", value
));
275 t
->rw_tmr1_ctrl
= value
;
279 D(printf ("RW_INTR_MASK=%x\n", value
));
280 t
->rw_intr_mask
= value
;
284 timer_watchdog_update(t
, value
);
287 t
->rw_ack_intr
= value
;
292 printf ("%s %x %x pc=%x\n",
293 __func__
, addr
, value
, env
->pc
);
298 static CPUReadMemoryFunc
*timer_read
[] = {
304 static CPUWriteMemoryFunc
*timer_write
[] = {
310 static void etraxfs_timer_reset(void *opaque
)
312 struct fs_timer_t
*t
= opaque
;
314 ptimer_stop(t
->ptimer_t0
);
315 ptimer_stop(t
->ptimer_t1
);
316 ptimer_stop(t
->ptimer_wd
);
320 qemu_irq_lower(t
->irq
[0]);
323 void etraxfs_timer_init(CPUState
*env
, qemu_irq
*irqs
,
324 target_phys_addr_t base
)
326 static struct fs_timer_t
*t
;
329 t
= qemu_mallocz(sizeof *t
);
333 t
->bh_t0
= qemu_bh_new(timer0_hit
, t
);
334 t
->bh_t1
= qemu_bh_new(timer1_hit
, t
);
335 t
->bh_wd
= qemu_bh_new(watchdog_hit
, t
);
336 t
->ptimer_t0
= ptimer_init(t
->bh_t0
);
337 t
->ptimer_t1
= ptimer_init(t
->bh_t1
);
338 t
->ptimer_wd
= ptimer_init(t
->bh_wd
);
343 timer_regs
= cpu_register_io_memory(0, timer_read
, timer_write
, t
);
344 cpu_register_physical_memory (base
, 0x5c, timer_regs
);
346 qemu_register_reset(etraxfs_timer_reset
, t
);