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1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "qemu-error.h"
33 #include "qemu-timer.h"
34 #include "isa.h"
35 #include "sysbus.h"
36 #include "qdev-addr.h"
37 #include "blockdev.h"
38 #include "sysemu.h"
39 #include "qemu-log.h"
40
41 /********************************************************/
42 /* debug Floppy devices */
43 //#define DEBUG_FLOPPY
44
45 #ifdef DEBUG_FLOPPY
46 #define FLOPPY_DPRINTF(fmt, ...) \
47 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
48 #else
49 #define FLOPPY_DPRINTF(fmt, ...)
50 #endif
51
52 /********************************************************/
53 /* Floppy drive emulation */
54
55 typedef enum FDriveRate {
56 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */
57 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */
58 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */
59 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */
60 } FDriveRate;
61
62 typedef struct FDFormat {
63 FDriveType drive;
64 uint8_t last_sect;
65 uint8_t max_track;
66 uint8_t max_head;
67 FDriveRate rate;
68 } FDFormat;
69
70 static const FDFormat fd_formats[] = {
71 /* First entry is default format */
72 /* 1.44 MB 3"1/2 floppy disks */
73 { FDRIVE_DRV_144, 18, 80, 1, FDRIVE_RATE_500K, },
74 { FDRIVE_DRV_144, 20, 80, 1, FDRIVE_RATE_500K, },
75 { FDRIVE_DRV_144, 21, 80, 1, FDRIVE_RATE_500K, },
76 { FDRIVE_DRV_144, 21, 82, 1, FDRIVE_RATE_500K, },
77 { FDRIVE_DRV_144, 21, 83, 1, FDRIVE_RATE_500K, },
78 { FDRIVE_DRV_144, 22, 80, 1, FDRIVE_RATE_500K, },
79 { FDRIVE_DRV_144, 23, 80, 1, FDRIVE_RATE_500K, },
80 { FDRIVE_DRV_144, 24, 80, 1, FDRIVE_RATE_500K, },
81 /* 2.88 MB 3"1/2 floppy disks */
82 { FDRIVE_DRV_288, 36, 80, 1, FDRIVE_RATE_1M, },
83 { FDRIVE_DRV_288, 39, 80, 1, FDRIVE_RATE_1M, },
84 { FDRIVE_DRV_288, 40, 80, 1, FDRIVE_RATE_1M, },
85 { FDRIVE_DRV_288, 44, 80, 1, FDRIVE_RATE_1M, },
86 { FDRIVE_DRV_288, 48, 80, 1, FDRIVE_RATE_1M, },
87 /* 720 kB 3"1/2 floppy disks */
88 { FDRIVE_DRV_144, 9, 80, 1, FDRIVE_RATE_250K, },
89 { FDRIVE_DRV_144, 10, 80, 1, FDRIVE_RATE_250K, },
90 { FDRIVE_DRV_144, 10, 82, 1, FDRIVE_RATE_250K, },
91 { FDRIVE_DRV_144, 10, 83, 1, FDRIVE_RATE_250K, },
92 { FDRIVE_DRV_144, 13, 80, 1, FDRIVE_RATE_250K, },
93 { FDRIVE_DRV_144, 14, 80, 1, FDRIVE_RATE_250K, },
94 /* 1.2 MB 5"1/4 floppy disks */
95 { FDRIVE_DRV_120, 15, 80, 1, FDRIVE_RATE_500K, },
96 { FDRIVE_DRV_120, 18, 80, 1, FDRIVE_RATE_500K, },
97 { FDRIVE_DRV_120, 18, 82, 1, FDRIVE_RATE_500K, },
98 { FDRIVE_DRV_120, 18, 83, 1, FDRIVE_RATE_500K, },
99 { FDRIVE_DRV_120, 20, 80, 1, FDRIVE_RATE_500K, },
100 /* 720 kB 5"1/4 floppy disks */
101 { FDRIVE_DRV_120, 9, 80, 1, FDRIVE_RATE_250K, },
102 { FDRIVE_DRV_120, 11, 80, 1, FDRIVE_RATE_250K, },
103 /* 360 kB 5"1/4 floppy disks */
104 { FDRIVE_DRV_120, 9, 40, 1, FDRIVE_RATE_300K, },
105 { FDRIVE_DRV_120, 9, 40, 0, FDRIVE_RATE_300K, },
106 { FDRIVE_DRV_120, 10, 41, 1, FDRIVE_RATE_300K, },
107 { FDRIVE_DRV_120, 10, 42, 1, FDRIVE_RATE_300K, },
108 /* 320 kB 5"1/4 floppy disks */
109 { FDRIVE_DRV_120, 8, 40, 1, FDRIVE_RATE_250K, },
110 { FDRIVE_DRV_120, 8, 40, 0, FDRIVE_RATE_250K, },
111 /* 360 kB must match 5"1/4 better than 3"1/2... */
112 { FDRIVE_DRV_144, 9, 80, 0, FDRIVE_RATE_250K, },
113 /* end */
114 { FDRIVE_DRV_NONE, -1, -1, 0, 0, },
115 };
116
117 static void pick_geometry(BlockDriverState *bs, int *nb_heads,
118 int *max_track, int *last_sect,
119 FDriveType drive_in, FDriveType *drive,
120 FDriveRate *rate)
121 {
122 const FDFormat *parse;
123 uint64_t nb_sectors, size;
124 int i, first_match, match;
125
126 bdrv_get_geometry(bs, &nb_sectors);
127 match = -1;
128 first_match = -1;
129 for (i = 0; ; i++) {
130 parse = &fd_formats[i];
131 if (parse->drive == FDRIVE_DRV_NONE) {
132 break;
133 }
134 if (drive_in == parse->drive ||
135 drive_in == FDRIVE_DRV_NONE) {
136 size = (parse->max_head + 1) * parse->max_track *
137 parse->last_sect;
138 if (nb_sectors == size) {
139 match = i;
140 break;
141 }
142 if (first_match == -1) {
143 first_match = i;
144 }
145 }
146 }
147 if (match == -1) {
148 if (first_match == -1) {
149 match = 1;
150 } else {
151 match = first_match;
152 }
153 parse = &fd_formats[match];
154 }
155 *nb_heads = parse->max_head + 1;
156 *max_track = parse->max_track;
157 *last_sect = parse->last_sect;
158 *drive = parse->drive;
159 *rate = parse->rate;
160 }
161
162 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
163 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
164
165 /* Will always be a fixed parameter for us */
166 #define FD_SECTOR_LEN 512
167 #define FD_SECTOR_SC 2 /* Sector size code */
168 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
169
170 typedef struct FDCtrl FDCtrl;
171
172 /* Floppy disk drive emulation */
173 typedef enum FDiskFlags {
174 FDISK_DBL_SIDES = 0x01,
175 } FDiskFlags;
176
177 typedef struct FDrive {
178 FDCtrl *fdctrl;
179 BlockDriverState *bs;
180 /* Drive status */
181 FDriveType drive;
182 uint8_t perpendicular; /* 2.88 MB access mode */
183 /* Position */
184 uint8_t head;
185 uint8_t track;
186 uint8_t sect;
187 /* Media */
188 FDiskFlags flags;
189 uint8_t last_sect; /* Nb sector per track */
190 uint8_t max_track; /* Nb of tracks */
191 uint16_t bps; /* Bytes per sector */
192 uint8_t ro; /* Is read-only */
193 uint8_t media_changed; /* Is media changed */
194 uint8_t media_rate; /* Data rate of medium */
195 } FDrive;
196
197 static void fd_init(FDrive *drv)
198 {
199 /* Drive */
200 drv->drive = FDRIVE_DRV_NONE;
201 drv->perpendicular = 0;
202 /* Disk */
203 drv->last_sect = 0;
204 drv->max_track = 0;
205 }
206
207 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
208
209 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
210 uint8_t last_sect, uint8_t num_sides)
211 {
212 return (((track * num_sides) + head) * last_sect) + sect - 1;
213 }
214
215 /* Returns current position, in sectors, for given drive */
216 static int fd_sector(FDrive *drv)
217 {
218 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
219 NUM_SIDES(drv));
220 }
221
222 /* Seek to a new position:
223 * returns 0 if already on right track
224 * returns 1 if track changed
225 * returns 2 if track is invalid
226 * returns 3 if sector is invalid
227 * returns 4 if seek is disabled
228 */
229 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
230 int enable_seek)
231 {
232 uint32_t sector;
233 int ret;
234
235 if (track > drv->max_track ||
236 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
237 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
238 head, track, sect, 1,
239 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
240 drv->max_track, drv->last_sect);
241 return 2;
242 }
243 if (sect > drv->last_sect) {
244 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
245 head, track, sect, 1,
246 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
247 drv->max_track, drv->last_sect);
248 return 3;
249 }
250 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
251 ret = 0;
252 if (sector != fd_sector(drv)) {
253 #if 0
254 if (!enable_seek) {
255 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
256 " (max=%d %02x %02x)\n",
257 head, track, sect, 1, drv->max_track,
258 drv->last_sect);
259 return 4;
260 }
261 #endif
262 drv->head = head;
263 if (drv->track != track) {
264 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
265 drv->media_changed = 0;
266 }
267 ret = 1;
268 }
269 drv->track = track;
270 drv->sect = sect;
271 }
272
273 if (drv->bs == NULL || !bdrv_is_inserted(drv->bs)) {
274 ret = 2;
275 }
276
277 return ret;
278 }
279
280 /* Set drive back to track 0 */
281 static void fd_recalibrate(FDrive *drv)
282 {
283 FLOPPY_DPRINTF("recalibrate\n");
284 fd_seek(drv, 0, 0, 1, 1);
285 }
286
287 /* Revalidate a disk drive after a disk change */
288 static void fd_revalidate(FDrive *drv)
289 {
290 int nb_heads, max_track, last_sect, ro;
291 FDriveType drive;
292 FDriveRate rate;
293
294 FLOPPY_DPRINTF("revalidate\n");
295 if (drv->bs != NULL) {
296 ro = bdrv_is_read_only(drv->bs);
297 pick_geometry(drv->bs, &nb_heads, &max_track,
298 &last_sect, drv->drive, &drive, &rate);
299 if (!bdrv_is_inserted(drv->bs)) {
300 FLOPPY_DPRINTF("No disk in drive\n");
301 } else {
302 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,
303 max_track, last_sect, ro ? "ro" : "rw");
304 }
305 if (nb_heads == 1) {
306 drv->flags &= ~FDISK_DBL_SIDES;
307 } else {
308 drv->flags |= FDISK_DBL_SIDES;
309 }
310 drv->max_track = max_track;
311 drv->last_sect = last_sect;
312 drv->ro = ro;
313 drv->drive = drive;
314 drv->media_rate = rate;
315 } else {
316 FLOPPY_DPRINTF("No drive connected\n");
317 drv->last_sect = 0;
318 drv->max_track = 0;
319 drv->flags &= ~FDISK_DBL_SIDES;
320 }
321 }
322
323 /********************************************************/
324 /* Intel 82078 floppy disk controller emulation */
325
326 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
327 static void fdctrl_reset_fifo(FDCtrl *fdctrl);
328 static int fdctrl_transfer_handler (void *opaque, int nchan,
329 int dma_pos, int dma_len);
330 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);
331 static FDrive *get_cur_drv(FDCtrl *fdctrl);
332
333 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
334 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
335 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
336 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
337 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
338 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
339 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
340 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
341 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
342 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
343 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
344 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
345
346 enum {
347 FD_DIR_WRITE = 0,
348 FD_DIR_READ = 1,
349 FD_DIR_SCANE = 2,
350 FD_DIR_SCANL = 3,
351 FD_DIR_SCANH = 4,
352 };
353
354 enum {
355 FD_STATE_MULTI = 0x01, /* multi track flag */
356 FD_STATE_FORMAT = 0x02, /* format flag */
357 FD_STATE_SEEK = 0x04, /* seek flag */
358 };
359
360 enum {
361 FD_REG_SRA = 0x00,
362 FD_REG_SRB = 0x01,
363 FD_REG_DOR = 0x02,
364 FD_REG_TDR = 0x03,
365 FD_REG_MSR = 0x04,
366 FD_REG_DSR = 0x04,
367 FD_REG_FIFO = 0x05,
368 FD_REG_DIR = 0x07,
369 FD_REG_CCR = 0x07,
370 };
371
372 enum {
373 FD_CMD_READ_TRACK = 0x02,
374 FD_CMD_SPECIFY = 0x03,
375 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
376 FD_CMD_WRITE = 0x05,
377 FD_CMD_READ = 0x06,
378 FD_CMD_RECALIBRATE = 0x07,
379 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
380 FD_CMD_WRITE_DELETED = 0x09,
381 FD_CMD_READ_ID = 0x0a,
382 FD_CMD_READ_DELETED = 0x0c,
383 FD_CMD_FORMAT_TRACK = 0x0d,
384 FD_CMD_DUMPREG = 0x0e,
385 FD_CMD_SEEK = 0x0f,
386 FD_CMD_VERSION = 0x10,
387 FD_CMD_SCAN_EQUAL = 0x11,
388 FD_CMD_PERPENDICULAR_MODE = 0x12,
389 FD_CMD_CONFIGURE = 0x13,
390 FD_CMD_LOCK = 0x14,
391 FD_CMD_VERIFY = 0x16,
392 FD_CMD_POWERDOWN_MODE = 0x17,
393 FD_CMD_PART_ID = 0x18,
394 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
395 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
396 FD_CMD_SAVE = 0x2e,
397 FD_CMD_OPTION = 0x33,
398 FD_CMD_RESTORE = 0x4e,
399 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
400 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
401 FD_CMD_FORMAT_AND_WRITE = 0xcd,
402 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
403 };
404
405 enum {
406 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
407 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
408 FD_CONFIG_POLL = 0x10, /* Poll enabled */
409 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
410 FD_CONFIG_EIS = 0x40, /* No implied seeks */
411 };
412
413 enum {
414 FD_SR0_DS0 = 0x01,
415 FD_SR0_DS1 = 0x02,
416 FD_SR0_HEAD = 0x04,
417 FD_SR0_EQPMT = 0x10,
418 FD_SR0_SEEK = 0x20,
419 FD_SR0_ABNTERM = 0x40,
420 FD_SR0_INVCMD = 0x80,
421 FD_SR0_RDYCHG = 0xc0,
422 };
423
424 enum {
425 FD_SR1_MA = 0x01, /* Missing address mark */
426 FD_SR1_NW = 0x02, /* Not writable */
427 FD_SR1_EC = 0x80, /* End of cylinder */
428 };
429
430 enum {
431 FD_SR2_SNS = 0x04, /* Scan not satisfied */
432 FD_SR2_SEH = 0x08, /* Scan equal hit */
433 };
434
435 enum {
436 FD_SRA_DIR = 0x01,
437 FD_SRA_nWP = 0x02,
438 FD_SRA_nINDX = 0x04,
439 FD_SRA_HDSEL = 0x08,
440 FD_SRA_nTRK0 = 0x10,
441 FD_SRA_STEP = 0x20,
442 FD_SRA_nDRV2 = 0x40,
443 FD_SRA_INTPEND = 0x80,
444 };
445
446 enum {
447 FD_SRB_MTR0 = 0x01,
448 FD_SRB_MTR1 = 0x02,
449 FD_SRB_WGATE = 0x04,
450 FD_SRB_RDATA = 0x08,
451 FD_SRB_WDATA = 0x10,
452 FD_SRB_DR0 = 0x20,
453 };
454
455 enum {
456 #if MAX_FD == 4
457 FD_DOR_SELMASK = 0x03,
458 #else
459 FD_DOR_SELMASK = 0x01,
460 #endif
461 FD_DOR_nRESET = 0x04,
462 FD_DOR_DMAEN = 0x08,
463 FD_DOR_MOTEN0 = 0x10,
464 FD_DOR_MOTEN1 = 0x20,
465 FD_DOR_MOTEN2 = 0x40,
466 FD_DOR_MOTEN3 = 0x80,
467 };
468
469 enum {
470 #if MAX_FD == 4
471 FD_TDR_BOOTSEL = 0x0c,
472 #else
473 FD_TDR_BOOTSEL = 0x04,
474 #endif
475 };
476
477 enum {
478 FD_DSR_DRATEMASK= 0x03,
479 FD_DSR_PWRDOWN = 0x40,
480 FD_DSR_SWRESET = 0x80,
481 };
482
483 enum {
484 FD_MSR_DRV0BUSY = 0x01,
485 FD_MSR_DRV1BUSY = 0x02,
486 FD_MSR_DRV2BUSY = 0x04,
487 FD_MSR_DRV3BUSY = 0x08,
488 FD_MSR_CMDBUSY = 0x10,
489 FD_MSR_NONDMA = 0x20,
490 FD_MSR_DIO = 0x40,
491 FD_MSR_RQM = 0x80,
492 };
493
494 enum {
495 FD_DIR_DSKCHG = 0x80,
496 };
497
498 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
499 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
500 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
501
502 struct FDCtrl {
503 MemoryRegion iomem;
504 qemu_irq irq;
505 /* Controller state */
506 QEMUTimer *result_timer;
507 int dma_chann;
508 /* Controller's identification */
509 uint8_t version;
510 /* HW */
511 uint8_t sra;
512 uint8_t srb;
513 uint8_t dor;
514 uint8_t dor_vmstate; /* only used as temp during vmstate */
515 uint8_t tdr;
516 uint8_t dsr;
517 uint8_t msr;
518 uint8_t cur_drv;
519 uint8_t status0;
520 uint8_t status1;
521 uint8_t status2;
522 /* Command FIFO */
523 uint8_t *fifo;
524 int32_t fifo_size;
525 uint32_t data_pos;
526 uint32_t data_len;
527 uint8_t data_state;
528 uint8_t data_dir;
529 uint8_t eot; /* last wanted sector */
530 /* States kept only to be returned back */
531 /* precompensation */
532 uint8_t precomp_trk;
533 uint8_t config;
534 uint8_t lock;
535 /* Power down config (also with status regB access mode */
536 uint8_t pwrd;
537 /* Floppy drives */
538 uint8_t num_floppies;
539 /* Sun4m quirks? */
540 int sun4m;
541 FDrive drives[MAX_FD];
542 int reset_sensei;
543 uint32_t check_media_rate;
544 /* Timers state */
545 uint8_t timer0;
546 uint8_t timer1;
547 };
548
549 typedef struct FDCtrlSysBus {
550 SysBusDevice busdev;
551 struct FDCtrl state;
552 } FDCtrlSysBus;
553
554 typedef struct FDCtrlISABus {
555 ISADevice busdev;
556 uint32_t iobase;
557 uint32_t irq;
558 uint32_t dma;
559 struct FDCtrl state;
560 int32_t bootindexA;
561 int32_t bootindexB;
562 } FDCtrlISABus;
563
564 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
565 {
566 FDCtrl *fdctrl = opaque;
567 uint32_t retval;
568
569 reg &= 7;
570 switch (reg) {
571 case FD_REG_SRA:
572 retval = fdctrl_read_statusA(fdctrl);
573 break;
574 case FD_REG_SRB:
575 retval = fdctrl_read_statusB(fdctrl);
576 break;
577 case FD_REG_DOR:
578 retval = fdctrl_read_dor(fdctrl);
579 break;
580 case FD_REG_TDR:
581 retval = fdctrl_read_tape(fdctrl);
582 break;
583 case FD_REG_MSR:
584 retval = fdctrl_read_main_status(fdctrl);
585 break;
586 case FD_REG_FIFO:
587 retval = fdctrl_read_data(fdctrl);
588 break;
589 case FD_REG_DIR:
590 retval = fdctrl_read_dir(fdctrl);
591 break;
592 default:
593 retval = (uint32_t)(-1);
594 break;
595 }
596 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
597
598 return retval;
599 }
600
601 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
602 {
603 FDCtrl *fdctrl = opaque;
604
605 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
606
607 reg &= 7;
608 switch (reg) {
609 case FD_REG_DOR:
610 fdctrl_write_dor(fdctrl, value);
611 break;
612 case FD_REG_TDR:
613 fdctrl_write_tape(fdctrl, value);
614 break;
615 case FD_REG_DSR:
616 fdctrl_write_rate(fdctrl, value);
617 break;
618 case FD_REG_FIFO:
619 fdctrl_write_data(fdctrl, value);
620 break;
621 case FD_REG_CCR:
622 fdctrl_write_ccr(fdctrl, value);
623 break;
624 default:
625 break;
626 }
627 }
628
629 static uint64_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg,
630 unsigned ize)
631 {
632 return fdctrl_read(opaque, (uint32_t)reg);
633 }
634
635 static void fdctrl_write_mem (void *opaque, target_phys_addr_t reg,
636 uint64_t value, unsigned size)
637 {
638 fdctrl_write(opaque, (uint32_t)reg, value);
639 }
640
641 static const MemoryRegionOps fdctrl_mem_ops = {
642 .read = fdctrl_read_mem,
643 .write = fdctrl_write_mem,
644 .endianness = DEVICE_NATIVE_ENDIAN,
645 };
646
647 static const MemoryRegionOps fdctrl_mem_strict_ops = {
648 .read = fdctrl_read_mem,
649 .write = fdctrl_write_mem,
650 .endianness = DEVICE_NATIVE_ENDIAN,
651 .valid = {
652 .min_access_size = 1,
653 .max_access_size = 1,
654 },
655 };
656
657 static bool fdrive_media_changed_needed(void *opaque)
658 {
659 FDrive *drive = opaque;
660
661 return (drive->bs != NULL && drive->media_changed != 1);
662 }
663
664 static const VMStateDescription vmstate_fdrive_media_changed = {
665 .name = "fdrive/media_changed",
666 .version_id = 1,
667 .minimum_version_id = 1,
668 .minimum_version_id_old = 1,
669 .fields = (VMStateField[]) {
670 VMSTATE_UINT8(media_changed, FDrive),
671 VMSTATE_END_OF_LIST()
672 }
673 };
674
675 static bool fdrive_media_rate_needed(void *opaque)
676 {
677 FDrive *drive = opaque;
678
679 return drive->fdctrl->check_media_rate;
680 }
681
682 static const VMStateDescription vmstate_fdrive_media_rate = {
683 .name = "fdrive/media_rate",
684 .version_id = 1,
685 .minimum_version_id = 1,
686 .minimum_version_id_old = 1,
687 .fields = (VMStateField[]) {
688 VMSTATE_UINT8(media_rate, FDrive),
689 VMSTATE_END_OF_LIST()
690 }
691 };
692
693 static const VMStateDescription vmstate_fdrive = {
694 .name = "fdrive",
695 .version_id = 1,
696 .minimum_version_id = 1,
697 .minimum_version_id_old = 1,
698 .fields = (VMStateField[]) {
699 VMSTATE_UINT8(head, FDrive),
700 VMSTATE_UINT8(track, FDrive),
701 VMSTATE_UINT8(sect, FDrive),
702 VMSTATE_END_OF_LIST()
703 },
704 .subsections = (VMStateSubsection[]) {
705 {
706 .vmsd = &vmstate_fdrive_media_changed,
707 .needed = &fdrive_media_changed_needed,
708 } , {
709 .vmsd = &vmstate_fdrive_media_rate,
710 .needed = &fdrive_media_rate_needed,
711 } , {
712 /* empty */
713 }
714 }
715 };
716
717 static void fdc_pre_save(void *opaque)
718 {
719 FDCtrl *s = opaque;
720
721 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
722 }
723
724 static int fdc_post_load(void *opaque, int version_id)
725 {
726 FDCtrl *s = opaque;
727
728 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
729 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
730 return 0;
731 }
732
733 static const VMStateDescription vmstate_fdc = {
734 .name = "fdc",
735 .version_id = 2,
736 .minimum_version_id = 2,
737 .minimum_version_id_old = 2,
738 .pre_save = fdc_pre_save,
739 .post_load = fdc_post_load,
740 .fields = (VMStateField []) {
741 /* Controller State */
742 VMSTATE_UINT8(sra, FDCtrl),
743 VMSTATE_UINT8(srb, FDCtrl),
744 VMSTATE_UINT8(dor_vmstate, FDCtrl),
745 VMSTATE_UINT8(tdr, FDCtrl),
746 VMSTATE_UINT8(dsr, FDCtrl),
747 VMSTATE_UINT8(msr, FDCtrl),
748 VMSTATE_UINT8(status0, FDCtrl),
749 VMSTATE_UINT8(status1, FDCtrl),
750 VMSTATE_UINT8(status2, FDCtrl),
751 /* Command FIFO */
752 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
753 uint8_t),
754 VMSTATE_UINT32(data_pos, FDCtrl),
755 VMSTATE_UINT32(data_len, FDCtrl),
756 VMSTATE_UINT8(data_state, FDCtrl),
757 VMSTATE_UINT8(data_dir, FDCtrl),
758 VMSTATE_UINT8(eot, FDCtrl),
759 /* States kept only to be returned back */
760 VMSTATE_UINT8(timer0, FDCtrl),
761 VMSTATE_UINT8(timer1, FDCtrl),
762 VMSTATE_UINT8(precomp_trk, FDCtrl),
763 VMSTATE_UINT8(config, FDCtrl),
764 VMSTATE_UINT8(lock, FDCtrl),
765 VMSTATE_UINT8(pwrd, FDCtrl),
766 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
767 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
768 vmstate_fdrive, FDrive),
769 VMSTATE_END_OF_LIST()
770 }
771 };
772
773 static void fdctrl_external_reset_sysbus(DeviceState *d)
774 {
775 FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
776 FDCtrl *s = &sys->state;
777
778 fdctrl_reset(s, 0);
779 }
780
781 static void fdctrl_external_reset_isa(DeviceState *d)
782 {
783 FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);
784 FDCtrl *s = &isa->state;
785
786 fdctrl_reset(s, 0);
787 }
788
789 static void fdctrl_handle_tc(void *opaque, int irq, int level)
790 {
791 //FDCtrl *s = opaque;
792
793 if (level) {
794 // XXX
795 FLOPPY_DPRINTF("TC pulsed\n");
796 }
797 }
798
799 /* Change IRQ state */
800 static void fdctrl_reset_irq(FDCtrl *fdctrl)
801 {
802 if (!(fdctrl->sra & FD_SRA_INTPEND))
803 return;
804 FLOPPY_DPRINTF("Reset interrupt\n");
805 qemu_set_irq(fdctrl->irq, 0);
806 fdctrl->sra &= ~FD_SRA_INTPEND;
807 }
808
809 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)
810 {
811 /* Sparc mutation */
812 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
813 /* XXX: not sure */
814 fdctrl->msr &= ~FD_MSR_CMDBUSY;
815 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
816 fdctrl->status0 = status0;
817 return;
818 }
819 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
820 qemu_set_irq(fdctrl->irq, 1);
821 fdctrl->sra |= FD_SRA_INTPEND;
822 }
823
824 fdctrl->reset_sensei = 0;
825 fdctrl->status0 = status0;
826 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
827 }
828
829 /* Reset controller */
830 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
831 {
832 int i;
833
834 FLOPPY_DPRINTF("reset controller\n");
835 fdctrl_reset_irq(fdctrl);
836 /* Initialise controller */
837 fdctrl->sra = 0;
838 fdctrl->srb = 0xc0;
839 if (!fdctrl->drives[1].bs)
840 fdctrl->sra |= FD_SRA_nDRV2;
841 fdctrl->cur_drv = 0;
842 fdctrl->dor = FD_DOR_nRESET;
843 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
844 fdctrl->msr = FD_MSR_RQM;
845 /* FIFO state */
846 fdctrl->data_pos = 0;
847 fdctrl->data_len = 0;
848 fdctrl->data_state = 0;
849 fdctrl->data_dir = FD_DIR_WRITE;
850 for (i = 0; i < MAX_FD; i++)
851 fd_recalibrate(&fdctrl->drives[i]);
852 fdctrl_reset_fifo(fdctrl);
853 if (do_irq) {
854 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
855 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
856 }
857 }
858
859 static inline FDrive *drv0(FDCtrl *fdctrl)
860 {
861 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
862 }
863
864 static inline FDrive *drv1(FDCtrl *fdctrl)
865 {
866 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
867 return &fdctrl->drives[1];
868 else
869 return &fdctrl->drives[0];
870 }
871
872 #if MAX_FD == 4
873 static inline FDrive *drv2(FDCtrl *fdctrl)
874 {
875 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
876 return &fdctrl->drives[2];
877 else
878 return &fdctrl->drives[1];
879 }
880
881 static inline FDrive *drv3(FDCtrl *fdctrl)
882 {
883 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
884 return &fdctrl->drives[3];
885 else
886 return &fdctrl->drives[2];
887 }
888 #endif
889
890 static FDrive *get_cur_drv(FDCtrl *fdctrl)
891 {
892 switch (fdctrl->cur_drv) {
893 case 0: return drv0(fdctrl);
894 case 1: return drv1(fdctrl);
895 #if MAX_FD == 4
896 case 2: return drv2(fdctrl);
897 case 3: return drv3(fdctrl);
898 #endif
899 default: return NULL;
900 }
901 }
902
903 /* Status A register : 0x00 (read-only) */
904 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
905 {
906 uint32_t retval = fdctrl->sra;
907
908 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
909
910 return retval;
911 }
912
913 /* Status B register : 0x01 (read-only) */
914 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
915 {
916 uint32_t retval = fdctrl->srb;
917
918 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
919
920 return retval;
921 }
922
923 /* Digital output register : 0x02 */
924 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
925 {
926 uint32_t retval = fdctrl->dor;
927
928 /* Selected drive */
929 retval |= fdctrl->cur_drv;
930 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
931
932 return retval;
933 }
934
935 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
936 {
937 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
938
939 /* Motors */
940 if (value & FD_DOR_MOTEN0)
941 fdctrl->srb |= FD_SRB_MTR0;
942 else
943 fdctrl->srb &= ~FD_SRB_MTR0;
944 if (value & FD_DOR_MOTEN1)
945 fdctrl->srb |= FD_SRB_MTR1;
946 else
947 fdctrl->srb &= ~FD_SRB_MTR1;
948
949 /* Drive */
950 if (value & 1)
951 fdctrl->srb |= FD_SRB_DR0;
952 else
953 fdctrl->srb &= ~FD_SRB_DR0;
954
955 /* Reset */
956 if (!(value & FD_DOR_nRESET)) {
957 if (fdctrl->dor & FD_DOR_nRESET) {
958 FLOPPY_DPRINTF("controller enter RESET state\n");
959 }
960 } else {
961 if (!(fdctrl->dor & FD_DOR_nRESET)) {
962 FLOPPY_DPRINTF("controller out of RESET state\n");
963 fdctrl_reset(fdctrl, 1);
964 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
965 }
966 }
967 /* Selected drive */
968 fdctrl->cur_drv = value & FD_DOR_SELMASK;
969
970 fdctrl->dor = value;
971 }
972
973 /* Tape drive register : 0x03 */
974 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
975 {
976 uint32_t retval = fdctrl->tdr;
977
978 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
979
980 return retval;
981 }
982
983 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
984 {
985 /* Reset mode */
986 if (!(fdctrl->dor & FD_DOR_nRESET)) {
987 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
988 return;
989 }
990 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
991 /* Disk boot selection indicator */
992 fdctrl->tdr = value & FD_TDR_BOOTSEL;
993 /* Tape indicators: never allow */
994 }
995
996 /* Main status register : 0x04 (read) */
997 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
998 {
999 uint32_t retval = fdctrl->msr;
1000
1001 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1002 fdctrl->dor |= FD_DOR_nRESET;
1003
1004 /* Sparc mutation */
1005 if (fdctrl->sun4m) {
1006 retval |= FD_MSR_DIO;
1007 fdctrl_reset_irq(fdctrl);
1008 };
1009
1010 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
1011
1012 return retval;
1013 }
1014
1015 /* Data select rate register : 0x04 (write) */
1016 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
1017 {
1018 /* Reset mode */
1019 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1020 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1021 return;
1022 }
1023 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
1024 /* Reset: autoclear */
1025 if (value & FD_DSR_SWRESET) {
1026 fdctrl->dor &= ~FD_DOR_nRESET;
1027 fdctrl_reset(fdctrl, 1);
1028 fdctrl->dor |= FD_DOR_nRESET;
1029 }
1030 if (value & FD_DSR_PWRDOWN) {
1031 fdctrl_reset(fdctrl, 1);
1032 }
1033 fdctrl->dsr = value;
1034 }
1035
1036 /* Configuration control register: 0x07 (write) */
1037 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
1038 {
1039 /* Reset mode */
1040 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1041 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1042 return;
1043 }
1044 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
1045
1046 /* Only the rate selection bits used in AT mode, and we
1047 * store those in the DSR.
1048 */
1049 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
1050 (value & FD_DSR_DRATEMASK);
1051 }
1052
1053 static int fdctrl_media_changed(FDrive *drv)
1054 {
1055 return drv->media_changed;
1056 }
1057
1058 /* Digital input register : 0x07 (read-only) */
1059 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
1060 {
1061 uint32_t retval = 0;
1062
1063 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
1064 retval |= FD_DIR_DSKCHG;
1065 }
1066 if (retval != 0) {
1067 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
1068 }
1069
1070 return retval;
1071 }
1072
1073 /* FIFO state control */
1074 static void fdctrl_reset_fifo(FDCtrl *fdctrl)
1075 {
1076 fdctrl->data_dir = FD_DIR_WRITE;
1077 fdctrl->data_pos = 0;
1078 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1079 }
1080
1081 /* Set FIFO status for the host to read */
1082 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, uint8_t status0)
1083 {
1084 fdctrl->data_dir = FD_DIR_READ;
1085 fdctrl->data_len = fifo_len;
1086 fdctrl->data_pos = 0;
1087 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1088 if (status0) {
1089 fdctrl_raise_irq(fdctrl, status0);
1090 }
1091 }
1092
1093 /* Set an error: unimplemented/unknown command */
1094 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
1095 {
1096 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
1097 fdctrl->fifo[0]);
1098 fdctrl->fifo[0] = FD_SR0_INVCMD;
1099 fdctrl_set_fifo(fdctrl, 1, 0);
1100 }
1101
1102 /* Seek to next sector
1103 * returns 0 when end of track reached (for DBL_SIDES on head 1)
1104 * otherwise returns 1
1105 */
1106 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
1107 {
1108 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1109 cur_drv->head, cur_drv->track, cur_drv->sect,
1110 fd_sector(cur_drv));
1111 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1112 error in fact */
1113 uint8_t new_head = cur_drv->head;
1114 uint8_t new_track = cur_drv->track;
1115 uint8_t new_sect = cur_drv->sect;
1116
1117 int ret = 1;
1118
1119 if (new_sect >= cur_drv->last_sect ||
1120 new_sect == fdctrl->eot) {
1121 new_sect = 1;
1122 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1123 if (new_head == 0 &&
1124 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1125 new_head = 1;
1126 } else {
1127 new_head = 0;
1128 new_track++;
1129 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) {
1130 ret = 0;
1131 }
1132 }
1133 } else {
1134 new_track++;
1135 ret = 0;
1136 }
1137 if (ret == 1) {
1138 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1139 new_head, new_track, new_sect, fd_sector(cur_drv));
1140 }
1141 } else {
1142 new_sect++;
1143 }
1144 fd_seek(cur_drv, new_head, new_track, new_sect, 1);
1145 return ret;
1146 }
1147
1148 /* Callback for transfer end (stop or abort) */
1149 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1150 uint8_t status1, uint8_t status2)
1151 {
1152 FDrive *cur_drv;
1153
1154 cur_drv = get_cur_drv(fdctrl);
1155 fdctrl->status0 = status0 | FD_SR0_SEEK | (cur_drv->head << 2) |
1156 GET_CUR_DRV(fdctrl);
1157
1158 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1159 status0, status1, status2, fdctrl->status0);
1160 fdctrl->fifo[0] = fdctrl->status0;
1161 fdctrl->fifo[1] = status1;
1162 fdctrl->fifo[2] = status2;
1163 fdctrl->fifo[3] = cur_drv->track;
1164 fdctrl->fifo[4] = cur_drv->head;
1165 fdctrl->fifo[5] = cur_drv->sect;
1166 fdctrl->fifo[6] = FD_SECTOR_SC;
1167 fdctrl->data_dir = FD_DIR_READ;
1168 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1169 DMA_release_DREQ(fdctrl->dma_chann);
1170 }
1171 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1172 fdctrl->msr &= ~FD_MSR_NONDMA;
1173 fdctrl_set_fifo(fdctrl, 7, fdctrl->status0);
1174 }
1175
1176 /* Prepare a data transfer (either DMA or FIFO) */
1177 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1178 {
1179 FDrive *cur_drv;
1180 uint8_t kh, kt, ks;
1181 int did_seek = 0;
1182
1183 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1184 cur_drv = get_cur_drv(fdctrl);
1185 kt = fdctrl->fifo[2];
1186 kh = fdctrl->fifo[3];
1187 ks = fdctrl->fifo[4];
1188 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1189 GET_CUR_DRV(fdctrl), kh, kt, ks,
1190 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1191 NUM_SIDES(cur_drv)));
1192 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1193 case 2:
1194 /* sect too big */
1195 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1196 fdctrl->fifo[3] = kt;
1197 fdctrl->fifo[4] = kh;
1198 fdctrl->fifo[5] = ks;
1199 return;
1200 case 3:
1201 /* track too big */
1202 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1203 fdctrl->fifo[3] = kt;
1204 fdctrl->fifo[4] = kh;
1205 fdctrl->fifo[5] = ks;
1206 return;
1207 case 4:
1208 /* No seek enabled */
1209 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1210 fdctrl->fifo[3] = kt;
1211 fdctrl->fifo[4] = kh;
1212 fdctrl->fifo[5] = ks;
1213 return;
1214 case 1:
1215 did_seek = 1;
1216 break;
1217 default:
1218 break;
1219 }
1220
1221 /* Check the data rate. If the programmed data rate does not match
1222 * the currently inserted medium, the operation has to fail. */
1223 if (fdctrl->check_media_rate &&
1224 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1225 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1226 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1227 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1228 fdctrl->fifo[3] = kt;
1229 fdctrl->fifo[4] = kh;
1230 fdctrl->fifo[5] = ks;
1231 return;
1232 }
1233
1234 /* Set the FIFO state */
1235 fdctrl->data_dir = direction;
1236 fdctrl->data_pos = 0;
1237 fdctrl->msr |= FD_MSR_CMDBUSY;
1238 if (fdctrl->fifo[0] & 0x80)
1239 fdctrl->data_state |= FD_STATE_MULTI;
1240 else
1241 fdctrl->data_state &= ~FD_STATE_MULTI;
1242 if (did_seek)
1243 fdctrl->data_state |= FD_STATE_SEEK;
1244 else
1245 fdctrl->data_state &= ~FD_STATE_SEEK;
1246 if (fdctrl->fifo[5] == 00) {
1247 fdctrl->data_len = fdctrl->fifo[8];
1248 } else {
1249 int tmp;
1250 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1251 tmp = (fdctrl->fifo[6] - ks + 1);
1252 if (fdctrl->fifo[0] & 0x80)
1253 tmp += fdctrl->fifo[6];
1254 fdctrl->data_len *= tmp;
1255 }
1256 fdctrl->eot = fdctrl->fifo[6];
1257 if (fdctrl->dor & FD_DOR_DMAEN) {
1258 int dma_mode;
1259 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1260 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1261 dma_mode = (dma_mode >> 2) & 3;
1262 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1263 dma_mode, direction,
1264 (128 << fdctrl->fifo[5]) *
1265 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1266 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1267 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1268 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1269 (direction == FD_DIR_READ && dma_mode == 1)) {
1270 /* No access is allowed until DMA transfer has completed */
1271 fdctrl->msr &= ~FD_MSR_RQM;
1272 /* Now, we just have to wait for the DMA controller to
1273 * recall us...
1274 */
1275 DMA_hold_DREQ(fdctrl->dma_chann);
1276 DMA_schedule(fdctrl->dma_chann);
1277 return;
1278 } else {
1279 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode,
1280 direction);
1281 }
1282 }
1283 FLOPPY_DPRINTF("start non-DMA transfer\n");
1284 fdctrl->msr |= FD_MSR_NONDMA;
1285 if (direction != FD_DIR_WRITE)
1286 fdctrl->msr |= FD_MSR_DIO;
1287 /* IO based transfer: calculate len */
1288 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1289 }
1290
1291 /* Prepare a transfer of deleted data */
1292 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1293 {
1294 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
1295
1296 /* We don't handle deleted data,
1297 * so we don't return *ANYTHING*
1298 */
1299 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1300 }
1301
1302 /* handlers for DMA transfers */
1303 static int fdctrl_transfer_handler (void *opaque, int nchan,
1304 int dma_pos, int dma_len)
1305 {
1306 FDCtrl *fdctrl;
1307 FDrive *cur_drv;
1308 int len, start_pos, rel_pos;
1309 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1310
1311 fdctrl = opaque;
1312 if (fdctrl->msr & FD_MSR_RQM) {
1313 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1314 return 0;
1315 }
1316 cur_drv = get_cur_drv(fdctrl);
1317 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1318 fdctrl->data_dir == FD_DIR_SCANH)
1319 status2 = FD_SR2_SNS;
1320 if (dma_len > fdctrl->data_len)
1321 dma_len = fdctrl->data_len;
1322 if (cur_drv->bs == NULL) {
1323 if (fdctrl->data_dir == FD_DIR_WRITE)
1324 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1325 else
1326 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1327 len = 0;
1328 goto transfer_error;
1329 }
1330 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1331 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1332 len = dma_len - fdctrl->data_pos;
1333 if (len + rel_pos > FD_SECTOR_LEN)
1334 len = FD_SECTOR_LEN - rel_pos;
1335 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1336 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1337 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1338 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1339 fd_sector(cur_drv) * FD_SECTOR_LEN);
1340 if (fdctrl->data_dir != FD_DIR_WRITE ||
1341 len < FD_SECTOR_LEN || rel_pos != 0) {
1342 /* READ & SCAN commands and realign to a sector for WRITE */
1343 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1344 fdctrl->fifo, 1) < 0) {
1345 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1346 fd_sector(cur_drv));
1347 /* Sure, image size is too small... */
1348 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1349 }
1350 }
1351 switch (fdctrl->data_dir) {
1352 case FD_DIR_READ:
1353 /* READ commands */
1354 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1355 fdctrl->data_pos, len);
1356 break;
1357 case FD_DIR_WRITE:
1358 /* WRITE commands */
1359 if (cur_drv->ro) {
1360 /* Handle readonly medium early, no need to do DMA, touch the
1361 * LED or attempt any writes. A real floppy doesn't attempt
1362 * to write to readonly media either. */
1363 fdctrl_stop_transfer(fdctrl,
1364 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1365 0x00);
1366 goto transfer_error;
1367 }
1368
1369 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1370 fdctrl->data_pos, len);
1371 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1372 fdctrl->fifo, 1) < 0) {
1373 FLOPPY_DPRINTF("error writing sector %d\n",
1374 fd_sector(cur_drv));
1375 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1376 goto transfer_error;
1377 }
1378 break;
1379 default:
1380 /* SCAN commands */
1381 {
1382 uint8_t tmpbuf[FD_SECTOR_LEN];
1383 int ret;
1384 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1385 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1386 if (ret == 0) {
1387 status2 = FD_SR2_SEH;
1388 goto end_transfer;
1389 }
1390 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1391 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1392 status2 = 0x00;
1393 goto end_transfer;
1394 }
1395 }
1396 break;
1397 }
1398 fdctrl->data_pos += len;
1399 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1400 if (rel_pos == 0) {
1401 /* Seek to next sector */
1402 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1403 break;
1404 }
1405 }
1406 end_transfer:
1407 len = fdctrl->data_pos - start_pos;
1408 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1409 fdctrl->data_pos, len, fdctrl->data_len);
1410 if (fdctrl->data_dir == FD_DIR_SCANE ||
1411 fdctrl->data_dir == FD_DIR_SCANL ||
1412 fdctrl->data_dir == FD_DIR_SCANH)
1413 status2 = FD_SR2_SEH;
1414 if (FD_DID_SEEK(fdctrl->data_state))
1415 status0 |= FD_SR0_SEEK;
1416 fdctrl->data_len -= len;
1417 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1418 transfer_error:
1419
1420 return len;
1421 }
1422
1423 /* Data register : 0x05 */
1424 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1425 {
1426 FDrive *cur_drv;
1427 uint32_t retval = 0;
1428 int pos;
1429
1430 cur_drv = get_cur_drv(fdctrl);
1431 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1432 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1433 FLOPPY_DPRINTF("error: controller not ready for reading\n");
1434 return 0;
1435 }
1436 pos = fdctrl->data_pos;
1437 if (fdctrl->msr & FD_MSR_NONDMA) {
1438 pos %= FD_SECTOR_LEN;
1439 if (pos == 0) {
1440 if (fdctrl->data_pos != 0)
1441 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1442 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1443 fd_sector(cur_drv));
1444 return 0;
1445 }
1446 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1447 FLOPPY_DPRINTF("error getting sector %d\n",
1448 fd_sector(cur_drv));
1449 /* Sure, image size is too small... */
1450 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1451 }
1452 }
1453 }
1454 retval = fdctrl->fifo[pos];
1455 if (++fdctrl->data_pos == fdctrl->data_len) {
1456 fdctrl->data_pos = 0;
1457 /* Switch from transfer mode to status mode
1458 * then from status mode to command mode
1459 */
1460 if (fdctrl->msr & FD_MSR_NONDMA) {
1461 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1462 } else {
1463 fdctrl_reset_fifo(fdctrl);
1464 fdctrl_reset_irq(fdctrl);
1465 }
1466 }
1467 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1468
1469 return retval;
1470 }
1471
1472 static void fdctrl_format_sector(FDCtrl *fdctrl)
1473 {
1474 FDrive *cur_drv;
1475 uint8_t kh, kt, ks;
1476
1477 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1478 cur_drv = get_cur_drv(fdctrl);
1479 kt = fdctrl->fifo[6];
1480 kh = fdctrl->fifo[7];
1481 ks = fdctrl->fifo[8];
1482 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1483 GET_CUR_DRV(fdctrl), kh, kt, ks,
1484 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1485 NUM_SIDES(cur_drv)));
1486 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1487 case 2:
1488 /* sect too big */
1489 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1490 fdctrl->fifo[3] = kt;
1491 fdctrl->fifo[4] = kh;
1492 fdctrl->fifo[5] = ks;
1493 return;
1494 case 3:
1495 /* track too big */
1496 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1497 fdctrl->fifo[3] = kt;
1498 fdctrl->fifo[4] = kh;
1499 fdctrl->fifo[5] = ks;
1500 return;
1501 case 4:
1502 /* No seek enabled */
1503 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1504 fdctrl->fifo[3] = kt;
1505 fdctrl->fifo[4] = kh;
1506 fdctrl->fifo[5] = ks;
1507 return;
1508 case 1:
1509 fdctrl->data_state |= FD_STATE_SEEK;
1510 break;
1511 default:
1512 break;
1513 }
1514 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1515 if (cur_drv->bs == NULL ||
1516 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1517 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
1518 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1519 } else {
1520 if (cur_drv->sect == cur_drv->last_sect) {
1521 fdctrl->data_state &= ~FD_STATE_FORMAT;
1522 /* Last sector done */
1523 if (FD_DID_SEEK(fdctrl->data_state))
1524 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1525 else
1526 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1527 } else {
1528 /* More to do */
1529 fdctrl->data_pos = 0;
1530 fdctrl->data_len = 4;
1531 }
1532 }
1533 }
1534
1535 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1536 {
1537 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1538 fdctrl->fifo[0] = fdctrl->lock << 4;
1539 fdctrl_set_fifo(fdctrl, 1, 0);
1540 }
1541
1542 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1543 {
1544 FDrive *cur_drv = get_cur_drv(fdctrl);
1545
1546 /* Drives position */
1547 fdctrl->fifo[0] = drv0(fdctrl)->track;
1548 fdctrl->fifo[1] = drv1(fdctrl)->track;
1549 #if MAX_FD == 4
1550 fdctrl->fifo[2] = drv2(fdctrl)->track;
1551 fdctrl->fifo[3] = drv3(fdctrl)->track;
1552 #else
1553 fdctrl->fifo[2] = 0;
1554 fdctrl->fifo[3] = 0;
1555 #endif
1556 /* timers */
1557 fdctrl->fifo[4] = fdctrl->timer0;
1558 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1559 fdctrl->fifo[6] = cur_drv->last_sect;
1560 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1561 (cur_drv->perpendicular << 2);
1562 fdctrl->fifo[8] = fdctrl->config;
1563 fdctrl->fifo[9] = fdctrl->precomp_trk;
1564 fdctrl_set_fifo(fdctrl, 10, 0);
1565 }
1566
1567 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1568 {
1569 /* Controller's version */
1570 fdctrl->fifo[0] = fdctrl->version;
1571 fdctrl_set_fifo(fdctrl, 1, 0);
1572 }
1573
1574 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1575 {
1576 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1577 fdctrl_set_fifo(fdctrl, 1, 0);
1578 }
1579
1580 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1581 {
1582 FDrive *cur_drv = get_cur_drv(fdctrl);
1583
1584 /* Drives position */
1585 drv0(fdctrl)->track = fdctrl->fifo[3];
1586 drv1(fdctrl)->track = fdctrl->fifo[4];
1587 #if MAX_FD == 4
1588 drv2(fdctrl)->track = fdctrl->fifo[5];
1589 drv3(fdctrl)->track = fdctrl->fifo[6];
1590 #endif
1591 /* timers */
1592 fdctrl->timer0 = fdctrl->fifo[7];
1593 fdctrl->timer1 = fdctrl->fifo[8];
1594 cur_drv->last_sect = fdctrl->fifo[9];
1595 fdctrl->lock = fdctrl->fifo[10] >> 7;
1596 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1597 fdctrl->config = fdctrl->fifo[11];
1598 fdctrl->precomp_trk = fdctrl->fifo[12];
1599 fdctrl->pwrd = fdctrl->fifo[13];
1600 fdctrl_reset_fifo(fdctrl);
1601 }
1602
1603 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1604 {
1605 FDrive *cur_drv = get_cur_drv(fdctrl);
1606
1607 fdctrl->fifo[0] = 0;
1608 fdctrl->fifo[1] = 0;
1609 /* Drives position */
1610 fdctrl->fifo[2] = drv0(fdctrl)->track;
1611 fdctrl->fifo[3] = drv1(fdctrl)->track;
1612 #if MAX_FD == 4
1613 fdctrl->fifo[4] = drv2(fdctrl)->track;
1614 fdctrl->fifo[5] = drv3(fdctrl)->track;
1615 #else
1616 fdctrl->fifo[4] = 0;
1617 fdctrl->fifo[5] = 0;
1618 #endif
1619 /* timers */
1620 fdctrl->fifo[6] = fdctrl->timer0;
1621 fdctrl->fifo[7] = fdctrl->timer1;
1622 fdctrl->fifo[8] = cur_drv->last_sect;
1623 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1624 (cur_drv->perpendicular << 2);
1625 fdctrl->fifo[10] = fdctrl->config;
1626 fdctrl->fifo[11] = fdctrl->precomp_trk;
1627 fdctrl->fifo[12] = fdctrl->pwrd;
1628 fdctrl->fifo[13] = 0;
1629 fdctrl->fifo[14] = 0;
1630 fdctrl_set_fifo(fdctrl, 15, 0);
1631 }
1632
1633 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1634 {
1635 FDrive *cur_drv = get_cur_drv(fdctrl);
1636
1637 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1638 qemu_mod_timer(fdctrl->result_timer,
1639 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 50));
1640 }
1641
1642 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1643 {
1644 FDrive *cur_drv;
1645
1646 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1647 cur_drv = get_cur_drv(fdctrl);
1648 fdctrl->data_state |= FD_STATE_FORMAT;
1649 if (fdctrl->fifo[0] & 0x80)
1650 fdctrl->data_state |= FD_STATE_MULTI;
1651 else
1652 fdctrl->data_state &= ~FD_STATE_MULTI;
1653 fdctrl->data_state &= ~FD_STATE_SEEK;
1654 cur_drv->bps =
1655 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1656 #if 0
1657 cur_drv->last_sect =
1658 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1659 fdctrl->fifo[3] / 2;
1660 #else
1661 cur_drv->last_sect = fdctrl->fifo[3];
1662 #endif
1663 /* TODO: implement format using DMA expected by the Bochs BIOS
1664 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1665 * the sector with the specified fill byte
1666 */
1667 fdctrl->data_state &= ~FD_STATE_FORMAT;
1668 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1669 }
1670
1671 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1672 {
1673 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1674 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1675 if (fdctrl->fifo[2] & 1)
1676 fdctrl->dor &= ~FD_DOR_DMAEN;
1677 else
1678 fdctrl->dor |= FD_DOR_DMAEN;
1679 /* No result back */
1680 fdctrl_reset_fifo(fdctrl);
1681 }
1682
1683 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1684 {
1685 FDrive *cur_drv;
1686
1687 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1688 cur_drv = get_cur_drv(fdctrl);
1689 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1690 /* 1 Byte status back */
1691 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1692 (cur_drv->track == 0 ? 0x10 : 0x00) |
1693 (cur_drv->head << 2) |
1694 GET_CUR_DRV(fdctrl) |
1695 0x28;
1696 fdctrl_set_fifo(fdctrl, 1, 0);
1697 }
1698
1699 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1700 {
1701 FDrive *cur_drv;
1702
1703 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1704 cur_drv = get_cur_drv(fdctrl);
1705 fd_recalibrate(cur_drv);
1706 fdctrl_reset_fifo(fdctrl);
1707 /* Raise Interrupt */
1708 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1709 }
1710
1711 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1712 {
1713 FDrive *cur_drv = get_cur_drv(fdctrl);
1714
1715 if (fdctrl->reset_sensei > 0) {
1716 fdctrl->fifo[0] =
1717 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1718 fdctrl->reset_sensei--;
1719 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
1720 fdctrl->fifo[0] = FD_SR0_INVCMD;
1721 fdctrl_set_fifo(fdctrl, 1, 0);
1722 return;
1723 } else {
1724 fdctrl->fifo[0] =
1725 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0))
1726 | GET_CUR_DRV(fdctrl);
1727 }
1728
1729 fdctrl->fifo[1] = cur_drv->track;
1730 fdctrl_set_fifo(fdctrl, 2, 0);
1731 fdctrl_reset_irq(fdctrl);
1732 fdctrl->status0 = FD_SR0_RDYCHG;
1733 }
1734
1735 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1736 {
1737 FDrive *cur_drv;
1738
1739 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1740 cur_drv = get_cur_drv(fdctrl);
1741 fdctrl_reset_fifo(fdctrl);
1742 /* The seek command just sends step pulses to the drive and doesn't care if
1743 * there is a medium inserted of if it's banging the head against the drive.
1744 */
1745 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
1746 /* Raise Interrupt */
1747 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1748 }
1749
1750 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1751 {
1752 FDrive *cur_drv = get_cur_drv(fdctrl);
1753
1754 if (fdctrl->fifo[1] & 0x80)
1755 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1756 /* No result back */
1757 fdctrl_reset_fifo(fdctrl);
1758 }
1759
1760 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1761 {
1762 fdctrl->config = fdctrl->fifo[2];
1763 fdctrl->precomp_trk = fdctrl->fifo[3];
1764 /* No result back */
1765 fdctrl_reset_fifo(fdctrl);
1766 }
1767
1768 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1769 {
1770 fdctrl->pwrd = fdctrl->fifo[1];
1771 fdctrl->fifo[0] = fdctrl->fifo[1];
1772 fdctrl_set_fifo(fdctrl, 1, 0);
1773 }
1774
1775 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1776 {
1777 /* No result back */
1778 fdctrl_reset_fifo(fdctrl);
1779 }
1780
1781 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1782 {
1783 FDrive *cur_drv = get_cur_drv(fdctrl);
1784
1785 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1786 /* Command parameters done */
1787 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1788 fdctrl->fifo[0] = fdctrl->fifo[1];
1789 fdctrl->fifo[2] = 0;
1790 fdctrl->fifo[3] = 0;
1791 fdctrl_set_fifo(fdctrl, 4, 0);
1792 } else {
1793 fdctrl_reset_fifo(fdctrl);
1794 }
1795 } else if (fdctrl->data_len > 7) {
1796 /* ERROR */
1797 fdctrl->fifo[0] = 0x80 |
1798 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1799 fdctrl_set_fifo(fdctrl, 1, 0);
1800 }
1801 }
1802
1803 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1804 {
1805 FDrive *cur_drv;
1806
1807 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1808 cur_drv = get_cur_drv(fdctrl);
1809 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1810 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1,
1811 cur_drv->sect, 1);
1812 } else {
1813 fd_seek(cur_drv, cur_drv->head,
1814 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1);
1815 }
1816 fdctrl_reset_fifo(fdctrl);
1817 /* Raise Interrupt */
1818 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1819 }
1820
1821 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1822 {
1823 FDrive *cur_drv;
1824
1825 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1826 cur_drv = get_cur_drv(fdctrl);
1827 if (fdctrl->fifo[2] > cur_drv->track) {
1828 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1);
1829 } else {
1830 fd_seek(cur_drv, cur_drv->head,
1831 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1);
1832 }
1833 fdctrl_reset_fifo(fdctrl);
1834 /* Raise Interrupt */
1835 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1836 }
1837
1838 static const struct {
1839 uint8_t value;
1840 uint8_t mask;
1841 const char* name;
1842 int parameters;
1843 void (*handler)(FDCtrl *fdctrl, int direction);
1844 int direction;
1845 } handlers[] = {
1846 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1847 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1848 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1849 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1850 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1851 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1852 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1853 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1854 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1855 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1856 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1857 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1858 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1859 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1860 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1861 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1862 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1863 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1864 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1865 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1866 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1867 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1868 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1869 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1870 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1871 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1872 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1873 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1874 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1875 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1876 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1877 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1878 };
1879 /* Associate command to an index in the 'handlers' array */
1880 static uint8_t command_to_handler[256];
1881
1882 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
1883 {
1884 FDrive *cur_drv;
1885 int pos;
1886
1887 /* Reset mode */
1888 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1889 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1890 return;
1891 }
1892 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1893 FLOPPY_DPRINTF("error: controller not ready for writing\n");
1894 return;
1895 }
1896 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1897 /* Is it write command time ? */
1898 if (fdctrl->msr & FD_MSR_NONDMA) {
1899 /* FIFO data write */
1900 pos = fdctrl->data_pos++;
1901 pos %= FD_SECTOR_LEN;
1902 fdctrl->fifo[pos] = value;
1903 if (pos == FD_SECTOR_LEN - 1 ||
1904 fdctrl->data_pos == fdctrl->data_len) {
1905 cur_drv = get_cur_drv(fdctrl);
1906 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1907 FLOPPY_DPRINTF("error writing sector %d\n",
1908 fd_sector(cur_drv));
1909 return;
1910 }
1911 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1912 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1913 fd_sector(cur_drv));
1914 return;
1915 }
1916 }
1917 /* Switch from transfer mode to status mode
1918 * then from status mode to command mode
1919 */
1920 if (fdctrl->data_pos == fdctrl->data_len)
1921 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1922 return;
1923 }
1924 if (fdctrl->data_pos == 0) {
1925 /* Command */
1926 pos = command_to_handler[value & 0xff];
1927 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1928 fdctrl->data_len = handlers[pos].parameters + 1;
1929 fdctrl->msr |= FD_MSR_CMDBUSY;
1930 }
1931
1932 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1933 fdctrl->fifo[fdctrl->data_pos++] = value;
1934 if (fdctrl->data_pos == fdctrl->data_len) {
1935 /* We now have all parameters
1936 * and will be able to treat the command
1937 */
1938 if (fdctrl->data_state & FD_STATE_FORMAT) {
1939 fdctrl_format_sector(fdctrl);
1940 return;
1941 }
1942
1943 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1944 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1945 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1946 }
1947 }
1948
1949 static void fdctrl_result_timer(void *opaque)
1950 {
1951 FDCtrl *fdctrl = opaque;
1952 FDrive *cur_drv = get_cur_drv(fdctrl);
1953
1954 /* Pretend we are spinning.
1955 * This is needed for Coherent, which uses READ ID to check for
1956 * sector interleaving.
1957 */
1958 if (cur_drv->last_sect != 0) {
1959 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1960 }
1961 /* READ_ID can't automatically succeed! */
1962 if (fdctrl->check_media_rate &&
1963 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1964 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
1965 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1966 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1967 } else {
1968 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1969 }
1970 }
1971
1972 static void fdctrl_change_cb(void *opaque, bool load)
1973 {
1974 FDrive *drive = opaque;
1975
1976 drive->media_changed = 1;
1977 fd_revalidate(drive);
1978 }
1979
1980 static const BlockDevOps fdctrl_block_ops = {
1981 .change_media_cb = fdctrl_change_cb,
1982 };
1983
1984 /* Init functions */
1985 static int fdctrl_connect_drives(FDCtrl *fdctrl)
1986 {
1987 unsigned int i;
1988 FDrive *drive;
1989
1990 for (i = 0; i < MAX_FD; i++) {
1991 drive = &fdctrl->drives[i];
1992 drive->fdctrl = fdctrl;
1993
1994 if (drive->bs) {
1995 if (bdrv_get_on_error(drive->bs, 0) != BLOCKDEV_ON_ERROR_ENOSPC) {
1996 error_report("fdc doesn't support drive option werror");
1997 return -1;
1998 }
1999 if (bdrv_get_on_error(drive->bs, 1) != BLOCKDEV_ON_ERROR_REPORT) {
2000 error_report("fdc doesn't support drive option rerror");
2001 return -1;
2002 }
2003 }
2004
2005 fd_init(drive);
2006 fdctrl_change_cb(drive, 0);
2007 if (drive->bs) {
2008 bdrv_set_dev_ops(drive->bs, &fdctrl_block_ops, drive);
2009 }
2010 }
2011 return 0;
2012 }
2013
2014 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
2015 {
2016 ISADevice *dev;
2017
2018 dev = isa_try_create(bus, "isa-fdc");
2019 if (!dev) {
2020 return NULL;
2021 }
2022
2023 if (fds[0]) {
2024 qdev_prop_set_drive_nofail(&dev->qdev, "driveA", fds[0]->bdrv);
2025 }
2026 if (fds[1]) {
2027 qdev_prop_set_drive_nofail(&dev->qdev, "driveB", fds[1]->bdrv);
2028 }
2029 qdev_init_nofail(&dev->qdev);
2030
2031 return dev;
2032 }
2033
2034 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
2035 target_phys_addr_t mmio_base, DriveInfo **fds)
2036 {
2037 FDCtrl *fdctrl;
2038 DeviceState *dev;
2039 FDCtrlSysBus *sys;
2040
2041 dev = qdev_create(NULL, "sysbus-fdc");
2042 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
2043 fdctrl = &sys->state;
2044 fdctrl->dma_chann = dma_chann; /* FIXME */
2045 if (fds[0]) {
2046 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
2047 }
2048 if (fds[1]) {
2049 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
2050 }
2051 qdev_init_nofail(dev);
2052 sysbus_connect_irq(&sys->busdev, 0, irq);
2053 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
2054 }
2055
2056 void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
2057 DriveInfo **fds, qemu_irq *fdc_tc)
2058 {
2059 DeviceState *dev;
2060 FDCtrlSysBus *sys;
2061
2062 dev = qdev_create(NULL, "SUNW,fdtwo");
2063 if (fds[0]) {
2064 qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv);
2065 }
2066 qdev_init_nofail(dev);
2067 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
2068 sysbus_connect_irq(&sys->busdev, 0, irq);
2069 sysbus_mmio_map(&sys->busdev, 0, io_base);
2070 *fdc_tc = qdev_get_gpio_in(dev, 0);
2071 }
2072
2073 static int fdctrl_init_common(FDCtrl *fdctrl)
2074 {
2075 int i, j;
2076 static int command_tables_inited = 0;
2077
2078 /* Fill 'command_to_handler' lookup table */
2079 if (!command_tables_inited) {
2080 command_tables_inited = 1;
2081 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
2082 for (j = 0; j < sizeof(command_to_handler); j++) {
2083 if ((j & handlers[i].mask) == handlers[i].value) {
2084 command_to_handler[j] = i;
2085 }
2086 }
2087 }
2088 }
2089
2090 FLOPPY_DPRINTF("init controller\n");
2091 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
2092 fdctrl->fifo_size = 512;
2093 fdctrl->result_timer = qemu_new_timer_ns(vm_clock,
2094 fdctrl_result_timer, fdctrl);
2095
2096 fdctrl->version = 0x90; /* Intel 82078 controller */
2097 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
2098 fdctrl->num_floppies = MAX_FD;
2099
2100 if (fdctrl->dma_chann != -1)
2101 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
2102 return fdctrl_connect_drives(fdctrl);
2103 }
2104
2105 static const MemoryRegionPortio fdc_portio_list[] = {
2106 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
2107 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
2108 PORTIO_END_OF_LIST(),
2109 };
2110
2111 static int isabus_fdc_init1(ISADevice *dev)
2112 {
2113 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
2114 FDCtrl *fdctrl = &isa->state;
2115 int ret;
2116
2117 isa_register_portio_list(dev, isa->iobase, fdc_portio_list, fdctrl, "fdc");
2118
2119 isa_init_irq(&isa->busdev, &fdctrl->irq, isa->irq);
2120 fdctrl->dma_chann = isa->dma;
2121
2122 qdev_set_legacy_instance_id(&dev->qdev, isa->iobase, 2);
2123 ret = fdctrl_init_common(fdctrl);
2124
2125 add_boot_device_path(isa->bootindexA, &dev->qdev, "/floppy@0");
2126 add_boot_device_path(isa->bootindexB, &dev->qdev, "/floppy@1");
2127
2128 return ret;
2129 }
2130
2131 static int sysbus_fdc_init1(SysBusDevice *dev)
2132 {
2133 FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
2134 FDCtrl *fdctrl = &sys->state;
2135 int ret;
2136
2137 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_ops, fdctrl, "fdc", 0x08);
2138 sysbus_init_mmio(dev, &fdctrl->iomem);
2139 sysbus_init_irq(dev, &fdctrl->irq);
2140 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2141 fdctrl->dma_chann = -1;
2142
2143 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
2144 ret = fdctrl_init_common(fdctrl);
2145
2146 return ret;
2147 }
2148
2149 static int sun4m_fdc_init1(SysBusDevice *dev)
2150 {
2151 FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
2152
2153 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_strict_ops, fdctrl,
2154 "fdctrl", 0x08);
2155 sysbus_init_mmio(dev, &fdctrl->iomem);
2156 sysbus_init_irq(dev, &fdctrl->irq);
2157 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2158
2159 fdctrl->sun4m = 1;
2160 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
2161 return fdctrl_init_common(fdctrl);
2162 }
2163
2164 FDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
2165 {
2166 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, fdc);
2167
2168 return isa->state.drives[i].drive;
2169 }
2170
2171 static const VMStateDescription vmstate_isa_fdc ={
2172 .name = "fdc",
2173 .version_id = 2,
2174 .minimum_version_id = 2,
2175 .fields = (VMStateField []) {
2176 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2177 VMSTATE_END_OF_LIST()
2178 }
2179 };
2180
2181 static Property isa_fdc_properties[] = {
2182 DEFINE_PROP_HEX32("iobase", FDCtrlISABus, iobase, 0x3f0),
2183 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2184 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
2185 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs),
2186 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs),
2187 DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1),
2188 DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1),
2189 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2190 0, true),
2191 DEFINE_PROP_END_OF_LIST(),
2192 };
2193
2194 static void isabus_fdc_class_init1(ObjectClass *klass, void *data)
2195 {
2196 DeviceClass *dc = DEVICE_CLASS(klass);
2197 ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
2198 ic->init = isabus_fdc_init1;
2199 dc->fw_name = "fdc";
2200 dc->no_user = 1;
2201 dc->reset = fdctrl_external_reset_isa;
2202 dc->vmsd = &vmstate_isa_fdc;
2203 dc->props = isa_fdc_properties;
2204 }
2205
2206 static TypeInfo isa_fdc_info = {
2207 .name = "isa-fdc",
2208 .parent = TYPE_ISA_DEVICE,
2209 .instance_size = sizeof(FDCtrlISABus),
2210 .class_init = isabus_fdc_class_init1,
2211 };
2212
2213 static const VMStateDescription vmstate_sysbus_fdc ={
2214 .name = "fdc",
2215 .version_id = 2,
2216 .minimum_version_id = 2,
2217 .fields = (VMStateField []) {
2218 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2219 VMSTATE_END_OF_LIST()
2220 }
2221 };
2222
2223 static Property sysbus_fdc_properties[] = {
2224 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs),
2225 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs),
2226 DEFINE_PROP_END_OF_LIST(),
2227 };
2228
2229 static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2230 {
2231 DeviceClass *dc = DEVICE_CLASS(klass);
2232 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2233
2234 k->init = sysbus_fdc_init1;
2235 dc->reset = fdctrl_external_reset_sysbus;
2236 dc->vmsd = &vmstate_sysbus_fdc;
2237 dc->props = sysbus_fdc_properties;
2238 }
2239
2240 static TypeInfo sysbus_fdc_info = {
2241 .name = "sysbus-fdc",
2242 .parent = TYPE_SYS_BUS_DEVICE,
2243 .instance_size = sizeof(FDCtrlSysBus),
2244 .class_init = sysbus_fdc_class_init,
2245 };
2246
2247 static Property sun4m_fdc_properties[] = {
2248 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs),
2249 DEFINE_PROP_END_OF_LIST(),
2250 };
2251
2252 static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2253 {
2254 DeviceClass *dc = DEVICE_CLASS(klass);
2255 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2256
2257 k->init = sun4m_fdc_init1;
2258 dc->reset = fdctrl_external_reset_sysbus;
2259 dc->vmsd = &vmstate_sysbus_fdc;
2260 dc->props = sun4m_fdc_properties;
2261 }
2262
2263 static TypeInfo sun4m_fdc_info = {
2264 .name = "SUNW,fdtwo",
2265 .parent = TYPE_SYS_BUS_DEVICE,
2266 .instance_size = sizeof(FDCtrlSysBus),
2267 .class_init = sun4m_fdc_class_init,
2268 };
2269
2270 static void fdc_register_types(void)
2271 {
2272 type_register_static(&isa_fdc_info);
2273 type_register_static(&sysbus_fdc_info);
2274 type_register_static(&sun4m_fdc_info);
2275 }
2276
2277 type_init(fdc_register_types)
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