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[qemu.git] / hw / fdc.c
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "block.h"
33 #include "qemu-timer.h"
34 #include "isa.h"
35 #include "sysbus.h"
36 #include "qdev-addr.h"
37
38 /********************************************************/
39 /* debug Floppy devices */
40 //#define DEBUG_FLOPPY
41
42 #ifdef DEBUG_FLOPPY
43 #define FLOPPY_DPRINTF(fmt, ...) \
44 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
45 #else
46 #define FLOPPY_DPRINTF(fmt, ...)
47 #endif
48
49 #define FLOPPY_ERROR(fmt, ...) \
50 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
51
52 /********************************************************/
53 /* Floppy drive emulation */
54
55 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
56 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
57
58 /* Will always be a fixed parameter for us */
59 #define FD_SECTOR_LEN 512
60 #define FD_SECTOR_SC 2 /* Sector size code */
61 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
62
63 /* Floppy disk drive emulation */
64 typedef enum fdisk_type_t {
65 FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */
66 FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */
67 FDRIVE_DISK_720 = 0x03, /* 720 kB disk */
68 FDRIVE_DISK_USER = 0x04, /* User defined geometry */
69 FDRIVE_DISK_NONE = 0x05, /* No disk */
70 } fdisk_type_t;
71
72 typedef enum fdrive_type_t {
73 FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */
74 FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */
75 FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */
76 FDRIVE_DRV_NONE = 0x03, /* No drive connected */
77 } fdrive_type_t;
78
79 typedef enum fdisk_flags_t {
80 FDISK_DBL_SIDES = 0x01,
81 } fdisk_flags_t;
82
83 typedef struct fdrive_t {
84 BlockDriverState *bs;
85 /* Drive status */
86 fdrive_type_t drive;
87 uint8_t perpendicular; /* 2.88 MB access mode */
88 /* Position */
89 uint8_t head;
90 uint8_t track;
91 uint8_t sect;
92 /* Media */
93 fdisk_flags_t flags;
94 uint8_t last_sect; /* Nb sector per track */
95 uint8_t max_track; /* Nb of tracks */
96 uint16_t bps; /* Bytes per sector */
97 uint8_t ro; /* Is read-only */
98 } fdrive_t;
99
100 static void fd_init (fdrive_t *drv, BlockDriverState *bs)
101 {
102 /* Drive */
103 drv->bs = bs;
104 drv->drive = FDRIVE_DRV_NONE;
105 drv->perpendicular = 0;
106 /* Disk */
107 drv->last_sect = 0;
108 drv->max_track = 0;
109 }
110
111 static int _fd_sector (uint8_t head, uint8_t track,
112 uint8_t sect, uint8_t last_sect)
113 {
114 return (((track * 2) + head) * last_sect) + sect - 1;
115 }
116
117 /* Returns current position, in sectors, for given drive */
118 static int fd_sector (fdrive_t *drv)
119 {
120 return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
121 }
122
123 /* Seek to a new position:
124 * returns 0 if already on right track
125 * returns 1 if track changed
126 * returns 2 if track is invalid
127 * returns 3 if sector is invalid
128 * returns 4 if seek is disabled
129 */
130 static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
131 int enable_seek)
132 {
133 uint32_t sector;
134 int ret;
135
136 if (track > drv->max_track ||
137 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
138 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
139 head, track, sect, 1,
140 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
141 drv->max_track, drv->last_sect);
142 return 2;
143 }
144 if (sect > drv->last_sect) {
145 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
146 head, track, sect, 1,
147 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
148 drv->max_track, drv->last_sect);
149 return 3;
150 }
151 sector = _fd_sector(head, track, sect, drv->last_sect);
152 ret = 0;
153 if (sector != fd_sector(drv)) {
154 #if 0
155 if (!enable_seek) {
156 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
157 head, track, sect, 1, drv->max_track, drv->last_sect);
158 return 4;
159 }
160 #endif
161 drv->head = head;
162 if (drv->track != track)
163 ret = 1;
164 drv->track = track;
165 drv->sect = sect;
166 }
167
168 return ret;
169 }
170
171 /* Set drive back to track 0 */
172 static void fd_recalibrate (fdrive_t *drv)
173 {
174 FLOPPY_DPRINTF("recalibrate\n");
175 drv->head = 0;
176 drv->track = 0;
177 drv->sect = 1;
178 }
179
180 /* Recognize floppy formats */
181 typedef struct fd_format_t {
182 fdrive_type_t drive;
183 fdisk_type_t disk;
184 uint8_t last_sect;
185 uint8_t max_track;
186 uint8_t max_head;
187 const char *str;
188 } fd_format_t;
189
190 static const fd_format_t fd_formats[] = {
191 /* First entry is default format */
192 /* 1.44 MB 3"1/2 floppy disks */
193 { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
194 { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1, "1.6 MB 3\"1/2", },
195 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
196 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
197 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
198 { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
199 { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
200 { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
201 /* 2.88 MB 3"1/2 floppy disks */
202 { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
203 { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
204 { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1, "3.2 MB 3\"1/2", },
205 { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
206 { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
207 /* 720 kB 3"1/2 floppy disks */
208 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 1, "720 kB 3\"1/2", },
209 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1, "800 kB 3\"1/2", },
210 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1, "820 kB 3\"1/2", },
211 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1, "830 kB 3\"1/2", },
212 { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
213 { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
214 /* 1.2 MB 5"1/4 floppy disks */
215 { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1, "1.2 kB 5\"1/4", },
216 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
217 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
218 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
219 { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1, "1.6 MB 5\"1/4", },
220 /* 720 kB 5"1/4 floppy disks */
221 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 80, 1, "720 kB 5\"1/4", },
222 { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1, "880 kB 5\"1/4", },
223 /* 360 kB 5"1/4 floppy disks */
224 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 1, "360 kB 5\"1/4", },
225 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 0, "180 kB 5\"1/4", },
226 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1, "410 kB 5\"1/4", },
227 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1, "420 kB 5\"1/4", },
228 /* 320 kB 5"1/4 floppy disks */
229 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 1, "320 kB 5\"1/4", },
230 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 0, "160 kB 5\"1/4", },
231 /* 360 kB must match 5"1/4 better than 3"1/2... */
232 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 0, "360 kB 3\"1/2", },
233 /* end */
234 { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
235 };
236
237 /* Revalidate a disk drive after a disk change */
238 static void fd_revalidate (fdrive_t *drv)
239 {
240 const fd_format_t *parse;
241 uint64_t nb_sectors, size;
242 int i, first_match, match;
243 int nb_heads, max_track, last_sect, ro;
244
245 FLOPPY_DPRINTF("revalidate\n");
246 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
247 ro = bdrv_is_read_only(drv->bs);
248 bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
249 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
250 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
251 nb_heads - 1, max_track, last_sect);
252 } else {
253 bdrv_get_geometry(drv->bs, &nb_sectors);
254 match = -1;
255 first_match = -1;
256 for (i = 0;; i++) {
257 parse = &fd_formats[i];
258 if (parse->drive == FDRIVE_DRV_NONE)
259 break;
260 if (drv->drive == parse->drive ||
261 drv->drive == FDRIVE_DRV_NONE) {
262 size = (parse->max_head + 1) * parse->max_track *
263 parse->last_sect;
264 if (nb_sectors == size) {
265 match = i;
266 break;
267 }
268 if (first_match == -1)
269 first_match = i;
270 }
271 }
272 if (match == -1) {
273 if (first_match == -1)
274 match = 1;
275 else
276 match = first_match;
277 parse = &fd_formats[match];
278 }
279 nb_heads = parse->max_head + 1;
280 max_track = parse->max_track;
281 last_sect = parse->last_sect;
282 drv->drive = parse->drive;
283 FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
284 nb_heads, max_track, last_sect, ro ? "ro" : "rw");
285 }
286 if (nb_heads == 1) {
287 drv->flags &= ~FDISK_DBL_SIDES;
288 } else {
289 drv->flags |= FDISK_DBL_SIDES;
290 }
291 drv->max_track = max_track;
292 drv->last_sect = last_sect;
293 drv->ro = ro;
294 } else {
295 FLOPPY_DPRINTF("No disk in drive\n");
296 drv->last_sect = 0;
297 drv->max_track = 0;
298 drv->flags &= ~FDISK_DBL_SIDES;
299 }
300 }
301
302 /********************************************************/
303 /* Intel 82078 floppy disk controller emulation */
304
305 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
306 static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
307 static int fdctrl_transfer_handler (void *opaque, int nchan,
308 int dma_pos, int dma_len);
309 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0);
310
311 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
312 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
313 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
314 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
315 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
316 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
317 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
318 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
319 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
320 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
321 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
322
323 enum {
324 FD_DIR_WRITE = 0,
325 FD_DIR_READ = 1,
326 FD_DIR_SCANE = 2,
327 FD_DIR_SCANL = 3,
328 FD_DIR_SCANH = 4,
329 };
330
331 enum {
332 FD_STATE_MULTI = 0x01, /* multi track flag */
333 FD_STATE_FORMAT = 0x02, /* format flag */
334 FD_STATE_SEEK = 0x04, /* seek flag */
335 };
336
337 enum {
338 FD_REG_SRA = 0x00,
339 FD_REG_SRB = 0x01,
340 FD_REG_DOR = 0x02,
341 FD_REG_TDR = 0x03,
342 FD_REG_MSR = 0x04,
343 FD_REG_DSR = 0x04,
344 FD_REG_FIFO = 0x05,
345 FD_REG_DIR = 0x07,
346 };
347
348 enum {
349 FD_CMD_READ_TRACK = 0x02,
350 FD_CMD_SPECIFY = 0x03,
351 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
352 FD_CMD_WRITE = 0x05,
353 FD_CMD_READ = 0x06,
354 FD_CMD_RECALIBRATE = 0x07,
355 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
356 FD_CMD_WRITE_DELETED = 0x09,
357 FD_CMD_READ_ID = 0x0a,
358 FD_CMD_READ_DELETED = 0x0c,
359 FD_CMD_FORMAT_TRACK = 0x0d,
360 FD_CMD_DUMPREG = 0x0e,
361 FD_CMD_SEEK = 0x0f,
362 FD_CMD_VERSION = 0x10,
363 FD_CMD_SCAN_EQUAL = 0x11,
364 FD_CMD_PERPENDICULAR_MODE = 0x12,
365 FD_CMD_CONFIGURE = 0x13,
366 FD_CMD_LOCK = 0x14,
367 FD_CMD_VERIFY = 0x16,
368 FD_CMD_POWERDOWN_MODE = 0x17,
369 FD_CMD_PART_ID = 0x18,
370 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
371 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
372 FD_CMD_SAVE = 0x2c,
373 FD_CMD_OPTION = 0x33,
374 FD_CMD_RESTORE = 0x4c,
375 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
376 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
377 FD_CMD_FORMAT_AND_WRITE = 0xcd,
378 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
379 };
380
381 enum {
382 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
383 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
384 FD_CONFIG_POLL = 0x10, /* Poll enabled */
385 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
386 FD_CONFIG_EIS = 0x40, /* No implied seeks */
387 };
388
389 enum {
390 FD_SR0_EQPMT = 0x10,
391 FD_SR0_SEEK = 0x20,
392 FD_SR0_ABNTERM = 0x40,
393 FD_SR0_INVCMD = 0x80,
394 FD_SR0_RDYCHG = 0xc0,
395 };
396
397 enum {
398 FD_SR1_EC = 0x80, /* End of cylinder */
399 };
400
401 enum {
402 FD_SR2_SNS = 0x04, /* Scan not satisfied */
403 FD_SR2_SEH = 0x08, /* Scan equal hit */
404 };
405
406 enum {
407 FD_SRA_DIR = 0x01,
408 FD_SRA_nWP = 0x02,
409 FD_SRA_nINDX = 0x04,
410 FD_SRA_HDSEL = 0x08,
411 FD_SRA_nTRK0 = 0x10,
412 FD_SRA_STEP = 0x20,
413 FD_SRA_nDRV2 = 0x40,
414 FD_SRA_INTPEND = 0x80,
415 };
416
417 enum {
418 FD_SRB_MTR0 = 0x01,
419 FD_SRB_MTR1 = 0x02,
420 FD_SRB_WGATE = 0x04,
421 FD_SRB_RDATA = 0x08,
422 FD_SRB_WDATA = 0x10,
423 FD_SRB_DR0 = 0x20,
424 };
425
426 enum {
427 #if MAX_FD == 4
428 FD_DOR_SELMASK = 0x03,
429 #else
430 FD_DOR_SELMASK = 0x01,
431 #endif
432 FD_DOR_nRESET = 0x04,
433 FD_DOR_DMAEN = 0x08,
434 FD_DOR_MOTEN0 = 0x10,
435 FD_DOR_MOTEN1 = 0x20,
436 FD_DOR_MOTEN2 = 0x40,
437 FD_DOR_MOTEN3 = 0x80,
438 };
439
440 enum {
441 #if MAX_FD == 4
442 FD_TDR_BOOTSEL = 0x0c,
443 #else
444 FD_TDR_BOOTSEL = 0x04,
445 #endif
446 };
447
448 enum {
449 FD_DSR_DRATEMASK= 0x03,
450 FD_DSR_PWRDOWN = 0x40,
451 FD_DSR_SWRESET = 0x80,
452 };
453
454 enum {
455 FD_MSR_DRV0BUSY = 0x01,
456 FD_MSR_DRV1BUSY = 0x02,
457 FD_MSR_DRV2BUSY = 0x04,
458 FD_MSR_DRV3BUSY = 0x08,
459 FD_MSR_CMDBUSY = 0x10,
460 FD_MSR_NONDMA = 0x20,
461 FD_MSR_DIO = 0x40,
462 FD_MSR_RQM = 0x80,
463 };
464
465 enum {
466 FD_DIR_DSKCHG = 0x80,
467 };
468
469 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
470 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
471 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
472
473 struct fdctrl_t {
474 /* Controller's identification */
475 uint8_t version;
476 /* HW */
477 qemu_irq irq;
478 int dma_chann;
479 /* Controller state */
480 QEMUTimer *result_timer;
481 uint8_t sra;
482 uint8_t srb;
483 uint8_t dor;
484 uint8_t dor_vmstate; /* only used as temp during vmstate */
485 uint8_t tdr;
486 uint8_t dsr;
487 uint8_t msr;
488 uint8_t cur_drv;
489 uint8_t status0;
490 uint8_t status1;
491 uint8_t status2;
492 /* Command FIFO */
493 uint8_t *fifo;
494 int32_t fifo_size;
495 uint32_t data_pos;
496 uint32_t data_len;
497 uint8_t data_state;
498 uint8_t data_dir;
499 uint8_t eot; /* last wanted sector */
500 /* States kept only to be returned back */
501 /* Timers state */
502 uint8_t timer0;
503 uint8_t timer1;
504 /* precompensation */
505 uint8_t precomp_trk;
506 uint8_t config;
507 uint8_t lock;
508 /* Power down config (also with status regB access mode */
509 uint8_t pwrd;
510 /* Sun4m quirks? */
511 int sun4m;
512 /* Floppy drives */
513 uint8_t num_floppies;
514 fdrive_t drives[MAX_FD];
515 int reset_sensei;
516 };
517
518 typedef struct fdctrl_sysbus_t {
519 SysBusDevice busdev;
520 struct fdctrl_t state;
521 } fdctrl_sysbus_t;
522
523 typedef struct fdctrl_isabus_t {
524 ISADevice busdev;
525 struct fdctrl_t state;
526 } fdctrl_isabus_t;
527
528 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
529 {
530 fdctrl_t *fdctrl = opaque;
531 uint32_t retval;
532
533 switch (reg) {
534 case FD_REG_SRA:
535 retval = fdctrl_read_statusA(fdctrl);
536 break;
537 case FD_REG_SRB:
538 retval = fdctrl_read_statusB(fdctrl);
539 break;
540 case FD_REG_DOR:
541 retval = fdctrl_read_dor(fdctrl);
542 break;
543 case FD_REG_TDR:
544 retval = fdctrl_read_tape(fdctrl);
545 break;
546 case FD_REG_MSR:
547 retval = fdctrl_read_main_status(fdctrl);
548 break;
549 case FD_REG_FIFO:
550 retval = fdctrl_read_data(fdctrl);
551 break;
552 case FD_REG_DIR:
553 retval = fdctrl_read_dir(fdctrl);
554 break;
555 default:
556 retval = (uint32_t)(-1);
557 break;
558 }
559 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
560
561 return retval;
562 }
563
564 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
565 {
566 fdctrl_t *fdctrl = opaque;
567
568 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
569
570 switch (reg) {
571 case FD_REG_DOR:
572 fdctrl_write_dor(fdctrl, value);
573 break;
574 case FD_REG_TDR:
575 fdctrl_write_tape(fdctrl, value);
576 break;
577 case FD_REG_DSR:
578 fdctrl_write_rate(fdctrl, value);
579 break;
580 case FD_REG_FIFO:
581 fdctrl_write_data(fdctrl, value);
582 break;
583 default:
584 break;
585 }
586 }
587
588 static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
589 {
590 return fdctrl_read(opaque, reg & 7);
591 }
592
593 static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
594 {
595 fdctrl_write(opaque, reg & 7, value);
596 }
597
598 static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
599 {
600 return fdctrl_read(opaque, (uint32_t)reg);
601 }
602
603 static void fdctrl_write_mem (void *opaque,
604 target_phys_addr_t reg, uint32_t value)
605 {
606 fdctrl_write(opaque, (uint32_t)reg, value);
607 }
608
609 static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {
610 fdctrl_read_mem,
611 fdctrl_read_mem,
612 fdctrl_read_mem,
613 };
614
615 static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {
616 fdctrl_write_mem,
617 fdctrl_write_mem,
618 fdctrl_write_mem,
619 };
620
621 static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {
622 fdctrl_read_mem,
623 NULL,
624 NULL,
625 };
626
627 static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {
628 fdctrl_write_mem,
629 NULL,
630 NULL,
631 };
632
633 static const VMStateDescription vmstate_fdrive = {
634 .name = "fdrive",
635 .version_id = 1,
636 .minimum_version_id = 1,
637 .minimum_version_id_old = 1,
638 .fields = (VMStateField []) {
639 VMSTATE_UINT8(head, fdrive_t),
640 VMSTATE_UINT8(track, fdrive_t),
641 VMSTATE_UINT8(sect, fdrive_t),
642 VMSTATE_END_OF_LIST()
643 }
644 };
645
646 static void fdc_pre_save(const void *opaque)
647 {
648 fdctrl_t *s = (void *)opaque;
649
650 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
651 }
652
653 static int fdc_post_load(void *opaque)
654 {
655 fdctrl_t *s = opaque;
656
657 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
658 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
659 return 0;
660 }
661
662 static const VMStateDescription vmstate_fdc = {
663 .name = "fdc",
664 .version_id = 2,
665 .minimum_version_id = 2,
666 .minimum_version_id_old = 2,
667 .pre_save = fdc_pre_save,
668 .post_load = fdc_post_load,
669 .fields = (VMStateField []) {
670 /* Controller State */
671 VMSTATE_UINT8(sra, fdctrl_t),
672 VMSTATE_UINT8(srb, fdctrl_t),
673 VMSTATE_UINT8(dor_vmstate, fdctrl_t),
674 VMSTATE_UINT8(tdr, fdctrl_t),
675 VMSTATE_UINT8(dsr, fdctrl_t),
676 VMSTATE_UINT8(msr, fdctrl_t),
677 VMSTATE_UINT8(status0, fdctrl_t),
678 VMSTATE_UINT8(status1, fdctrl_t),
679 VMSTATE_UINT8(status2, fdctrl_t),
680 /* Command FIFO */
681 VMSTATE_VARRAY(fifo, fdctrl_t, fifo_size, 0, vmstate_info_uint8, uint8),
682 VMSTATE_UINT32(data_pos, fdctrl_t),
683 VMSTATE_UINT32(data_len, fdctrl_t),
684 VMSTATE_UINT8(data_state, fdctrl_t),
685 VMSTATE_UINT8(data_dir, fdctrl_t),
686 VMSTATE_UINT8(eot, fdctrl_t),
687 /* States kept only to be returned back */
688 VMSTATE_UINT8(timer0, fdctrl_t),
689 VMSTATE_UINT8(timer1, fdctrl_t),
690 VMSTATE_UINT8(precomp_trk, fdctrl_t),
691 VMSTATE_UINT8(config, fdctrl_t),
692 VMSTATE_UINT8(lock, fdctrl_t),
693 VMSTATE_UINT8(pwrd, fdctrl_t),
694 VMSTATE_UINT8_EQUAL(num_floppies, fdctrl_t),
695 VMSTATE_STRUCT_ARRAY(drives, fdctrl_t, MAX_FD, 1,
696 vmstate_fdrive, fdrive_t),
697 VMSTATE_END_OF_LIST()
698 }
699 };
700
701 static void fdctrl_external_reset(void *opaque)
702 {
703 fdctrl_t *s = opaque;
704
705 fdctrl_reset(s, 0);
706 }
707
708 static void fdctrl_handle_tc(void *opaque, int irq, int level)
709 {
710 //fdctrl_t *s = opaque;
711
712 if (level) {
713 // XXX
714 FLOPPY_DPRINTF("TC pulsed\n");
715 }
716 }
717
718 /* XXX: may change if moved to bdrv */
719 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
720 {
721 return fdctrl->drives[drive_num].drive;
722 }
723
724 /* Change IRQ state */
725 static void fdctrl_reset_irq (fdctrl_t *fdctrl)
726 {
727 if (!(fdctrl->sra & FD_SRA_INTPEND))
728 return;
729 FLOPPY_DPRINTF("Reset interrupt\n");
730 qemu_set_irq(fdctrl->irq, 0);
731 fdctrl->sra &= ~FD_SRA_INTPEND;
732 }
733
734 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0)
735 {
736 /* Sparc mutation */
737 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
738 /* XXX: not sure */
739 fdctrl->msr &= ~FD_MSR_CMDBUSY;
740 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
741 fdctrl->status0 = status0;
742 return;
743 }
744 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
745 qemu_set_irq(fdctrl->irq, 1);
746 fdctrl->sra |= FD_SRA_INTPEND;
747 }
748 fdctrl->reset_sensei = 0;
749 fdctrl->status0 = status0;
750 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
751 }
752
753 /* Reset controller */
754 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
755 {
756 int i;
757
758 FLOPPY_DPRINTF("reset controller\n");
759 fdctrl_reset_irq(fdctrl);
760 /* Initialise controller */
761 fdctrl->sra = 0;
762 fdctrl->srb = 0xc0;
763 if (!fdctrl->drives[1].bs)
764 fdctrl->sra |= FD_SRA_nDRV2;
765 fdctrl->cur_drv = 0;
766 fdctrl->dor = FD_DOR_nRESET;
767 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
768 fdctrl->msr = FD_MSR_RQM;
769 /* FIFO state */
770 fdctrl->data_pos = 0;
771 fdctrl->data_len = 0;
772 fdctrl->data_state = 0;
773 fdctrl->data_dir = FD_DIR_WRITE;
774 for (i = 0; i < MAX_FD; i++)
775 fd_recalibrate(&fdctrl->drives[i]);
776 fdctrl_reset_fifo(fdctrl);
777 if (do_irq) {
778 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
779 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
780 }
781 }
782
783 static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
784 {
785 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
786 }
787
788 static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
789 {
790 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
791 return &fdctrl->drives[1];
792 else
793 return &fdctrl->drives[0];
794 }
795
796 #if MAX_FD == 4
797 static inline fdrive_t *drv2 (fdctrl_t *fdctrl)
798 {
799 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
800 return &fdctrl->drives[2];
801 else
802 return &fdctrl->drives[1];
803 }
804
805 static inline fdrive_t *drv3 (fdctrl_t *fdctrl)
806 {
807 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
808 return &fdctrl->drives[3];
809 else
810 return &fdctrl->drives[2];
811 }
812 #endif
813
814 static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
815 {
816 switch (fdctrl->cur_drv) {
817 case 0: return drv0(fdctrl);
818 case 1: return drv1(fdctrl);
819 #if MAX_FD == 4
820 case 2: return drv2(fdctrl);
821 case 3: return drv3(fdctrl);
822 #endif
823 default: return NULL;
824 }
825 }
826
827 /* Status A register : 0x00 (read-only) */
828 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
829 {
830 uint32_t retval = fdctrl->sra;
831
832 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
833
834 return retval;
835 }
836
837 /* Status B register : 0x01 (read-only) */
838 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
839 {
840 uint32_t retval = fdctrl->srb;
841
842 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
843
844 return retval;
845 }
846
847 /* Digital output register : 0x02 */
848 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
849 {
850 uint32_t retval = fdctrl->dor;
851
852 /* Selected drive */
853 retval |= fdctrl->cur_drv;
854 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
855
856 return retval;
857 }
858
859 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
860 {
861 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
862
863 /* Motors */
864 if (value & FD_DOR_MOTEN0)
865 fdctrl->srb |= FD_SRB_MTR0;
866 else
867 fdctrl->srb &= ~FD_SRB_MTR0;
868 if (value & FD_DOR_MOTEN1)
869 fdctrl->srb |= FD_SRB_MTR1;
870 else
871 fdctrl->srb &= ~FD_SRB_MTR1;
872
873 /* Drive */
874 if (value & 1)
875 fdctrl->srb |= FD_SRB_DR0;
876 else
877 fdctrl->srb &= ~FD_SRB_DR0;
878
879 /* Reset */
880 if (!(value & FD_DOR_nRESET)) {
881 if (fdctrl->dor & FD_DOR_nRESET) {
882 FLOPPY_DPRINTF("controller enter RESET state\n");
883 }
884 } else {
885 if (!(fdctrl->dor & FD_DOR_nRESET)) {
886 FLOPPY_DPRINTF("controller out of RESET state\n");
887 fdctrl_reset(fdctrl, 1);
888 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
889 }
890 }
891 /* Selected drive */
892 fdctrl->cur_drv = value & FD_DOR_SELMASK;
893
894 fdctrl->dor = value;
895 }
896
897 /* Tape drive register : 0x03 */
898 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
899 {
900 uint32_t retval = fdctrl->tdr;
901
902 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
903
904 return retval;
905 }
906
907 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
908 {
909 /* Reset mode */
910 if (!(fdctrl->dor & FD_DOR_nRESET)) {
911 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
912 return;
913 }
914 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
915 /* Disk boot selection indicator */
916 fdctrl->tdr = value & FD_TDR_BOOTSEL;
917 /* Tape indicators: never allow */
918 }
919
920 /* Main status register : 0x04 (read) */
921 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
922 {
923 uint32_t retval = fdctrl->msr;
924
925 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
926 fdctrl->dor |= FD_DOR_nRESET;
927
928 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
929
930 return retval;
931 }
932
933 /* Data select rate register : 0x04 (write) */
934 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
935 {
936 /* Reset mode */
937 if (!(fdctrl->dor & FD_DOR_nRESET)) {
938 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
939 return;
940 }
941 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
942 /* Reset: autoclear */
943 if (value & FD_DSR_SWRESET) {
944 fdctrl->dor &= ~FD_DOR_nRESET;
945 fdctrl_reset(fdctrl, 1);
946 fdctrl->dor |= FD_DOR_nRESET;
947 }
948 if (value & FD_DSR_PWRDOWN) {
949 fdctrl_reset(fdctrl, 1);
950 }
951 fdctrl->dsr = value;
952 }
953
954 static int fdctrl_media_changed(fdrive_t *drv)
955 {
956 int ret;
957
958 if (!drv->bs)
959 return 0;
960 ret = bdrv_media_changed(drv->bs);
961 if (ret) {
962 fd_revalidate(drv);
963 }
964 return ret;
965 }
966
967 /* Digital input register : 0x07 (read-only) */
968 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
969 {
970 uint32_t retval = 0;
971
972 if (fdctrl_media_changed(drv0(fdctrl))
973 || fdctrl_media_changed(drv1(fdctrl))
974 #if MAX_FD == 4
975 || fdctrl_media_changed(drv2(fdctrl))
976 || fdctrl_media_changed(drv3(fdctrl))
977 #endif
978 )
979 retval |= FD_DIR_DSKCHG;
980 if (retval != 0)
981 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
982
983 return retval;
984 }
985
986 /* FIFO state control */
987 static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
988 {
989 fdctrl->data_dir = FD_DIR_WRITE;
990 fdctrl->data_pos = 0;
991 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
992 }
993
994 /* Set FIFO status for the host to read */
995 static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
996 {
997 fdctrl->data_dir = FD_DIR_READ;
998 fdctrl->data_len = fifo_len;
999 fdctrl->data_pos = 0;
1000 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1001 if (do_irq)
1002 fdctrl_raise_irq(fdctrl, 0x00);
1003 }
1004
1005 /* Set an error: unimplemented/unknown command */
1006 static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
1007 {
1008 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
1009 fdctrl->fifo[0] = FD_SR0_INVCMD;
1010 fdctrl_set_fifo(fdctrl, 1, 0);
1011 }
1012
1013 /* Seek to next sector */
1014 static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
1015 {
1016 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1017 cur_drv->head, cur_drv->track, cur_drv->sect,
1018 fd_sector(cur_drv));
1019 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1020 error in fact */
1021 if (cur_drv->sect >= cur_drv->last_sect ||
1022 cur_drv->sect == fdctrl->eot) {
1023 cur_drv->sect = 1;
1024 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1025 if (cur_drv->head == 0 &&
1026 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1027 cur_drv->head = 1;
1028 } else {
1029 cur_drv->head = 0;
1030 cur_drv->track++;
1031 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1032 return 0;
1033 }
1034 } else {
1035 cur_drv->track++;
1036 return 0;
1037 }
1038 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1039 cur_drv->head, cur_drv->track,
1040 cur_drv->sect, fd_sector(cur_drv));
1041 } else {
1042 cur_drv->sect++;
1043 }
1044 return 1;
1045 }
1046
1047 /* Callback for transfer end (stop or abort) */
1048 static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
1049 uint8_t status1, uint8_t status2)
1050 {
1051 fdrive_t *cur_drv;
1052
1053 cur_drv = get_cur_drv(fdctrl);
1054 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1055 status0, status1, status2,
1056 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1057 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1058 fdctrl->fifo[1] = status1;
1059 fdctrl->fifo[2] = status2;
1060 fdctrl->fifo[3] = cur_drv->track;
1061 fdctrl->fifo[4] = cur_drv->head;
1062 fdctrl->fifo[5] = cur_drv->sect;
1063 fdctrl->fifo[6] = FD_SECTOR_SC;
1064 fdctrl->data_dir = FD_DIR_READ;
1065 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1066 DMA_release_DREQ(fdctrl->dma_chann);
1067 }
1068 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1069 fdctrl->msr &= ~FD_MSR_NONDMA;
1070 fdctrl_set_fifo(fdctrl, 7, 1);
1071 }
1072
1073 /* Prepare a data transfer (either DMA or FIFO) */
1074 static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
1075 {
1076 fdrive_t *cur_drv;
1077 uint8_t kh, kt, ks;
1078 int did_seek = 0;
1079
1080 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1081 cur_drv = get_cur_drv(fdctrl);
1082 kt = fdctrl->fifo[2];
1083 kh = fdctrl->fifo[3];
1084 ks = fdctrl->fifo[4];
1085 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1086 GET_CUR_DRV(fdctrl), kh, kt, ks,
1087 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1088 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1089 case 2:
1090 /* sect too big */
1091 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1092 fdctrl->fifo[3] = kt;
1093 fdctrl->fifo[4] = kh;
1094 fdctrl->fifo[5] = ks;
1095 return;
1096 case 3:
1097 /* track too big */
1098 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1099 fdctrl->fifo[3] = kt;
1100 fdctrl->fifo[4] = kh;
1101 fdctrl->fifo[5] = ks;
1102 return;
1103 case 4:
1104 /* No seek enabled */
1105 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1106 fdctrl->fifo[3] = kt;
1107 fdctrl->fifo[4] = kh;
1108 fdctrl->fifo[5] = ks;
1109 return;
1110 case 1:
1111 did_seek = 1;
1112 break;
1113 default:
1114 break;
1115 }
1116
1117 /* Set the FIFO state */
1118 fdctrl->data_dir = direction;
1119 fdctrl->data_pos = 0;
1120 fdctrl->msr |= FD_MSR_CMDBUSY;
1121 if (fdctrl->fifo[0] & 0x80)
1122 fdctrl->data_state |= FD_STATE_MULTI;
1123 else
1124 fdctrl->data_state &= ~FD_STATE_MULTI;
1125 if (did_seek)
1126 fdctrl->data_state |= FD_STATE_SEEK;
1127 else
1128 fdctrl->data_state &= ~FD_STATE_SEEK;
1129 if (fdctrl->fifo[5] == 00) {
1130 fdctrl->data_len = fdctrl->fifo[8];
1131 } else {
1132 int tmp;
1133 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1134 tmp = (fdctrl->fifo[6] - ks + 1);
1135 if (fdctrl->fifo[0] & 0x80)
1136 tmp += fdctrl->fifo[6];
1137 fdctrl->data_len *= tmp;
1138 }
1139 fdctrl->eot = fdctrl->fifo[6];
1140 if (fdctrl->dor & FD_DOR_DMAEN) {
1141 int dma_mode;
1142 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1143 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1144 dma_mode = (dma_mode >> 2) & 3;
1145 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1146 dma_mode, direction,
1147 (128 << fdctrl->fifo[5]) *
1148 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1149 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1150 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1151 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1152 (direction == FD_DIR_READ && dma_mode == 1)) {
1153 /* No access is allowed until DMA transfer has completed */
1154 fdctrl->msr &= ~FD_MSR_RQM;
1155 /* Now, we just have to wait for the DMA controller to
1156 * recall us...
1157 */
1158 DMA_hold_DREQ(fdctrl->dma_chann);
1159 DMA_schedule(fdctrl->dma_chann);
1160 return;
1161 } else {
1162 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1163 }
1164 }
1165 FLOPPY_DPRINTF("start non-DMA transfer\n");
1166 fdctrl->msr |= FD_MSR_NONDMA;
1167 if (direction != FD_DIR_WRITE)
1168 fdctrl->msr |= FD_MSR_DIO;
1169 /* IO based transfer: calculate len */
1170 fdctrl_raise_irq(fdctrl, 0x00);
1171
1172 return;
1173 }
1174
1175 /* Prepare a transfer of deleted data */
1176 static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
1177 {
1178 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1179
1180 /* We don't handle deleted data,
1181 * so we don't return *ANYTHING*
1182 */
1183 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1184 }
1185
1186 /* handlers for DMA transfers */
1187 static int fdctrl_transfer_handler (void *opaque, int nchan,
1188 int dma_pos, int dma_len)
1189 {
1190 fdctrl_t *fdctrl;
1191 fdrive_t *cur_drv;
1192 int len, start_pos, rel_pos;
1193 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1194
1195 fdctrl = opaque;
1196 if (fdctrl->msr & FD_MSR_RQM) {
1197 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1198 return 0;
1199 }
1200 cur_drv = get_cur_drv(fdctrl);
1201 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1202 fdctrl->data_dir == FD_DIR_SCANH)
1203 status2 = FD_SR2_SNS;
1204 if (dma_len > fdctrl->data_len)
1205 dma_len = fdctrl->data_len;
1206 if (cur_drv->bs == NULL) {
1207 if (fdctrl->data_dir == FD_DIR_WRITE)
1208 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1209 else
1210 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1211 len = 0;
1212 goto transfer_error;
1213 }
1214 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1215 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1216 len = dma_len - fdctrl->data_pos;
1217 if (len + rel_pos > FD_SECTOR_LEN)
1218 len = FD_SECTOR_LEN - rel_pos;
1219 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1220 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1221 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1222 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1223 fd_sector(cur_drv) * FD_SECTOR_LEN);
1224 if (fdctrl->data_dir != FD_DIR_WRITE ||
1225 len < FD_SECTOR_LEN || rel_pos != 0) {
1226 /* READ & SCAN commands and realign to a sector for WRITE */
1227 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1228 fdctrl->fifo, 1) < 0) {
1229 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1230 fd_sector(cur_drv));
1231 /* Sure, image size is too small... */
1232 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1233 }
1234 }
1235 switch (fdctrl->data_dir) {
1236 case FD_DIR_READ:
1237 /* READ commands */
1238 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1239 fdctrl->data_pos, len);
1240 break;
1241 case FD_DIR_WRITE:
1242 /* WRITE commands */
1243 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1244 fdctrl->data_pos, len);
1245 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1246 fdctrl->fifo, 1) < 0) {
1247 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1248 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1249 goto transfer_error;
1250 }
1251 break;
1252 default:
1253 /* SCAN commands */
1254 {
1255 uint8_t tmpbuf[FD_SECTOR_LEN];
1256 int ret;
1257 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1258 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1259 if (ret == 0) {
1260 status2 = FD_SR2_SEH;
1261 goto end_transfer;
1262 }
1263 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1264 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1265 status2 = 0x00;
1266 goto end_transfer;
1267 }
1268 }
1269 break;
1270 }
1271 fdctrl->data_pos += len;
1272 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1273 if (rel_pos == 0) {
1274 /* Seek to next sector */
1275 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1276 break;
1277 }
1278 }
1279 end_transfer:
1280 len = fdctrl->data_pos - start_pos;
1281 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1282 fdctrl->data_pos, len, fdctrl->data_len);
1283 if (fdctrl->data_dir == FD_DIR_SCANE ||
1284 fdctrl->data_dir == FD_DIR_SCANL ||
1285 fdctrl->data_dir == FD_DIR_SCANH)
1286 status2 = FD_SR2_SEH;
1287 if (FD_DID_SEEK(fdctrl->data_state))
1288 status0 |= FD_SR0_SEEK;
1289 fdctrl->data_len -= len;
1290 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1291 transfer_error:
1292
1293 return len;
1294 }
1295
1296 /* Data register : 0x05 */
1297 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
1298 {
1299 fdrive_t *cur_drv;
1300 uint32_t retval = 0;
1301 int pos;
1302
1303 cur_drv = get_cur_drv(fdctrl);
1304 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1305 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1306 FLOPPY_ERROR("controller not ready for reading\n");
1307 return 0;
1308 }
1309 pos = fdctrl->data_pos;
1310 if (fdctrl->msr & FD_MSR_NONDMA) {
1311 pos %= FD_SECTOR_LEN;
1312 if (pos == 0) {
1313 if (fdctrl->data_pos != 0)
1314 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1315 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1316 fd_sector(cur_drv));
1317 return 0;
1318 }
1319 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1320 FLOPPY_DPRINTF("error getting sector %d\n",
1321 fd_sector(cur_drv));
1322 /* Sure, image size is too small... */
1323 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1324 }
1325 }
1326 }
1327 retval = fdctrl->fifo[pos];
1328 if (++fdctrl->data_pos == fdctrl->data_len) {
1329 fdctrl->data_pos = 0;
1330 /* Switch from transfer mode to status mode
1331 * then from status mode to command mode
1332 */
1333 if (fdctrl->msr & FD_MSR_NONDMA) {
1334 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1335 } else {
1336 fdctrl_reset_fifo(fdctrl);
1337 fdctrl_reset_irq(fdctrl);
1338 }
1339 }
1340 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1341
1342 return retval;
1343 }
1344
1345 static void fdctrl_format_sector (fdctrl_t *fdctrl)
1346 {
1347 fdrive_t *cur_drv;
1348 uint8_t kh, kt, ks;
1349
1350 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1351 cur_drv = get_cur_drv(fdctrl);
1352 kt = fdctrl->fifo[6];
1353 kh = fdctrl->fifo[7];
1354 ks = fdctrl->fifo[8];
1355 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1356 GET_CUR_DRV(fdctrl), kh, kt, ks,
1357 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1358 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1359 case 2:
1360 /* sect too big */
1361 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1362 fdctrl->fifo[3] = kt;
1363 fdctrl->fifo[4] = kh;
1364 fdctrl->fifo[5] = ks;
1365 return;
1366 case 3:
1367 /* track too big */
1368 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1369 fdctrl->fifo[3] = kt;
1370 fdctrl->fifo[4] = kh;
1371 fdctrl->fifo[5] = ks;
1372 return;
1373 case 4:
1374 /* No seek enabled */
1375 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1376 fdctrl->fifo[3] = kt;
1377 fdctrl->fifo[4] = kh;
1378 fdctrl->fifo[5] = ks;
1379 return;
1380 case 1:
1381 fdctrl->data_state |= FD_STATE_SEEK;
1382 break;
1383 default:
1384 break;
1385 }
1386 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1387 if (cur_drv->bs == NULL ||
1388 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1389 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1390 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1391 } else {
1392 if (cur_drv->sect == cur_drv->last_sect) {
1393 fdctrl->data_state &= ~FD_STATE_FORMAT;
1394 /* Last sector done */
1395 if (FD_DID_SEEK(fdctrl->data_state))
1396 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1397 else
1398 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1399 } else {
1400 /* More to do */
1401 fdctrl->data_pos = 0;
1402 fdctrl->data_len = 4;
1403 }
1404 }
1405 }
1406
1407 static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
1408 {
1409 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1410 fdctrl->fifo[0] = fdctrl->lock << 4;
1411 fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1412 }
1413
1414 static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
1415 {
1416 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1417
1418 /* Drives position */
1419 fdctrl->fifo[0] = drv0(fdctrl)->track;
1420 fdctrl->fifo[1] = drv1(fdctrl)->track;
1421 #if MAX_FD == 4
1422 fdctrl->fifo[2] = drv2(fdctrl)->track;
1423 fdctrl->fifo[3] = drv3(fdctrl)->track;
1424 #else
1425 fdctrl->fifo[2] = 0;
1426 fdctrl->fifo[3] = 0;
1427 #endif
1428 /* timers */
1429 fdctrl->fifo[4] = fdctrl->timer0;
1430 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1431 fdctrl->fifo[6] = cur_drv->last_sect;
1432 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1433 (cur_drv->perpendicular << 2);
1434 fdctrl->fifo[8] = fdctrl->config;
1435 fdctrl->fifo[9] = fdctrl->precomp_trk;
1436 fdctrl_set_fifo(fdctrl, 10, 0);
1437 }
1438
1439 static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
1440 {
1441 /* Controller's version */
1442 fdctrl->fifo[0] = fdctrl->version;
1443 fdctrl_set_fifo(fdctrl, 1, 1);
1444 }
1445
1446 static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
1447 {
1448 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1449 fdctrl_set_fifo(fdctrl, 1, 0);
1450 }
1451
1452 static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
1453 {
1454 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1455
1456 /* Drives position */
1457 drv0(fdctrl)->track = fdctrl->fifo[3];
1458 drv1(fdctrl)->track = fdctrl->fifo[4];
1459 #if MAX_FD == 4
1460 drv2(fdctrl)->track = fdctrl->fifo[5];
1461 drv3(fdctrl)->track = fdctrl->fifo[6];
1462 #endif
1463 /* timers */
1464 fdctrl->timer0 = fdctrl->fifo[7];
1465 fdctrl->timer1 = fdctrl->fifo[8];
1466 cur_drv->last_sect = fdctrl->fifo[9];
1467 fdctrl->lock = fdctrl->fifo[10] >> 7;
1468 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1469 fdctrl->config = fdctrl->fifo[11];
1470 fdctrl->precomp_trk = fdctrl->fifo[12];
1471 fdctrl->pwrd = fdctrl->fifo[13];
1472 fdctrl_reset_fifo(fdctrl);
1473 }
1474
1475 static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
1476 {
1477 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1478
1479 fdctrl->fifo[0] = 0;
1480 fdctrl->fifo[1] = 0;
1481 /* Drives position */
1482 fdctrl->fifo[2] = drv0(fdctrl)->track;
1483 fdctrl->fifo[3] = drv1(fdctrl)->track;
1484 #if MAX_FD == 4
1485 fdctrl->fifo[4] = drv2(fdctrl)->track;
1486 fdctrl->fifo[5] = drv3(fdctrl)->track;
1487 #else
1488 fdctrl->fifo[4] = 0;
1489 fdctrl->fifo[5] = 0;
1490 #endif
1491 /* timers */
1492 fdctrl->fifo[6] = fdctrl->timer0;
1493 fdctrl->fifo[7] = fdctrl->timer1;
1494 fdctrl->fifo[8] = cur_drv->last_sect;
1495 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1496 (cur_drv->perpendicular << 2);
1497 fdctrl->fifo[10] = fdctrl->config;
1498 fdctrl->fifo[11] = fdctrl->precomp_trk;
1499 fdctrl->fifo[12] = fdctrl->pwrd;
1500 fdctrl->fifo[13] = 0;
1501 fdctrl->fifo[14] = 0;
1502 fdctrl_set_fifo(fdctrl, 15, 1);
1503 }
1504
1505 static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
1506 {
1507 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1508
1509 /* XXX: should set main status register to busy */
1510 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1511 qemu_mod_timer(fdctrl->result_timer,
1512 qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));
1513 }
1514
1515 static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
1516 {
1517 fdrive_t *cur_drv;
1518
1519 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1520 cur_drv = get_cur_drv(fdctrl);
1521 fdctrl->data_state |= FD_STATE_FORMAT;
1522 if (fdctrl->fifo[0] & 0x80)
1523 fdctrl->data_state |= FD_STATE_MULTI;
1524 else
1525 fdctrl->data_state &= ~FD_STATE_MULTI;
1526 fdctrl->data_state &= ~FD_STATE_SEEK;
1527 cur_drv->bps =
1528 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1529 #if 0
1530 cur_drv->last_sect =
1531 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1532 fdctrl->fifo[3] / 2;
1533 #else
1534 cur_drv->last_sect = fdctrl->fifo[3];
1535 #endif
1536 /* TODO: implement format using DMA expected by the Bochs BIOS
1537 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1538 * the sector with the specified fill byte
1539 */
1540 fdctrl->data_state &= ~FD_STATE_FORMAT;
1541 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1542 }
1543
1544 static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
1545 {
1546 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1547 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1548 if (fdctrl->fifo[2] & 1)
1549 fdctrl->dor &= ~FD_DOR_DMAEN;
1550 else
1551 fdctrl->dor |= FD_DOR_DMAEN;
1552 /* No result back */
1553 fdctrl_reset_fifo(fdctrl);
1554 }
1555
1556 static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
1557 {
1558 fdrive_t *cur_drv;
1559
1560 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1561 cur_drv = get_cur_drv(fdctrl);
1562 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1563 /* 1 Byte status back */
1564 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1565 (cur_drv->track == 0 ? 0x10 : 0x00) |
1566 (cur_drv->head << 2) |
1567 GET_CUR_DRV(fdctrl) |
1568 0x28;
1569 fdctrl_set_fifo(fdctrl, 1, 0);
1570 }
1571
1572 static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
1573 {
1574 fdrive_t *cur_drv;
1575
1576 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1577 cur_drv = get_cur_drv(fdctrl);
1578 fd_recalibrate(cur_drv);
1579 fdctrl_reset_fifo(fdctrl);
1580 /* Raise Interrupt */
1581 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1582 }
1583
1584 static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
1585 {
1586 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1587
1588 if(fdctrl->reset_sensei > 0) {
1589 fdctrl->fifo[0] =
1590 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1591 fdctrl->reset_sensei--;
1592 } else {
1593 /* XXX: status0 handling is broken for read/write
1594 commands, so we do this hack. It should be suppressed
1595 ASAP */
1596 fdctrl->fifo[0] =
1597 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1598 }
1599
1600 fdctrl->fifo[1] = cur_drv->track;
1601 fdctrl_set_fifo(fdctrl, 2, 0);
1602 fdctrl_reset_irq(fdctrl);
1603 fdctrl->status0 = FD_SR0_RDYCHG;
1604 }
1605
1606 static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
1607 {
1608 fdrive_t *cur_drv;
1609
1610 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1611 cur_drv = get_cur_drv(fdctrl);
1612 fdctrl_reset_fifo(fdctrl);
1613 if (fdctrl->fifo[2] > cur_drv->max_track) {
1614 fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1615 } else {
1616 cur_drv->track = fdctrl->fifo[2];
1617 /* Raise Interrupt */
1618 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1619 }
1620 }
1621
1622 static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
1623 {
1624 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1625
1626 if (fdctrl->fifo[1] & 0x80)
1627 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1628 /* No result back */
1629 fdctrl_reset_fifo(fdctrl);
1630 }
1631
1632 static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
1633 {
1634 fdctrl->config = fdctrl->fifo[2];
1635 fdctrl->precomp_trk = fdctrl->fifo[3];
1636 /* No result back */
1637 fdctrl_reset_fifo(fdctrl);
1638 }
1639
1640 static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
1641 {
1642 fdctrl->pwrd = fdctrl->fifo[1];
1643 fdctrl->fifo[0] = fdctrl->fifo[1];
1644 fdctrl_set_fifo(fdctrl, 1, 1);
1645 }
1646
1647 static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
1648 {
1649 /* No result back */
1650 fdctrl_reset_fifo(fdctrl);
1651 }
1652
1653 static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
1654 {
1655 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1656
1657 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1658 /* Command parameters done */
1659 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1660 fdctrl->fifo[0] = fdctrl->fifo[1];
1661 fdctrl->fifo[2] = 0;
1662 fdctrl->fifo[3] = 0;
1663 fdctrl_set_fifo(fdctrl, 4, 1);
1664 } else {
1665 fdctrl_reset_fifo(fdctrl);
1666 }
1667 } else if (fdctrl->data_len > 7) {
1668 /* ERROR */
1669 fdctrl->fifo[0] = 0x80 |
1670 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1671 fdctrl_set_fifo(fdctrl, 1, 1);
1672 }
1673 }
1674
1675 static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
1676 {
1677 fdrive_t *cur_drv;
1678
1679 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1680 cur_drv = get_cur_drv(fdctrl);
1681 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1682 cur_drv->track = cur_drv->max_track - 1;
1683 } else {
1684 cur_drv->track += fdctrl->fifo[2];
1685 }
1686 fdctrl_reset_fifo(fdctrl);
1687 /* Raise Interrupt */
1688 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1689 }
1690
1691 static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
1692 {
1693 fdrive_t *cur_drv;
1694
1695 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1696 cur_drv = get_cur_drv(fdctrl);
1697 if (fdctrl->fifo[2] > cur_drv->track) {
1698 cur_drv->track = 0;
1699 } else {
1700 cur_drv->track -= fdctrl->fifo[2];
1701 }
1702 fdctrl_reset_fifo(fdctrl);
1703 /* Raise Interrupt */
1704 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1705 }
1706
1707 static const struct {
1708 uint8_t value;
1709 uint8_t mask;
1710 const char* name;
1711 int parameters;
1712 void (*handler)(fdctrl_t *fdctrl, int direction);
1713 int direction;
1714 } handlers[] = {
1715 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1716 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1717 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1718 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1719 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1720 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1721 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1722 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1723 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1724 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1725 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1726 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1727 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1728 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1729 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1730 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1731 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1732 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1733 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1734 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1735 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1736 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1737 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1738 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1739 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1740 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1741 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1742 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1743 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1744 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1745 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1746 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1747 };
1748 /* Associate command to an index in the 'handlers' array */
1749 static uint8_t command_to_handler[256];
1750
1751 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
1752 {
1753 fdrive_t *cur_drv;
1754 int pos;
1755
1756 /* Reset mode */
1757 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1758 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1759 return;
1760 }
1761 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1762 FLOPPY_ERROR("controller not ready for writing\n");
1763 return;
1764 }
1765 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1766 /* Is it write command time ? */
1767 if (fdctrl->msr & FD_MSR_NONDMA) {
1768 /* FIFO data write */
1769 pos = fdctrl->data_pos++;
1770 pos %= FD_SECTOR_LEN;
1771 fdctrl->fifo[pos] = value;
1772 if (pos == FD_SECTOR_LEN - 1 ||
1773 fdctrl->data_pos == fdctrl->data_len) {
1774 cur_drv = get_cur_drv(fdctrl);
1775 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1776 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1777 return;
1778 }
1779 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1780 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1781 fd_sector(cur_drv));
1782 return;
1783 }
1784 }
1785 /* Switch from transfer mode to status mode
1786 * then from status mode to command mode
1787 */
1788 if (fdctrl->data_pos == fdctrl->data_len)
1789 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1790 return;
1791 }
1792 if (fdctrl->data_pos == 0) {
1793 /* Command */
1794 pos = command_to_handler[value & 0xff];
1795 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1796 fdctrl->data_len = handlers[pos].parameters + 1;
1797 }
1798
1799 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1800 fdctrl->fifo[fdctrl->data_pos++] = value;
1801 if (fdctrl->data_pos == fdctrl->data_len) {
1802 /* We now have all parameters
1803 * and will be able to treat the command
1804 */
1805 if (fdctrl->data_state & FD_STATE_FORMAT) {
1806 fdctrl_format_sector(fdctrl);
1807 return;
1808 }
1809
1810 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1811 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1812 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1813 }
1814 }
1815
1816 static void fdctrl_result_timer(void *opaque)
1817 {
1818 fdctrl_t *fdctrl = opaque;
1819 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1820
1821 /* Pretend we are spinning.
1822 * This is needed for Coherent, which uses READ ID to check for
1823 * sector interleaving.
1824 */
1825 if (cur_drv->last_sect != 0) {
1826 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1827 }
1828 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1829 }
1830
1831 /* Init functions */
1832 static void fdctrl_connect_drives(fdctrl_t *fdctrl, BlockDriverState **fds)
1833 {
1834 unsigned int i;
1835
1836 for (i = 0; i < MAX_FD; i++) {
1837 fd_init(&fdctrl->drives[i], fds[i]);
1838 fd_revalidate(&fdctrl->drives[i]);
1839 }
1840 }
1841
1842 fdctrl_t *fdctrl_init_isa(BlockDriverState **fds)
1843 {
1844 fdctrl_t *fdctrl;
1845 ISADevice *dev;
1846 int dma_chann = 2;
1847
1848 dev = isa_create_simple("isa-fdc");
1849 fdctrl = &(DO_UPCAST(fdctrl_isabus_t, busdev, dev)->state);
1850
1851 fdctrl->dma_chann = dma_chann;
1852 DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
1853
1854 fdctrl_connect_drives(fdctrl, fds);
1855
1856 return fdctrl;
1857 }
1858
1859 fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1860 target_phys_addr_t mmio_base,
1861 BlockDriverState **fds)
1862 {
1863 fdctrl_t *fdctrl;
1864 DeviceState *dev;
1865 fdctrl_sysbus_t *sys;
1866
1867 dev = qdev_create(NULL, "sysbus-fdc");
1868 qdev_init(dev);
1869 sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
1870 fdctrl = &sys->state;
1871 sysbus_connect_irq(&sys->busdev, 0, irq);
1872 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1873
1874 fdctrl->dma_chann = dma_chann;
1875 DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
1876 fdctrl_connect_drives(fdctrl, fds);
1877
1878 return fdctrl;
1879 }
1880
1881 fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1882 BlockDriverState **fds, qemu_irq *fdc_tc)
1883 {
1884 DeviceState *dev;
1885 fdctrl_sysbus_t *sys;
1886 fdctrl_t *fdctrl;
1887
1888 dev = qdev_create(NULL, "SUNW,fdtwo");
1889 qdev_init(dev);
1890 sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
1891 fdctrl = &sys->state;
1892 sysbus_connect_irq(&sys->busdev, 0, irq);
1893 sysbus_mmio_map(&sys->busdev, 0, io_base);
1894 *fdc_tc = qdev_get_gpio_in(dev, 0);
1895
1896 fdctrl->dma_chann = -1;
1897
1898 fdctrl_connect_drives(fdctrl, fds);
1899
1900 return fdctrl;
1901 }
1902
1903 static int fdctrl_init_common(fdctrl_t *fdctrl)
1904 {
1905 int i, j;
1906 static int command_tables_inited = 0;
1907
1908 /* Fill 'command_to_handler' lookup table */
1909 if (!command_tables_inited) {
1910 command_tables_inited = 1;
1911 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1912 for (j = 0; j < sizeof(command_to_handler); j++) {
1913 if ((j & handlers[i].mask) == handlers[i].value) {
1914 command_to_handler[j] = i;
1915 }
1916 }
1917 }
1918 }
1919
1920 FLOPPY_DPRINTF("init controller\n");
1921 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1922 fdctrl->fifo_size = 512;
1923 fdctrl->result_timer = qemu_new_timer(vm_clock,
1924 fdctrl_result_timer, fdctrl);
1925
1926 fdctrl->version = 0x90; /* Intel 82078 controller */
1927 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1928 fdctrl->num_floppies = MAX_FD;
1929
1930 fdctrl_external_reset(fdctrl);
1931 vmstate_register(-1, &vmstate_fdc, fdctrl);
1932 qemu_register_reset(fdctrl_external_reset, fdctrl);
1933 return 0;
1934 }
1935
1936 static int isabus_fdc_init1(ISADevice *dev)
1937 {
1938 fdctrl_isabus_t *isa = DO_UPCAST(fdctrl_isabus_t, busdev, dev);
1939 fdctrl_t *fdctrl = &isa->state;
1940 int iobase = 0x3f0;
1941 int isairq = 6;
1942
1943 register_ioport_read(iobase + 0x01, 5, 1,
1944 &fdctrl_read_port, fdctrl);
1945 register_ioport_read(iobase + 0x07, 1, 1,
1946 &fdctrl_read_port, fdctrl);
1947 register_ioport_write(iobase + 0x01, 5, 1,
1948 &fdctrl_write_port, fdctrl);
1949 register_ioport_write(iobase + 0x07, 1, 1,
1950 &fdctrl_write_port, fdctrl);
1951 isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
1952
1953 return fdctrl_init_common(fdctrl);
1954 }
1955
1956 static int sysbus_fdc_init1(SysBusDevice *dev)
1957 {
1958 fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state);
1959 int io;
1960
1961 io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl);
1962 sysbus_init_mmio(dev, 0x08, io);
1963 sysbus_init_irq(dev, &fdctrl->irq);
1964 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1965
1966 return fdctrl_init_common(fdctrl);
1967 }
1968
1969 static int sun4m_fdc_init1(SysBusDevice *dev)
1970 {
1971 fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state);
1972 int io;
1973
1974 io = cpu_register_io_memory(fdctrl_mem_read_strict,
1975 fdctrl_mem_write_strict, fdctrl);
1976 sysbus_init_mmio(dev, 0x08, io);
1977 sysbus_init_irq(dev, &fdctrl->irq);
1978 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1979
1980 fdctrl->sun4m = 1;
1981 return fdctrl_init_common(fdctrl);
1982 }
1983
1984 static ISADeviceInfo isa_fdc_info = {
1985 .init = isabus_fdc_init1,
1986 .qdev.name = "isa-fdc",
1987 .qdev.size = sizeof(fdctrl_isabus_t),
1988 };
1989
1990 static SysBusDeviceInfo sysbus_fdc_info = {
1991 .init = sysbus_fdc_init1,
1992 .qdev.name = "sysbus-fdc",
1993 .qdev.size = sizeof(fdctrl_sysbus_t),
1994 };
1995
1996 static SysBusDeviceInfo sun4m_fdc_info = {
1997 .init = sun4m_fdc_init1,
1998 .qdev.name = "SUNW,fdtwo",
1999 .qdev.size = sizeof(fdctrl_sysbus_t),
2000 };
2001
2002 static void fdc_register_devices(void)
2003 {
2004 isa_qdev_register(&isa_fdc_info);
2005 sysbus_register_withprop(&sysbus_fdc_info);
2006 sysbus_register_withprop(&sun4m_fdc_info);
2007 }
2008
2009 device_init(fdc_register_devices)
Qemu copy for testing