hw/gpio/omap_gpio.c

   1 /*
   2  * TI OMAP processors GPIO emulation.
   3  *
   4  * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
   5  * Copyright (C) 2007-2009 Nokia Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 or
  10  * (at your option) version 3 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "hw/hw.h"
  22 #include "hw/arm/omap.h"
  23 #include "hw/sysbus.h"
  24
  25 struct omap_gpio_s {
  26     qemu_irq irq;
  27     qemu_irq handler[16];
  28
  29     uint16_t inputs;
  30     uint16_t outputs;
  31     uint16_t dir;
  32     uint16_t edge;
  33     uint16_t mask;
  34     uint16_t ints;
  35     uint16_t pins;
  36 };
  37
  38 #define TYPE_OMAP1_GPIO "omap-gpio"
  39 #define OMAP1_GPIO(obj) \
  40     OBJECT_CHECK(struct omap_gpif_s, (obj), TYPE_OMAP1_GPIO)
  41
  42 struct omap_gpif_s {
  43     SysBusDevice parent_obj;
  44
  45     MemoryRegion iomem;
  46     int mpu_model;
  47     void *clk;
  48     struct omap_gpio_s omap1;
  49 };
  50
  51 /* General-Purpose I/O of OMAP1 */
  52 static void omap_gpio_set(void *opaque, int line, int level)
  53 {
  54     struct omap_gpio_s *s = &((struct omap_gpif_s *) opaque)->omap1;
  55     uint16_t prev = s->inputs;
  56
  57     if (level)
  58         s->inputs |= 1 << line;
  59     else
  60         s->inputs &= ~(1 << line);
  61
  62     if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
  63                     (1 << line) & s->dir & ~s->mask) {
  64         s->ints |= 1 << line;
  65         qemu_irq_raise(s->irq);
  66     }
  67 }
  68
  69 static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
  70                                unsigned size)
  71 {
  72     struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
  73     int offset = addr & OMAP_MPUI_REG_MASK;
  74
  75     if (size != 2) {
  76         return omap_badwidth_read16(opaque, addr);
  77     }
  78
  79     switch (offset) {
  80     case 0x00:  /* DATA_INPUT */
  81         return s->inputs & s->pins;
  82
  83     case 0x04:  /* DATA_OUTPUT */
  84         return s->outputs;
  85
  86     case 0x08:  /* DIRECTION_CONTROL */
  87         return s->dir;
  88
  89     case 0x0c:  /* INTERRUPT_CONTROL */
  90         return s->edge;
  91
  92     case 0x10:  /* INTERRUPT_MASK */
  93         return s->mask;
  94
  95     case 0x14:  /* INTERRUPT_STATUS */
  96         return s->ints;
  97
  98     case 0x18:  /* PIN_CONTROL (not in OMAP310) */
  99         OMAP_BAD_REG(addr);
 100         return s->pins;
 101     }
 102
 103     OMAP_BAD_REG(addr);
 104     return 0;
 105 }
 106
 107 static void omap_gpio_write(void *opaque, hwaddr addr,
 108                             uint64_t value, unsigned size)
 109 {
 110     struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
 111     int offset = addr & OMAP_MPUI_REG_MASK;
 112     uint16_t diff;
 113     int ln;
 114
 115     if (size != 2) {
 116         return omap_badwidth_write16(opaque, addr, value);
 117     }
 118
 119     switch (offset) {
 120     case 0x00:  /* DATA_INPUT */
 121         OMAP_RO_REG(addr);
 122         return;
 123
 124     case 0x04:  /* DATA_OUTPUT */
 125         diff = (s->outputs ^ value) & ~s->dir;
 126         s->outputs = value;
 127         while ((ln = ffs(diff))) {
 128             ln --;
 129             if (s->handler[ln])
 130                 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
 131             diff &= ~(1 << ln);
 132         }
 133         break;
 134
 135     case 0x08:  /* DIRECTION_CONTROL */
 136         diff = s->outputs & (s->dir ^ value);
 137         s->dir = value;
 138
 139         value = s->outputs & ~s->dir;
 140         while ((ln = ffs(diff))) {
 141             ln --;
 142             if (s->handler[ln])
 143                 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
 144             diff &= ~(1 << ln);
 145         }
 146         break;
 147
 148     case 0x0c:  /* INTERRUPT_CONTROL */
 149         s->edge = value;
 150         break;
 151
 152     case 0x10:  /* INTERRUPT_MASK */
 153         s->mask = value;
 154         break;
 155
 156     case 0x14:  /* INTERRUPT_STATUS */
 157         s->ints &= ~value;
 158         if (!s->ints)
 159             qemu_irq_lower(s->irq);
 160         break;
 161
 162     case 0x18:  /* PIN_CONTROL (not in OMAP310 TRM) */
 163         OMAP_BAD_REG(addr);
 164         s->pins = value;
 165         break;
 166
 167     default:
 168         OMAP_BAD_REG(addr);
 169         return;
 170     }
 171 }
 172
 173 /* *Some* sources say the memory region is 32-bit.  */
 174 static const MemoryRegionOps omap_gpio_ops = {
 175     .read = omap_gpio_read,
 176     .write = omap_gpio_write,
 177     .endianness = DEVICE_NATIVE_ENDIAN,
 178 };
 179
 180 static void omap_gpio_reset(struct omap_gpio_s *s)
 181 {
 182     s->inputs = 0;
 183     s->outputs = ~0;
 184     s->dir = ~0;
 185     s->edge = ~0;
 186     s->mask = ~0;
 187     s->ints = 0;
 188     s->pins = ~0;
 189 }
 190
 191 struct omap2_gpio_s {
 192     qemu_irq irq[2];
 193     qemu_irq wkup;
 194     qemu_irq *handler;
 195     MemoryRegion iomem;
 196
 197     uint8_t revision;
 198     uint8_t config[2];
 199     uint32_t inputs;
 200     uint32_t outputs;
 201     uint32_t dir;
 202     uint32_t level[2];
 203     uint32_t edge[2];
 204     uint32_t mask[2];
 205     uint32_t wumask;
 206     uint32_t ints[2];
 207     uint32_t debounce;
 208     uint8_t delay;
 209 };
 210
 211 struct omap2_gpif_s {
 212     SysBusDevice busdev;
 213     MemoryRegion iomem;
 214     int mpu_model;
 215     void *iclk;
 216     void *fclk[6];
 217     int modulecount;
 218     struct omap2_gpio_s *modules;
 219     qemu_irq *handler;
 220     int autoidle;
 221     int gpo;
 222 };
 223
 224 /* General-Purpose Interface of OMAP2/3 */
 225 static inline void omap2_gpio_module_int_update(struct omap2_gpio_s *s,
 226                                                 int line)
 227 {
 228     qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]);
 229 }
 230
 231 static void omap2_gpio_module_wake(struct omap2_gpio_s *s, int line)
 232 {
 233     if (!(s->config[0] & (1 << 2)))                     /* ENAWAKEUP */
 234         return;
 235     if (!(s->config[0] & (3 << 3)))                     /* Force Idle */
 236         return;
 237     if (!(s->wumask & (1 << line)))
 238         return;
 239
 240     qemu_irq_raise(s->wkup);
 241 }
 242
 243 static inline void omap2_gpio_module_out_update(struct omap2_gpio_s *s,
 244                 uint32_t diff)
 245 {
 246     int ln;
 247
 248     s->outputs ^= diff;
 249     diff &= ~s->dir;
 250     while ((ln = ffs(diff))) {
 251         ln --;
 252         qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1);
 253         diff &= ~(1 << ln);
 254     }
 255 }
 256
 257 static void omap2_gpio_module_level_update(struct omap2_gpio_s *s, int line)
 258 {
 259     s->ints[line] |= s->dir &
 260             ((s->inputs & s->level[1]) | (~s->inputs & s->level[0]));
 261     omap2_gpio_module_int_update(s, line);
 262 }
 263
 264 static inline void omap2_gpio_module_int(struct omap2_gpio_s *s, int line)
 265 {
 266     s->ints[0] |= 1 << line;
 267     omap2_gpio_module_int_update(s, 0);
 268     s->ints[1] |= 1 << line;
 269     omap2_gpio_module_int_update(s, 1);
 270     omap2_gpio_module_wake(s, line);
 271 }
 272
 273 static void omap2_gpio_set(void *opaque, int line, int level)
 274 {
 275     struct omap2_gpif_s *p = opaque;
 276     struct omap2_gpio_s *s = &p->modules[line >> 5];
 277
 278     line &= 31;
 279     if (level) {
 280         if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1]))
 281             omap2_gpio_module_int(s, line);
 282         s->inputs |= 1 << line;
 283     } else {
 284         if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0]))
 285             omap2_gpio_module_int(s, line);
 286         s->inputs &= ~(1 << line);
 287     }
 288 }
 289
 290 static void omap2_gpio_module_reset(struct omap2_gpio_s *s)
 291 {
 292     s->config[0] = 0;
 293     s->config[1] = 2;
 294     s->ints[0] = 0;
 295     s->ints[1] = 0;
 296     s->mask[0] = 0;
 297     s->mask[1] = 0;
 298     s->wumask = 0;
 299     s->dir = ~0;
 300     s->level[0] = 0;
 301     s->level[1] = 0;
 302     s->edge[0] = 0;
 303     s->edge[1] = 0;
 304     s->debounce = 0;
 305     s->delay = 0;
 306 }
 307
 308 static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr)
 309 {
 310     struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
 311
 312     switch (addr) {
 313     case 0x00:  /* GPIO_REVISION */
 314         return s->revision;
 315
 316     case 0x10:  /* GPIO_SYSCONFIG */
 317         return s->config[0];
 318
 319     case 0x14:  /* GPIO_SYSSTATUS */
 320         return 0x01;
 321
 322     case 0x18:  /* GPIO_IRQSTATUS1 */
 323         return s->ints[0];
 324
 325     case 0x1c:  /* GPIO_IRQENABLE1 */
 326     case 0x60:  /* GPIO_CLEARIRQENABLE1 */
 327     case 0x64:  /* GPIO_SETIRQENABLE1 */
 328         return s->mask[0];
 329
 330     case 0x20:  /* GPIO_WAKEUPENABLE */
 331     case 0x80:  /* GPIO_CLEARWKUENA */
 332     case 0x84:  /* GPIO_SETWKUENA */
 333         return s->wumask;
 334
 335     case 0x28:  /* GPIO_IRQSTATUS2 */
 336         return s->ints[1];
 337
 338     case 0x2c:  /* GPIO_IRQENABLE2 */
 339     case 0x70:  /* GPIO_CLEARIRQENABLE2 */
 340     case 0x74:  /* GPIO_SETIREQNEABLE2 */
 341         return s->mask[1];
 342
 343     case 0x30:  /* GPIO_CTRL */
 344         return s->config[1];
 345
 346     case 0x34:  /* GPIO_OE */
 347         return s->dir;
 348
 349     case 0x38:  /* GPIO_DATAIN */
 350         return s->inputs;
 351
 352     case 0x3c:  /* GPIO_DATAOUT */
 353     case 0x90:  /* GPIO_CLEARDATAOUT */
 354     case 0x94:  /* GPIO_SETDATAOUT */
 355         return s->outputs;
 356
 357     case 0x40:  /* GPIO_LEVELDETECT0 */
 358         return s->level[0];
 359
 360     case 0x44:  /* GPIO_LEVELDETECT1 */
 361         return s->level[1];
 362
 363     case 0x48:  /* GPIO_RISINGDETECT */
 364         return s->edge[0];
 365
 366     case 0x4c:  /* GPIO_FALLINGDETECT */
 367         return s->edge[1];
 368
 369     case 0x50:  /* GPIO_DEBOUNCENABLE */
 370         return s->debounce;
 371
 372     case 0x54:  /* GPIO_DEBOUNCINGTIME */
 373         return s->delay;
 374     }
 375
 376     OMAP_BAD_REG(addr);
 377     return 0;
 378 }
 379
 380 static void omap2_gpio_module_write(void *opaque, hwaddr addr,
 381                 uint32_t value)
 382 {
 383     struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
 384     uint32_t diff;
 385     int ln;
 386
 387     switch (addr) {
 388     case 0x00:  /* GPIO_REVISION */
 389     case 0x14:  /* GPIO_SYSSTATUS */
 390     case 0x38:  /* GPIO_DATAIN */
 391         OMAP_RO_REG(addr);
 392         break;
 393
 394     case 0x10:  /* GPIO_SYSCONFIG */
 395         if (((value >> 3) & 3) == 3)
 396             fprintf(stderr, "%s: bad IDLEMODE value\n", __FUNCTION__);
 397         if (value & 2)
 398             omap2_gpio_module_reset(s);
 399         s->config[0] = value & 0x1d;
 400         break;
 401
 402     case 0x18:  /* GPIO_IRQSTATUS1 */
 403         if (s->ints[0] & value) {
 404             s->ints[0] &= ~value;
 405             omap2_gpio_module_level_update(s, 0);
 406         }
 407         break;
 408
 409     case 0x1c:  /* GPIO_IRQENABLE1 */
 410         s->mask[0] = value;
 411         omap2_gpio_module_int_update(s, 0);
 412         break;
 413
 414     case 0x20:  /* GPIO_WAKEUPENABLE */
 415         s->wumask = value;
 416         break;
 417
 418     case 0x28:  /* GPIO_IRQSTATUS2 */
 419         if (s->ints[1] & value) {
 420             s->ints[1] &= ~value;
 421             omap2_gpio_module_level_update(s, 1);
 422         }
 423         break;
 424
 425     case 0x2c:  /* GPIO_IRQENABLE2 */
 426         s->mask[1] = value;
 427         omap2_gpio_module_int_update(s, 1);
 428         break;
 429
 430     case 0x30:  /* GPIO_CTRL */
 431         s->config[1] = value & 7;
 432         break;
 433
 434     case 0x34:  /* GPIO_OE */
 435         diff = s->outputs & (s->dir ^ value);
 436         s->dir = value;
 437
 438         value = s->outputs & ~s->dir;
 439         while ((ln = ffs(diff))) {
 440             diff &= ~(1 <<-- ln);
 441             qemu_set_irq(s->handler[ln], (value >> ln) & 1);
 442         }
 443
 444         omap2_gpio_module_level_update(s, 0);
 445         omap2_gpio_module_level_update(s, 1);
 446         break;
 447
 448     case 0x3c:  /* GPIO_DATAOUT */
 449         omap2_gpio_module_out_update(s, s->outputs ^ value);
 450         break;
 451
 452     case 0x40:  /* GPIO_LEVELDETECT0 */
 453         s->level[0] = value;
 454         omap2_gpio_module_level_update(s, 0);
 455         omap2_gpio_module_level_update(s, 1);
 456         break;
 457
 458     case 0x44:  /* GPIO_LEVELDETECT1 */
 459         s->level[1] = value;
 460         omap2_gpio_module_level_update(s, 0);
 461         omap2_gpio_module_level_update(s, 1);
 462         break;
 463
 464     case 0x48:  /* GPIO_RISINGDETECT */
 465         s->edge[0] = value;
 466         break;
 467
 468     case 0x4c:  /* GPIO_FALLINGDETECT */
 469         s->edge[1] = value;
 470         break;
 471
 472     case 0x50:  /* GPIO_DEBOUNCENABLE */
 473         s->debounce = value;
 474         break;
 475
 476     case 0x54:  /* GPIO_DEBOUNCINGTIME */
 477         s->delay = value;
 478         break;
 479
 480     case 0x60:  /* GPIO_CLEARIRQENABLE1 */
 481         s->mask[0] &= ~value;
 482         omap2_gpio_module_int_update(s, 0);
 483         break;
 484
 485     case 0x64:  /* GPIO_SETIRQENABLE1 */
 486         s->mask[0] |= value;
 487         omap2_gpio_module_int_update(s, 0);
 488         break;
 489
 490     case 0x70:  /* GPIO_CLEARIRQENABLE2 */
 491         s->mask[1] &= ~value;
 492         omap2_gpio_module_int_update(s, 1);
 493         break;
 494
 495     case 0x74:  /* GPIO_SETIREQNEABLE2 */
 496         s->mask[1] |= value;
 497         omap2_gpio_module_int_update(s, 1);
 498         break;
 499
 500     case 0x80:  /* GPIO_CLEARWKUENA */
 501         s->wumask &= ~value;
 502         break;
 503
 504     case 0x84:  /* GPIO_SETWKUENA */
 505         s->wumask |= value;
 506         break;
 507
 508     case 0x90:  /* GPIO_CLEARDATAOUT */
 509         omap2_gpio_module_out_update(s, s->outputs & value);
 510         break;
 511
 512     case 0x94:  /* GPIO_SETDATAOUT */
 513         omap2_gpio_module_out_update(s, ~s->outputs & value);
 514         break;
 515
 516     default:
 517         OMAP_BAD_REG(addr);
 518         return;
 519     }
 520 }
 521
 522 static uint32_t omap2_gpio_module_readp(void *opaque, hwaddr addr)
 523 {
 524     return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3);
 525 }
 526
 527 static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
 528                 uint32_t value)
 529 {
 530     uint32_t cur = 0;
 531     uint32_t mask = 0xffff;
 532
 533     switch (addr & ~3) {
 534     case 0x00:  /* GPIO_REVISION */
 535     case 0x14:  /* GPIO_SYSSTATUS */
 536     case 0x38:  /* GPIO_DATAIN */
 537         OMAP_RO_REG(addr);
 538         break;
 539
 540     case 0x10:  /* GPIO_SYSCONFIG */
 541     case 0x1c:  /* GPIO_IRQENABLE1 */
 542     case 0x20:  /* GPIO_WAKEUPENABLE */
 543     case 0x2c:  /* GPIO_IRQENABLE2 */
 544     case 0x30:  /* GPIO_CTRL */
 545     case 0x34:  /* GPIO_OE */
 546     case 0x3c:  /* GPIO_DATAOUT */
 547     case 0x40:  /* GPIO_LEVELDETECT0 */
 548     case 0x44:  /* GPIO_LEVELDETECT1 */
 549     case 0x48:  /* GPIO_RISINGDETECT */
 550     case 0x4c:  /* GPIO_FALLINGDETECT */
 551     case 0x50:  /* GPIO_DEBOUNCENABLE */
 552     case 0x54:  /* GPIO_DEBOUNCINGTIME */
 553         cur = omap2_gpio_module_read(opaque, addr & ~3) &
 554                 ~(mask << ((addr & 3) << 3));
 555
 556         /* Fall through.  */
 557     case 0x18:  /* GPIO_IRQSTATUS1 */
 558     case 0x28:  /* GPIO_IRQSTATUS2 */
 559     case 0x60:  /* GPIO_CLEARIRQENABLE1 */
 560     case 0x64:  /* GPIO_SETIRQENABLE1 */
 561     case 0x70:  /* GPIO_CLEARIRQENABLE2 */
 562     case 0x74:  /* GPIO_SETIREQNEABLE2 */
 563     case 0x80:  /* GPIO_CLEARWKUENA */
 564     case 0x84:  /* GPIO_SETWKUENA */
 565     case 0x90:  /* GPIO_CLEARDATAOUT */
 566     case 0x94:  /* GPIO_SETDATAOUT */
 567         value <<= (addr & 3) << 3;
 568         omap2_gpio_module_write(opaque, addr, cur | value);
 569         break;
 570
 571     default:
 572         OMAP_BAD_REG(addr);
 573         return;
 574     }
 575 }
 576
 577 static const MemoryRegionOps omap2_gpio_module_ops = {
 578     .old_mmio = {
 579         .read = {
 580             omap2_gpio_module_readp,
 581             omap2_gpio_module_readp,
 582             omap2_gpio_module_read,
 583         },
 584         .write = {
 585             omap2_gpio_module_writep,
 586             omap2_gpio_module_writep,
 587             omap2_gpio_module_write,
 588         },
 589     },
 590     .endianness = DEVICE_NATIVE_ENDIAN,
 591 };
 592
 593 static void omap_gpif_reset(DeviceState *dev)
 594 {
 595     struct omap_gpif_s *s = OMAP1_GPIO(dev);
 596
 597     omap_gpio_reset(&s->omap1);
 598 }
 599
 600 static void omap2_gpif_reset(DeviceState *dev)
 601 {
 602     int i;
 603     struct omap2_gpif_s *s = FROM_SYSBUS(struct omap2_gpif_s,
 604                     SYS_BUS_DEVICE(dev));
 605     for (i = 0; i < s->modulecount; i++) {
 606         omap2_gpio_module_reset(&s->modules[i]);
 607     }
 608     s->autoidle = 0;
 609     s->gpo = 0;
 610 }
 611
 612 static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr,
 613                                     unsigned size)
 614 {
 615     struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
 616
 617     switch (addr) {
 618     case 0x00:  /* IPGENERICOCPSPL_REVISION */
 619         return 0x18;
 620
 621     case 0x10:  /* IPGENERICOCPSPL_SYSCONFIG */
 622         return s->autoidle;
 623
 624     case 0x14:  /* IPGENERICOCPSPL_SYSSTATUS */
 625         return 0x01;
 626
 627     case 0x18:  /* IPGENERICOCPSPL_IRQSTATUS */
 628         return 0x00;
 629
 630     case 0x40:  /* IPGENERICOCPSPL_GPO */
 631         return s->gpo;
 632
 633     case 0x50:  /* IPGENERICOCPSPL_GPI */
 634         return 0x00;
 635     }
 636
 637     OMAP_BAD_REG(addr);
 638     return 0;
 639 }
 640
 641 static void omap2_gpif_top_write(void *opaque, hwaddr addr,
 642                                  uint64_t value, unsigned size)
 643 {
 644     struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
 645
 646     switch (addr) {
 647     case 0x00:  /* IPGENERICOCPSPL_REVISION */
 648     case 0x14:  /* IPGENERICOCPSPL_SYSSTATUS */
 649     case 0x18:  /* IPGENERICOCPSPL_IRQSTATUS */
 650     case 0x50:  /* IPGENERICOCPSPL_GPI */
 651         OMAP_RO_REG(addr);
 652         break;
 653
 654     case 0x10:  /* IPGENERICOCPSPL_SYSCONFIG */
 655         if (value & (1 << 1))                                   /* SOFTRESET */
 656             omap2_gpif_reset(&s->busdev.qdev);
 657         s->autoidle = value & 1;
 658         break;
 659
 660     case 0x40:  /* IPGENERICOCPSPL_GPO */
 661         s->gpo = value & 1;
 662         break;
 663
 664     default:
 665         OMAP_BAD_REG(addr);
 666         return;
 667     }
 668 }
 669
 670 static const MemoryRegionOps omap2_gpif_top_ops = {
 671     .read = omap2_gpif_top_read,
 672     .write = omap2_gpif_top_write,
 673     .endianness = DEVICE_NATIVE_ENDIAN,
 674 };
 675
 676 static int omap_gpio_init(SysBusDevice *sbd)
 677 {
 678     DeviceState *dev = DEVICE(sbd);
 679     struct omap_gpif_s *s = OMAP1_GPIO(dev);
 680
 681     if (!s->clk) {
 682         hw_error("omap-gpio: clk not connected\n");
 683     }
 684     qdev_init_gpio_in(dev, omap_gpio_set, 16);
 685     qdev_init_gpio_out(dev, s->omap1.handler, 16);
 686     sysbus_init_irq(sbd, &s->omap1.irq);
 687     memory_region_init_io(&s->iomem, OBJECT(s), &omap_gpio_ops, &s->omap1,
 688                           "omap.gpio", 0x1000);
 689     sysbus_init_mmio(sbd, &s->iomem);
 690     return 0;
 691 }
 692
 693 static int omap2_gpio_init(SysBusDevice *dev)
 694 {
 695     int i;
 696     struct omap2_gpif_s *s = FROM_SYSBUS(struct omap2_gpif_s, dev);
 697     if (!s->iclk) {
 698         hw_error("omap2-gpio: iclk not connected\n");
 699     }
 700     if (s->mpu_model < omap3430) {
 701         s->modulecount = (s->mpu_model < omap2430) ? 4 : 5;
 702         memory_region_init_io(&s->iomem, OBJECT(s), &omap2_gpif_top_ops, s,
 703                               "omap2.gpio", 0x1000);
 704         sysbus_init_mmio(dev, &s->iomem);
 705     } else {
 706         s->modulecount = 6;
 707     }
 708     s->modules = g_malloc0(s->modulecount * sizeof(struct omap2_gpio_s));
 709     s->handler = g_malloc0(s->modulecount * 32 * sizeof(qemu_irq));
 710     qdev_init_gpio_in(&dev->qdev, omap2_gpio_set, s->modulecount * 32);
 711     qdev_init_gpio_out(&dev->qdev, s->handler, s->modulecount * 32);
 712     for (i = 0; i < s->modulecount; i++) {
 713         struct omap2_gpio_s *m = &s->modules[i];
 714         if (!s->fclk[i]) {
 715             hw_error("omap2-gpio: fclk%d not connected\n", i);
 716         }
 717         m->revision = (s->mpu_model < omap3430) ? 0x18 : 0x25;
 718         m->handler = &s->handler[i * 32];
 719         sysbus_init_irq(dev, &m->irq[0]); /* mpu irq */
 720         sysbus_init_irq(dev, &m->irq[1]); /* dsp irq */
 721         sysbus_init_irq(dev, &m->wkup);
 722         memory_region_init_io(&m->iomem, OBJECT(s), &omap2_gpio_module_ops, m,
 723                               "omap.gpio-module", 0x1000);
 724         sysbus_init_mmio(dev, &m->iomem);
 725     }
 726     return 0;
 727 }
 728
 729 /* Using qdev pointer properties for the clocks is not ideal.
 730  * qdev should support a generic means of defining a 'port' with
 731  * an arbitrary interface for connecting two devices. Then we
 732  * could reframe the omap clock API in terms of clock ports,
 733  * and get some type safety. For now the best qdev provides is
 734  * passing an arbitrary pointer.
 735  * (It's not possible to pass in the string which is the clock
 736  * name, because this device does not have the necessary information
 737  * (ie the struct omap_mpu_state_s*) to do the clockname to pointer
 738  * translation.)
 739  */
 740
 741 static Property omap_gpio_properties[] = {
 742     DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s, mpu_model, 0),
 743     DEFINE_PROP_PTR("clk", struct omap_gpif_s, clk),
 744     DEFINE_PROP_END_OF_LIST(),
 745 };
 746
 747 static void omap_gpio_class_init(ObjectClass *klass, void *data)
 748 {
 749     DeviceClass *dc = DEVICE_CLASS(klass);
 750     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 751
 752     k->init = omap_gpio_init;
 753     dc->reset = omap_gpif_reset;
 754     dc->props = omap_gpio_properties;
 755 }
 756
 757 static const TypeInfo omap_gpio_info = {
 758     .name          = TYPE_OMAP1_GPIO,
 759     .parent        = TYPE_SYS_BUS_DEVICE,
 760     .instance_size = sizeof(struct omap_gpif_s),
 761     .class_init    = omap_gpio_class_init,
 762 };
 763
 764 static Property omap2_gpio_properties[] = {
 765     DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s, mpu_model, 0),
 766     DEFINE_PROP_PTR("iclk", struct omap2_gpif_s, iclk),
 767     DEFINE_PROP_PTR("fclk0", struct omap2_gpif_s, fclk[0]),
 768     DEFINE_PROP_PTR("fclk1", struct omap2_gpif_s, fclk[1]),
 769     DEFINE_PROP_PTR("fclk2", struct omap2_gpif_s, fclk[2]),
 770     DEFINE_PROP_PTR("fclk3", struct omap2_gpif_s, fclk[3]),
 771     DEFINE_PROP_PTR("fclk4", struct omap2_gpif_s, fclk[4]),
 772     DEFINE_PROP_PTR("fclk5", struct omap2_gpif_s, fclk[5]),
 773     DEFINE_PROP_END_OF_LIST(),
 774 };
 775
 776 static void omap2_gpio_class_init(ObjectClass *klass, void *data)
 777 {
 778     DeviceClass *dc = DEVICE_CLASS(klass);
 779     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 780
 781     k->init = omap2_gpio_init;
 782     dc->reset = omap2_gpif_reset;
 783     dc->props = omap2_gpio_properties;
 784 }
 785
 786 static const TypeInfo omap2_gpio_info = {
 787     .name          = "omap2-gpio",
 788     .parent        = TYPE_SYS_BUS_DEVICE,
 789     .instance_size = sizeof(struct omap2_gpif_s),
 790     .class_init    = omap2_gpio_class_init,
 791 };
 792
 793 static void omap_gpio_register_types(void)
 794 {
 795     type_register_static(&omap_gpio_info);
 796     type_register_static(&omap2_gpio_info);
 797 }
 798
 799 type_init(omap_gpio_register_types)