2 * QEMU GT64120 PCI host
4 * Copyright (c) 2006,2007 Aurelien Jarno
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 typedef target_phys_addr_t pci_addr_t
;
33 #define dprintf(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
35 #define dprintf(fmt, ...)
38 #define GT_REGS (0x1000 >> 2)
40 /* CPU Configuration */
41 #define GT_CPU (0x000 >> 2)
42 #define GT_MULTI (0x120 >> 2)
44 /* CPU Address Decode */
45 #define GT_SCS10LD (0x008 >> 2)
46 #define GT_SCS10HD (0x010 >> 2)
47 #define GT_SCS32LD (0x018 >> 2)
48 #define GT_SCS32HD (0x020 >> 2)
49 #define GT_CS20LD (0x028 >> 2)
50 #define GT_CS20HD (0x030 >> 2)
51 #define GT_CS3BOOTLD (0x038 >> 2)
52 #define GT_CS3BOOTHD (0x040 >> 2)
53 #define GT_PCI0IOLD (0x048 >> 2)
54 #define GT_PCI0IOHD (0x050 >> 2)
55 #define GT_PCI0M0LD (0x058 >> 2)
56 #define GT_PCI0M0HD (0x060 >> 2)
57 #define GT_PCI0M1LD (0x080 >> 2)
58 #define GT_PCI0M1HD (0x088 >> 2)
59 #define GT_PCI1IOLD (0x090 >> 2)
60 #define GT_PCI1IOHD (0x098 >> 2)
61 #define GT_PCI1M0LD (0x0a0 >> 2)
62 #define GT_PCI1M0HD (0x0a8 >> 2)
63 #define GT_PCI1M1LD (0x0b0 >> 2)
64 #define GT_PCI1M1HD (0x0b8 >> 2)
65 #define GT_ISD (0x068 >> 2)
67 #define GT_SCS10AR (0x0d0 >> 2)
68 #define GT_SCS32AR (0x0d8 >> 2)
69 #define GT_CS20R (0x0e0 >> 2)
70 #define GT_CS3BOOTR (0x0e8 >> 2)
72 #define GT_PCI0IOREMAP (0x0f0 >> 2)
73 #define GT_PCI0M0REMAP (0x0f8 >> 2)
74 #define GT_PCI0M1REMAP (0x100 >> 2)
75 #define GT_PCI1IOREMAP (0x108 >> 2)
76 #define GT_PCI1M0REMAP (0x110 >> 2)
77 #define GT_PCI1M1REMAP (0x118 >> 2)
79 /* CPU Error Report */
80 #define GT_CPUERR_ADDRLO (0x070 >> 2)
81 #define GT_CPUERR_ADDRHI (0x078 >> 2)
82 #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
83 #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
84 #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
86 /* CPU Sync Barrier */
87 #define GT_PCI0SYNC (0x0c0 >> 2)
88 #define GT_PCI1SYNC (0x0c8 >> 2)
90 /* SDRAM and Device Address Decode */
91 #define GT_SCS0LD (0x400 >> 2)
92 #define GT_SCS0HD (0x404 >> 2)
93 #define GT_SCS1LD (0x408 >> 2)
94 #define GT_SCS1HD (0x40c >> 2)
95 #define GT_SCS2LD (0x410 >> 2)
96 #define GT_SCS2HD (0x414 >> 2)
97 #define GT_SCS3LD (0x418 >> 2)
98 #define GT_SCS3HD (0x41c >> 2)
99 #define GT_CS0LD (0x420 >> 2)
100 #define GT_CS0HD (0x424 >> 2)
101 #define GT_CS1LD (0x428 >> 2)
102 #define GT_CS1HD (0x42c >> 2)
103 #define GT_CS2LD (0x430 >> 2)
104 #define GT_CS2HD (0x434 >> 2)
105 #define GT_CS3LD (0x438 >> 2)
106 #define GT_CS3HD (0x43c >> 2)
107 #define GT_BOOTLD (0x440 >> 2)
108 #define GT_BOOTHD (0x444 >> 2)
109 #define GT_ADERR (0x470 >> 2)
111 /* SDRAM Configuration */
112 #define GT_SDRAM_CFG (0x448 >> 2)
113 #define GT_SDRAM_OPMODE (0x474 >> 2)
114 #define GT_SDRAM_BM (0x478 >> 2)
115 #define GT_SDRAM_ADDRDECODE (0x47c >> 2)
117 /* SDRAM Parameters */
118 #define GT_SDRAM_B0 (0x44c >> 2)
119 #define GT_SDRAM_B1 (0x450 >> 2)
120 #define GT_SDRAM_B2 (0x454 >> 2)
121 #define GT_SDRAM_B3 (0x458 >> 2)
123 /* Device Parameters */
124 #define GT_DEV_B0 (0x45c >> 2)
125 #define GT_DEV_B1 (0x460 >> 2)
126 #define GT_DEV_B2 (0x464 >> 2)
127 #define GT_DEV_B3 (0x468 >> 2)
128 #define GT_DEV_BOOT (0x46c >> 2)
131 #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
132 #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
133 #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
134 #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
135 #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
138 #define GT_DMA0_CNT (0x800 >> 2)
139 #define GT_DMA1_CNT (0x804 >> 2)
140 #define GT_DMA2_CNT (0x808 >> 2)
141 #define GT_DMA3_CNT (0x80c >> 2)
142 #define GT_DMA0_SA (0x810 >> 2)
143 #define GT_DMA1_SA (0x814 >> 2)
144 #define GT_DMA2_SA (0x818 >> 2)
145 #define GT_DMA3_SA (0x81c >> 2)
146 #define GT_DMA0_DA (0x820 >> 2)
147 #define GT_DMA1_DA (0x824 >> 2)
148 #define GT_DMA2_DA (0x828 >> 2)
149 #define GT_DMA3_DA (0x82c >> 2)
150 #define GT_DMA0_NEXT (0x830 >> 2)
151 #define GT_DMA1_NEXT (0x834 >> 2)
152 #define GT_DMA2_NEXT (0x838 >> 2)
153 #define GT_DMA3_NEXT (0x83c >> 2)
154 #define GT_DMA0_CUR (0x870 >> 2)
155 #define GT_DMA1_CUR (0x874 >> 2)
156 #define GT_DMA2_CUR (0x878 >> 2)
157 #define GT_DMA3_CUR (0x87c >> 2)
159 /* DMA Channel Control */
160 #define GT_DMA0_CTRL (0x840 >> 2)
161 #define GT_DMA1_CTRL (0x844 >> 2)
162 #define GT_DMA2_CTRL (0x848 >> 2)
163 #define GT_DMA3_CTRL (0x84c >> 2)
166 #define GT_DMA_ARB (0x860 >> 2)
169 #define GT_TC0 (0x850 >> 2)
170 #define GT_TC1 (0x854 >> 2)
171 #define GT_TC2 (0x858 >> 2)
172 #define GT_TC3 (0x85c >> 2)
173 #define GT_TC_CONTROL (0x864 >> 2)
176 #define GT_PCI0_CMD (0xc00 >> 2)
177 #define GT_PCI0_TOR (0xc04 >> 2)
178 #define GT_PCI0_BS_SCS10 (0xc08 >> 2)
179 #define GT_PCI0_BS_SCS32 (0xc0c >> 2)
180 #define GT_PCI0_BS_CS20 (0xc10 >> 2)
181 #define GT_PCI0_BS_CS3BT (0xc14 >> 2)
182 #define GT_PCI1_IACK (0xc30 >> 2)
183 #define GT_PCI0_IACK (0xc34 >> 2)
184 #define GT_PCI0_BARE (0xc3c >> 2)
185 #define GT_PCI0_PREFMBR (0xc40 >> 2)
186 #define GT_PCI0_SCS10_BAR (0xc48 >> 2)
187 #define GT_PCI0_SCS32_BAR (0xc4c >> 2)
188 #define GT_PCI0_CS20_BAR (0xc50 >> 2)
189 #define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
190 #define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
191 #define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
192 #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
193 #define GT_PCI1_CMD (0xc80 >> 2)
194 #define GT_PCI1_TOR (0xc84 >> 2)
195 #define GT_PCI1_BS_SCS10 (0xc88 >> 2)
196 #define GT_PCI1_BS_SCS32 (0xc8c >> 2)
197 #define GT_PCI1_BS_CS20 (0xc90 >> 2)
198 #define GT_PCI1_BS_CS3BT (0xc94 >> 2)
199 #define GT_PCI1_BARE (0xcbc >> 2)
200 #define GT_PCI1_PREFMBR (0xcc0 >> 2)
201 #define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
202 #define GT_PCI1_SCS32_BAR (0xccc >> 2)
203 #define GT_PCI1_CS20_BAR (0xcd0 >> 2)
204 #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
205 #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
206 #define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
207 #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
208 #define GT_PCI1_CFGADDR (0xcf0 >> 2)
209 #define GT_PCI1_CFGDATA (0xcf4 >> 2)
210 #define GT_PCI0_CFGADDR (0xcf8 >> 2)
211 #define GT_PCI0_CFGDATA (0xcfc >> 2)
214 #define GT_INTRCAUSE (0xc18 >> 2)
215 #define GT_INTRMASK (0xc1c >> 2)
216 #define GT_PCI0_ICMASK (0xc24 >> 2)
217 #define GT_PCI0_SERR0MASK (0xc28 >> 2)
218 #define GT_CPU_INTSEL (0xc70 >> 2)
219 #define GT_PCI0_INTSEL (0xc74 >> 2)
220 #define GT_HINTRCAUSE (0xc98 >> 2)
221 #define GT_HINTRMASK (0xc9c >> 2)
222 #define GT_PCI0_HICMASK (0xca4 >> 2)
223 #define GT_PCI1_SERR1MASK (0xca8 >> 2)
226 typedef PCIHostState GT64120PCIState
;
228 #define PCI_MAPPING_ENTRY(regname) \
229 target_phys_addr_t regname ##_start; \
230 target_phys_addr_t regname ##_length; \
231 int regname ##_handle
233 typedef struct GT64120State
{
234 GT64120PCIState
*pci
;
235 uint32_t regs
[GT_REGS
];
236 PCI_MAPPING_ENTRY(PCI0IO
);
237 PCI_MAPPING_ENTRY(ISD
);
240 /* Adjust range to avoid touching space which isn't mappable via PCI */
241 /* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
242 0x1fc00000 - 0x1fd00000 */
243 static void check_reserved_space (target_phys_addr_t
*start
,
244 target_phys_addr_t
*length
)
246 target_phys_addr_t begin
= *start
;
247 target_phys_addr_t end
= *start
+ *length
;
249 if (end
>= 0x1e000000LL
&& end
< 0x1f100000LL
)
251 if (begin
>= 0x1e000000LL
&& begin
< 0x1f100000LL
)
252 begin
= 0x1f100000LL
;
253 if (end
>= 0x1fc00000LL
&& end
< 0x1fd00000LL
)
255 if (begin
>= 0x1fc00000LL
&& begin
< 0x1fd00000LL
)
256 begin
= 0x1fd00000LL
;
257 /* XXX: This is broken when a reserved range splits the requested range */
258 if (end
>= 0x1f100000LL
&& begin
< 0x1e000000LL
)
260 if (end
>= 0x1fd00000LL
&& begin
< 0x1fc00000LL
)
264 *length
= end
- begin
;
267 static void gt64120_isd_mapping(GT64120State
*s
)
269 target_phys_addr_t start
= s
->regs
[GT_ISD
] << 21;
270 target_phys_addr_t length
= 0x1000;
273 cpu_register_physical_memory(s
->ISD_start
, s
->ISD_length
,
275 check_reserved_space(&start
, &length
);
277 /* Map new address */
278 dprintf("ISD: %x@%x -> %x@%x, %x\n", s
->ISD_length
, s
->ISD_start
,
279 length
, start
, s
->ISD_handle
);
280 s
->ISD_start
= start
;
281 s
->ISD_length
= length
;
282 cpu_register_physical_memory(s
->ISD_start
, s
->ISD_length
, s
->ISD_handle
);
285 static void gt64120_pci_mapping(GT64120State
*s
)
287 /* Update IO mapping */
288 if ((s
->regs
[GT_PCI0IOLD
] & 0x7f) <= s
->regs
[GT_PCI0IOHD
])
290 /* Unmap old IO address */
291 if (s
->PCI0IO_length
)
293 cpu_register_physical_memory(s
->PCI0IO_start
, s
->PCI0IO_length
, IO_MEM_UNASSIGNED
);
295 /* Map new IO address */
296 s
->PCI0IO_start
= s
->regs
[GT_PCI0IOLD
] << 21;
297 s
->PCI0IO_length
= ((s
->regs
[GT_PCI0IOHD
] + 1) - (s
->regs
[GT_PCI0IOLD
] & 0x7f)) << 21;
298 isa_mem_base
= s
->PCI0IO_start
;
299 isa_mmio_init(s
->PCI0IO_start
, s
->PCI0IO_length
);
303 static void gt64120_writel (void *opaque
, target_phys_addr_t addr
,
306 GT64120State
*s
= opaque
;
309 #ifdef TARGET_WORDS_BIGENDIAN
313 saddr
= (addr
& 0xfff) >> 2;
316 /* CPU Configuration */
318 s
->regs
[GT_CPU
] = val
;
321 /* Read-only register as only one GT64xxx is present on the CPU bus */
324 /* CPU Address Decode */
326 s
->regs
[GT_PCI0IOLD
] = val
& 0x00007fff;
327 s
->regs
[GT_PCI0IOREMAP
] = val
& 0x000007ff;
328 gt64120_pci_mapping(s
);
331 s
->regs
[GT_PCI0M0LD
] = val
& 0x00007fff;
332 s
->regs
[GT_PCI0M0REMAP
] = val
& 0x000007ff;
333 gt64120_pci_mapping(s
);
336 s
->regs
[GT_PCI0M1LD
] = val
& 0x00007fff;
337 s
->regs
[GT_PCI0M1REMAP
] = val
& 0x000007ff;
338 gt64120_pci_mapping(s
);
341 s
->regs
[GT_PCI1IOLD
] = val
& 0x00007fff;
342 s
->regs
[GT_PCI1IOREMAP
] = val
& 0x000007ff;
343 gt64120_pci_mapping(s
);
346 s
->regs
[GT_PCI1M0LD
] = val
& 0x00007fff;
347 s
->regs
[GT_PCI1M0REMAP
] = val
& 0x000007ff;
348 gt64120_pci_mapping(s
);
351 s
->regs
[GT_PCI1M1LD
] = val
& 0x00007fff;
352 s
->regs
[GT_PCI1M1REMAP
] = val
& 0x000007ff;
353 gt64120_pci_mapping(s
);
361 s
->regs
[saddr
] = val
& 0x0000007f;
362 gt64120_pci_mapping(s
);
365 s
->regs
[saddr
] = val
& 0x00007fff;
366 gt64120_isd_mapping(s
);
375 s
->regs
[saddr
] = val
& 0x000007ff;
376 gt64120_pci_mapping(s
);
379 /* CPU Error Report */
380 case GT_CPUERR_ADDRLO
:
381 case GT_CPUERR_ADDRHI
:
382 case GT_CPUERR_DATALO
:
383 case GT_CPUERR_DATAHI
:
384 case GT_CPUERR_PARITY
:
385 /* Read-only registers, do nothing */
388 /* CPU Sync Barrier */
391 /* Read-only registers, do nothing */
394 /* SDRAM and Device Address Decode */
414 /* SDRAM Configuration */
416 case GT_SDRAM_OPMODE
:
418 case GT_SDRAM_ADDRDECODE
:
419 /* Accept and ignore SDRAM interleave configuration */
420 s
->regs
[saddr
] = val
;
423 /* Device Parameters */
429 /* Not implemented */
430 dprintf ("Unimplemented device register offset 0x%x\n", saddr
<< 2);
434 case GT_ECC_ERRDATALO
:
435 case GT_ECC_ERRDATAHI
:
439 /* Read-only registers, do nothing */
463 /* Not implemented */
464 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr
<< 2);
467 /* DMA Channel Control */
472 /* Not implemented */
473 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr
<< 2);
478 /* Not implemented */
479 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr
<< 2);
488 /* Not implemented */
489 dprintf ("Unimplemented timer register offset 0x%x\n", saddr
<< 2);
495 s
->regs
[saddr
] = val
& 0x0401fc0f;
498 case GT_PCI0_BS_SCS10
:
499 case GT_PCI0_BS_SCS32
:
500 case GT_PCI0_BS_CS20
:
501 case GT_PCI0_BS_CS3BT
:
505 case GT_PCI0_PREFMBR
:
506 case GT_PCI0_SCS10_BAR
:
507 case GT_PCI0_SCS32_BAR
:
508 case GT_PCI0_CS20_BAR
:
509 case GT_PCI0_CS3BT_BAR
:
510 case GT_PCI0_SSCS10_BAR
:
511 case GT_PCI0_SSCS32_BAR
:
512 case GT_PCI0_SCS3BT_BAR
:
514 case GT_PCI1_BS_SCS10
:
515 case GT_PCI1_BS_SCS32
:
516 case GT_PCI1_BS_CS20
:
517 case GT_PCI1_BS_CS3BT
:
519 case GT_PCI1_PREFMBR
:
520 case GT_PCI1_SCS10_BAR
:
521 case GT_PCI1_SCS32_BAR
:
522 case GT_PCI1_CS20_BAR
:
523 case GT_PCI1_CS3BT_BAR
:
524 case GT_PCI1_SSCS10_BAR
:
525 case GT_PCI1_SSCS32_BAR
:
526 case GT_PCI1_SCS3BT_BAR
:
527 case GT_PCI1_CFGADDR
:
528 case GT_PCI1_CFGDATA
:
529 /* not implemented */
531 case GT_PCI0_CFGADDR
:
532 s
->pci
->config_reg
= val
& 0x80fffffc;
534 case GT_PCI0_CFGDATA
:
535 if (s
->pci
->config_reg
& (1u << 31))
536 pci_host_data_writel(s
->pci
, 0, val
);
541 /* not really implemented */
542 s
->regs
[saddr
] = ~(~(s
->regs
[saddr
]) | ~(val
& 0xfffffffe));
543 s
->regs
[saddr
] |= !!(s
->regs
[saddr
] & 0xfffffffe);
544 dprintf("INTRCAUSE %x\n", val
);
547 s
->regs
[saddr
] = val
& 0x3c3ffffe;
548 dprintf("INTRMASK %x\n", val
);
551 s
->regs
[saddr
] = val
& 0x03fffffe;
552 dprintf("ICMASK %x\n", val
);
554 case GT_PCI0_SERR0MASK
:
555 s
->regs
[saddr
] = val
& 0x0000003f;
556 dprintf("SERR0MASK %x\n", val
);
559 /* Reserved when only PCI_0 is configured. */
564 case GT_PCI0_HICMASK
:
565 case GT_PCI1_SERR1MASK
:
566 /* not implemented */
569 /* SDRAM Parameters */
574 /* We don't simulate electrical parameters of the SDRAM.
575 Accept, but ignore the values. */
576 s
->regs
[saddr
] = val
;
580 dprintf ("Bad register offset 0x%x\n", (int)addr
);
585 static uint32_t gt64120_readl (void *opaque
,
586 target_phys_addr_t addr
)
588 GT64120State
*s
= opaque
;
593 saddr
= (addr
& 0xfff) >> 2;
597 /* CPU Configuration */
599 /* Only one GT64xxx is present on the CPU bus, return
601 val
= s
->regs
[saddr
];
604 /* CPU Error Report */
605 case GT_CPUERR_ADDRLO
:
606 case GT_CPUERR_ADDRHI
:
607 case GT_CPUERR_DATALO
:
608 case GT_CPUERR_DATAHI
:
609 case GT_CPUERR_PARITY
:
610 /* Emulated memory has no error, always return the initial
612 val
= s
->regs
[saddr
];
615 /* CPU Sync Barrier */
618 /* Reading those register should empty all FIFO on the PCI
619 bus, which are not emulated. The return value should be
620 a random value that should be ignored. */
625 case GT_ECC_ERRDATALO
:
626 case GT_ECC_ERRDATAHI
:
630 /* Emulated memory has no error, always return the initial
632 val
= s
->regs
[saddr
];
667 val
= s
->regs
[saddr
];
670 /* Read the IRQ number */
671 val
= pic_read_irq(isa_pic
);
674 /* SDRAM and Device Address Decode */
694 val
= s
->regs
[saddr
];
697 /* SDRAM Configuration */
699 case GT_SDRAM_OPMODE
:
701 case GT_SDRAM_ADDRDECODE
:
702 val
= s
->regs
[saddr
];
705 /* SDRAM Parameters */
710 /* We don't simulate electrical parameters of the SDRAM.
711 Just return the last written value. */
712 val
= s
->regs
[saddr
];
715 /* Device Parameters */
721 val
= s
->regs
[saddr
];
745 val
= s
->regs
[saddr
];
748 /* DMA Channel Control */
753 val
= s
->regs
[saddr
];
758 val
= s
->regs
[saddr
];
767 val
= s
->regs
[saddr
];
771 case GT_PCI0_CFGADDR
:
772 val
= s
->pci
->config_reg
;
774 case GT_PCI0_CFGDATA
:
775 if (!(s
->pci
->config_reg
& (1u << 31)))
778 val
= pci_host_data_readl(s
->pci
, 0);
783 case GT_PCI0_BS_SCS10
:
784 case GT_PCI0_BS_SCS32
:
785 case GT_PCI0_BS_CS20
:
786 case GT_PCI0_BS_CS3BT
:
789 case GT_PCI0_PREFMBR
:
790 case GT_PCI0_SCS10_BAR
:
791 case GT_PCI0_SCS32_BAR
:
792 case GT_PCI0_CS20_BAR
:
793 case GT_PCI0_CS3BT_BAR
:
794 case GT_PCI0_SSCS10_BAR
:
795 case GT_PCI0_SSCS32_BAR
:
796 case GT_PCI0_SCS3BT_BAR
:
799 case GT_PCI1_BS_SCS10
:
800 case GT_PCI1_BS_SCS32
:
801 case GT_PCI1_BS_CS20
:
802 case GT_PCI1_BS_CS3BT
:
804 case GT_PCI1_PREFMBR
:
805 case GT_PCI1_SCS10_BAR
:
806 case GT_PCI1_SCS32_BAR
:
807 case GT_PCI1_CS20_BAR
:
808 case GT_PCI1_CS3BT_BAR
:
809 case GT_PCI1_SSCS10_BAR
:
810 case GT_PCI1_SSCS32_BAR
:
811 case GT_PCI1_SCS3BT_BAR
:
812 case GT_PCI1_CFGADDR
:
813 case GT_PCI1_CFGDATA
:
814 val
= s
->regs
[saddr
];
819 val
= s
->regs
[saddr
];
820 dprintf("INTRCAUSE %x\n", val
);
823 val
= s
->regs
[saddr
];
824 dprintf("INTRMASK %x\n", val
);
827 val
= s
->regs
[saddr
];
828 dprintf("ICMASK %x\n", val
);
830 case GT_PCI0_SERR0MASK
:
831 val
= s
->regs
[saddr
];
832 dprintf("SERR0MASK %x\n", val
);
835 /* Reserved when only PCI_0 is configured. */
840 case GT_PCI0_HICMASK
:
841 case GT_PCI1_SERR1MASK
:
842 val
= s
->regs
[saddr
];
846 val
= s
->regs
[saddr
];
847 dprintf ("Bad register offset 0x%x\n", (int)addr
);
851 #ifdef TARGET_WORDS_BIGENDIAN
857 static CPUWriteMemoryFunc
*gt64120_write
[] = {
863 static CPUReadMemoryFunc
*gt64120_read
[] = {
869 static int pci_gt64120_map_irq(PCIDevice
*pci_dev
, int irq_num
)
873 slot
= (pci_dev
->devfn
>> 3);
879 /* AMD 79C973 Ethernet */
882 /* Crystal 4281 Sound */
885 /* PCI slot 1 to 4 */
887 return ((slot
- 18) + irq_num
) & 0x03;
888 /* Unknown device, don't do any translation */
894 extern PCIDevice
*piix4_dev
;
895 static int pci_irq_levels
[4];
897 static void pci_gt64120_set_irq(qemu_irq
*pic
, int irq_num
, int level
)
899 int i
, pic_irq
, pic_level
;
901 pci_irq_levels
[irq_num
] = level
;
903 /* now we change the pic irq level according to the piix irq mappings */
905 pic_irq
= piix4_dev
->config
[0x60 + irq_num
];
907 /* The pic level is the logical OR of all the PCI irqs mapped
910 for (i
= 0; i
< 4; i
++) {
911 if (pic_irq
== piix4_dev
->config
[0x60 + i
])
912 pic_level
|= pci_irq_levels
[i
];
914 qemu_set_irq(pic
[pic_irq
], pic_level
);
919 void gt64120_reset(void *opaque
)
921 GT64120State
*s
= opaque
;
923 /* FIXME: Malta specific hw assumptions ahead */
925 /* CPU Configuration */
926 #ifdef TARGET_WORDS_BIGENDIAN
927 s
->regs
[GT_CPU
] = 0x00000000;
929 s
->regs
[GT_CPU
] = 0x00001000;
931 s
->regs
[GT_MULTI
] = 0x00000003;
933 /* CPU Address decode */
934 s
->regs
[GT_SCS10LD
] = 0x00000000;
935 s
->regs
[GT_SCS10HD
] = 0x00000007;
936 s
->regs
[GT_SCS32LD
] = 0x00000008;
937 s
->regs
[GT_SCS32HD
] = 0x0000000f;
938 s
->regs
[GT_CS20LD
] = 0x000000e0;
939 s
->regs
[GT_CS20HD
] = 0x00000070;
940 s
->regs
[GT_CS3BOOTLD
] = 0x000000f8;
941 s
->regs
[GT_CS3BOOTHD
] = 0x0000007f;
943 s
->regs
[GT_PCI0IOLD
] = 0x00000080;
944 s
->regs
[GT_PCI0IOHD
] = 0x0000000f;
945 s
->regs
[GT_PCI0M0LD
] = 0x00000090;
946 s
->regs
[GT_PCI0M0HD
] = 0x0000001f;
947 s
->regs
[GT_ISD
] = 0x000000a0;
948 s
->regs
[GT_PCI0M1LD
] = 0x00000790;
949 s
->regs
[GT_PCI0M1HD
] = 0x0000001f;
950 s
->regs
[GT_PCI1IOLD
] = 0x00000100;
951 s
->regs
[GT_PCI1IOHD
] = 0x0000000f;
952 s
->regs
[GT_PCI1M0LD
] = 0x00000110;
953 s
->regs
[GT_PCI1M0HD
] = 0x0000001f;
954 s
->regs
[GT_PCI1M1LD
] = 0x00000120;
955 s
->regs
[GT_PCI1M1HD
] = 0x0000002f;
957 s
->regs
[GT_SCS10AR
] = 0x00000000;
958 s
->regs
[GT_SCS32AR
] = 0x00000008;
959 s
->regs
[GT_CS20R
] = 0x000000e0;
960 s
->regs
[GT_CS3BOOTR
] = 0x000000f8;
962 s
->regs
[GT_PCI0IOREMAP
] = 0x00000080;
963 s
->regs
[GT_PCI0M0REMAP
] = 0x00000090;
964 s
->regs
[GT_PCI0M1REMAP
] = 0x00000790;
965 s
->regs
[GT_PCI1IOREMAP
] = 0x00000100;
966 s
->regs
[GT_PCI1M0REMAP
] = 0x00000110;
967 s
->regs
[GT_PCI1M1REMAP
] = 0x00000120;
969 /* CPU Error Report */
970 s
->regs
[GT_CPUERR_ADDRLO
] = 0x00000000;
971 s
->regs
[GT_CPUERR_ADDRHI
] = 0x00000000;
972 s
->regs
[GT_CPUERR_DATALO
] = 0xffffffff;
973 s
->regs
[GT_CPUERR_DATAHI
] = 0xffffffff;
974 s
->regs
[GT_CPUERR_PARITY
] = 0x000000ff;
976 /* CPU Sync Barrier */
977 s
->regs
[GT_PCI0SYNC
] = 0x00000000;
978 s
->regs
[GT_PCI1SYNC
] = 0x00000000;
980 /* SDRAM and Device Address Decode */
981 s
->regs
[GT_SCS0LD
] = 0x00000000;
982 s
->regs
[GT_SCS0HD
] = 0x00000007;
983 s
->regs
[GT_SCS1LD
] = 0x00000008;
984 s
->regs
[GT_SCS1HD
] = 0x0000000f;
985 s
->regs
[GT_SCS2LD
] = 0x00000010;
986 s
->regs
[GT_SCS2HD
] = 0x00000017;
987 s
->regs
[GT_SCS3LD
] = 0x00000018;
988 s
->regs
[GT_SCS3HD
] = 0x0000001f;
989 s
->regs
[GT_CS0LD
] = 0x000000c0;
990 s
->regs
[GT_CS0HD
] = 0x000000c7;
991 s
->regs
[GT_CS1LD
] = 0x000000c8;
992 s
->regs
[GT_CS1HD
] = 0x000000cf;
993 s
->regs
[GT_CS2LD
] = 0x000000d0;
994 s
->regs
[GT_CS2HD
] = 0x000000df;
995 s
->regs
[GT_CS3LD
] = 0x000000f0;
996 s
->regs
[GT_CS3HD
] = 0x000000fb;
997 s
->regs
[GT_BOOTLD
] = 0x000000fc;
998 s
->regs
[GT_BOOTHD
] = 0x000000ff;
999 s
->regs
[GT_ADERR
] = 0xffffffff;
1001 /* SDRAM Configuration */
1002 s
->regs
[GT_SDRAM_CFG
] = 0x00000200;
1003 s
->regs
[GT_SDRAM_OPMODE
] = 0x00000000;
1004 s
->regs
[GT_SDRAM_BM
] = 0x00000007;
1005 s
->regs
[GT_SDRAM_ADDRDECODE
] = 0x00000002;
1007 /* SDRAM Parameters */
1008 s
->regs
[GT_SDRAM_B0
] = 0x00000005;
1009 s
->regs
[GT_SDRAM_B1
] = 0x00000005;
1010 s
->regs
[GT_SDRAM_B2
] = 0x00000005;
1011 s
->regs
[GT_SDRAM_B3
] = 0x00000005;
1014 s
->regs
[GT_ECC_ERRDATALO
] = 0x00000000;
1015 s
->regs
[GT_ECC_ERRDATAHI
] = 0x00000000;
1016 s
->regs
[GT_ECC_MEM
] = 0x00000000;
1017 s
->regs
[GT_ECC_CALC
] = 0x00000000;
1018 s
->regs
[GT_ECC_ERRADDR
] = 0x00000000;
1020 /* Device Parameters */
1021 s
->regs
[GT_DEV_B0
] = 0x386fffff;
1022 s
->regs
[GT_DEV_B1
] = 0x386fffff;
1023 s
->regs
[GT_DEV_B2
] = 0x386fffff;
1024 s
->regs
[GT_DEV_B3
] = 0x386fffff;
1025 s
->regs
[GT_DEV_BOOT
] = 0x146fffff;
1027 /* DMA registers are all zeroed at reset */
1030 s
->regs
[GT_TC0
] = 0xffffffff;
1031 s
->regs
[GT_TC1
] = 0x00ffffff;
1032 s
->regs
[GT_TC2
] = 0x00ffffff;
1033 s
->regs
[GT_TC3
] = 0x00ffffff;
1034 s
->regs
[GT_TC_CONTROL
] = 0x00000000;
1037 #ifdef TARGET_WORDS_BIGENDIAN
1038 s
->regs
[GT_PCI0_CMD
] = 0x00000000;
1040 s
->regs
[GT_PCI0_CMD
] = 0x00010001;
1042 s
->regs
[GT_PCI0_TOR
] = 0x0000070f;
1043 s
->regs
[GT_PCI0_BS_SCS10
] = 0x00fff000;
1044 s
->regs
[GT_PCI0_BS_SCS32
] = 0x00fff000;
1045 s
->regs
[GT_PCI0_BS_CS20
] = 0x01fff000;
1046 s
->regs
[GT_PCI0_BS_CS3BT
] = 0x00fff000;
1047 s
->regs
[GT_PCI1_IACK
] = 0x00000000;
1048 s
->regs
[GT_PCI0_IACK
] = 0x00000000;
1049 s
->regs
[GT_PCI0_BARE
] = 0x0000000f;
1050 s
->regs
[GT_PCI0_PREFMBR
] = 0x00000040;
1051 s
->regs
[GT_PCI0_SCS10_BAR
] = 0x00000000;
1052 s
->regs
[GT_PCI0_SCS32_BAR
] = 0x01000000;
1053 s
->regs
[GT_PCI0_CS20_BAR
] = 0x1c000000;
1054 s
->regs
[GT_PCI0_CS3BT_BAR
] = 0x1f000000;
1055 s
->regs
[GT_PCI0_SSCS10_BAR
] = 0x00000000;
1056 s
->regs
[GT_PCI0_SSCS32_BAR
] = 0x01000000;
1057 s
->regs
[GT_PCI0_SCS3BT_BAR
] = 0x1f000000;
1058 #ifdef TARGET_WORDS_BIGENDIAN
1059 s
->regs
[GT_PCI1_CMD
] = 0x00000000;
1061 s
->regs
[GT_PCI1_CMD
] = 0x00010001;
1063 s
->regs
[GT_PCI1_TOR
] = 0x0000070f;
1064 s
->regs
[GT_PCI1_BS_SCS10
] = 0x00fff000;
1065 s
->regs
[GT_PCI1_BS_SCS32
] = 0x00fff000;
1066 s
->regs
[GT_PCI1_BS_CS20
] = 0x01fff000;
1067 s
->regs
[GT_PCI1_BS_CS3BT
] = 0x00fff000;
1068 s
->regs
[GT_PCI1_BARE
] = 0x0000000f;
1069 s
->regs
[GT_PCI1_PREFMBR
] = 0x00000040;
1070 s
->regs
[GT_PCI1_SCS10_BAR
] = 0x00000000;
1071 s
->regs
[GT_PCI1_SCS32_BAR
] = 0x01000000;
1072 s
->regs
[GT_PCI1_CS20_BAR
] = 0x1c000000;
1073 s
->regs
[GT_PCI1_CS3BT_BAR
] = 0x1f000000;
1074 s
->regs
[GT_PCI1_SSCS10_BAR
] = 0x00000000;
1075 s
->regs
[GT_PCI1_SSCS32_BAR
] = 0x01000000;
1076 s
->regs
[GT_PCI1_SCS3BT_BAR
] = 0x1f000000;
1077 s
->regs
[GT_PCI1_CFGADDR
] = 0x00000000;
1078 s
->regs
[GT_PCI1_CFGDATA
] = 0x00000000;
1079 s
->regs
[GT_PCI0_CFGADDR
] = 0x00000000;
1080 s
->regs
[GT_PCI0_CFGDATA
] = 0x00000000;
1082 /* Interrupt registers are all zeroed at reset */
1084 gt64120_isd_mapping(s
);
1085 gt64120_pci_mapping(s
);
1088 static uint32_t gt64120_read_config(PCIDevice
*d
, uint32_t address
, int len
)
1090 uint32_t val
= pci_default_read_config(d
, address
, len
);
1091 #ifdef TARGET_WORDS_BIGENDIAN
1097 static void gt64120_write_config(PCIDevice
*d
, uint32_t address
, uint32_t val
,
1100 #ifdef TARGET_WORDS_BIGENDIAN
1103 pci_default_write_config(d
, address
, val
, len
);
1106 static void gt64120_save(QEMUFile
* f
, void *opaque
)
1108 PCIDevice
*d
= opaque
;
1109 pci_device_save(d
, f
);
1112 static int gt64120_load(QEMUFile
* f
, void *opaque
, int version_id
)
1114 PCIDevice
*d
= opaque
;
1117 if (version_id
!= 1)
1119 ret
= pci_device_load(d
, f
);
1125 PCIBus
*pci_gt64120_init(qemu_irq
*pic
)
1130 s
= qemu_mallocz(sizeof(GT64120State
));
1131 s
->pci
= qemu_mallocz(sizeof(GT64120PCIState
));
1133 s
->pci
->bus
= pci_register_bus(pci_gt64120_set_irq
, pci_gt64120_map_irq
,
1135 s
->ISD_handle
= cpu_register_io_memory(0, gt64120_read
, gt64120_write
, s
);
1136 d
= pci_register_device(s
->pci
->bus
, "GT64120 PCI Bus", sizeof(PCIDevice
),
1137 0, gt64120_read_config
, gt64120_write_config
);
1139 /* FIXME: Malta specific hw assumptions ahead */
1141 d
->config
[0x00] = 0xab; /* vendor_id */
1142 d
->config
[0x01] = 0x11;
1143 d
->config
[0x02] = 0x20; /* device_id */
1144 d
->config
[0x03] = 0x46;
1146 d
->config
[0x04] = 0x00;
1147 d
->config
[0x05] = 0x00;
1148 d
->config
[0x06] = 0x80;
1149 d
->config
[0x07] = 0x02;
1151 d
->config
[0x08] = 0x10;
1152 d
->config
[0x09] = 0x00;
1153 d
->config
[0x0A] = 0x00;
1154 d
->config
[0x0B] = 0x06;
1156 d
->config
[0x10] = 0x08;
1157 d
->config
[0x14] = 0x08;
1158 d
->config
[0x17] = 0x01;
1159 d
->config
[0x1B] = 0x1c;
1160 d
->config
[0x1F] = 0x1f;
1161 d
->config
[0x23] = 0x14;
1162 d
->config
[0x24] = 0x01;
1163 d
->config
[0x27] = 0x14;
1164 d
->config
[0x3D] = 0x01;
1168 register_savevm("GT64120 PCI Bus", 0, 1, gt64120_save
, gt64120_load
, d
);