2 * QEMU GT64120 PCI host
4 * Copyright (c) 2006,2007 Aurelien Jarno
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 typedef target_phys_addr_t pci_addr_t
;
36 #define dprintf(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
38 #define dprintf(fmt, ...)
41 #define GT_REGS (0x1000 >> 2)
43 /* CPU Configuration */
44 #define GT_CPU (0x000 >> 2)
45 #define GT_MULTI (0x120 >> 2)
47 /* CPU Address Decode */
48 #define GT_SCS10LD (0x008 >> 2)
49 #define GT_SCS10HD (0x010 >> 2)
50 #define GT_SCS32LD (0x018 >> 2)
51 #define GT_SCS32HD (0x020 >> 2)
52 #define GT_CS20LD (0x028 >> 2)
53 #define GT_CS20HD (0x030 >> 2)
54 #define GT_CS3BOOTLD (0x038 >> 2)
55 #define GT_CS3BOOTHD (0x040 >> 2)
56 #define GT_PCI0IOLD (0x048 >> 2)
57 #define GT_PCI0IOHD (0x050 >> 2)
58 #define GT_PCI0M0LD (0x058 >> 2)
59 #define GT_PCI0M0HD (0x060 >> 2)
60 #define GT_PCI0M1LD (0x080 >> 2)
61 #define GT_PCI0M1HD (0x088 >> 2)
62 #define GT_PCI1IOLD (0x090 >> 2)
63 #define GT_PCI1IOHD (0x098 >> 2)
64 #define GT_PCI1M0LD (0x0a0 >> 2)
65 #define GT_PCI1M0HD (0x0a8 >> 2)
66 #define GT_PCI1M1LD (0x0b0 >> 2)
67 #define GT_PCI1M1HD (0x0b8 >> 2)
68 #define GT_ISD (0x068 >> 2)
70 #define GT_SCS10AR (0x0d0 >> 2)
71 #define GT_SCS32AR (0x0d8 >> 2)
72 #define GT_CS20R (0x0e0 >> 2)
73 #define GT_CS3BOOTR (0x0e8 >> 2)
75 #define GT_PCI0IOREMAP (0x0f0 >> 2)
76 #define GT_PCI0M0REMAP (0x0f8 >> 2)
77 #define GT_PCI0M1REMAP (0x100 >> 2)
78 #define GT_PCI1IOREMAP (0x108 >> 2)
79 #define GT_PCI1M0REMAP (0x110 >> 2)
80 #define GT_PCI1M1REMAP (0x118 >> 2)
82 /* CPU Error Report */
83 #define GT_CPUERR_ADDRLO (0x070 >> 2)
84 #define GT_CPUERR_ADDRHI (0x078 >> 2)
85 #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
86 #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
87 #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
89 /* CPU Sync Barrier */
90 #define GT_PCI0SYNC (0x0c0 >> 2)
91 #define GT_PCI1SYNC (0x0c8 >> 2)
93 /* SDRAM and Device Address Decode */
94 #define GT_SCS0LD (0x400 >> 2)
95 #define GT_SCS0HD (0x404 >> 2)
96 #define GT_SCS1LD (0x408 >> 2)
97 #define GT_SCS1HD (0x40c >> 2)
98 #define GT_SCS2LD (0x410 >> 2)
99 #define GT_SCS2HD (0x414 >> 2)
100 #define GT_SCS3LD (0x418 >> 2)
101 #define GT_SCS3HD (0x41c >> 2)
102 #define GT_CS0LD (0x420 >> 2)
103 #define GT_CS0HD (0x424 >> 2)
104 #define GT_CS1LD (0x428 >> 2)
105 #define GT_CS1HD (0x42c >> 2)
106 #define GT_CS2LD (0x430 >> 2)
107 #define GT_CS2HD (0x434 >> 2)
108 #define GT_CS3LD (0x438 >> 2)
109 #define GT_CS3HD (0x43c >> 2)
110 #define GT_BOOTLD (0x440 >> 2)
111 #define GT_BOOTHD (0x444 >> 2)
112 #define GT_ADERR (0x470 >> 2)
114 /* SDRAM Configuration */
115 #define GT_SDRAM_CFG (0x448 >> 2)
116 #define GT_SDRAM_OPMODE (0x474 >> 2)
117 #define GT_SDRAM_BM (0x478 >> 2)
118 #define GT_SDRAM_ADDRDECODE (0x47c >> 2)
120 /* SDRAM Parameters */
121 #define GT_SDRAM_B0 (0x44c >> 2)
122 #define GT_SDRAM_B1 (0x450 >> 2)
123 #define GT_SDRAM_B2 (0x454 >> 2)
124 #define GT_SDRAM_B3 (0x458 >> 2)
126 /* Device Parameters */
127 #define GT_DEV_B0 (0x45c >> 2)
128 #define GT_DEV_B1 (0x460 >> 2)
129 #define GT_DEV_B2 (0x464 >> 2)
130 #define GT_DEV_B3 (0x468 >> 2)
131 #define GT_DEV_BOOT (0x46c >> 2)
134 #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
135 #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
136 #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
137 #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
138 #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
141 #define GT_DMA0_CNT (0x800 >> 2)
142 #define GT_DMA1_CNT (0x804 >> 2)
143 #define GT_DMA2_CNT (0x808 >> 2)
144 #define GT_DMA3_CNT (0x80c >> 2)
145 #define GT_DMA0_SA (0x810 >> 2)
146 #define GT_DMA1_SA (0x814 >> 2)
147 #define GT_DMA2_SA (0x818 >> 2)
148 #define GT_DMA3_SA (0x81c >> 2)
149 #define GT_DMA0_DA (0x820 >> 2)
150 #define GT_DMA1_DA (0x824 >> 2)
151 #define GT_DMA2_DA (0x828 >> 2)
152 #define GT_DMA3_DA (0x82c >> 2)
153 #define GT_DMA0_NEXT (0x830 >> 2)
154 #define GT_DMA1_NEXT (0x834 >> 2)
155 #define GT_DMA2_NEXT (0x838 >> 2)
156 #define GT_DMA3_NEXT (0x83c >> 2)
157 #define GT_DMA0_CUR (0x870 >> 2)
158 #define GT_DMA1_CUR (0x874 >> 2)
159 #define GT_DMA2_CUR (0x878 >> 2)
160 #define GT_DMA3_CUR (0x87c >> 2)
162 /* DMA Channel Control */
163 #define GT_DMA0_CTRL (0x840 >> 2)
164 #define GT_DMA1_CTRL (0x844 >> 2)
165 #define GT_DMA2_CTRL (0x848 >> 2)
166 #define GT_DMA3_CTRL (0x84c >> 2)
169 #define GT_DMA_ARB (0x860 >> 2)
172 #define GT_TC0 (0x850 >> 2)
173 #define GT_TC1 (0x854 >> 2)
174 #define GT_TC2 (0x858 >> 2)
175 #define GT_TC3 (0x85c >> 2)
176 #define GT_TC_CONTROL (0x864 >> 2)
179 #define GT_PCI0_CMD (0xc00 >> 2)
180 #define GT_PCI0_TOR (0xc04 >> 2)
181 #define GT_PCI0_BS_SCS10 (0xc08 >> 2)
182 #define GT_PCI0_BS_SCS32 (0xc0c >> 2)
183 #define GT_PCI0_BS_CS20 (0xc10 >> 2)
184 #define GT_PCI0_BS_CS3BT (0xc14 >> 2)
185 #define GT_PCI1_IACK (0xc30 >> 2)
186 #define GT_PCI0_IACK (0xc34 >> 2)
187 #define GT_PCI0_BARE (0xc3c >> 2)
188 #define GT_PCI0_PREFMBR (0xc40 >> 2)
189 #define GT_PCI0_SCS10_BAR (0xc48 >> 2)
190 #define GT_PCI0_SCS32_BAR (0xc4c >> 2)
191 #define GT_PCI0_CS20_BAR (0xc50 >> 2)
192 #define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
193 #define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
194 #define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
195 #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
196 #define GT_PCI1_CMD (0xc80 >> 2)
197 #define GT_PCI1_TOR (0xc84 >> 2)
198 #define GT_PCI1_BS_SCS10 (0xc88 >> 2)
199 #define GT_PCI1_BS_SCS32 (0xc8c >> 2)
200 #define GT_PCI1_BS_CS20 (0xc90 >> 2)
201 #define GT_PCI1_BS_CS3BT (0xc94 >> 2)
202 #define GT_PCI1_BARE (0xcbc >> 2)
203 #define GT_PCI1_PREFMBR (0xcc0 >> 2)
204 #define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
205 #define GT_PCI1_SCS32_BAR (0xccc >> 2)
206 #define GT_PCI1_CS20_BAR (0xcd0 >> 2)
207 #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
208 #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
209 #define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
210 #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
211 #define GT_PCI1_CFGADDR (0xcf0 >> 2)
212 #define GT_PCI1_CFGDATA (0xcf4 >> 2)
213 #define GT_PCI0_CFGADDR (0xcf8 >> 2)
214 #define GT_PCI0_CFGDATA (0xcfc >> 2)
217 #define GT_INTRCAUSE (0xc18 >> 2)
218 #define GT_INTRMASK (0xc1c >> 2)
219 #define GT_PCI0_ICMASK (0xc24 >> 2)
220 #define GT_PCI0_SERR0MASK (0xc28 >> 2)
221 #define GT_CPU_INTSEL (0xc70 >> 2)
222 #define GT_PCI0_INTSEL (0xc74 >> 2)
223 #define GT_HINTRCAUSE (0xc98 >> 2)
224 #define GT_HINTRMASK (0xc9c >> 2)
225 #define GT_PCI0_HICMASK (0xca4 >> 2)
226 #define GT_PCI1_SERR1MASK (0xca8 >> 2)
229 typedef PCIHostState GT64120PCIState
;
231 #define PCI_MAPPING_ENTRY(regname) \
232 target_phys_addr_t regname ##_start; \
233 target_phys_addr_t regname ##_length; \
234 int regname ##_handle
236 typedef struct GT64120State
{
237 GT64120PCIState
*pci
;
238 uint32_t regs
[GT_REGS
];
239 PCI_MAPPING_ENTRY(PCI0IO
);
240 PCI_MAPPING_ENTRY(ISD
);
243 /* Adjust range to avoid touching space which isn't mappable via PCI */
244 /* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
245 0x1fc00000 - 0x1fd00000 */
246 static void check_reserved_space (target_phys_addr_t
*start
,
247 target_phys_addr_t
*length
)
249 target_phys_addr_t begin
= *start
;
250 target_phys_addr_t end
= *start
+ *length
;
252 if (end
>= 0x1e000000LL
&& end
< 0x1f100000LL
)
254 if (begin
>= 0x1e000000LL
&& begin
< 0x1f100000LL
)
255 begin
= 0x1f100000LL
;
256 if (end
>= 0x1fc00000LL
&& end
< 0x1fd00000LL
)
258 if (begin
>= 0x1fc00000LL
&& begin
< 0x1fd00000LL
)
259 begin
= 0x1fd00000LL
;
260 /* XXX: This is broken when a reserved range splits the requested range */
261 if (end
>= 0x1f100000LL
&& begin
< 0x1e000000LL
)
263 if (end
>= 0x1fd00000LL
&& begin
< 0x1fc00000LL
)
267 *length
= end
- begin
;
270 static void gt64120_isd_mapping(GT64120State
*s
)
272 target_phys_addr_t start
= s
->regs
[GT_ISD
] << 21;
273 target_phys_addr_t length
= 0x1000;
276 cpu_register_physical_memory(s
->ISD_start
, s
->ISD_length
,
278 check_reserved_space(&start
, &length
);
280 /* Map new address */
281 dprintf("ISD: %x@%x -> %x@%x, %x\n", s
->ISD_length
, s
->ISD_start
,
282 length
, start
, s
->ISD_handle
);
283 s
->ISD_start
= start
;
284 s
->ISD_length
= length
;
285 cpu_register_physical_memory(s
->ISD_start
, s
->ISD_length
, s
->ISD_handle
);
288 static void gt64120_pci_mapping(GT64120State
*s
)
290 /* Update IO mapping */
291 if ((s
->regs
[GT_PCI0IOLD
] & 0x7f) <= s
->regs
[GT_PCI0IOHD
])
293 /* Unmap old IO address */
294 if (s
->PCI0IO_length
)
296 cpu_register_physical_memory(s
->PCI0IO_start
, s
->PCI0IO_length
, IO_MEM_UNASSIGNED
);
298 /* Map new IO address */
299 s
->PCI0IO_start
= s
->regs
[GT_PCI0IOLD
] << 21;
300 s
->PCI0IO_length
= ((s
->regs
[GT_PCI0IOHD
] + 1) - (s
->regs
[GT_PCI0IOLD
] & 0x7f)) << 21;
301 isa_mem_base
= s
->PCI0IO_start
;
302 isa_mmio_init(s
->PCI0IO_start
, s
->PCI0IO_length
);
306 static void gt64120_writel (void *opaque
, target_phys_addr_t addr
,
309 GT64120State
*s
= opaque
;
312 if (!(s
->regs
[GT_PCI0_CMD
] & 1))
315 saddr
= (addr
& 0xfff) >> 2;
318 /* CPU Configuration */
320 s
->regs
[GT_CPU
] = val
;
323 /* Read-only register as only one GT64xxx is present on the CPU bus */
326 /* CPU Address Decode */
328 s
->regs
[GT_PCI0IOLD
] = val
& 0x00007fff;
329 s
->regs
[GT_PCI0IOREMAP
] = val
& 0x000007ff;
330 gt64120_pci_mapping(s
);
333 s
->regs
[GT_PCI0M0LD
] = val
& 0x00007fff;
334 s
->regs
[GT_PCI0M0REMAP
] = val
& 0x000007ff;
337 s
->regs
[GT_PCI0M1LD
] = val
& 0x00007fff;
338 s
->regs
[GT_PCI0M1REMAP
] = val
& 0x000007ff;
341 s
->regs
[GT_PCI1IOLD
] = val
& 0x00007fff;
342 s
->regs
[GT_PCI1IOREMAP
] = val
& 0x000007ff;
345 s
->regs
[GT_PCI1M0LD
] = val
& 0x00007fff;
346 s
->regs
[GT_PCI1M0REMAP
] = val
& 0x000007ff;
349 s
->regs
[GT_PCI1M1LD
] = val
& 0x00007fff;
350 s
->regs
[GT_PCI1M1REMAP
] = val
& 0x000007ff;
353 s
->regs
[saddr
] = val
& 0x0000007f;
354 gt64120_pci_mapping(s
);
361 s
->regs
[saddr
] = val
& 0x0000007f;
364 s
->regs
[saddr
] = val
& 0x00007fff;
365 gt64120_isd_mapping(s
);
374 s
->regs
[saddr
] = val
& 0x000007ff;
377 /* CPU Error Report */
378 case GT_CPUERR_ADDRLO
:
379 case GT_CPUERR_ADDRHI
:
380 case GT_CPUERR_DATALO
:
381 case GT_CPUERR_DATAHI
:
382 case GT_CPUERR_PARITY
:
383 /* Read-only registers, do nothing */
386 /* CPU Sync Barrier */
389 /* Read-only registers, do nothing */
392 /* SDRAM and Device Address Decode */
412 /* SDRAM Configuration */
414 case GT_SDRAM_OPMODE
:
416 case GT_SDRAM_ADDRDECODE
:
417 /* Accept and ignore SDRAM interleave configuration */
418 s
->regs
[saddr
] = val
;
421 /* Device Parameters */
427 /* Not implemented */
428 dprintf ("Unimplemented device register offset 0x%x\n", saddr
<< 2);
432 case GT_ECC_ERRDATALO
:
433 case GT_ECC_ERRDATAHI
:
437 /* Read-only registers, do nothing */
461 /* Not implemented */
462 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr
<< 2);
465 /* DMA Channel Control */
470 /* Not implemented */
471 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr
<< 2);
476 /* Not implemented */
477 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr
<< 2);
486 /* Not implemented */
487 dprintf ("Unimplemented timer register offset 0x%x\n", saddr
<< 2);
493 s
->regs
[saddr
] = val
& 0x0401fc0f;
496 case GT_PCI0_BS_SCS10
:
497 case GT_PCI0_BS_SCS32
:
498 case GT_PCI0_BS_CS20
:
499 case GT_PCI0_BS_CS3BT
:
503 case GT_PCI0_PREFMBR
:
504 case GT_PCI0_SCS10_BAR
:
505 case GT_PCI0_SCS32_BAR
:
506 case GT_PCI0_CS20_BAR
:
507 case GT_PCI0_CS3BT_BAR
:
508 case GT_PCI0_SSCS10_BAR
:
509 case GT_PCI0_SSCS32_BAR
:
510 case GT_PCI0_SCS3BT_BAR
:
512 case GT_PCI1_BS_SCS10
:
513 case GT_PCI1_BS_SCS32
:
514 case GT_PCI1_BS_CS20
:
515 case GT_PCI1_BS_CS3BT
:
517 case GT_PCI1_PREFMBR
:
518 case GT_PCI1_SCS10_BAR
:
519 case GT_PCI1_SCS32_BAR
:
520 case GT_PCI1_CS20_BAR
:
521 case GT_PCI1_CS3BT_BAR
:
522 case GT_PCI1_SSCS10_BAR
:
523 case GT_PCI1_SSCS32_BAR
:
524 case GT_PCI1_SCS3BT_BAR
:
525 case GT_PCI1_CFGADDR
:
526 case GT_PCI1_CFGDATA
:
527 /* not implemented */
529 case GT_PCI0_CFGADDR
:
530 s
->pci
->config_reg
= val
& 0x80fffffc;
532 case GT_PCI0_CFGDATA
:
533 pci_host_data_writel(s
->pci
, 0, val
);
538 /* not really implemented */
539 s
->regs
[saddr
] = ~(~(s
->regs
[saddr
]) | ~(val
& 0xfffffffe));
540 s
->regs
[saddr
] |= !!(s
->regs
[saddr
] & 0xfffffffe);
541 dprintf("INTRCAUSE %x\n", val
);
544 s
->regs
[saddr
] = val
& 0x3c3ffffe;
545 dprintf("INTRMASK %x\n", val
);
548 s
->regs
[saddr
] = val
& 0x03fffffe;
549 dprintf("ICMASK %x\n", val
);
551 case GT_PCI0_SERR0MASK
:
552 s
->regs
[saddr
] = val
& 0x0000003f;
553 dprintf("SERR0MASK %x\n", val
);
556 /* Reserved when only PCI_0 is configured. */
561 case GT_PCI0_HICMASK
:
562 case GT_PCI1_SERR1MASK
:
563 /* not implemented */
566 /* SDRAM Parameters */
571 /* We don't simulate electrical parameters of the SDRAM.
572 Accept, but ignore the values. */
573 s
->regs
[saddr
] = val
;
577 dprintf ("Bad register offset 0x%x\n", (int)addr
);
582 static uint32_t gt64120_readl (void *opaque
,
583 target_phys_addr_t addr
)
585 GT64120State
*s
= opaque
;
589 saddr
= (addr
& 0xfff) >> 2;
592 /* CPU Configuration */
594 /* Only one GT64xxx is present on the CPU bus, return
596 val
= s
->regs
[saddr
];
599 /* CPU Error Report */
600 case GT_CPUERR_ADDRLO
:
601 case GT_CPUERR_ADDRHI
:
602 case GT_CPUERR_DATALO
:
603 case GT_CPUERR_DATAHI
:
604 case GT_CPUERR_PARITY
:
605 /* Emulated memory has no error, always return the initial
607 val
= s
->regs
[saddr
];
610 /* CPU Sync Barrier */
613 /* Reading those register should empty all FIFO on the PCI
614 bus, which are not emulated. The return value should be
615 a random value that should be ignored. */
620 case GT_ECC_ERRDATALO
:
621 case GT_ECC_ERRDATAHI
:
625 /* Emulated memory has no error, always return the initial
627 val
= s
->regs
[saddr
];
662 val
= s
->regs
[saddr
];
665 /* Read the IRQ number */
666 val
= pic_read_irq(isa_pic
);
669 /* SDRAM and Device Address Decode */
689 val
= s
->regs
[saddr
];
692 /* SDRAM Configuration */
694 case GT_SDRAM_OPMODE
:
696 case GT_SDRAM_ADDRDECODE
:
697 val
= s
->regs
[saddr
];
700 /* SDRAM Parameters */
705 /* We don't simulate electrical parameters of the SDRAM.
706 Just return the last written value. */
707 val
= s
->regs
[saddr
];
710 /* Device Parameters */
716 val
= s
->regs
[saddr
];
740 val
= s
->regs
[saddr
];
743 /* DMA Channel Control */
748 val
= s
->regs
[saddr
];
753 val
= s
->regs
[saddr
];
762 val
= s
->regs
[saddr
];
766 case GT_PCI0_CFGADDR
:
767 val
= s
->pci
->config_reg
;
769 case GT_PCI0_CFGDATA
:
770 val
= pci_host_data_readl(s
->pci
, 0);
775 case GT_PCI0_BS_SCS10
:
776 case GT_PCI0_BS_SCS32
:
777 case GT_PCI0_BS_CS20
:
778 case GT_PCI0_BS_CS3BT
:
781 case GT_PCI0_PREFMBR
:
782 case GT_PCI0_SCS10_BAR
:
783 case GT_PCI0_SCS32_BAR
:
784 case GT_PCI0_CS20_BAR
:
785 case GT_PCI0_CS3BT_BAR
:
786 case GT_PCI0_SSCS10_BAR
:
787 case GT_PCI0_SSCS32_BAR
:
788 case GT_PCI0_SCS3BT_BAR
:
791 case GT_PCI1_BS_SCS10
:
792 case GT_PCI1_BS_SCS32
:
793 case GT_PCI1_BS_CS20
:
794 case GT_PCI1_BS_CS3BT
:
796 case GT_PCI1_PREFMBR
:
797 case GT_PCI1_SCS10_BAR
:
798 case GT_PCI1_SCS32_BAR
:
799 case GT_PCI1_CS20_BAR
:
800 case GT_PCI1_CS3BT_BAR
:
801 case GT_PCI1_SSCS10_BAR
:
802 case GT_PCI1_SSCS32_BAR
:
803 case GT_PCI1_SCS3BT_BAR
:
804 case GT_PCI1_CFGADDR
:
805 case GT_PCI1_CFGDATA
:
806 val
= s
->regs
[saddr
];
811 val
= s
->regs
[saddr
];
812 dprintf("INTRCAUSE %x\n", val
);
815 val
= s
->regs
[saddr
];
816 dprintf("INTRMASK %x\n", val
);
819 val
= s
->regs
[saddr
];
820 dprintf("ICMASK %x\n", val
);
822 case GT_PCI0_SERR0MASK
:
823 val
= s
->regs
[saddr
];
824 dprintf("SERR0MASK %x\n", val
);
827 /* Reserved when only PCI_0 is configured. */
832 case GT_PCI0_HICMASK
:
833 case GT_PCI1_SERR1MASK
:
834 val
= s
->regs
[saddr
];
838 val
= s
->regs
[saddr
];
839 dprintf ("Bad register offset 0x%x\n", (int)addr
);
843 if (!(s
->regs
[GT_PCI0_CMD
] & 1))
849 static CPUWriteMemoryFunc
*gt64120_write
[] = {
855 static CPUReadMemoryFunc
*gt64120_read
[] = {
861 static int pci_gt64120_map_irq(PCIDevice
*pci_dev
, int irq_num
)
865 slot
= (pci_dev
->devfn
>> 3);
871 /* AMD 79C973 Ethernet */
874 /* Crystal 4281 Sound */
877 /* PCI slot 1 to 4 */
879 return ((slot
- 18) + irq_num
) & 0x03;
880 /* Unknown device, don't do any translation */
886 extern PCIDevice
*piix4_dev
;
887 static int pci_irq_levels
[4];
889 static void pci_gt64120_set_irq(qemu_irq
*pic
, int irq_num
, int level
)
891 int i
, pic_irq
, pic_level
;
893 pci_irq_levels
[irq_num
] = level
;
895 /* now we change the pic irq level according to the piix irq mappings */
897 pic_irq
= piix4_dev
->config
[0x60 + irq_num
];
899 /* The pic level is the logical OR of all the PCI irqs mapped
902 for (i
= 0; i
< 4; i
++) {
903 if (pic_irq
== piix4_dev
->config
[0x60 + i
])
904 pic_level
|= pci_irq_levels
[i
];
906 qemu_set_irq(pic
[pic_irq
], pic_level
);
911 static void gt64120_reset(void *opaque
)
913 GT64120State
*s
= opaque
;
915 /* FIXME: Malta specific hw assumptions ahead */
917 /* CPU Configuration */
918 #ifdef TARGET_WORDS_BIGENDIAN
919 s
->regs
[GT_CPU
] = 0x00000000;
921 s
->regs
[GT_CPU
] = 0x00001000;
923 s
->regs
[GT_MULTI
] = 0x00000003;
925 /* CPU Address decode */
926 s
->regs
[GT_SCS10LD
] = 0x00000000;
927 s
->regs
[GT_SCS10HD
] = 0x00000007;
928 s
->regs
[GT_SCS32LD
] = 0x00000008;
929 s
->regs
[GT_SCS32HD
] = 0x0000000f;
930 s
->regs
[GT_CS20LD
] = 0x000000e0;
931 s
->regs
[GT_CS20HD
] = 0x00000070;
932 s
->regs
[GT_CS3BOOTLD
] = 0x000000f8;
933 s
->regs
[GT_CS3BOOTHD
] = 0x0000007f;
935 s
->regs
[GT_PCI0IOLD
] = 0x00000080;
936 s
->regs
[GT_PCI0IOHD
] = 0x0000000f;
937 s
->regs
[GT_PCI0M0LD
] = 0x00000090;
938 s
->regs
[GT_PCI0M0HD
] = 0x0000001f;
939 s
->regs
[GT_ISD
] = 0x000000a0;
940 s
->regs
[GT_PCI0M1LD
] = 0x00000790;
941 s
->regs
[GT_PCI0M1HD
] = 0x0000001f;
942 s
->regs
[GT_PCI1IOLD
] = 0x00000100;
943 s
->regs
[GT_PCI1IOHD
] = 0x0000000f;
944 s
->regs
[GT_PCI1M0LD
] = 0x00000110;
945 s
->regs
[GT_PCI1M0HD
] = 0x0000001f;
946 s
->regs
[GT_PCI1M1LD
] = 0x00000120;
947 s
->regs
[GT_PCI1M1HD
] = 0x0000002f;
949 s
->regs
[GT_SCS10AR
] = 0x00000000;
950 s
->regs
[GT_SCS32AR
] = 0x00000008;
951 s
->regs
[GT_CS20R
] = 0x000000e0;
952 s
->regs
[GT_CS3BOOTR
] = 0x000000f8;
954 s
->regs
[GT_PCI0IOREMAP
] = 0x00000080;
955 s
->regs
[GT_PCI0M0REMAP
] = 0x00000090;
956 s
->regs
[GT_PCI0M1REMAP
] = 0x00000790;
957 s
->regs
[GT_PCI1IOREMAP
] = 0x00000100;
958 s
->regs
[GT_PCI1M0REMAP
] = 0x00000110;
959 s
->regs
[GT_PCI1M1REMAP
] = 0x00000120;
961 /* CPU Error Report */
962 s
->regs
[GT_CPUERR_ADDRLO
] = 0x00000000;
963 s
->regs
[GT_CPUERR_ADDRHI
] = 0x00000000;
964 s
->regs
[GT_CPUERR_DATALO
] = 0xffffffff;
965 s
->regs
[GT_CPUERR_DATAHI
] = 0xffffffff;
966 s
->regs
[GT_CPUERR_PARITY
] = 0x000000ff;
968 /* CPU Sync Barrier */
969 s
->regs
[GT_PCI0SYNC
] = 0x00000000;
970 s
->regs
[GT_PCI1SYNC
] = 0x00000000;
972 /* SDRAM and Device Address Decode */
973 s
->regs
[GT_SCS0LD
] = 0x00000000;
974 s
->regs
[GT_SCS0HD
] = 0x00000007;
975 s
->regs
[GT_SCS1LD
] = 0x00000008;
976 s
->regs
[GT_SCS1HD
] = 0x0000000f;
977 s
->regs
[GT_SCS2LD
] = 0x00000010;
978 s
->regs
[GT_SCS2HD
] = 0x00000017;
979 s
->regs
[GT_SCS3LD
] = 0x00000018;
980 s
->regs
[GT_SCS3HD
] = 0x0000001f;
981 s
->regs
[GT_CS0LD
] = 0x000000c0;
982 s
->regs
[GT_CS0HD
] = 0x000000c7;
983 s
->regs
[GT_CS1LD
] = 0x000000c8;
984 s
->regs
[GT_CS1HD
] = 0x000000cf;
985 s
->regs
[GT_CS2LD
] = 0x000000d0;
986 s
->regs
[GT_CS2HD
] = 0x000000df;
987 s
->regs
[GT_CS3LD
] = 0x000000f0;
988 s
->regs
[GT_CS3HD
] = 0x000000fb;
989 s
->regs
[GT_BOOTLD
] = 0x000000fc;
990 s
->regs
[GT_BOOTHD
] = 0x000000ff;
991 s
->regs
[GT_ADERR
] = 0xffffffff;
993 /* SDRAM Configuration */
994 s
->regs
[GT_SDRAM_CFG
] = 0x00000200;
995 s
->regs
[GT_SDRAM_OPMODE
] = 0x00000000;
996 s
->regs
[GT_SDRAM_BM
] = 0x00000007;
997 s
->regs
[GT_SDRAM_ADDRDECODE
] = 0x00000002;
999 /* SDRAM Parameters */
1000 s
->regs
[GT_SDRAM_B0
] = 0x00000005;
1001 s
->regs
[GT_SDRAM_B1
] = 0x00000005;
1002 s
->regs
[GT_SDRAM_B2
] = 0x00000005;
1003 s
->regs
[GT_SDRAM_B3
] = 0x00000005;
1006 s
->regs
[GT_ECC_ERRDATALO
] = 0x00000000;
1007 s
->regs
[GT_ECC_ERRDATAHI
] = 0x00000000;
1008 s
->regs
[GT_ECC_MEM
] = 0x00000000;
1009 s
->regs
[GT_ECC_CALC
] = 0x00000000;
1010 s
->regs
[GT_ECC_ERRADDR
] = 0x00000000;
1012 /* Device Parameters */
1013 s
->regs
[GT_DEV_B0
] = 0x386fffff;
1014 s
->regs
[GT_DEV_B1
] = 0x386fffff;
1015 s
->regs
[GT_DEV_B2
] = 0x386fffff;
1016 s
->regs
[GT_DEV_B3
] = 0x386fffff;
1017 s
->regs
[GT_DEV_BOOT
] = 0x146fffff;
1019 /* DMA registers are all zeroed at reset */
1022 s
->regs
[GT_TC0
] = 0xffffffff;
1023 s
->regs
[GT_TC1
] = 0x00ffffff;
1024 s
->regs
[GT_TC2
] = 0x00ffffff;
1025 s
->regs
[GT_TC3
] = 0x00ffffff;
1026 s
->regs
[GT_TC_CONTROL
] = 0x00000000;
1029 #ifdef TARGET_WORDS_BIGENDIAN
1030 s
->regs
[GT_PCI0_CMD
] = 0x00000000;
1032 s
->regs
[GT_PCI0_CMD
] = 0x00010001;
1034 s
->regs
[GT_PCI0_TOR
] = 0x0000070f;
1035 s
->regs
[GT_PCI0_BS_SCS10
] = 0x00fff000;
1036 s
->regs
[GT_PCI0_BS_SCS32
] = 0x00fff000;
1037 s
->regs
[GT_PCI0_BS_CS20
] = 0x01fff000;
1038 s
->regs
[GT_PCI0_BS_CS3BT
] = 0x00fff000;
1039 s
->regs
[GT_PCI1_IACK
] = 0x00000000;
1040 s
->regs
[GT_PCI0_IACK
] = 0x00000000;
1041 s
->regs
[GT_PCI0_BARE
] = 0x0000000f;
1042 s
->regs
[GT_PCI0_PREFMBR
] = 0x00000040;
1043 s
->regs
[GT_PCI0_SCS10_BAR
] = 0x00000000;
1044 s
->regs
[GT_PCI0_SCS32_BAR
] = 0x01000000;
1045 s
->regs
[GT_PCI0_CS20_BAR
] = 0x1c000000;
1046 s
->regs
[GT_PCI0_CS3BT_BAR
] = 0x1f000000;
1047 s
->regs
[GT_PCI0_SSCS10_BAR
] = 0x00000000;
1048 s
->regs
[GT_PCI0_SSCS32_BAR
] = 0x01000000;
1049 s
->regs
[GT_PCI0_SCS3BT_BAR
] = 0x1f000000;
1050 #ifdef TARGET_WORDS_BIGENDIAN
1051 s
->regs
[GT_PCI1_CMD
] = 0x00000000;
1053 s
->regs
[GT_PCI1_CMD
] = 0x00010001;
1055 s
->regs
[GT_PCI1_TOR
] = 0x0000070f;
1056 s
->regs
[GT_PCI1_BS_SCS10
] = 0x00fff000;
1057 s
->regs
[GT_PCI1_BS_SCS32
] = 0x00fff000;
1058 s
->regs
[GT_PCI1_BS_CS20
] = 0x01fff000;
1059 s
->regs
[GT_PCI1_BS_CS3BT
] = 0x00fff000;
1060 s
->regs
[GT_PCI1_BARE
] = 0x0000000f;
1061 s
->regs
[GT_PCI1_PREFMBR
] = 0x00000040;
1062 s
->regs
[GT_PCI1_SCS10_BAR
] = 0x00000000;
1063 s
->regs
[GT_PCI1_SCS32_BAR
] = 0x01000000;
1064 s
->regs
[GT_PCI1_CS20_BAR
] = 0x1c000000;
1065 s
->regs
[GT_PCI1_CS3BT_BAR
] = 0x1f000000;
1066 s
->regs
[GT_PCI1_SSCS10_BAR
] = 0x00000000;
1067 s
->regs
[GT_PCI1_SSCS32_BAR
] = 0x01000000;
1068 s
->regs
[GT_PCI1_SCS3BT_BAR
] = 0x1f000000;
1069 s
->regs
[GT_PCI1_CFGADDR
] = 0x00000000;
1070 s
->regs
[GT_PCI1_CFGDATA
] = 0x00000000;
1071 s
->regs
[GT_PCI0_CFGADDR
] = 0x00000000;
1072 s
->regs
[GT_PCI0_CFGDATA
] = 0x00000000;
1074 /* Interrupt registers are all zeroed at reset */
1076 gt64120_isd_mapping(s
);
1077 gt64120_pci_mapping(s
);
1080 static uint32_t gt64120_read_config(PCIDevice
*d
, uint32_t address
, int len
)
1082 return pci_default_read_config(d
, address
, len
);
1085 static void gt64120_write_config(PCIDevice
*d
, uint32_t address
, uint32_t val
,
1088 pci_default_write_config(d
, address
, val
, len
);
1091 static void gt64120_save(QEMUFile
* f
, void *opaque
)
1093 PCIDevice
*d
= opaque
;
1094 pci_device_save(d
, f
);
1097 static int gt64120_load(QEMUFile
* f
, void *opaque
, int version_id
)
1099 PCIDevice
*d
= opaque
;
1102 if (version_id
!= 1)
1104 ret
= pci_device_load(d
, f
);
1110 PCIBus
*pci_gt64120_init(qemu_irq
*pic
)
1115 (void)&pci_host_data_writeb
; /* avoid warning */
1116 (void)&pci_host_data_writew
; /* avoid warning */
1117 (void)&pci_host_data_readb
; /* avoid warning */
1118 (void)&pci_host_data_readw
; /* avoid warning */
1120 s
= qemu_mallocz(sizeof(GT64120State
));
1121 s
->pci
= qemu_mallocz(sizeof(GT64120PCIState
));
1123 s
->pci
->bus
= pci_register_bus(pci_gt64120_set_irq
, pci_gt64120_map_irq
,
1125 s
->ISD_handle
= cpu_register_io_memory(0, gt64120_read
, gt64120_write
, s
);
1126 d
= pci_register_device(s
->pci
->bus
, "GT64120 PCI Bus", sizeof(PCIDevice
),
1127 0, gt64120_read_config
, gt64120_write_config
);
1129 /* FIXME: Malta specific hw assumptions ahead */
1131 d
->config
[0x00] = 0xab; /* vendor_id */
1132 d
->config
[0x01] = 0x11;
1133 d
->config
[0x02] = 0x20; /* device_id */
1134 d
->config
[0x03] = 0x46;
1136 d
->config
[0x04] = 0x00;
1137 d
->config
[0x05] = 0x00;
1138 d
->config
[0x06] = 0x80;
1139 d
->config
[0x07] = 0x02;
1141 d
->config
[0x08] = 0x10;
1142 d
->config
[0x09] = 0x00;
1143 d
->config
[0x0A] = 0x00;
1144 d
->config
[0x0B] = 0x06;
1146 d
->config
[0x10] = 0x08;
1147 d
->config
[0x14] = 0x08;
1148 d
->config
[0x17] = 0x01;
1149 d
->config
[0x1B] = 0x1c;
1150 d
->config
[0x1F] = 0x1f;
1151 d
->config
[0x23] = 0x14;
1152 d
->config
[0x24] = 0x01;
1153 d
->config
[0x27] = 0x14;
1154 d
->config
[0x3D] = 0x01;
1158 register_savevm("GT64120 PCI Bus", 0, 1, gt64120_save
, gt64120_load
, d
);