2 * High Precisition Event Timer emulation
4 * Copyright (c) 2007 Alexander Graf
5 * Copyright (c) 2008 IBM Corporation
7 * Authors: Beth Kon <bkon@us.ibm.com>
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 * *****************************************************************
24 * This driver attempts to emulate an HPET device in software.
30 #include "qemu-timer.h"
31 #include "hpet_emul.h"
36 #define DPRINTF printf
42 typedef struct HPETTimer
{ /* timers */
43 uint8_t tn
; /*timer number*/
44 QEMUTimer
*qemu_timer
;
45 struct HPETState
*state
;
46 /* Memory-mapped, software visible timer registers */
47 uint64_t config
; /* configuration/cap */
48 uint64_t cmp
; /* comparator */
49 uint64_t fsb
; /* FSB route, not supported now */
50 /* Hidden register state */
51 uint64_t period
; /* Last value written to comparator */
52 uint8_t wrap_flag
; /* timer pop will indicate wrap for one-shot 32-bit
53 * mode. Next pop will be actual timer expiration.
57 typedef struct HPETState
{
60 qemu_irq irqs
[HPET_NUM_IRQ_ROUTES
];
61 HPETTimer timer
[HPET_NUM_TIMERS
];
63 /* Memory-mapped, software visible registers */
64 uint64_t capability
; /* capabilities */
65 uint64_t config
; /* configuration */
66 uint64_t isr
; /* interrupt status reg */
67 uint64_t hpet_counter
; /* main counter */
70 static HPETState
*hpet_statep
;
72 uint32_t hpet_in_legacy_mode(void)
77 return hpet_statep
->config
& HPET_CFG_LEGACY
;
80 static uint32_t timer_int_route(struct HPETTimer
*timer
)
82 return (timer
->config
& HPET_TN_INT_ROUTE_MASK
) >> HPET_TN_INT_ROUTE_SHIFT
;
85 static uint32_t hpet_enabled(void)
87 return hpet_statep
->config
& HPET_CFG_ENABLE
;
90 static uint32_t timer_is_periodic(HPETTimer
*t
)
92 return t
->config
& HPET_TN_PERIODIC
;
95 static uint32_t timer_enabled(HPETTimer
*t
)
97 return t
->config
& HPET_TN_ENABLE
;
100 static uint32_t hpet_time_after(uint64_t a
, uint64_t b
)
102 return ((int32_t)(b
) - (int32_t)(a
) < 0);
105 static uint32_t hpet_time_after64(uint64_t a
, uint64_t b
)
107 return ((int64_t)(b
) - (int64_t)(a
) < 0);
110 static uint64_t ticks_to_ns(uint64_t value
)
112 return (muldiv64(value
, HPET_CLK_PERIOD
, FS_PER_NS
));
115 static uint64_t ns_to_ticks(uint64_t value
)
117 return (muldiv64(value
, FS_PER_NS
, HPET_CLK_PERIOD
));
120 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old
, uint64_t mask
)
127 static int activating_bit(uint64_t old
, uint64_t new, uint64_t mask
)
129 return (!(old
& mask
) && (new & mask
));
132 static int deactivating_bit(uint64_t old
, uint64_t new, uint64_t mask
)
134 return ((old
& mask
) && !(new & mask
));
137 static uint64_t hpet_get_ticks(void)
139 return ns_to_ticks(qemu_get_clock(vm_clock
) + hpet_statep
->hpet_offset
);
143 * calculate diff between comparator value and current ticks
145 static inline uint64_t hpet_calculate_diff(HPETTimer
*t
, uint64_t current
)
148 if (t
->config
& HPET_TN_32BIT
) {
151 cmp
= (uint32_t)t
->cmp
;
152 diff
= cmp
- (uint32_t)current
;
153 diff
= (int32_t)diff
> 0 ? diff
: (uint32_t)0;
154 return (uint64_t)diff
;
159 diff
= cmp
- current
;
160 diff
= (int64_t)diff
> 0 ? diff
: (uint64_t)0;
165 static void update_irq(struct HPETTimer
*timer
)
169 if (timer
->tn
<= 1 && hpet_in_legacy_mode()) {
170 /* if LegacyReplacementRoute bit is set, HPET specification requires
171 * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
172 * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
174 route
= (timer
->tn
== 0) ? 0 : 8;
176 route
= timer_int_route(timer
);
178 if (!timer_enabled(timer
) || !hpet_enabled()) {
181 qemu_irq_pulse(timer
->state
->irqs
[route
]);
184 static void hpet_pre_save(void *opaque
)
186 HPETState
*s
= opaque
;
188 /* save current counter value */
189 s
->hpet_counter
= hpet_get_ticks();
192 static int hpet_post_load(void *opaque
, int version_id
)
194 HPETState
*s
= opaque
;
196 /* Recalculate the offset between the main counter and guest time */
197 s
->hpet_offset
= ticks_to_ns(s
->hpet_counter
) - qemu_get_clock(vm_clock
);
201 static const VMStateDescription vmstate_hpet_timer
= {
202 .name
= "hpet_timer",
204 .minimum_version_id
= 1,
205 .minimum_version_id_old
= 1,
206 .fields
= (VMStateField
[]) {
207 VMSTATE_UINT8(tn
, HPETTimer
),
208 VMSTATE_UINT64(config
, HPETTimer
),
209 VMSTATE_UINT64(cmp
, HPETTimer
),
210 VMSTATE_UINT64(fsb
, HPETTimer
),
211 VMSTATE_UINT64(period
, HPETTimer
),
212 VMSTATE_UINT8(wrap_flag
, HPETTimer
),
213 VMSTATE_TIMER(qemu_timer
, HPETTimer
),
214 VMSTATE_END_OF_LIST()
218 static const VMStateDescription vmstate_hpet
= {
221 .minimum_version_id
= 1,
222 .minimum_version_id_old
= 1,
223 .pre_save
= hpet_pre_save
,
224 .post_load
= hpet_post_load
,
225 .fields
= (VMStateField
[]) {
226 VMSTATE_UINT64(config
, HPETState
),
227 VMSTATE_UINT64(isr
, HPETState
),
228 VMSTATE_UINT64(hpet_counter
, HPETState
),
229 VMSTATE_STRUCT_ARRAY(timer
, HPETState
, HPET_NUM_TIMERS
, 0,
230 vmstate_hpet_timer
, HPETTimer
),
231 VMSTATE_END_OF_LIST()
236 * timer expiration callback
238 static void hpet_timer(void *opaque
)
240 HPETTimer
*t
= opaque
;
243 uint64_t period
= t
->period
;
244 uint64_t cur_tick
= hpet_get_ticks();
246 if (timer_is_periodic(t
) && period
!= 0) {
247 if (t
->config
& HPET_TN_32BIT
) {
248 while (hpet_time_after(cur_tick
, t
->cmp
)) {
249 t
->cmp
= (uint32_t)(t
->cmp
+ t
->period
);
252 while (hpet_time_after64(cur_tick
, t
->cmp
)) {
256 diff
= hpet_calculate_diff(t
, cur_tick
);
257 qemu_mod_timer(t
->qemu_timer
,
258 qemu_get_clock(vm_clock
) + (int64_t)ticks_to_ns(diff
));
259 } else if (t
->config
& HPET_TN_32BIT
&& !timer_is_periodic(t
)) {
261 diff
= hpet_calculate_diff(t
, cur_tick
);
262 qemu_mod_timer(t
->qemu_timer
, qemu_get_clock(vm_clock
) +
263 (int64_t)ticks_to_ns(diff
));
270 static void hpet_set_timer(HPETTimer
*t
)
273 uint32_t wrap_diff
; /* how many ticks until we wrap? */
274 uint64_t cur_tick
= hpet_get_ticks();
276 /* whenever new timer is being set up, make sure wrap_flag is 0 */
278 diff
= hpet_calculate_diff(t
, cur_tick
);
280 /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
281 * counter wraps in addition to an interrupt with comparator match.
283 if (t
->config
& HPET_TN_32BIT
&& !timer_is_periodic(t
)) {
284 wrap_diff
= 0xffffffff - (uint32_t)cur_tick
;
285 if (wrap_diff
< (uint32_t)diff
) {
290 qemu_mod_timer(t
->qemu_timer
,
291 qemu_get_clock(vm_clock
) + (int64_t)ticks_to_ns(diff
));
294 static void hpet_del_timer(HPETTimer
*t
)
296 qemu_del_timer(t
->qemu_timer
);
300 static uint32_t hpet_ram_readb(void *opaque
, target_phys_addr_t addr
)
302 printf("qemu: hpet_read b at %" PRIx64
"\n", addr
);
306 static uint32_t hpet_ram_readw(void *opaque
, target_phys_addr_t addr
)
308 printf("qemu: hpet_read w at %" PRIx64
"\n", addr
);
313 static uint32_t hpet_ram_readl(void *opaque
, target_phys_addr_t addr
)
315 HPETState
*s
= opaque
;
316 uint64_t cur_tick
, index
;
318 DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64
"\n", addr
);
320 /*address range of all TN regs*/
321 if (index
>= 0x100 && index
<= 0x3ff) {
322 uint8_t timer_id
= (addr
- 0x100) / 0x20;
323 HPETTimer
*timer
= &s
->timer
[timer_id
];
325 if (timer_id
> HPET_NUM_TIMERS
- 1) {
326 DPRINTF("qemu: timer id out of range\n");
330 switch ((addr
- 0x100) % 0x20) {
332 return timer
->config
;
333 case HPET_TN_CFG
+ 4: // Interrupt capabilities
334 return timer
->config
>> 32;
335 case HPET_TN_CMP
: // comparator register
337 case HPET_TN_CMP
+ 4:
338 return timer
->cmp
>> 32;
340 return timer
->fsb
>> 32;
342 DPRINTF("qemu: invalid hpet_ram_readl\n");
348 return s
->capability
;
350 return s
->capability
>> 32;
354 DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
357 if (hpet_enabled()) {
358 cur_tick
= hpet_get_ticks();
360 cur_tick
= s
->hpet_counter
;
362 DPRINTF("qemu: reading counter = %" PRIx64
"\n", cur_tick
);
364 case HPET_COUNTER
+ 4:
365 if (hpet_enabled()) {
366 cur_tick
= hpet_get_ticks();
368 cur_tick
= s
->hpet_counter
;
370 DPRINTF("qemu: reading counter + 4 = %" PRIx64
"\n", cur_tick
);
371 return cur_tick
>> 32;
375 DPRINTF("qemu: invalid hpet_ram_readl\n");
383 static void hpet_ram_writeb(void *opaque
, target_phys_addr_t addr
,
386 printf("qemu: invalid hpet_write b at %" PRIx64
" = %#x\n",
390 static void hpet_ram_writew(void *opaque
, target_phys_addr_t addr
,
393 printf("qemu: invalid hpet_write w at %" PRIx64
" = %#x\n",
398 static void hpet_ram_writel(void *opaque
, target_phys_addr_t addr
,
402 HPETState
*s
= opaque
;
403 uint64_t old_val
, new_val
, val
, index
;
405 DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64
" = %#x\n", addr
, value
);
407 old_val
= hpet_ram_readl(opaque
, addr
);
410 /*address range of all TN regs*/
411 if (index
>= 0x100 && index
<= 0x3ff) {
412 uint8_t timer_id
= (addr
- 0x100) / 0x20;
413 HPETTimer
*timer
= &s
->timer
[timer_id
];
415 DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id
);
416 if (timer_id
> HPET_NUM_TIMERS
- 1) {
417 DPRINTF("qemu: timer id out of range\n");
420 switch ((addr
- 0x100) % 0x20) {
422 DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
423 val
= hpet_fixup_reg(new_val
, old_val
, HPET_TN_CFG_WRITE_MASK
);
424 timer
->config
= (timer
->config
& 0xffffffff00000000ULL
) | val
;
425 if (new_val
& HPET_TN_32BIT
) {
426 timer
->cmp
= (uint32_t)timer
->cmp
;
427 timer
->period
= (uint32_t)timer
->period
;
429 if (new_val
& HPET_TN_TYPE_LEVEL
) {
430 printf("qemu: level-triggered hpet not supported\n");
433 if (activating_bit(old_val
, new_val
, HPET_TN_ENABLE
)) {
434 hpet_set_timer(timer
);
435 } else if (deactivating_bit(old_val
, new_val
, HPET_TN_ENABLE
)) {
436 hpet_del_timer(timer
);
439 case HPET_TN_CFG
+ 4: // Interrupt capabilities
440 DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
442 case HPET_TN_CMP
: // comparator register
443 DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
444 if (timer
->config
& HPET_TN_32BIT
) {
445 new_val
= (uint32_t)new_val
;
447 if (!timer_is_periodic(timer
)
448 || (timer
->config
& HPET_TN_SETVAL
)) {
449 timer
->cmp
= (timer
->cmp
& 0xffffffff00000000ULL
) | new_val
;
451 if (timer_is_periodic(timer
)) {
453 * FIXME: Clamp period to reasonable min value?
454 * Clamp period to reasonable max value
456 new_val
&= (timer
->config
& HPET_TN_32BIT
? ~0u : ~0ull) >> 1;
458 (timer
->period
& 0xffffffff00000000ULL
) | new_val
;
460 timer
->config
&= ~HPET_TN_SETVAL
;
461 if (hpet_enabled()) {
462 hpet_set_timer(timer
);
465 case HPET_TN_CMP
+ 4: // comparator register high order
466 DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
467 if (!timer_is_periodic(timer
)
468 || (timer
->config
& HPET_TN_SETVAL
)) {
469 timer
->cmp
= (timer
->cmp
& 0xffffffffULL
) | new_val
<< 32;
472 * FIXME: Clamp period to reasonable min value?
473 * Clamp period to reasonable max value
475 new_val
&= (timer
->config
& HPET_TN_32BIT
? ~0u : ~0ull) >> 1;
477 (timer
->period
& 0xffffffffULL
) | new_val
<< 32;
479 timer
->config
&= ~HPET_TN_SETVAL
;
480 if (hpet_enabled()) {
481 hpet_set_timer(timer
);
484 case HPET_TN_ROUTE
+ 4:
485 DPRINTF("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
488 DPRINTF("qemu: invalid hpet_ram_writel\n");
497 val
= hpet_fixup_reg(new_val
, old_val
, HPET_CFG_WRITE_MASK
);
498 s
->config
= (s
->config
& 0xffffffff00000000ULL
) | val
;
499 if (activating_bit(old_val
, new_val
, HPET_CFG_ENABLE
)) {
500 /* Enable main counter and interrupt generation. */
502 ticks_to_ns(s
->hpet_counter
) - qemu_get_clock(vm_clock
);
503 for (i
= 0; i
< HPET_NUM_TIMERS
; i
++) {
504 if ((&s
->timer
[i
])->cmp
!= ~0ULL) {
505 hpet_set_timer(&s
->timer
[i
]);
508 } else if (deactivating_bit(old_val
, new_val
, HPET_CFG_ENABLE
)) {
509 /* Halt main counter and disable interrupt generation. */
510 s
->hpet_counter
= hpet_get_ticks();
511 for (i
= 0; i
< HPET_NUM_TIMERS
; i
++) {
512 hpet_del_timer(&s
->timer
[i
]);
515 /* i8254 and RTC are disabled when HPET is in legacy mode */
516 if (activating_bit(old_val
, new_val
, HPET_CFG_LEGACY
)) {
518 } else if (deactivating_bit(old_val
, new_val
, HPET_CFG_LEGACY
)) {
523 DPRINTF("qemu: invalid HPET_CFG+4 write \n");
526 /* FIXME: need to handle level-triggered interrupts */
529 if (hpet_enabled()) {
530 DPRINTF("qemu: Writing counter while HPET enabled!\n");
533 (s
->hpet_counter
& 0xffffffff00000000ULL
) | value
;
534 DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64
"\n",
535 value
, s
->hpet_counter
);
537 case HPET_COUNTER
+ 4:
538 if (hpet_enabled()) {
539 DPRINTF("qemu: Writing counter while HPET enabled!\n");
542 (s
->hpet_counter
& 0xffffffffULL
) | (((uint64_t)value
) << 32);
543 DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64
"\n",
544 value
, s
->hpet_counter
);
547 DPRINTF("qemu: invalid hpet_ram_writel\n");
553 static CPUReadMemoryFunc
* const hpet_ram_read
[] = {
564 static CPUWriteMemoryFunc
* const hpet_ram_write
[] = {
575 static void hpet_reset(DeviceState
*d
)
577 HPETState
*s
= FROM_SYSBUS(HPETState
, sysbus_from_qdev(d
));
579 static int count
= 0;
581 for (i
= 0; i
< HPET_NUM_TIMERS
; i
++) {
582 HPETTimer
*timer
= &s
->timer
[i
];
584 hpet_del_timer(timer
);
586 timer
->config
= HPET_TN_PERIODIC_CAP
| HPET_TN_SIZE_CAP
;
587 /* advertise availability of ioapic inti2 */
588 timer
->config
|= 0x00000004ULL
<< 32;
589 timer
->period
= 0ULL;
590 timer
->wrap_flag
= 0;
593 s
->hpet_counter
= 0ULL;
594 s
->hpet_offset
= 0ULL;
595 /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
596 s
->capability
= 0x8086a201ULL
;
597 s
->capability
|= ((HPET_CLK_PERIOD
) << 32);
600 /* we don't enable pit when hpet_reset is first called (by hpet_init)
601 * because hpet is taking over for pit here. On subsequent invocations,
602 * hpet_reset is called due to system reset. At this point control must
603 * be returned to pit until SW reenables hpet.
610 static int hpet_init(SysBusDevice
*dev
)
612 HPETState
*s
= FROM_SYSBUS(HPETState
, dev
);
616 assert(!hpet_statep
);
618 for (i
= 0; i
< HPET_NUM_IRQ_ROUTES
; i
++) {
619 sysbus_init_irq(dev
, &s
->irqs
[i
]);
621 for (i
= 0; i
< HPET_NUM_TIMERS
; i
++) {
622 timer
= &s
->timer
[i
];
623 timer
->qemu_timer
= qemu_new_timer(vm_clock
, hpet_timer
, timer
);
629 iomemtype
= cpu_register_io_memory(hpet_ram_read
,
631 sysbus_init_mmio(dev
, 0x400, iomemtype
);
635 static SysBusDeviceInfo hpet_device_info
= {
637 .qdev
.size
= sizeof(HPETState
),
639 .qdev
.vmsd
= &vmstate_hpet
,
640 .qdev
.reset
= hpet_reset
,
644 static void hpet_register_device(void)
646 sysbus_register_withprop(&hpet_device_info
);
649 device_init(hpet_register_device
)