hw/hpet.c

   1 /*
   2  *  High Precisition Event Timer emulation
   3  *
   4  *  Copyright (c) 2007 Alexander Graf
   5  *  Copyright (c) 2008 IBM Corporation
   6  *
   7  *  Authors: Beth Kon <bkon@us.ibm.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * *****************************************************************
  23  *
  24  * This driver attempts to emulate an HPET device in software.
  25  */
  26
  27 #include "hw.h"
  28 #include "pc.h"
  29 #include "console.h"
  30 #include "qemu-timer.h"
  31 #include "hpet_emul.h"
  32 #include "sysbus.h"
  33 #include "mc146818rtc.h"
  34
  35 //#define HPET_DEBUG
  36 #ifdef HPET_DEBUG
  37 #define DPRINTF printf
  38 #else
  39 #define DPRINTF(...)
  40 #endif
  41
  42 struct HPETState;
  43 typedef struct HPETTimer {  /* timers */
  44     uint8_t tn;             /*timer number*/
  45     QEMUTimer *qemu_timer;
  46     struct HPETState *state;
  47     /* Memory-mapped, software visible timer registers */
  48     uint64_t config;        /* configuration/cap */
  49     uint64_t cmp;           /* comparator */
  50     uint64_t fsb;           /* FSB route, not supported now */
  51     /* Hidden register state */
  52     uint64_t period;        /* Last value written to comparator */
  53     uint8_t wrap_flag;      /* timer pop will indicate wrap for one-shot 32-bit
  54                              * mode. Next pop will be actual timer expiration.
  55                              */
  56 } HPETTimer;
  57
  58 typedef struct HPETState {
  59     SysBusDevice busdev;
  60     uint64_t hpet_offset;
  61     qemu_irq irqs[HPET_NUM_IRQ_ROUTES];
  62     uint8_t rtc_irq_level;
  63     HPETTimer timer[HPET_NUM_TIMERS];
  64
  65     /* Memory-mapped, software visible registers */
  66     uint64_t capability;        /* capabilities */
  67     uint64_t config;            /* configuration */
  68     uint64_t isr;               /* interrupt status reg */
  69     uint64_t hpet_counter;      /* main counter */
  70 } HPETState;
  71
  72 static uint32_t hpet_in_legacy_mode(HPETState *s)
  73 {
  74     return s->config & HPET_CFG_LEGACY;
  75 }
  76
  77 static uint32_t timer_int_route(struct HPETTimer *timer)
  78 {
  79     return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
  80 }
  81
  82 static uint32_t hpet_enabled(HPETState *s)
  83 {
  84     return s->config & HPET_CFG_ENABLE;
  85 }
  86
  87 static uint32_t timer_is_periodic(HPETTimer *t)
  88 {
  89     return t->config & HPET_TN_PERIODIC;
  90 }
  91
  92 static uint32_t timer_enabled(HPETTimer *t)
  93 {
  94     return t->config & HPET_TN_ENABLE;
  95 }
  96
  97 static uint32_t hpet_time_after(uint64_t a, uint64_t b)
  98 {
  99     return ((int32_t)(b) - (int32_t)(a) < 0);
 100 }
 101
 102 static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
 103 {
 104     return ((int64_t)(b) - (int64_t)(a) < 0);
 105 }
 106
 107 static uint64_t ticks_to_ns(uint64_t value)
 108 {
 109     return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
 110 }
 111
 112 static uint64_t ns_to_ticks(uint64_t value)
 113 {
 114     return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
 115 }
 116
 117 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
 118 {
 119     new &= mask;
 120     new |= old & ~mask;
 121     return new;
 122 }
 123
 124 static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
 125 {
 126     return (!(old & mask) && (new & mask));
 127 }
 128
 129 static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
 130 {
 131     return ((old & mask) && !(new & mask));
 132 }
 133
 134 static uint64_t hpet_get_ticks(HPETState *s)
 135 {
 136     return ns_to_ticks(qemu_get_clock(vm_clock) + s->hpet_offset);
 137 }
 138
 139 /*
 140  * calculate diff between comparator value and current ticks
 141  */
 142 static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
 143 {
 144
 145     if (t->config & HPET_TN_32BIT) {
 146         uint32_t diff, cmp;
 147
 148         cmp = (uint32_t)t->cmp;
 149         diff = cmp - (uint32_t)current;
 150         diff = (int32_t)diff > 0 ? diff : (uint32_t)0;
 151         return (uint64_t)diff;
 152     } else {
 153         uint64_t diff, cmp;
 154
 155         cmp = t->cmp;
 156         diff = cmp - current;
 157         diff = (int64_t)diff > 0 ? diff : (uint64_t)0;
 158         return diff;
 159     }
 160 }
 161
 162 static void update_irq(struct HPETTimer *timer)
 163 {
 164     int route;
 165
 166     if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) {
 167         /* if LegacyReplacementRoute bit is set, HPET specification requires
 168          * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
 169          * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
 170          */
 171         route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ;
 172     } else {
 173         route = timer_int_route(timer);
 174     }
 175     if (!timer_enabled(timer) || !hpet_enabled(timer->state)) {
 176         return;
 177     }
 178     qemu_irq_pulse(timer->state->irqs[route]);
 179 }
 180
 181 static void hpet_pre_save(void *opaque)
 182 {
 183     HPETState *s = opaque;
 184
 185     /* save current counter value */
 186     s->hpet_counter = hpet_get_ticks(s);
 187 }
 188
 189 static int hpet_post_load(void *opaque, int version_id)
 190 {
 191     HPETState *s = opaque;
 192
 193     /* Recalculate the offset between the main counter and guest time */
 194     s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
 195     return 0;
 196 }
 197
 198 static const VMStateDescription vmstate_hpet_timer = {
 199     .name = "hpet_timer",
 200     .version_id = 1,
 201     .minimum_version_id = 1,
 202     .minimum_version_id_old = 1,
 203     .fields      = (VMStateField []) {
 204         VMSTATE_UINT8(tn, HPETTimer),
 205         VMSTATE_UINT64(config, HPETTimer),
 206         VMSTATE_UINT64(cmp, HPETTimer),
 207         VMSTATE_UINT64(fsb, HPETTimer),
 208         VMSTATE_UINT64(period, HPETTimer),
 209         VMSTATE_UINT8(wrap_flag, HPETTimer),
 210         VMSTATE_TIMER(qemu_timer, HPETTimer),
 211         VMSTATE_END_OF_LIST()
 212     }
 213 };
 214
 215 static const VMStateDescription vmstate_hpet = {
 216     .name = "hpet",
 217     .version_id = 1,
 218     .minimum_version_id = 1,
 219     .minimum_version_id_old = 1,
 220     .pre_save = hpet_pre_save,
 221     .post_load = hpet_post_load,
 222     .fields      = (VMStateField []) {
 223         VMSTATE_UINT64(config, HPETState),
 224         VMSTATE_UINT64(isr, HPETState),
 225         VMSTATE_UINT64(hpet_counter, HPETState),
 226         VMSTATE_STRUCT_ARRAY(timer, HPETState, HPET_NUM_TIMERS, 0,
 227                              vmstate_hpet_timer, HPETTimer),
 228         VMSTATE_END_OF_LIST()
 229     }
 230 };
 231
 232 /*
 233  * timer expiration callback
 234  */
 235 static void hpet_timer(void *opaque)
 236 {
 237     HPETTimer *t = opaque;
 238     uint64_t diff;
 239
 240     uint64_t period = t->period;
 241     uint64_t cur_tick = hpet_get_ticks(t->state);
 242
 243     if (timer_is_periodic(t) && period != 0) {
 244         if (t->config & HPET_TN_32BIT) {
 245             while (hpet_time_after(cur_tick, t->cmp)) {
 246                 t->cmp = (uint32_t)(t->cmp + t->period);
 247             }
 248         } else {
 249             while (hpet_time_after64(cur_tick, t->cmp)) {
 250                 t->cmp += period;
 251             }
 252         }
 253         diff = hpet_calculate_diff(t, cur_tick);
 254         qemu_mod_timer(t->qemu_timer,
 255                        qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff));
 256     } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 257         if (t->wrap_flag) {
 258             diff = hpet_calculate_diff(t, cur_tick);
 259             qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) +
 260                            (int64_t)ticks_to_ns(diff));
 261             t->wrap_flag = 0;
 262         }
 263     }
 264     update_irq(t);
 265 }
 266
 267 static void hpet_set_timer(HPETTimer *t)
 268 {
 269     uint64_t diff;
 270     uint32_t wrap_diff;  /* how many ticks until we wrap? */
 271     uint64_t cur_tick = hpet_get_ticks(t->state);
 272
 273     /* whenever new timer is being set up, make sure wrap_flag is 0 */
 274     t->wrap_flag = 0;
 275     diff = hpet_calculate_diff(t, cur_tick);
 276
 277     /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
 278      * counter wraps in addition to an interrupt with comparator match.
 279      */
 280     if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 281         wrap_diff = 0xffffffff - (uint32_t)cur_tick;
 282         if (wrap_diff < (uint32_t)diff) {
 283             diff = wrap_diff;
 284             t->wrap_flag = 1;
 285         }
 286     }
 287     qemu_mod_timer(t->qemu_timer,
 288                    qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff));
 289 }
 290
 291 static void hpet_del_timer(HPETTimer *t)
 292 {
 293     qemu_del_timer(t->qemu_timer);
 294 }
 295
 296 #ifdef HPET_DEBUG
 297 static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
 298 {
 299     printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
 300     return 0;
 301 }
 302
 303 static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
 304 {
 305     printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
 306     return 0;
 307 }
 308 #endif
 309
 310 static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
 311 {
 312     HPETState *s = opaque;
 313     uint64_t cur_tick, index;
 314
 315     DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
 316     index = addr;
 317     /*address range of all TN regs*/
 318     if (index >= 0x100 && index <= 0x3ff) {
 319         uint8_t timer_id = (addr - 0x100) / 0x20;
 320         HPETTimer *timer = &s->timer[timer_id];
 321
 322         if (timer_id > HPET_NUM_TIMERS - 1) {
 323             DPRINTF("qemu: timer id out of range\n");
 324             return 0;
 325         }
 326
 327         switch ((addr - 0x100) % 0x20) {
 328         case HPET_TN_CFG:
 329             return timer->config;
 330         case HPET_TN_CFG + 4: // Interrupt capabilities
 331             return timer->config >> 32;
 332         case HPET_TN_CMP: // comparator register
 333             return timer->cmp;
 334         case HPET_TN_CMP + 4:
 335             return timer->cmp >> 32;
 336         case HPET_TN_ROUTE:
 337             return timer->fsb >> 32;
 338         default:
 339             DPRINTF("qemu: invalid hpet_ram_readl\n");
 340             break;
 341         }
 342     } else {
 343         switch (index) {
 344         case HPET_ID:
 345             return s->capability;
 346         case HPET_PERIOD:
 347             return s->capability >> 32;
 348         case HPET_CFG:
 349             return s->config;
 350         case HPET_CFG + 4:
 351             DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
 352             return 0;
 353         case HPET_COUNTER:
 354             if (hpet_enabled(s)) {
 355                 cur_tick = hpet_get_ticks(s);
 356             } else {
 357                 cur_tick = s->hpet_counter;
 358             }
 359             DPRINTF("qemu: reading counter  = %" PRIx64 "\n", cur_tick);
 360             return cur_tick;
 361         case HPET_COUNTER + 4:
 362             if (hpet_enabled(s)) {
 363                 cur_tick = hpet_get_ticks(s);
 364             } else {
 365                 cur_tick = s->hpet_counter;
 366             }
 367             DPRINTF("qemu: reading counter + 4  = %" PRIx64 "\n", cur_tick);
 368             return cur_tick >> 32;
 369         case HPET_STATUS:
 370             return s->isr;
 371         default:
 372             DPRINTF("qemu: invalid hpet_ram_readl\n");
 373             break;
 374         }
 375     }
 376     return 0;
 377 }
 378
 379 #ifdef HPET_DEBUG
 380 static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
 381                             uint32_t value)
 382 {
 383     printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n",
 384            addr, value);
 385 }
 386
 387 static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
 388                             uint32_t value)
 389 {
 390     printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n",
 391            addr, value);
 392 }
 393 #endif
 394
 395 static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
 396                             uint32_t value)
 397 {
 398     int i;
 399     HPETState *s = opaque;
 400     uint64_t old_val, new_val, val, index;
 401
 402     DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
 403     index = addr;
 404     old_val = hpet_ram_readl(opaque, addr);
 405     new_val = value;
 406
 407     /*address range of all TN regs*/
 408     if (index >= 0x100 && index <= 0x3ff) {
 409         uint8_t timer_id = (addr - 0x100) / 0x20;
 410         HPETTimer *timer = &s->timer[timer_id];
 411
 412         DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
 413         if (timer_id > HPET_NUM_TIMERS - 1) {
 414             DPRINTF("qemu: timer id out of range\n");
 415             return;
 416         }
 417         switch ((addr - 0x100) % 0x20) {
 418         case HPET_TN_CFG:
 419             DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
 420             val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
 421             timer->config = (timer->config & 0xffffffff00000000ULL) | val;
 422             if (new_val & HPET_TN_32BIT) {
 423                 timer->cmp = (uint32_t)timer->cmp;
 424                 timer->period = (uint32_t)timer->period;
 425             }
 426             if (new_val & HPET_TN_TYPE_LEVEL) {
 427                 printf("qemu: level-triggered hpet not supported\n");
 428                 exit (-1);
 429             }
 430             if (activating_bit(old_val, new_val, HPET_TN_ENABLE)) {
 431                 hpet_set_timer(timer);
 432             } else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) {
 433                 hpet_del_timer(timer);
 434             }
 435             break;
 436         case HPET_TN_CFG + 4: // Interrupt capabilities
 437             DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
 438             break;
 439         case HPET_TN_CMP: // comparator register
 440             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
 441             if (timer->config & HPET_TN_32BIT) {
 442                 new_val = (uint32_t)new_val;
 443             }
 444             if (!timer_is_periodic(timer)
 445                 || (timer->config & HPET_TN_SETVAL)) {
 446                 timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
 447             }
 448             if (timer_is_periodic(timer)) {
 449                 /*
 450                  * FIXME: Clamp period to reasonable min value?
 451                  * Clamp period to reasonable max value
 452                  */
 453                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 454                 timer->period =
 455                     (timer->period & 0xffffffff00000000ULL) | new_val;
 456             }
 457             timer->config &= ~HPET_TN_SETVAL;
 458             if (hpet_enabled(s)) {
 459                 hpet_set_timer(timer);
 460             }
 461             break;
 462         case HPET_TN_CMP + 4: // comparator register high order
 463             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
 464             if (!timer_is_periodic(timer)
 465                 || (timer->config & HPET_TN_SETVAL)) {
 466                 timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32;
 467             } else {
 468                 /*
 469                  * FIXME: Clamp period to reasonable min value?
 470                  * Clamp period to reasonable max value
 471                  */
 472                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 473                 timer->period =
 474                     (timer->period & 0xffffffffULL) | new_val << 32;
 475                 }
 476                 timer->config &= ~HPET_TN_SETVAL;
 477                 if (hpet_enabled(s)) {
 478                     hpet_set_timer(timer);
 479                 }
 480                 break;
 481         case HPET_TN_ROUTE + 4:
 482             DPRINTF("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
 483             break;
 484         default:
 485             DPRINTF("qemu: invalid hpet_ram_writel\n");
 486             break;
 487         }
 488         return;
 489     } else {
 490         switch (index) {
 491         case HPET_ID:
 492             return;
 493         case HPET_CFG:
 494             val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
 495             s->config = (s->config & 0xffffffff00000000ULL) | val;
 496             if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 497                 /* Enable main counter and interrupt generation. */
 498                 s->hpet_offset =
 499                     ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
 500                 for (i = 0; i < HPET_NUM_TIMERS; i++) {
 501                     if ((&s->timer[i])->cmp != ~0ULL) {
 502                         hpet_set_timer(&s->timer[i]);
 503                     }
 504                 }
 505             } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 506                 /* Halt main counter and disable interrupt generation. */
 507                 s->hpet_counter = hpet_get_ticks(s);
 508                 for (i = 0; i < HPET_NUM_TIMERS; i++) {
 509                     hpet_del_timer(&s->timer[i]);
 510                 }
 511             }
 512             /* i8254 and RTC are disabled when HPET is in legacy mode */
 513             if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 514                 hpet_pit_disable();
 515                 qemu_irq_lower(s->irqs[RTC_ISA_IRQ]);
 516             } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 517                 hpet_pit_enable();
 518                 qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level);
 519             }
 520             break;
 521         case HPET_CFG + 4:
 522             DPRINTF("qemu: invalid HPET_CFG+4 write \n");
 523             break;
 524         case HPET_STATUS:
 525             /* FIXME: need to handle level-triggered interrupts */
 526             break;
 527         case HPET_COUNTER:
 528             if (hpet_enabled(s)) {
 529                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 530             }
 531             s->hpet_counter =
 532                 (s->hpet_counter & 0xffffffff00000000ULL) | value;
 533             DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
 534                     value, s->hpet_counter);
 535             break;
 536         case HPET_COUNTER + 4:
 537             if (hpet_enabled(s)) {
 538                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 539             }
 540             s->hpet_counter =
 541                 (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
 542             DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
 543                     value, s->hpet_counter);
 544             break;
 545         default:
 546             DPRINTF("qemu: invalid hpet_ram_writel\n");
 547             break;
 548         }
 549     }
 550 }
 551
 552 static CPUReadMemoryFunc * const hpet_ram_read[] = {
 553 #ifdef HPET_DEBUG
 554     hpet_ram_readb,
 555     hpet_ram_readw,
 556 #else
 557     NULL,
 558     NULL,
 559 #endif
 560     hpet_ram_readl,
 561 };
 562
 563 static CPUWriteMemoryFunc * const hpet_ram_write[] = {
 564 #ifdef HPET_DEBUG
 565     hpet_ram_writeb,
 566     hpet_ram_writew,
 567 #else
 568     NULL,
 569     NULL,
 570 #endif
 571     hpet_ram_writel,
 572 };
 573
 574 static void hpet_reset(DeviceState *d)
 575 {
 576     HPETState *s = FROM_SYSBUS(HPETState, sysbus_from_qdev(d));
 577     int i;
 578     static int count = 0;
 579
 580     for (i = 0; i < HPET_NUM_TIMERS; i++) {
 581         HPETTimer *timer = &s->timer[i];
 582
 583         hpet_del_timer(timer);
 584         timer->cmp = ~0ULL;
 585         timer->config =  HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
 586         /* advertise availability of ioapic inti2 */
 587         timer->config |=  0x00000004ULL << 32;
 588         timer->period = 0ULL;
 589         timer->wrap_flag = 0;
 590     }
 591
 592     s->hpet_counter = 0ULL;
 593     s->hpet_offset = 0ULL;
 594     /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
 595     s->capability = 0x8086a201ULL;
 596     s->capability |= ((HPET_CLK_PERIOD) << 32);
 597     s->config = 0ULL;
 598     if (count > 0) {
 599         /* we don't enable pit when hpet_reset is first called (by hpet_init)
 600          * because hpet is taking over for pit here. On subsequent invocations,
 601          * hpet_reset is called due to system reset. At this point control must
 602          * be returned to pit until SW reenables hpet.
 603          */
 604         hpet_pit_enable();
 605     }
 606     count = 1;
 607 }
 608
 609 static void hpet_handle_rtc_irq(void *opaque, int n, int level)
 610 {
 611     HPETState *s = FROM_SYSBUS(HPETState, opaque);
 612
 613     s->rtc_irq_level = level;
 614     if (!hpet_in_legacy_mode(s)) {
 615         qemu_set_irq(s->irqs[RTC_ISA_IRQ], level);
 616     }
 617 }
 618
 619 static int hpet_init(SysBusDevice *dev)
 620 {
 621     HPETState *s = FROM_SYSBUS(HPETState, dev);
 622     int i, iomemtype;
 623     HPETTimer *timer;
 624
 625     for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) {
 626         sysbus_init_irq(dev, &s->irqs[i]);
 627     }
 628     for (i = 0; i < HPET_NUM_TIMERS; i++) {
 629         timer = &s->timer[i];
 630         timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer);
 631         timer->tn = i;
 632         timer->state = s;
 633     }
 634
 635     isa_reserve_irq(RTC_ISA_IRQ);
 636     qdev_init_gpio_in(&dev->qdev, hpet_handle_rtc_irq, 1);
 637
 638     /* HPET Area */
 639     iomemtype = cpu_register_io_memory(hpet_ram_read,
 640                                        hpet_ram_write, s);
 641     sysbus_init_mmio(dev, 0x400, iomemtype);
 642     return 0;
 643 }
 644
 645 static SysBusDeviceInfo hpet_device_info = {
 646     .qdev.name    = "hpet",
 647     .qdev.size    = sizeof(HPETState),
 648     .qdev.no_user = 1,
 649     .qdev.vmsd    = &vmstate_hpet,
 650     .qdev.reset   = hpet_reset,
 651     .init         = hpet_init,
 652 };
 653
 654 static void hpet_register_device(void)
 655 {
 656     sysbus_register_withprop(&hpet_device_info);
 657 }
 658
 659 device_init(hpet_register_device)