hw/hppa/lasi.c

   1 /*
   2  * HP-PARISC Lasi chipset emulation.
   3  *
   4  * (C) 2019 by Helge Deller <deller@gmx.de>
   5  *
   6  * This work is licensed under the GNU GPL license version 2 or later.
   7  *
   8  * Documentation available at:
   9  * https://parisc.wiki.kernel.org/images-parisc/7/79/Lasi_ers.pdf
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "qemu/units.h"
  14 #include "qemu/log.h"
  15 #include "qapi/error.h"
  16 #include "cpu.h"
  17 #include "trace.h"
  18 #include "hw/hw.h"
  19 #include "hw/irq.h"
  20 #include "sysemu/sysemu.h"
  21 #include "sysemu/runstate.h"
  22 #include "hppa_sys.h"
  23 #include "hw/net/lasi_82596.h"
  24 #include "hw/char/parallel.h"
  25 #include "hw/char/serial.h"
  26 #include "hw/input/lasips2.h"
  27 #include "exec/address-spaces.h"
  28 #include "migration/vmstate.h"
  29 #include "qom/object.h"
  30
  31 #define TYPE_LASI_CHIP "lasi-chip"
  32
  33 #define LASI_IRR        0x00    /* RO */
  34 #define LASI_IMR        0x04
  35 #define LASI_IPR        0x08
  36 #define LASI_ICR        0x0c
  37 #define LASI_IAR        0x10
  38
  39 #define LASI_PCR        0x0C000 /* LASI Power Control register */
  40 #define LASI_ERRLOG     0x0C004 /* LASI Error Logging register */
  41 #define LASI_VER        0x0C008 /* LASI Version Control register */
  42 #define LASI_IORESET    0x0C00C /* LASI I/O Reset register */
  43 #define LASI_AMR        0x0C010 /* LASI Arbitration Mask register */
  44 #define LASI_IO_CONF    0x7FFFE /* LASI primary configuration register */
  45 #define LASI_IO_CONF2   0x7FFFF /* LASI secondary configuration register */
  46
  47 #define LASI_BIT(x)     (1ul << (x))
  48 #define LASI_IRQ_BITS   (LASI_BIT(5) | LASI_BIT(7) | LASI_BIT(8) | LASI_BIT(9) \
  49             | LASI_BIT(13) | LASI_BIT(14) | LASI_BIT(16) | LASI_BIT(17) \
  50             | LASI_BIT(18) | LASI_BIT(19) | LASI_BIT(20) | LASI_BIT(21) \
  51             | LASI_BIT(26))
  52
  53 #define ICR_BUS_ERROR_BIT  LASI_BIT(8)  /* bit 8 in ICR */
  54 #define ICR_TOC_BIT        LASI_BIT(1)  /* bit 1 in ICR */
  55
  56 typedef struct LasiState LasiState;
  57 DECLARE_INSTANCE_CHECKER(LasiState, LASI_CHIP,
  58                          TYPE_LASI_CHIP)
  59
  60 struct LasiState {
  61     PCIHostState parent_obj;
  62
  63     uint32_t irr;
  64     uint32_t imr;
  65     uint32_t ipr;
  66     uint32_t icr;
  67     uint32_t iar;
  68
  69     uint32_t errlog;
  70     uint32_t amr;
  71     uint32_t rtc;
  72     time_t rtc_ref;
  73
  74     MemoryRegion this_mem;
  75 };
  76
  77 static bool lasi_chip_mem_valid(void *opaque, hwaddr addr,
  78                                 unsigned size, bool is_write,
  79                                 MemTxAttrs attrs)
  80 {
  81     bool ret = false;
  82
  83     switch (addr) {
  84     case LASI_IRR:
  85     case LASI_IMR:
  86     case LASI_IPR:
  87     case LASI_ICR:
  88     case LASI_IAR:
  89
  90     case (LASI_LAN_HPA - LASI_HPA):
  91     case (LASI_LPT_HPA - LASI_HPA):
  92     case (LASI_UART_HPA - LASI_HPA):
  93     case (LASI_RTC_HPA - LASI_HPA):
  94
  95     case LASI_PCR ... LASI_AMR:
  96         ret = true;
  97     }
  98
  99     trace_lasi_chip_mem_valid(addr, ret);
 100     return ret;
 101 }
 102
 103 static MemTxResult lasi_chip_read_with_attrs(void *opaque, hwaddr addr,
 104                                              uint64_t *data, unsigned size,
 105                                              MemTxAttrs attrs)
 106 {
 107     LasiState *s = opaque;
 108     MemTxResult ret = MEMTX_OK;
 109     uint32_t val;
 110
 111     switch (addr) {
 112     case LASI_IRR:
 113         val = s->irr;
 114         break;
 115     case LASI_IMR:
 116         val = s->imr;
 117         break;
 118     case LASI_IPR:
 119         val = s->ipr;
 120         /* Any read to IPR clears the register.  */
 121         s->ipr = 0;
 122         break;
 123     case LASI_ICR:
 124         val = s->icr & ICR_BUS_ERROR_BIT; /* bus_error */
 125         break;
 126     case LASI_IAR:
 127         val = s->iar;
 128         break;
 129
 130     case (LASI_LAN_HPA - LASI_HPA):
 131     case (LASI_LPT_HPA - LASI_HPA):
 132     case (LASI_UART_HPA - LASI_HPA):
 133         val = 0;
 134         break;
 135     case (LASI_RTC_HPA - LASI_HPA):
 136         val = time(NULL);
 137         val += s->rtc_ref;
 138         break;
 139
 140     case LASI_PCR:
 141     case LASI_VER:      /* only version 0 existed. */
 142     case LASI_IORESET:
 143         val = 0;
 144         break;
 145     case LASI_ERRLOG:
 146         val = s->errlog;
 147         break;
 148     case LASI_AMR:
 149         val = s->amr;
 150         break;
 151
 152     default:
 153         /* Controlled by lasi_chip_mem_valid above. */
 154         g_assert_not_reached();
 155     }
 156
 157     trace_lasi_chip_read(addr, val);
 158
 159     *data = val;
 160     return ret;
 161 }
 162
 163 static MemTxResult lasi_chip_write_with_attrs(void *opaque, hwaddr addr,
 164                                               uint64_t val, unsigned size,
 165                                               MemTxAttrs attrs)
 166 {
 167     LasiState *s = opaque;
 168
 169     trace_lasi_chip_write(addr, val);
 170
 171     switch (addr) {
 172     case LASI_IRR:
 173         /* read-only.  */
 174         break;
 175     case LASI_IMR:
 176         s->imr = val;
 177         if (((val & LASI_IRQ_BITS) != val) && (val != 0xffffffff))
 178             qemu_log_mask(LOG_GUEST_ERROR,
 179                 "LASI: tried to set invalid %lx IMR value.\n",
 180                 (unsigned long) val);
 181         break;
 182     case LASI_IPR:
 183         /* Any write to IPR clears the register. */
 184         s->ipr = 0;
 185         break;
 186     case LASI_ICR:
 187         s->icr = val;
 188         /* if (val & ICR_TOC_BIT) issue_toc(); */
 189         break;
 190     case LASI_IAR:
 191         s->iar = val;
 192         break;
 193
 194     case (LASI_LAN_HPA - LASI_HPA):
 195         /* XXX: reset LAN card */
 196         break;
 197     case (LASI_LPT_HPA - LASI_HPA):
 198         /* XXX: reset parallel port */
 199         break;
 200     case (LASI_UART_HPA - LASI_HPA):
 201         /* XXX: reset serial port */
 202         break;
 203     case (LASI_RTC_HPA - LASI_HPA):
 204         s->rtc_ref = val - time(NULL);
 205         break;
 206
 207     case LASI_PCR:
 208         if (val == 0x02) /* immediately power off */
 209             qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 210         break;
 211     case LASI_ERRLOG:
 212         s->errlog = val;
 213         break;
 214     case LASI_VER:
 215         /* read-only.  */
 216         break;
 217     case LASI_IORESET:
 218         break;  /* XXX: TODO: Reset various devices. */
 219     case LASI_AMR:
 220         s->amr = val;
 221         break;
 222
 223     default:
 224         /* Controlled by lasi_chip_mem_valid above. */
 225         g_assert_not_reached();
 226     }
 227     return MEMTX_OK;
 228 }
 229
 230 static const MemoryRegionOps lasi_chip_ops = {
 231     .read_with_attrs = lasi_chip_read_with_attrs,
 232     .write_with_attrs = lasi_chip_write_with_attrs,
 233     .endianness = DEVICE_BIG_ENDIAN,
 234     .valid = {
 235         .min_access_size = 1,
 236         .max_access_size = 4,
 237         .accepts = lasi_chip_mem_valid,
 238     },
 239     .impl = {
 240         .min_access_size = 1,
 241         .max_access_size = 4,
 242     },
 243 };
 244
 245 static const VMStateDescription vmstate_lasi = {
 246     .name = "Lasi",
 247     .version_id = 1,
 248     .minimum_version_id = 1,
 249     .fields = (VMStateField[]) {
 250         VMSTATE_UINT32(irr, LasiState),
 251         VMSTATE_UINT32(imr, LasiState),
 252         VMSTATE_UINT32(ipr, LasiState),
 253         VMSTATE_UINT32(icr, LasiState),
 254         VMSTATE_UINT32(iar, LasiState),
 255         VMSTATE_UINT32(errlog, LasiState),
 256         VMSTATE_UINT32(amr, LasiState),
 257         VMSTATE_END_OF_LIST()
 258     }
 259 };
 260
 261
 262 static void lasi_set_irq(void *opaque, int irq, int level)
 263 {
 264     LasiState *s = opaque;
 265     uint32_t bit = 1u << irq;
 266
 267     if (level) {
 268         s->ipr |= bit;
 269         if (bit & s->imr) {
 270             uint32_t iar = s->iar;
 271             s->irr |= bit;
 272             if ((s->icr & ICR_BUS_ERROR_BIT) == 0) {
 273                 stl_be_phys(&address_space_memory, iar & -32, iar & 31);
 274             }
 275         }
 276     }
 277 }
 278
 279 static int lasi_get_irq(unsigned long hpa)
 280 {
 281     switch (hpa) {
 282     case LASI_HPA:
 283         return 14;
 284     case LASI_UART_HPA:
 285         return 5;
 286     case LASI_LPT_HPA:
 287         return 7;
 288     case LASI_LAN_HPA:
 289         return 8;
 290     case LASI_SCSI_HPA:
 291         return 9;
 292     case LASI_AUDIO_HPA:
 293         return 13;
 294     case LASI_PS2KBD_HPA:
 295     case LASI_PS2MOU_HPA:
 296         return 26;
 297     default:
 298         g_assert_not_reached();
 299     }
 300 }
 301
 302 DeviceState *lasi_init(MemoryRegion *address_space)
 303 {
 304     DeviceState *dev;
 305     LasiState *s;
 306
 307     dev = qdev_new(TYPE_LASI_CHIP);
 308     s = LASI_CHIP(dev);
 309     s->iar = CPU_HPA + 3;
 310
 311     /* Lasi access from main memory.  */
 312     memory_region_init_io(&s->this_mem, OBJECT(s), &lasi_chip_ops,
 313                           s, "lasi", 0x100000);
 314     memory_region_add_subregion(address_space, LASI_HPA, &s->this_mem);
 315
 316     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 317
 318     /* LAN */
 319     if (enable_lasi_lan()) {
 320         qemu_irq lan_irq = qemu_allocate_irq(lasi_set_irq, s,
 321                 lasi_get_irq(LASI_LAN_HPA));
 322         lasi_82596_init(address_space, LASI_LAN_HPA, lan_irq);
 323     }
 324
 325     /* Parallel port */
 326     qemu_irq lpt_irq = qemu_allocate_irq(lasi_set_irq, s,
 327             lasi_get_irq(LASI_LPT_HPA));
 328     parallel_mm_init(address_space, LASI_LPT_HPA + 0x800, 0,
 329                      lpt_irq, parallel_hds[0]);
 330
 331     /* Real time clock (RTC), it's only one 32-bit counter @9000 */
 332
 333     s->rtc = time(NULL);
 334     s->rtc_ref = 0;
 335
 336     if (serial_hd(1)) {
 337         /* Serial port */
 338         qemu_irq serial_irq = qemu_allocate_irq(lasi_set_irq, s,
 339                 lasi_get_irq(LASI_UART_HPA));
 340         serial_mm_init(address_space, LASI_UART_HPA + 0x800, 0,
 341                 serial_irq, 8000000 / 16,
 342                 serial_hd(0), DEVICE_NATIVE_ENDIAN);
 343     }
 344
 345     /* PS/2 Keyboard/Mouse */
 346     qemu_irq ps2kbd_irq = qemu_allocate_irq(lasi_set_irq, s,
 347             lasi_get_irq(LASI_PS2KBD_HPA));
 348     lasips2_init(address_space, LASI_PS2KBD_HPA,  ps2kbd_irq);
 349
 350     return dev;
 351 }
 352
 353 static void lasi_class_init(ObjectClass *klass, void *data)
 354 {
 355     DeviceClass *dc = DEVICE_CLASS(klass);
 356
 357     dc->vmsd = &vmstate_lasi;
 358 }
 359
 360 static const TypeInfo lasi_pcihost_info = {
 361     .name          = TYPE_LASI_CHIP,
 362     .parent        = TYPE_SYS_BUS_DEVICE,
 363     .instance_size = sizeof(LasiState),
 364     .class_init    = lasi_class_init,
 365 };
 366
 367 static void lasi_register_types(void)
 368 {
 369     type_register_static(&lasi_pcihost_info);
 370 }
 371
 372 type_init(lasi_register_types)