hw/i2c/aspeed_i2c.c

   1 /*
   2  * ARM Aspeed I2C controller
   3  *
   4  * Copyright (C) 2016 IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "hw/sysbus.h"
  23 #include "qemu/log.h"
  24 #include "qemu/module.h"
  25 #include "hw/i2c/aspeed_i2c.h"
  26 #include "hw/irq.h"
  27
  28 /* I2C Global Register */
  29
  30 #define I2C_CTRL_STATUS         0x00        /* Device Interrupt Status */
  31 #define I2C_CTRL_ASSIGN         0x08        /* Device Interrupt Target
  32                                                Assignment */
  33
  34 /* I2C Device (Bus) Register */
  35
  36 #define I2CD_FUN_CTRL_REG       0x00       /* I2CD Function Control  */
  37 #define   I2CD_BUFF_SEL_MASK               (0x7 << 20)
  38 #define   I2CD_BUFF_SEL(x)                 (x << 20)
  39 #define   I2CD_M_SDA_LOCK_EN               (0x1 << 16)
  40 #define   I2CD_MULTI_MASTER_DIS            (0x1 << 15)
  41 #define   I2CD_M_SCL_DRIVE_EN              (0x1 << 14)
  42 #define   I2CD_MSB_STS                     (0x1 << 9)
  43 #define   I2CD_SDA_DRIVE_1T_EN             (0x1 << 8)
  44 #define   I2CD_M_SDA_DRIVE_1T_EN           (0x1 << 7)
  45 #define   I2CD_M_HIGH_SPEED_EN             (0x1 << 6)
  46 #define   I2CD_DEF_ADDR_EN                 (0x1 << 5)
  47 #define   I2CD_DEF_ALERT_EN                (0x1 << 4)
  48 #define   I2CD_DEF_ARP_EN                  (0x1 << 3)
  49 #define   I2CD_DEF_GCALL_EN                (0x1 << 2)
  50 #define   I2CD_SLAVE_EN                    (0x1 << 1)
  51 #define   I2CD_MASTER_EN                   (0x1)
  52
  53 #define I2CD_AC_TIMING_REG1     0x04       /* Clock and AC Timing Control #1 */
  54 #define I2CD_AC_TIMING_REG2     0x08       /* Clock and AC Timing Control #1 */
  55 #define I2CD_INTR_CTRL_REG      0x0c       /* I2CD Interrupt Control */
  56 #define I2CD_INTR_STS_REG       0x10       /* I2CD Interrupt Status */
  57
  58 #define   I2CD_INTR_SLAVE_ADDR_MATCH       (0x1 << 31) /* 0: addr1 1: addr2 */
  59 #define   I2CD_INTR_SLAVE_ADDR_RX_PENDING  (0x1 << 30)
  60 /* bits[19-16] Reserved */
  61
  62 /* All bits below are cleared by writing 1 */
  63 #define   I2CD_INTR_SLAVE_INACTIVE_TIMEOUT (0x1 << 15)
  64 #define   I2CD_INTR_SDA_DL_TIMEOUT         (0x1 << 14)
  65 #define   I2CD_INTR_BUS_RECOVER_DONE       (0x1 << 13)
  66 #define   I2CD_INTR_SMBUS_ALERT            (0x1 << 12) /* Bus [0-3] only */
  67 #define   I2CD_INTR_SMBUS_ARP_ADDR         (0x1 << 11) /* Removed */
  68 #define   I2CD_INTR_SMBUS_DEV_ALERT_ADDR   (0x1 << 10) /* Removed */
  69 #define   I2CD_INTR_SMBUS_DEF_ADDR         (0x1 << 9)  /* Removed */
  70 #define   I2CD_INTR_GCALL_ADDR             (0x1 << 8)  /* Removed */
  71 #define   I2CD_INTR_SLAVE_ADDR_RX_MATCH    (0x1 << 7)  /* use RX_DONE */
  72 #define   I2CD_INTR_SCL_TIMEOUT            (0x1 << 6)
  73 #define   I2CD_INTR_ABNORMAL               (0x1 << 5)
  74 #define   I2CD_INTR_NORMAL_STOP            (0x1 << 4)
  75 #define   I2CD_INTR_ARBIT_LOSS             (0x1 << 3)
  76 #define   I2CD_INTR_RX_DONE                (0x1 << 2)
  77 #define   I2CD_INTR_TX_NAK                 (0x1 << 1)
  78 #define   I2CD_INTR_TX_ACK                 (0x1 << 0)
  79
  80 #define I2CD_CMD_REG            0x14       /* I2CD Command/Status */
  81 #define   I2CD_SDA_OE                      (0x1 << 28)
  82 #define   I2CD_SDA_O                       (0x1 << 27)
  83 #define   I2CD_SCL_OE                      (0x1 << 26)
  84 #define   I2CD_SCL_O                       (0x1 << 25)
  85 #define   I2CD_TX_TIMING                   (0x1 << 24)
  86 #define   I2CD_TX_STATUS                   (0x1 << 23)
  87
  88 #define   I2CD_TX_STATE_SHIFT              19 /* Tx State Machine */
  89 #define   I2CD_TX_STATE_MASK                  0xf
  90 #define     I2CD_IDLE                         0x0
  91 #define     I2CD_MACTIVE                      0x8
  92 #define     I2CD_MSTART                       0x9
  93 #define     I2CD_MSTARTR                      0xa
  94 #define     I2CD_MSTOP                        0xb
  95 #define     I2CD_MTXD                         0xc
  96 #define     I2CD_MRXACK                       0xd
  97 #define     I2CD_MRXD                         0xe
  98 #define     I2CD_MTXACK                       0xf
  99 #define     I2CD_SWAIT                        0x1
 100 #define     I2CD_SRXD                         0x4
 101 #define     I2CD_STXACK                       0x5
 102 #define     I2CD_STXD                         0x6
 103 #define     I2CD_SRXACK                       0x7
 104 #define     I2CD_RECOVER                      0x3
 105
 106 #define   I2CD_SCL_LINE_STS                (0x1 << 18)
 107 #define   I2CD_SDA_LINE_STS                (0x1 << 17)
 108 #define   I2CD_BUS_BUSY_STS                (0x1 << 16)
 109 #define   I2CD_SDA_OE_OUT_DIR              (0x1 << 15)
 110 #define   I2CD_SDA_O_OUT_DIR               (0x1 << 14)
 111 #define   I2CD_SCL_OE_OUT_DIR              (0x1 << 13)
 112 #define   I2CD_SCL_O_OUT_DIR               (0x1 << 12)
 113 #define   I2CD_BUS_RECOVER_CMD_EN          (0x1 << 11)
 114 #define   I2CD_S_ALT_EN                    (0x1 << 10)
 115 #define   I2CD_RX_DMA_ENABLE               (0x1 << 9)
 116 #define   I2CD_TX_DMA_ENABLE               (0x1 << 8)
 117
 118 /* Command Bit */
 119 #define   I2CD_M_STOP_CMD                  (0x1 << 5)
 120 #define   I2CD_M_S_RX_CMD_LAST             (0x1 << 4)
 121 #define   I2CD_M_RX_CMD                    (0x1 << 3)
 122 #define   I2CD_S_TX_CMD                    (0x1 << 2)
 123 #define   I2CD_M_TX_CMD                    (0x1 << 1)
 124 #define   I2CD_M_START_CMD                 (0x1)
 125
 126 #define I2CD_DEV_ADDR_REG       0x18       /* Slave Device Address */
 127 #define I2CD_BUF_CTRL_REG       0x1c       /* Pool Buffer Control */
 128 #define I2CD_BYTE_BUF_REG       0x20       /* Transmit/Receive Byte Buffer */
 129 #define   I2CD_BYTE_BUF_TX_SHIFT           0
 130 #define   I2CD_BYTE_BUF_TX_MASK            0xff
 131 #define   I2CD_BYTE_BUF_RX_SHIFT           8
 132 #define   I2CD_BYTE_BUF_RX_MASK            0xff
 133
 134
 135 static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus)
 136 {
 137     return bus->ctrl & I2CD_MASTER_EN;
 138 }
 139
 140 static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus)
 141 {
 142     return bus->ctrl & (I2CD_MASTER_EN | I2CD_SLAVE_EN);
 143 }
 144
 145 static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus)
 146 {
 147     bus->intr_status &= bus->intr_ctrl;
 148     if (bus->intr_status) {
 149         bus->controller->intr_status |= 1 << bus->id;
 150         qemu_irq_raise(bus->controller->irq);
 151     }
 152 }
 153
 154 static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset,
 155                                     unsigned size)
 156 {
 157     AspeedI2CBus *bus = opaque;
 158
 159     switch (offset) {
 160     case I2CD_FUN_CTRL_REG:
 161         return bus->ctrl;
 162     case I2CD_AC_TIMING_REG1:
 163         return bus->timing[0];
 164     case I2CD_AC_TIMING_REG2:
 165         return bus->timing[1];
 166     case I2CD_INTR_CTRL_REG:
 167         return bus->intr_ctrl;
 168     case I2CD_INTR_STS_REG:
 169         return bus->intr_status;
 170     case I2CD_BYTE_BUF_REG:
 171         return bus->buf;
 172     case I2CD_CMD_REG:
 173         return bus->cmd | (i2c_bus_busy(bus->bus) << 16);
 174     default:
 175         qemu_log_mask(LOG_GUEST_ERROR,
 176                       "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset);
 177         return -1;
 178     }
 179 }
 180
 181 static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state)
 182 {
 183     bus->cmd &= ~(I2CD_TX_STATE_MASK << I2CD_TX_STATE_SHIFT);
 184     bus->cmd |= (state & I2CD_TX_STATE_MASK) << I2CD_TX_STATE_SHIFT;
 185 }
 186
 187 static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus)
 188 {
 189     return (bus->cmd >> I2CD_TX_STATE_SHIFT) & I2CD_TX_STATE_MASK;
 190 }
 191
 192 static void aspeed_i2c_handle_rx_cmd(AspeedI2CBus *bus)
 193 {
 194     uint8_t ret;
 195
 196     aspeed_i2c_set_state(bus, I2CD_MRXD);
 197     ret = i2c_recv(bus->bus);
 198     bus->intr_status |= I2CD_INTR_RX_DONE;
 199     bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT;
 200     if (bus->cmd & I2CD_M_S_RX_CMD_LAST) {
 201         i2c_nack(bus->bus);
 202     }
 203     bus->cmd &= ~(I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST);
 204     aspeed_i2c_set_state(bus, I2CD_MACTIVE);
 205 }
 206
 207 /*
 208  * The state machine needs some refinement. It is only used to track
 209  * invalid STOP commands for the moment.
 210  */
 211 static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
 212 {
 213     bus->cmd &= ~0xFFFF;
 214     bus->cmd |= value & 0xFFFF;
 215
 216     if (bus->cmd & I2CD_M_START_CMD) {
 217         uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ?
 218             I2CD_MSTARTR : I2CD_MSTART;
 219
 220         aspeed_i2c_set_state(bus, state);
 221
 222         if (i2c_start_transfer(bus->bus, extract32(bus->buf, 1, 7),
 223                                extract32(bus->buf, 0, 1))) {
 224             bus->intr_status |= I2CD_INTR_TX_NAK;
 225         } else {
 226             bus->intr_status |= I2CD_INTR_TX_ACK;
 227         }
 228
 229         /* START command is also a TX command, as the slave address is
 230          * sent on the bus */
 231         bus->cmd &= ~(I2CD_M_START_CMD | I2CD_M_TX_CMD);
 232
 233         /* No slave found */
 234         if (!i2c_bus_busy(bus->bus)) {
 235             return;
 236         }
 237         aspeed_i2c_set_state(bus, I2CD_MACTIVE);
 238     }
 239
 240     if (bus->cmd & I2CD_M_TX_CMD) {
 241         aspeed_i2c_set_state(bus, I2CD_MTXD);
 242         if (i2c_send(bus->bus, bus->buf)) {
 243             bus->intr_status |= (I2CD_INTR_TX_NAK);
 244             i2c_end_transfer(bus->bus);
 245         } else {
 246             bus->intr_status |= I2CD_INTR_TX_ACK;
 247         }
 248         bus->cmd &= ~I2CD_M_TX_CMD;
 249         aspeed_i2c_set_state(bus, I2CD_MACTIVE);
 250     }
 251
 252     if ((bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) &&
 253         !(bus->intr_status & I2CD_INTR_RX_DONE)) {
 254         aspeed_i2c_handle_rx_cmd(bus);
 255     }
 256
 257     if (bus->cmd & I2CD_M_STOP_CMD) {
 258         if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) {
 259             qemu_log_mask(LOG_GUEST_ERROR, "%s: abnormal stop\n", __func__);
 260             bus->intr_status |= I2CD_INTR_ABNORMAL;
 261         } else {
 262             aspeed_i2c_set_state(bus, I2CD_MSTOP);
 263             i2c_end_transfer(bus->bus);
 264             bus->intr_status |= I2CD_INTR_NORMAL_STOP;
 265         }
 266         bus->cmd &= ~I2CD_M_STOP_CMD;
 267         aspeed_i2c_set_state(bus, I2CD_IDLE);
 268     }
 269 }
 270
 271 static void aspeed_i2c_bus_write(void *opaque, hwaddr offset,
 272                                  uint64_t value, unsigned size)
 273 {
 274     AspeedI2CBus *bus = opaque;
 275     bool handle_rx;
 276
 277     switch (offset) {
 278     case I2CD_FUN_CTRL_REG:
 279         if (value & I2CD_SLAVE_EN) {
 280             qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
 281                           __func__);
 282             break;
 283         }
 284         bus->ctrl = value & 0x0071C3FF;
 285         break;
 286     case I2CD_AC_TIMING_REG1:
 287         bus->timing[0] = value & 0xFFFFF0F;
 288         break;
 289     case I2CD_AC_TIMING_REG2:
 290         bus->timing[1] = value & 0x7;
 291         break;
 292     case I2CD_INTR_CTRL_REG:
 293         bus->intr_ctrl = value & 0x7FFF;
 294         break;
 295     case I2CD_INTR_STS_REG:
 296         handle_rx = (bus->intr_status & I2CD_INTR_RX_DONE) &&
 297                 (value & I2CD_INTR_RX_DONE);
 298         bus->intr_status &= ~(value & 0x7FFF);
 299         if (!bus->intr_status) {
 300             bus->controller->intr_status &= ~(1 << bus->id);
 301             qemu_irq_lower(bus->controller->irq);
 302         }
 303         if (handle_rx && (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST))) {
 304             aspeed_i2c_handle_rx_cmd(bus);
 305             aspeed_i2c_bus_raise_interrupt(bus);
 306         }
 307         break;
 308     case I2CD_DEV_ADDR_REG:
 309         qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
 310                       __func__);
 311         break;
 312     case I2CD_BYTE_BUF_REG:
 313         bus->buf = (value & I2CD_BYTE_BUF_TX_MASK) << I2CD_BYTE_BUF_TX_SHIFT;
 314         break;
 315     case I2CD_CMD_REG:
 316         if (!aspeed_i2c_bus_is_enabled(bus)) {
 317             break;
 318         }
 319
 320         if (!aspeed_i2c_bus_is_master(bus)) {
 321             qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
 322                           __func__);
 323             break;
 324         }
 325
 326         aspeed_i2c_bus_handle_cmd(bus, value);
 327         aspeed_i2c_bus_raise_interrupt(bus);
 328         break;
 329
 330     default:
 331         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
 332                       __func__, offset);
 333     }
 334 }
 335
 336 static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset,
 337                                    unsigned size)
 338 {
 339     AspeedI2CState *s = opaque;
 340
 341     switch (offset) {
 342     case I2C_CTRL_STATUS:
 343         return s->intr_status;
 344     default:
 345         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
 346                       __func__, offset);
 347         break;
 348     }
 349
 350     return -1;
 351 }
 352
 353 static void aspeed_i2c_ctrl_write(void *opaque, hwaddr offset,
 354                                   uint64_t value, unsigned size)
 355 {
 356     switch (offset) {
 357     case I2C_CTRL_STATUS:
 358     default:
 359         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
 360                       __func__, offset);
 361         break;
 362     }
 363 }
 364
 365 static const MemoryRegionOps aspeed_i2c_bus_ops = {
 366     .read = aspeed_i2c_bus_read,
 367     .write = aspeed_i2c_bus_write,
 368     .endianness = DEVICE_LITTLE_ENDIAN,
 369 };
 370
 371 static const MemoryRegionOps aspeed_i2c_ctrl_ops = {
 372     .read = aspeed_i2c_ctrl_read,
 373     .write = aspeed_i2c_ctrl_write,
 374     .endianness = DEVICE_LITTLE_ENDIAN,
 375 };
 376
 377 static const VMStateDescription aspeed_i2c_bus_vmstate = {
 378     .name = TYPE_ASPEED_I2C,
 379     .version_id = 1,
 380     .minimum_version_id = 1,
 381     .fields = (VMStateField[]) {
 382         VMSTATE_UINT8(id, AspeedI2CBus),
 383         VMSTATE_UINT32(ctrl, AspeedI2CBus),
 384         VMSTATE_UINT32_ARRAY(timing, AspeedI2CBus, 2),
 385         VMSTATE_UINT32(intr_ctrl, AspeedI2CBus),
 386         VMSTATE_UINT32(intr_status, AspeedI2CBus),
 387         VMSTATE_UINT32(cmd, AspeedI2CBus),
 388         VMSTATE_UINT32(buf, AspeedI2CBus),
 389         VMSTATE_END_OF_LIST()
 390     }
 391 };
 392
 393 static const VMStateDescription aspeed_i2c_vmstate = {
 394     .name = TYPE_ASPEED_I2C,
 395     .version_id = 1,
 396     .minimum_version_id = 1,
 397     .fields = (VMStateField[]) {
 398         VMSTATE_UINT32(intr_status, AspeedI2CState),
 399         VMSTATE_STRUCT_ARRAY(busses, AspeedI2CState,
 400                              ASPEED_I2C_NR_BUSSES, 1, aspeed_i2c_bus_vmstate,
 401                              AspeedI2CBus),
 402         VMSTATE_END_OF_LIST()
 403     }
 404 };
 405
 406 static void aspeed_i2c_reset(DeviceState *dev)
 407 {
 408     int i;
 409     AspeedI2CState *s = ASPEED_I2C(dev);
 410
 411     s->intr_status = 0;
 412
 413     for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) {
 414         s->busses[i].intr_ctrl = 0;
 415         s->busses[i].intr_status = 0;
 416         s->busses[i].cmd = 0;
 417         s->busses[i].buf = 0;
 418         i2c_end_transfer(s->busses[i].bus);
 419     }
 420 }
 421
 422 /*
 423  * Address Definitions
 424  *
 425  *   0x000 ... 0x03F: Global Register
 426  *   0x040 ... 0x07F: Device 1
 427  *   0x080 ... 0x0BF: Device 2
 428  *   0x0C0 ... 0x0FF: Device 3
 429  *   0x100 ... 0x13F: Device 4
 430  *   0x140 ... 0x17F: Device 5
 431  *   0x180 ... 0x1BF: Device 6
 432  *   0x1C0 ... 0x1FF: Device 7
 433  *   0x200 ... 0x2FF: Buffer Pool  (unused in linux driver)
 434  *   0x300 ... 0x33F: Device 8
 435  *   0x340 ... 0x37F: Device 9
 436  *   0x380 ... 0x3BF: Device 10
 437  *   0x3C0 ... 0x3FF: Device 11
 438  *   0x400 ... 0x43F: Device 12
 439  *   0x440 ... 0x47F: Device 13
 440  *   0x480 ... 0x4BF: Device 14
 441  *   0x800 ... 0xFFF: Buffer Pool  (unused in linux driver)
 442  */
 443 static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
 444 {
 445     int i;
 446     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 447     AspeedI2CState *s = ASPEED_I2C(dev);
 448
 449     sysbus_init_irq(sbd, &s->irq);
 450     memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s,
 451                           "aspeed.i2c", 0x1000);
 452     sysbus_init_mmio(sbd, &s->iomem);
 453
 454     for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) {
 455         char name[16];
 456         int offset = i < 7 ? 1 : 5;
 457         snprintf(name, sizeof(name), "aspeed.i2c.%d", i);
 458         s->busses[i].controller = s;
 459         s->busses[i].id = i;
 460         s->busses[i].bus = i2c_init_bus(dev, name);
 461         memory_region_init_io(&s->busses[i].mr, OBJECT(dev),
 462                               &aspeed_i2c_bus_ops, &s->busses[i], name, 0x40);
 463         memory_region_add_subregion(&s->iomem, 0x40 * (i + offset),
 464                                     &s->busses[i].mr);
 465     }
 466 }
 467
 468 static void aspeed_i2c_class_init(ObjectClass *klass, void *data)
 469 {
 470     DeviceClass *dc = DEVICE_CLASS(klass);
 471
 472     dc->vmsd = &aspeed_i2c_vmstate;
 473     dc->reset = aspeed_i2c_reset;
 474     dc->realize = aspeed_i2c_realize;
 475     dc->desc = "Aspeed I2C Controller";
 476 }
 477
 478 static const TypeInfo aspeed_i2c_info = {
 479     .name          = TYPE_ASPEED_I2C,
 480     .parent        = TYPE_SYS_BUS_DEVICE,
 481     .instance_size = sizeof(AspeedI2CState),
 482     .class_init    = aspeed_i2c_class_init,
 483 };
 484
 485 static void aspeed_i2c_register_types(void)
 486 {
 487     type_register_static(&aspeed_i2c_info);
 488 }
 489
 490 type_init(aspeed_i2c_register_types)
 491
 492
 493 I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr)
 494 {
 495     AspeedI2CState *s = ASPEED_I2C(dev);
 496     I2CBus *bus = NULL;
 497
 498     if (busnr >= 0 && busnr < ASPEED_I2C_NR_BUSSES) {
 499         bus = s->busses[busnr].bus;
 500     }
 501
 502     return bus;
 503 }