2 * i.MX I2C Bus Serial Interface Emulation
4 * Copyright (C) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "hw/i2c/imx_i2c.h"
22 #include "hw/i2c/i2c.h"
25 #define IMX_I2C_DEBUG 0
29 #define DPRINT(fmt, args...) \
30 do { fprintf(stderr, "%s: "fmt, __func__, ## args); } while (0)
32 static const char *imx_i2c_get_regname(unsigned offset
)
50 #define DPRINT(fmt, args...) do { } while (0)
53 static inline bool imx_i2c_is_enabled(IMXI2CState
*s
)
55 return s
->i2cr
& I2CR_IEN
;
58 static inline bool imx_i2c_interrupt_is_enabled(IMXI2CState
*s
)
60 return s
->i2cr
& I2CR_IIEN
;
63 static inline bool imx_i2c_is_master(IMXI2CState
*s
)
65 return s
->i2cr
& I2CR_MSTA
;
68 static void imx_i2c_reset(DeviceState
*dev
)
70 IMXI2CState
*s
= IMX_I2C(dev
);
72 if (s
->address
!= ADDR_RESET
) {
73 i2c_end_transfer(s
->bus
);
76 s
->address
= ADDR_RESET
;
81 s
->i2dr_read
= I2DR_RESET
;
82 s
->i2dr_write
= I2DR_RESET
;
85 static inline void imx_i2c_raise_interrupt(IMXI2CState
*s
)
88 * raise an interrupt if the device is enabled and it is configured
89 * to generate some interrupts.
91 if (imx_i2c_is_enabled(s
) && imx_i2c_interrupt_is_enabled(s
)) {
93 qemu_irq_raise(s
->irq
);
97 static uint64_t imx_i2c_read(void *opaque
, hwaddr offset
,
101 IMXI2CState
*s
= IMX_I2C(opaque
);
117 value
= s
->i2dr_read
;
119 if (imx_i2c_is_master(s
)) {
122 if (s
->address
== ADDR_RESET
) {
123 /* something is wrong as the address is not set */
124 qemu_log_mask(LOG_GUEST_ERROR
, "%s[%s]: Trying to read "
125 "without specifying the slave address\n",
126 TYPE_IMX_I2C
, __func__
);
127 } else if (s
->i2cr
& I2CR_MTX
) {
128 qemu_log_mask(LOG_GUEST_ERROR
, "%s[%s]: Trying to read "
129 "but MTX is set\n", TYPE_IMX_I2C
, __func__
);
131 /* get the next byte */
132 ret
= i2c_recv(s
->bus
);
135 imx_i2c_raise_interrupt(s
);
137 qemu_log_mask(LOG_GUEST_ERROR
, "%s[%s]: read failed "
138 "for device 0x%02x\n", TYPE_IMX_I2C
,
139 __func__
, s
->address
);
146 qemu_log_mask(LOG_UNIMP
, "%s[%s]: slave mode not implemented\n",
147 TYPE_IMX_I2C
, __func__
);
151 qemu_log_mask(LOG_GUEST_ERROR
, "%s[%s]: Bad address at offset %d\n",
152 TYPE_IMX_I2C
, __func__
, s
->address
);
157 DPRINT("read %s [0x%02x] -> 0x%02x\n", imx_i2c_get_regname(offset
),
158 (unsigned int)offset
, value
);
160 return (uint64_t)value
;
163 static void imx_i2c_write(void *opaque
, hwaddr offset
,
164 uint64_t value
, unsigned size
)
166 IMXI2CState
*s
= IMX_I2C(opaque
);
168 DPRINT("write %s [0x%02x] <- 0x%02x\n", imx_i2c_get_regname(offset
),
169 (unsigned int)offset
, (int)value
);
175 s
->iadr
= value
& IADR_MASK
;
176 /* i2c_set_slave_address(s->bus, (uint8_t)s->iadr); */
179 s
->ifdr
= value
& IFDR_MASK
;
182 if (imx_i2c_is_enabled(s
) && ((value
& I2CR_IEN
) == 0)) {
183 /* This is a soft reset. IADR is preserved during soft resets */
184 uint16_t iadr
= s
->iadr
;
185 imx_i2c_reset(DEVICE(s
));
187 } else { /* normal write */
188 s
->i2cr
= value
& I2CR_MASK
;
190 if (imx_i2c_is_master(s
)) {
191 /* set the bus to busy */
193 } else { /* slave mode */
194 /* bus is not busy anymore */
195 s
->i2sr
&= ~I2SR_IBB
;
198 * if we unset the master mode then it ends the ongoing
201 if (s
->address
!= ADDR_RESET
) {
202 i2c_end_transfer(s
->bus
);
203 s
->address
= ADDR_RESET
;
207 if (s
->i2cr
& I2CR_RSTA
) { /* Restart */
208 /* if this is a restart then it ends the ongoing transfer */
209 if (s
->address
!= ADDR_RESET
) {
210 i2c_end_transfer(s
->bus
);
211 s
->address
= ADDR_RESET
;
212 s
->i2cr
&= ~I2CR_RSTA
;
219 * if the user writes 0 to IIF then lower the interrupt and
222 if ((s
->i2sr
& I2SR_IIF
) && !(value
& I2SR_IIF
)) {
223 s
->i2sr
&= ~I2SR_IIF
;
224 qemu_irq_lower(s
->irq
);
228 * if the user writes 0 to IAL, reset the bit
230 if ((s
->i2sr
& I2SR_IAL
) && !(value
& I2SR_IAL
)) {
231 s
->i2sr
&= ~I2SR_IAL
;
236 /* if the device is not enabled, nothing to do */
237 if (!imx_i2c_is_enabled(s
)) {
241 s
->i2dr_write
= value
& I2DR_MASK
;
243 if (imx_i2c_is_master(s
)) {
244 /* If this is the first write cycle then it is the slave addr */
245 if (s
->address
== ADDR_RESET
) {
246 if (i2c_start_transfer(s
->bus
, extract32(s
->i2dr_write
, 1, 7),
247 extract32(s
->i2dr_write
, 0, 1))) {
248 /* if non zero is returned, the adress is not valid */
249 s
->i2sr
|= I2SR_RXAK
;
251 s
->address
= s
->i2dr_write
;
252 s
->i2sr
&= ~I2SR_RXAK
;
253 imx_i2c_raise_interrupt(s
);
255 } else { /* This is a normal data write */
256 if (i2c_send(s
->bus
, s
->i2dr_write
)) {
257 /* if the target return non zero then end the transfer */
258 s
->i2sr
|= I2SR_RXAK
;
259 s
->address
= ADDR_RESET
;
260 i2c_end_transfer(s
->bus
);
262 s
->i2sr
&= ~I2SR_RXAK
;
263 imx_i2c_raise_interrupt(s
);
267 qemu_log_mask(LOG_UNIMP
, "%s[%s]: slave mode not implemented\n",
268 TYPE_IMX_I2C
, __func__
);
272 qemu_log_mask(LOG_GUEST_ERROR
, "%s[%s]: Bad address at offset %d\n",
273 TYPE_IMX_I2C
, __func__
, s
->address
);
278 static const MemoryRegionOps imx_i2c_ops
= {
279 .read
= imx_i2c_read
,
280 .write
= imx_i2c_write
,
281 .valid
.min_access_size
= 1,
282 .valid
.max_access_size
= 2,
283 .endianness
= DEVICE_NATIVE_ENDIAN
,
286 static const VMStateDescription imx_i2c_vmstate
= {
287 .name
= TYPE_IMX_I2C
,
289 .minimum_version_id
= 1,
290 .fields
= (VMStateField
[]) {
291 VMSTATE_UINT16(address
, IMXI2CState
),
292 VMSTATE_UINT16(iadr
, IMXI2CState
),
293 VMSTATE_UINT16(ifdr
, IMXI2CState
),
294 VMSTATE_UINT16(i2cr
, IMXI2CState
),
295 VMSTATE_UINT16(i2sr
, IMXI2CState
),
296 VMSTATE_UINT16(i2dr_read
, IMXI2CState
),
297 VMSTATE_UINT16(i2dr_write
, IMXI2CState
),
298 VMSTATE_END_OF_LIST()
302 static void imx_i2c_realize(DeviceState
*dev
, Error
**errp
)
304 IMXI2CState
*s
= IMX_I2C(dev
);
306 memory_region_init_io(&s
->iomem
, OBJECT(s
), &imx_i2c_ops
, s
, TYPE_IMX_I2C
,
308 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), &s
->iomem
);
309 sysbus_init_irq(SYS_BUS_DEVICE(dev
), &s
->irq
);
310 s
->bus
= i2c_init_bus(DEVICE(dev
), "i2c");
313 static void imx_i2c_class_init(ObjectClass
*klass
, void *data
)
315 DeviceClass
*dc
= DEVICE_CLASS(klass
);
317 dc
->vmsd
= &imx_i2c_vmstate
;
318 dc
->reset
= imx_i2c_reset
;
319 dc
->realize
= imx_i2c_realize
;
322 static const TypeInfo imx_i2c_type_info
= {
323 .name
= TYPE_IMX_I2C
,
324 .parent
= TYPE_SYS_BUS_DEVICE
,
325 .instance_size
= sizeof(IMXI2CState
),
326 .class_init
= imx_i2c_class_init
,
329 static void imx_i2c_register_types(void)
331 type_register_static(&imx_i2c_type_info
);
334 type_init(imx_i2c_register_types
)