2 * Copyright (C) 2014 Freescale Semiconductor, Inc. All rights reserved.
4 * Author: Amit Tomar, <Amit.Tomar@freescale.com>
7 * This file is derived from IMX I2C controller,
8 * by Jean-Christophe DUBOIS .
10 * Thanks to Scott Wood and Alexander Graf for their kind help on this.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License, version 2 or later,
14 * as published by the Free Software Foundation.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "hw/i2c/i2c.h"
24 #include "qemu/module.h"
25 #include "hw/sysbus.h"
26 #include "migration/vmstate.h"
27 #include "qom/object.h"
29 /* #define DEBUG_I2C */
32 #define DPRINTF(fmt, ...) \
33 do { fprintf(stderr, "mpc_i2c[%s]: " fmt, __func__, ## __VA_ARGS__); \
36 #define DPRINTF(fmt, ...) do {} while (0)
39 #define TYPE_MPC_I2C "mpc-i2c"
40 typedef struct MPCI2CState MPCI2CState
;
41 DECLARE_INSTANCE_CHECKER(MPCI2CState
, MPC_I2C
,
44 #define MPC_I2C_ADR 0x00
45 #define MPC_I2C_FDR 0x04
46 #define MPC_I2C_CR 0x08
47 #define MPC_I2C_SR 0x0c
48 #define MPC_I2C_DR 0x10
49 #define MPC_I2C_DFSRR 0x14
51 #define CCR_MEN (1 << 7)
52 #define CCR_MIEN (1 << 6)
53 #define CCR_MSTA (1 << 5)
54 #define CCR_MTX (1 << 4)
55 #define CCR_TXAK (1 << 3)
56 #define CCR_RSTA (1 << 2)
57 #define CCR_BCST (1 << 0)
59 #define CSR_MCF (1 << 7)
60 #define CSR_MAAS (1 << 6)
61 #define CSR_MBB (1 << 5)
62 #define CSR_MAL (1 << 4)
63 #define CSR_SRW (1 << 2)
64 #define CSR_MIF (1 << 1)
65 #define CSR_RXAK (1 << 0)
67 #define CADR_MASK 0xFE
68 #define CFDR_MASK 0x3F
73 #define CYCLE_RESET 0xFF
76 SysBusDevice parent_obj
;
91 static bool mpc_i2c_is_enabled(MPCI2CState
*s
)
93 return s
->cr
& CCR_MEN
;
96 static bool mpc_i2c_is_master(MPCI2CState
*s
)
98 return s
->cr
& CCR_MSTA
;
101 static bool mpc_i2c_direction_is_tx(MPCI2CState
*s
)
103 return s
->cr
& CCR_MTX
;
106 static bool mpc_i2c_irq_pending(MPCI2CState
*s
)
108 return s
->sr
& CSR_MIF
;
111 static bool mpc_i2c_irq_is_enabled(MPCI2CState
*s
)
113 return s
->cr
& CCR_MIEN
;
116 static void mpc_i2c_reset(DeviceState
*dev
)
118 MPCI2CState
*i2c
= MPC_I2C(dev
);
128 static void mpc_i2c_irq(MPCI2CState
*s
)
130 bool irq_active
= false;
132 if (mpc_i2c_is_enabled(s
) && mpc_i2c_irq_is_enabled(s
)
133 && mpc_i2c_irq_pending(s
)) {
138 qemu_irq_raise(s
->irq
);
140 qemu_irq_lower(s
->irq
);
144 static void mpc_i2c_soft_reset(MPCI2CState
*s
)
146 /* This is a soft reset. ADR is preserved during soft resets */
147 uint8_t adr
= s
->adr
;
148 mpc_i2c_reset(DEVICE(s
));
152 static void mpc_i2c_address_send(MPCI2CState
*s
)
154 /* if returns non zero slave address is not right */
155 if (i2c_start_transfer(s
->bus
, s
->dr
>> 1, s
->dr
& (0x01))) {
160 s
->sr
|= CSR_MCF
; /* Set after Byte Transfer is completed */
161 s
->sr
|= CSR_MIF
; /* Set after Byte Transfer is completed */
166 static void mpc_i2c_data_send(MPCI2CState
*s
)
168 if (i2c_send(s
->bus
, s
->dr
)) {
169 /* End of transfer */
171 i2c_end_transfer(s
->bus
);
174 s
->sr
|= CSR_MCF
; /* Set after Byte Transfer is completed */
175 s
->sr
|= CSR_MIF
; /* Set after Byte Transfer is completed */
180 static void mpc_i2c_data_recive(MPCI2CState
*s
)
183 /* get the next byte */
184 ret
= i2c_recv(s
->bus
);
186 s
->sr
|= CSR_MCF
; /* Set after Byte Transfer is completed */
187 s
->sr
|= CSR_MIF
; /* Set after Byte Transfer is completed */
190 DPRINTF("read failed for device");
196 static uint64_t mpc_i2c_read(void *opaque
, hwaddr addr
, unsigned size
)
198 MPCI2CState
*s
= opaque
;
216 if (mpc_i2c_is_master(s
)) { /* master mode */
217 if (mpc_i2c_direction_is_tx(s
)) {
218 DPRINTF("MTX is set not in recv mode\n");
220 mpc_i2c_data_recive(s
);
226 DPRINTF("ERROR: Bad read addr 0x%x\n", (unsigned int)addr
);
230 DPRINTF("%s: addr " TARGET_FMT_plx
" %02" PRIx32
"\n", __func__
,
232 return (uint64_t)value
;
235 static void mpc_i2c_write(void *opaque
, hwaddr addr
,
236 uint64_t value
, unsigned size
)
238 MPCI2CState
*s
= opaque
;
240 DPRINTF("%s: addr " TARGET_FMT_plx
" val %08" PRIx64
"\n", __func__
,
244 s
->adr
= value
& CADR_MASK
;
247 s
->fdr
= value
& CFDR_MASK
;
250 if (mpc_i2c_is_enabled(s
) && ((value
& CCR_MEN
) == 0)) {
251 mpc_i2c_soft_reset(s
);
255 s
->cr
= value
& CCR_MASK
;
256 if (mpc_i2c_is_master(s
)) { /* master mode */
257 /* set the bus to busy after master is set as per RM */
260 /* bus is not busy anymore */
262 /* Reset the address for fresh write/read cycle */
263 if (s
->address
!= CYCLE_RESET
) {
264 i2c_end_transfer(s
->bus
);
265 s
->address
= CYCLE_RESET
;
268 /* For restart end the onging transfer */
269 if (s
->cr
& CCR_RSTA
) {
270 if (s
->address
!= CYCLE_RESET
) {
271 s
->address
= CYCLE_RESET
;
272 i2c_end_transfer(s
->bus
);
278 s
->sr
= value
& CSR_MASK
;
279 /* Lower the interrupt */
280 if (!(s
->sr
& CSR_MIF
) || !(s
->sr
& CSR_MAL
)) {
285 /* if the device is not enabled, nothing to do */
286 if (!mpc_i2c_is_enabled(s
)) {
289 s
->dr
= value
& CDR_MASK
;
290 if (mpc_i2c_is_master(s
)) { /* master mode */
291 if (s
->address
== CYCLE_RESET
) {
292 mpc_i2c_address_send(s
);
294 mpc_i2c_data_send(s
);
302 DPRINTF("ERROR: Bad write addr 0x%x\n", (unsigned int)addr
);
307 static const MemoryRegionOps i2c_ops
= {
308 .read
= mpc_i2c_read
,
309 .write
= mpc_i2c_write
,
310 .valid
.max_access_size
= 1,
311 .endianness
= DEVICE_NATIVE_ENDIAN
,
314 static const VMStateDescription mpc_i2c_vmstate
= {
315 .name
= TYPE_MPC_I2C
,
317 .minimum_version_id
= 1,
318 .fields
= (VMStateField
[]) {
319 VMSTATE_UINT8(address
, MPCI2CState
),
320 VMSTATE_UINT8(adr
, MPCI2CState
),
321 VMSTATE_UINT8(fdr
, MPCI2CState
),
322 VMSTATE_UINT8(cr
, MPCI2CState
),
323 VMSTATE_UINT8(sr
, MPCI2CState
),
324 VMSTATE_UINT8(dr
, MPCI2CState
),
325 VMSTATE_UINT8(dfssr
, MPCI2CState
),
326 VMSTATE_END_OF_LIST()
330 static void mpc_i2c_realize(DeviceState
*dev
, Error
**errp
)
332 MPCI2CState
*i2c
= MPC_I2C(dev
);
333 sysbus_init_irq(SYS_BUS_DEVICE(dev
), &i2c
->irq
);
334 memory_region_init_io(&i2c
->iomem
, OBJECT(i2c
), &i2c_ops
, i2c
,
336 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), &i2c
->iomem
);
337 i2c
->bus
= i2c_init_bus(dev
, "i2c");
340 static void mpc_i2c_class_init(ObjectClass
*klass
, void *data
)
342 DeviceClass
*dc
= DEVICE_CLASS(klass
);
344 dc
->vmsd
= &mpc_i2c_vmstate
;
345 dc
->reset
= mpc_i2c_reset
;
346 dc
->realize
= mpc_i2c_realize
;
347 dc
->desc
= "MPC I2C Controller";
350 static const TypeInfo mpc_i2c_type_info
= {
351 .name
= TYPE_MPC_I2C
,
352 .parent
= TYPE_SYS_BUS_DEVICE
,
353 .instance_size
= sizeof(MPCI2CState
),
354 .class_init
= mpc_i2c_class_init
,
357 static void mpc_i2c_register_types(void)
359 type_register_static(&mpc_i2c_type_info
);
362 type_init(mpc_i2c_register_types
)