hw/i2c/pm_smbus.c

   1 /*
   2  * PC SMBus implementation
   3  * splitted from acpi.c
   4  *
   5  * Copyright (c) 2006 Fabrice Bellard
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License version 2 as published by the Free Software Foundation.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/>.
  19  */
  20 #include "qemu/osdep.h"
  21 #include "hw/hw.h"
  22 #include "hw/i2c/pm_smbus.h"
  23 #include "hw/i2c/smbus.h"
  24
  25 #define SMBHSTSTS       0x00
  26 #define SMBHSTCNT       0x02
  27 #define SMBHSTCMD       0x03
  28 #define SMBHSTADD       0x04
  29 #define SMBHSTDAT0      0x05
  30 #define SMBHSTDAT1      0x06
  31 #define SMBBLKDAT       0x07
  32
  33 #define STS_HOST_BUSY   (1 << 0)
  34 #define STS_INTR        (1 << 1)
  35 #define STS_DEV_ERR     (1 << 2)
  36 #define STS_BUS_ERR     (1 << 3)
  37 #define STS_FAILED      (1 << 4)
  38 #define STS_SMBALERT    (1 << 5)
  39 #define STS_INUSE_STS   (1 << 6)
  40 #define STS_BYTE_DONE   (1 << 7)
  41 /* Signs of successfully transaction end :
  42 *  ByteDoneStatus = 1 (STS_BYTE_DONE) and INTR = 1 (STS_INTR )
  43 */
  44
  45 #define CTL_INTREN      (1 << 0)
  46 #define CTL_KILL        (1 << 1)
  47 #define CTL_LAST_BYTE   (1 << 5)
  48 #define CTL_START       (1 << 6)
  49 #define CTL_PEC_EN      (1 << 7)
  50 #define CTL_RETURN_MASK 0x1f
  51
  52 #define PROT_QUICK          0
  53 #define PROT_BYTE           1
  54 #define PROT_BYTE_DATA      2
  55 #define PROT_WORD_DATA      3
  56 #define PROT_PROC_CALL      4
  57 #define PROT_BLOCK_DATA     5
  58 #define PROT_I2C_BLOCK_DATA 6
  59
  60 /*#define DEBUG*/
  61
  62 #ifdef DEBUG
  63 # define SMBUS_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  64 #else
  65 # define SMBUS_DPRINTF(format, ...)     do { } while (0)
  66 #endif
  67
  68
  69 static void smb_transaction(PMSMBus *s)
  70 {
  71     uint8_t prot = (s->smb_ctl >> 2) & 0x07;
  72     uint8_t read = s->smb_addr & 0x01;
  73     uint8_t cmd = s->smb_cmd;
  74     uint8_t addr = s->smb_addr >> 1;
  75     I2CBus *bus = s->smbus;
  76     int ret;
  77
  78     assert(s->smb_stat & STS_HOST_BUSY);
  79     s->smb_stat &= ~STS_HOST_BUSY;
  80
  81     SMBUS_DPRINTF("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
  82     /* Transaction isn't exec if STS_DEV_ERR bit set */
  83     if ((s->smb_stat & STS_DEV_ERR) != 0)  {
  84         goto error;
  85     }
  86
  87     switch(prot) {
  88     case PROT_QUICK:
  89         ret = smbus_quick_command(bus, addr, read);
  90         goto done;
  91     case PROT_BYTE:
  92         if (read) {
  93             ret = smbus_receive_byte(bus, addr);
  94             goto data8;
  95         } else {
  96             ret = smbus_send_byte(bus, addr, cmd);
  97             goto done;
  98         }
  99     case PROT_BYTE_DATA:
 100         if (read) {
 101             ret = smbus_read_byte(bus, addr, cmd);
 102             goto data8;
 103         } else {
 104             ret = smbus_write_byte(bus, addr, cmd, s->smb_data0);
 105             goto done;
 106         }
 107         break;
 108     case PROT_WORD_DATA:
 109         if (read) {
 110             ret = smbus_read_word(bus, addr, cmd);
 111             goto data16;
 112         } else {
 113             ret = smbus_write_word(bus, addr, cmd,
 114                                    (s->smb_data1 << 8) | s->smb_data0);
 115             goto done;
 116         }
 117         break;
 118     case PROT_I2C_BLOCK_DATA:
 119         if (read) {
 120             int xfersize = s->smb_data0;
 121             if (xfersize > sizeof(s->smb_data)) {
 122                 xfersize = sizeof(s->smb_data);
 123             }
 124             ret = smbus_read_block(bus, addr, s->smb_data1, s->smb_data,
 125                                    xfersize, false, true);
 126             goto data8;
 127         } else {
 128             ret = smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0,
 129                                     false);
 130             goto done;
 131         }
 132         break;
 133     default:
 134         goto error;
 135     }
 136     abort();
 137
 138 data16:
 139     if (ret < 0) {
 140         goto error;
 141     }
 142     s->smb_data1 = ret >> 8;
 143 data8:
 144     if (ret < 0) {
 145         goto error;
 146     }
 147     s->smb_data0 = ret;
 148 done:
 149     if (ret < 0) {
 150         goto error;
 151     }
 152     s->smb_stat |= STS_BYTE_DONE | STS_INTR;
 153     return;
 154
 155 error:
 156     s->smb_stat |= STS_DEV_ERR;
 157     return;
 158
 159 }
 160
 161 static void smb_transaction_start(PMSMBus *s)
 162 {
 163     /* Do not execute immediately the command ; it will be
 164      * executed when guest will read SMB_STAT register */
 165     s->smb_stat |= STS_HOST_BUSY;
 166 }
 167
 168 static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val,
 169                               unsigned width)
 170 {
 171     PMSMBus *s = opaque;
 172
 173     SMBUS_DPRINTF("SMB writeb port=0x%04" HWADDR_PRIx
 174                   " val=0x%02" PRIx64 "\n", addr, val);
 175     switch(addr) {
 176     case SMBHSTSTS:
 177         s->smb_stat = (~(val & 0xff)) & s->smb_stat;
 178         s->smb_index = 0;
 179         break;
 180     case SMBHSTCNT:
 181         s->smb_ctl = val;
 182         if (s->smb_ctl & CTL_START) {
 183             smb_transaction_start(s);
 184         }
 185         break;
 186     case SMBHSTCMD:
 187         s->smb_cmd = val;
 188         break;
 189     case SMBHSTADD:
 190         s->smb_addr = val;
 191         break;
 192     case SMBHSTDAT0:
 193         s->smb_data0 = val;
 194         break;
 195     case SMBHSTDAT1:
 196         s->smb_data1 = val;
 197         break;
 198     case SMBBLKDAT:
 199         s->smb_data[s->smb_index++] = val;
 200         if (s->smb_index > 31)
 201             s->smb_index = 0;
 202         break;
 203     default:
 204         break;
 205     }
 206 }
 207
 208 static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width)
 209 {
 210     PMSMBus *s = opaque;
 211     uint32_t val;
 212
 213     switch(addr) {
 214     case SMBHSTSTS:
 215         val = s->smb_stat;
 216         if (s->smb_stat & STS_HOST_BUSY) {
 217             /* execute command now */
 218             smb_transaction(s);
 219         }
 220         break;
 221     case SMBHSTCNT:
 222         s->smb_index = 0;
 223         val = s->smb_ctl & CTL_RETURN_MASK;
 224         break;
 225     case SMBHSTCMD:
 226         val = s->smb_cmd;
 227         break;
 228     case SMBHSTADD:
 229         val = s->smb_addr;
 230         break;
 231     case SMBHSTDAT0:
 232         val = s->smb_data0;
 233         break;
 234     case SMBHSTDAT1:
 235         val = s->smb_data1;
 236         break;
 237     case SMBBLKDAT:
 238         val = s->smb_data[s->smb_index++];
 239         if (s->smb_index > 31)
 240             s->smb_index = 0;
 241         break;
 242     default:
 243         val = 0;
 244         break;
 245     }
 246     SMBUS_DPRINTF("SMB readb port=0x%04" HWADDR_PRIx " val=0x%02x\n",
 247                   addr, val);
 248
 249     return val;
 250 }
 251
 252 static const MemoryRegionOps pm_smbus_ops = {
 253     .read = smb_ioport_readb,
 254     .write = smb_ioport_writeb,
 255     .valid.min_access_size = 1,
 256     .valid.max_access_size = 1,
 257     .endianness = DEVICE_LITTLE_ENDIAN,
 258 };
 259
 260 void pm_smbus_init(DeviceState *parent, PMSMBus *smb)
 261 {
 262     smb->smbus = i2c_init_bus(parent, "i2c");
 263     memory_region_init_io(&smb->io, OBJECT(parent), &pm_smbus_ops, smb,
 264                           "pm-smbus", 64);
 265 }