2 * QEMU SMBus EEPROM device
4 * Copyright (c) 2007 Arastra, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qapi/error.h"
28 #include "hw/boards.h"
29 #include "hw/i2c/i2c.h"
30 #include "hw/i2c/smbus_slave.h"
31 #include "hw/qdev-properties.h"
32 #include "migration/vmstate.h"
33 #include "hw/i2c/smbus_eeprom.h"
34 #include "qom/object.h"
38 #define TYPE_SMBUS_EEPROM "smbus-eeprom"
40 typedef struct SMBusEEPROMDevice SMBusEEPROMDevice
;
41 DECLARE_INSTANCE_CHECKER(SMBusEEPROMDevice
, SMBUS_EEPROM
,
44 #define SMBUS_EEPROM_SIZE 256
46 struct SMBusEEPROMDevice
{
48 uint8_t data
[SMBUS_EEPROM_SIZE
];
54 static uint8_t eeprom_receive_byte(SMBusDevice
*dev
)
56 SMBusEEPROMDevice
*eeprom
= SMBUS_EEPROM(dev
);
57 uint8_t *data
= eeprom
->data
;
58 uint8_t val
= data
[eeprom
->offset
++];
60 eeprom
->accessed
= true;
62 printf("eeprom_receive_byte: addr=0x%02x val=0x%02x\n",
63 dev
->i2c
.address
, val
);
68 static int eeprom_write_data(SMBusDevice
*dev
, uint8_t *buf
, uint8_t len
)
70 SMBusEEPROMDevice
*eeprom
= SMBUS_EEPROM(dev
);
71 uint8_t *data
= eeprom
->data
;
73 eeprom
->accessed
= true;
75 printf("eeprom_write_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n",
76 dev
->i2c
.address
, buf
[0], buf
[1]);
78 /* len is guaranteed to be > 0 */
79 eeprom
->offset
= buf
[0];
83 for (; len
> 0; len
--) {
84 data
[eeprom
->offset
] = *buf
++;
85 eeprom
->offset
= (eeprom
->offset
+ 1) % SMBUS_EEPROM_SIZE
;
91 static bool smbus_eeprom_vmstate_needed(void *opaque
)
93 MachineClass
*mc
= MACHINE_GET_CLASS(qdev_get_machine());
94 SMBusEEPROMDevice
*eeprom
= opaque
;
96 return (eeprom
->accessed
|| smbus_vmstate_needed(&eeprom
->smbusdev
)) &&
97 !mc
->smbus_no_migration_support
;
100 static const VMStateDescription vmstate_smbus_eeprom
= {
101 .name
= "smbus-eeprom",
103 .minimum_version_id
= 1,
104 .needed
= smbus_eeprom_vmstate_needed
,
105 .fields
= (VMStateField
[]) {
106 VMSTATE_SMBUS_DEVICE(smbusdev
, SMBusEEPROMDevice
),
107 VMSTATE_UINT8_ARRAY(data
, SMBusEEPROMDevice
, SMBUS_EEPROM_SIZE
),
108 VMSTATE_UINT8(offset
, SMBusEEPROMDevice
),
109 VMSTATE_BOOL(accessed
, SMBusEEPROMDevice
),
110 VMSTATE_END_OF_LIST()
115 * Reset the EEPROM contents to the initial state on a reset. This
116 * isn't really how an EEPROM works, of course, but the general
117 * principle of QEMU is to restore function on reset to what it would
118 * be if QEMU was stopped and started.
120 * The proper thing to do would be to have a backing blockdev to hold
121 * the contents and restore that on startup, and not do this on reset.
122 * But until that time, act as if we had been stopped and restarted.
124 static void smbus_eeprom_reset(DeviceState
*dev
)
126 SMBusEEPROMDevice
*eeprom
= SMBUS_EEPROM(dev
);
128 memcpy(eeprom
->data
, eeprom
->init_data
, SMBUS_EEPROM_SIZE
);
132 static void smbus_eeprom_realize(DeviceState
*dev
, Error
**errp
)
134 SMBusEEPROMDevice
*eeprom
= SMBUS_EEPROM(dev
);
136 smbus_eeprom_reset(dev
);
137 if (eeprom
->init_data
== NULL
) {
138 error_setg(errp
, "init_data cannot be NULL");
142 static void smbus_eeprom_class_initfn(ObjectClass
*klass
, void *data
)
144 DeviceClass
*dc
= DEVICE_CLASS(klass
);
145 SMBusDeviceClass
*sc
= SMBUS_DEVICE_CLASS(klass
);
147 dc
->realize
= smbus_eeprom_realize
;
148 dc
->reset
= smbus_eeprom_reset
;
149 sc
->receive_byte
= eeprom_receive_byte
;
150 sc
->write_data
= eeprom_write_data
;
151 dc
->vmsd
= &vmstate_smbus_eeprom
;
152 /* Reason: init_data */
153 dc
->user_creatable
= false;
156 static const TypeInfo smbus_eeprom_info
= {
157 .name
= TYPE_SMBUS_EEPROM
,
158 .parent
= TYPE_SMBUS_DEVICE
,
159 .instance_size
= sizeof(SMBusEEPROMDevice
),
160 .class_init
= smbus_eeprom_class_initfn
,
163 static void smbus_eeprom_register_types(void)
165 type_register_static(&smbus_eeprom_info
);
168 type_init(smbus_eeprom_register_types
)
170 void smbus_eeprom_init_one(I2CBus
*smbus
, uint8_t address
, uint8_t *eeprom_buf
)
174 dev
= qdev_new(TYPE_SMBUS_EEPROM
);
175 qdev_prop_set_uint8(dev
, "address", address
);
176 /* FIXME: use an array of byte or block backend property? */
177 SMBUS_EEPROM(dev
)->init_data
= eeprom_buf
;
178 qdev_realize_and_unref(dev
, (BusState
*)smbus
, &error_fatal
);
181 void smbus_eeprom_init(I2CBus
*smbus
, int nb_eeprom
,
182 const uint8_t *eeprom_spd
, int eeprom_spd_size
)
185 /* XXX: make this persistent */
187 assert(nb_eeprom
<= 8);
188 uint8_t *eeprom_buf
= g_malloc0(8 * SMBUS_EEPROM_SIZE
);
189 if (eeprom_spd_size
> 0) {
190 memcpy(eeprom_buf
, eeprom_spd
, eeprom_spd_size
);
193 for (i
= 0; i
< nb_eeprom
; i
++) {
194 smbus_eeprom_init_one(smbus
, 0x50 + i
,
195 eeprom_buf
+ (i
* SMBUS_EEPROM_SIZE
));
199 /* Generate SDRAM SPD EEPROM data describing a module of type and size */
200 uint8_t *spd_data_generate(enum sdram_type type
, ram_addr_t ram_size
)
206 int min_log2
, max_log2
, sz_log2
;
223 g_assert_not_reached();
225 size
= ram_size
>> 20; /* work in terms of megabytes */
226 sz_log2
= 31 - clz32(size
);
227 size
= 1U << sz_log2
;
228 assert(ram_size
== size
* MiB
);
229 assert(sz_log2
>= min_log2
);
232 while (sz_log2
> max_log2
&& nbanks
< 8) {
237 assert(size
== (1ULL << sz_log2
) * nbanks
);
239 /* split to 2 banks if possible to avoid a bug in MIPS Malta firmware */
240 if (nbanks
== 1 && sz_log2
> min_log2
) {
245 density
= 1ULL << (sz_log2
- 2);
248 density
= (density
& 0xe0) | (density
>> 8 & 0x1f);
251 density
= (density
& 0xf8) | (density
>> 8 & 0x07);
259 spd
= g_malloc0(256);
260 spd
[0] = 128; /* data bytes in EEPROM */
261 spd
[1] = 8; /* log2 size of EEPROM */
263 spd
[3] = 13; /* row address bits */
264 spd
[4] = 10; /* column address bits */
265 spd
[5] = (type
== DDR2
? nbanks
- 1 : nbanks
);
266 spd
[6] = 64; /* module data width */
267 /* reserved / data width high */
268 spd
[8] = 4; /* interface voltage level */
269 spd
[9] = 0x25; /* highest CAS latency */
270 spd
[10] = 1; /* access time */
271 /* DIMM configuration 0 = non-ECC */
272 spd
[12] = 0x82; /* refresh requirements */
273 spd
[13] = 8; /* primary SDRAM width */
274 /* ECC SDRAM width */
275 spd
[15] = (type
== DDR2
? 0 : 1); /* reserved / delay for random col rd */
276 spd
[16] = 12; /* burst lengths supported */
277 spd
[17] = 4; /* banks per SDRAM device */
278 spd
[18] = 12; /* ~CAS latencies supported */
279 spd
[19] = (type
== DDR2
? 0 : 1); /* reserved / ~CS latencies supported */
280 spd
[20] = 2; /* DIMM type / ~WE latencies */
281 /* module features */
282 /* memory chip features */
283 spd
[23] = 0x12; /* clock cycle time @ medium CAS latency */
284 /* data access time */
285 /* clock cycle time @ short CAS latency */
286 /* data access time */
287 spd
[27] = 20; /* min. row precharge time */
288 spd
[28] = 15; /* min. row active row delay */
289 spd
[29] = 20; /* min. ~RAS to ~CAS delay */
290 spd
[30] = 45; /* min. active to precharge time */
292 spd
[32] = 20; /* addr/cmd setup time */
293 spd
[33] = 8; /* addr/cmd hold time */
294 spd
[34] = 20; /* data input setup time */
295 spd
[35] = 8; /* data input hold time */
298 for (i
= 0; i
< 63; i
++) {