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Merge remote-tracking branch 'remotes/rth/tags/pull-sparc-20161031-2' into staging
[mirror_qemu.git] / hw / i386 / acpi-build.c
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "acpi-build.h"
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
30 #include "qom/cpu.h"
31 #include "hw/i386/pc.h"
32 #include "target-i386/cpu.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/acpi/cpu.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "sysemu/tpm_backend.h"
46 #include "hw/timer/mc146818rtc_regs.h"
47 #include "sysemu/numa.h"
48
49 /* Supported chipsets: */
50 #include "hw/acpi/piix4.h"
51 #include "hw/acpi/pcihp.h"
52 #include "hw/i386/ich9.h"
53 #include "hw/pci/pci_bus.h"
54 #include "hw/pci-host/q35.h"
55 #include "hw/i386/x86-iommu.h"
56
57 #include "hw/acpi/aml-build.h"
58
59 #include "qapi/qmp/qint.h"
60 #include "qom/qom-qobject.h"
61 #include "hw/i386/amd_iommu.h"
62 #include "hw/i386/intel_iommu.h"
63
64 #include "hw/acpi/ipmi.h"
65
66 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
67 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
68 * a little bit, there should be plenty of free space since the DSDT
69 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
70 */
71 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
72 #define ACPI_BUILD_ALIGN_SIZE 0x1000
73
74 #define ACPI_BUILD_TABLE_SIZE 0x20000
75
76 /* #define DEBUG_ACPI_BUILD */
77 #ifdef DEBUG_ACPI_BUILD
78 #define ACPI_BUILD_DPRINTF(fmt, ...) \
79 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
80 #else
81 #define ACPI_BUILD_DPRINTF(fmt, ...)
82 #endif
83
84 /* Default IOAPIC ID */
85 #define ACPI_BUILD_IOAPIC_ID 0x0
86
87 typedef struct AcpiMcfgInfo {
88 uint64_t mcfg_base;
89 uint32_t mcfg_size;
90 } AcpiMcfgInfo;
91
92 typedef struct AcpiPmInfo {
93 bool s3_disabled;
94 bool s4_disabled;
95 bool pcihp_bridge_en;
96 uint8_t s4_val;
97 uint16_t sci_int;
98 uint8_t acpi_enable_cmd;
99 uint8_t acpi_disable_cmd;
100 uint32_t gpe0_blk;
101 uint32_t gpe0_blk_len;
102 uint32_t io_base;
103 uint16_t cpu_hp_io_base;
104 uint16_t mem_hp_io_base;
105 uint16_t mem_hp_io_len;
106 uint16_t pcihp_io_base;
107 uint16_t pcihp_io_len;
108 } AcpiPmInfo;
109
110 typedef struct AcpiMiscInfo {
111 bool is_piix4;
112 bool has_hpet;
113 TPMVersion tpm_version;
114 const unsigned char *dsdt_code;
115 unsigned dsdt_size;
116 uint16_t pvpanic_port;
117 uint16_t applesmc_io_base;
118 } AcpiMiscInfo;
119
120 typedef struct AcpiBuildPciBusHotplugState {
121 GArray *device_table;
122 GArray *notify_table;
123 struct AcpiBuildPciBusHotplugState *parent;
124 bool pcihp_bridge_en;
125 } AcpiBuildPciBusHotplugState;
126
127 static void acpi_get_pm_info(AcpiPmInfo *pm)
128 {
129 Object *piix = piix4_pm_find();
130 Object *lpc = ich9_lpc_find();
131 Object *obj = NULL;
132 QObject *o;
133
134 pm->cpu_hp_io_base = 0;
135 pm->pcihp_io_base = 0;
136 pm->pcihp_io_len = 0;
137 if (piix) {
138 obj = piix;
139 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
140 pm->pcihp_io_base =
141 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
142 pm->pcihp_io_len =
143 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
144 }
145 if (lpc) {
146 obj = lpc;
147 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
148 }
149 assert(obj);
150
151 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
152 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
153
154 /* Fill in optional s3/s4 related properties */
155 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
156 if (o) {
157 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
158 } else {
159 pm->s3_disabled = false;
160 }
161 qobject_decref(o);
162 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
163 if (o) {
164 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
165 } else {
166 pm->s4_disabled = false;
167 }
168 qobject_decref(o);
169 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
170 if (o) {
171 pm->s4_val = qint_get_int(qobject_to_qint(o));
172 } else {
173 pm->s4_val = false;
174 }
175 qobject_decref(o);
176
177 /* Fill in mandatory properties */
178 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
179
180 pm->acpi_enable_cmd = object_property_get_int(obj,
181 ACPI_PM_PROP_ACPI_ENABLE_CMD,
182 NULL);
183 pm->acpi_disable_cmd = object_property_get_int(obj,
184 ACPI_PM_PROP_ACPI_DISABLE_CMD,
185 NULL);
186 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
187 NULL);
188 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
189 NULL);
190 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
191 NULL);
192 pm->pcihp_bridge_en =
193 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
194 NULL);
195 }
196
197 static void acpi_get_misc_info(AcpiMiscInfo *info)
198 {
199 Object *piix = piix4_pm_find();
200 Object *lpc = ich9_lpc_find();
201 assert(!!piix != !!lpc);
202
203 if (piix) {
204 info->is_piix4 = true;
205 }
206 if (lpc) {
207 info->is_piix4 = false;
208 }
209
210 info->has_hpet = hpet_find();
211 info->tpm_version = tpm_get_version();
212 info->pvpanic_port = pvpanic_port();
213 info->applesmc_io_base = applesmc_port();
214 }
215
216 /*
217 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
218 * On i386 arch we only have two pci hosts, so we can look only for them.
219 */
220 static Object *acpi_get_i386_pci_host(void)
221 {
222 PCIHostState *host;
223
224 host = OBJECT_CHECK(PCIHostState,
225 object_resolve_path("/machine/i440fx", NULL),
226 TYPE_PCI_HOST_BRIDGE);
227 if (!host) {
228 host = OBJECT_CHECK(PCIHostState,
229 object_resolve_path("/machine/q35", NULL),
230 TYPE_PCI_HOST_BRIDGE);
231 }
232
233 return OBJECT(host);
234 }
235
236 static void acpi_get_pci_holes(Range *hole, Range *hole64)
237 {
238 Object *pci_host;
239
240 pci_host = acpi_get_i386_pci_host();
241 g_assert(pci_host);
242
243 range_set_bounds1(hole,
244 object_property_get_int(pci_host,
245 PCI_HOST_PROP_PCI_HOLE_START,
246 NULL),
247 object_property_get_int(pci_host,
248 PCI_HOST_PROP_PCI_HOLE_END,
249 NULL));
250 range_set_bounds1(hole64,
251 object_property_get_int(pci_host,
252 PCI_HOST_PROP_PCI_HOLE64_START,
253 NULL),
254 object_property_get_int(pci_host,
255 PCI_HOST_PROP_PCI_HOLE64_END,
256 NULL));
257 }
258
259 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
260
261 static void acpi_align_size(GArray *blob, unsigned align)
262 {
263 /* Align size to multiple of given size. This reduces the chance
264 * we need to change size in the future (breaking cross version migration).
265 */
266 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
267 }
268
269 /* FACS */
270 static void
271 build_facs(GArray *table_data, BIOSLinker *linker)
272 {
273 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
274 memcpy(&facs->signature, "FACS", 4);
275 facs->length = cpu_to_le32(sizeof(*facs));
276 }
277
278 /* Load chipset information in FADT */
279 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
280 {
281 fadt->model = 1;
282 fadt->reserved1 = 0;
283 fadt->sci_int = cpu_to_le16(pm->sci_int);
284 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
285 fadt->acpi_enable = pm->acpi_enable_cmd;
286 fadt->acpi_disable = pm->acpi_disable_cmd;
287 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
288 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
289 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
290 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
291 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
292 /* EVT, CNT, TMR length matches hw/acpi/core.c */
293 fadt->pm1_evt_len = 4;
294 fadt->pm1_cnt_len = 2;
295 fadt->pm_tmr_len = 4;
296 fadt->gpe0_blk_len = pm->gpe0_blk_len;
297 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
298 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
299 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
300 (1 << ACPI_FADT_F_PROC_C1) |
301 (1 << ACPI_FADT_F_SLP_BUTTON) |
302 (1 << ACPI_FADT_F_RTC_S4));
303 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
304 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
305 * For more than 8 CPUs, "Clustered Logical" mode has to be used
306 */
307 if (max_cpus > 8) {
308 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
309 }
310 fadt->century = RTC_CENTURY;
311 }
312
313
314 /* FADT */
315 static void
316 build_fadt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm,
317 unsigned facs_tbl_offset, unsigned dsdt_tbl_offset,
318 const char *oem_id, const char *oem_table_id)
319 {
320 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
321 unsigned fw_ctrl_offset = (char *)&fadt->firmware_ctrl - table_data->data;
322 unsigned dsdt_entry_offset = (char *)&fadt->dsdt - table_data->data;
323
324 /* FACS address to be filled by Guest linker */
325 bios_linker_loader_add_pointer(linker,
326 ACPI_BUILD_TABLE_FILE, fw_ctrl_offset, sizeof(fadt->firmware_ctrl),
327 ACPI_BUILD_TABLE_FILE, facs_tbl_offset);
328
329 /* DSDT address to be filled by Guest linker */
330 fadt_setup(fadt, pm);
331 bios_linker_loader_add_pointer(linker,
332 ACPI_BUILD_TABLE_FILE, dsdt_entry_offset, sizeof(fadt->dsdt),
333 ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset);
334
335 build_header(linker, table_data,
336 (void *)fadt, "FACP", sizeof(*fadt), 1, oem_id, oem_table_id);
337 }
338
339 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
340 CPUArchIdList *apic_ids, GArray *entry)
341 {
342 uint32_t apic_id = apic_ids->cpus[uid].arch_id;
343
344 /* ACPI spec says that LAPIC entry for non present
345 * CPU may be omitted from MADT or it must be marked
346 * as disabled. However omitting non present CPU from
347 * MADT breaks hotplug on linux. So possible CPUs
348 * should be put in MADT but kept disabled.
349 */
350 if (apic_id < 255) {
351 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
352
353 apic->type = ACPI_APIC_PROCESSOR;
354 apic->length = sizeof(*apic);
355 apic->processor_id = uid;
356 apic->local_apic_id = apic_id;
357 if (apic_ids->cpus[uid].cpu != NULL) {
358 apic->flags = cpu_to_le32(1);
359 } else {
360 apic->flags = cpu_to_le32(0);
361 }
362 } else {
363 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic);
364
365 apic->type = ACPI_APIC_LOCAL_X2APIC;
366 apic->length = sizeof(*apic);
367 apic->uid = cpu_to_le32(uid);
368 apic->x2apic_id = cpu_to_le32(apic_id);
369 if (apic_ids->cpus[uid].cpu != NULL) {
370 apic->flags = cpu_to_le32(1);
371 } else {
372 apic->flags = cpu_to_le32(0);
373 }
374 }
375 }
376
377 static void
378 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
379 {
380 MachineClass *mc = MACHINE_GET_CLASS(pcms);
381 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
382 int madt_start = table_data->len;
383 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
384 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
385 bool x2apic_mode = false;
386
387 AcpiMultipleApicTable *madt;
388 AcpiMadtIoApic *io_apic;
389 AcpiMadtIntsrcovr *intsrcovr;
390 int i;
391
392 madt = acpi_data_push(table_data, sizeof *madt);
393 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
394 madt->flags = cpu_to_le32(1);
395
396 for (i = 0; i < apic_ids->len; i++) {
397 adevc->madt_cpu(adev, i, apic_ids, table_data);
398 if (apic_ids->cpus[i].arch_id > 254) {
399 x2apic_mode = true;
400 }
401 }
402 g_free(apic_ids);
403
404 io_apic = acpi_data_push(table_data, sizeof *io_apic);
405 io_apic->type = ACPI_APIC_IO;
406 io_apic->length = sizeof(*io_apic);
407 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
408 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
409 io_apic->interrupt = cpu_to_le32(0);
410
411 if (pcms->apic_xrupt_override) {
412 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
413 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
414 intsrcovr->length = sizeof(*intsrcovr);
415 intsrcovr->source = 0;
416 intsrcovr->gsi = cpu_to_le32(2);
417 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
418 }
419 for (i = 1; i < 16; i++) {
420 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
421 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
422 /* No need for a INT source override structure. */
423 continue;
424 }
425 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
426 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
427 intsrcovr->length = sizeof(*intsrcovr);
428 intsrcovr->source = i;
429 intsrcovr->gsi = cpu_to_le32(i);
430 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
431 }
432
433 if (x2apic_mode) {
434 AcpiMadtLocalX2ApicNmi *local_nmi;
435
436 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
437 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI;
438 local_nmi->length = sizeof(*local_nmi);
439 local_nmi->uid = 0xFFFFFFFF; /* all processors */
440 local_nmi->flags = cpu_to_le16(0);
441 local_nmi->lint = 1; /* ACPI_LINT1 */
442 } else {
443 AcpiMadtLocalNmi *local_nmi;
444
445 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
446 local_nmi->type = ACPI_APIC_LOCAL_NMI;
447 local_nmi->length = sizeof(*local_nmi);
448 local_nmi->processor_id = 0xff; /* all processors */
449 local_nmi->flags = cpu_to_le16(0);
450 local_nmi->lint = 1; /* ACPI_LINT1 */
451 }
452
453 build_header(linker, table_data,
454 (void *)(table_data->data + madt_start), "APIC",
455 table_data->len - madt_start, 1, NULL, NULL);
456 }
457
458 /* Assign BSEL property to all buses. In the future, this can be changed
459 * to only assign to buses that support hotplug.
460 */
461 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
462 {
463 unsigned *bsel_alloc = opaque;
464 unsigned *bus_bsel;
465
466 if (qbus_is_hotpluggable(BUS(bus))) {
467 bus_bsel = g_malloc(sizeof *bus_bsel);
468
469 *bus_bsel = (*bsel_alloc)++;
470 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
471 bus_bsel, NULL);
472 }
473
474 return bsel_alloc;
475 }
476
477 static void acpi_set_pci_info(void)
478 {
479 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
480 unsigned bsel_alloc = 0;
481
482 if (bus) {
483 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
484 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
485 }
486 }
487
488 static void build_append_pcihp_notify_entry(Aml *method, int slot)
489 {
490 Aml *if_ctx;
491 int32_t devfn = PCI_DEVFN(slot, 0);
492
493 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
494 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
495 aml_append(method, if_ctx);
496 }
497
498 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
499 bool pcihp_bridge_en)
500 {
501 Aml *dev, *notify_method, *method;
502 QObject *bsel;
503 PCIBus *sec;
504 int i;
505
506 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
507 if (bsel) {
508 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
509
510 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
511 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
512 }
513
514 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
515 DeviceClass *dc;
516 PCIDeviceClass *pc;
517 PCIDevice *pdev = bus->devices[i];
518 int slot = PCI_SLOT(i);
519 bool hotplug_enabled_dev;
520 bool bridge_in_acpi;
521
522 if (!pdev) {
523 if (bsel) { /* add hotplug slots for non present devices */
524 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
525 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
526 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
527 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
528 aml_append(method,
529 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
530 );
531 aml_append(dev, method);
532 aml_append(parent_scope, dev);
533
534 build_append_pcihp_notify_entry(notify_method, slot);
535 }
536 continue;
537 }
538
539 pc = PCI_DEVICE_GET_CLASS(pdev);
540 dc = DEVICE_GET_CLASS(pdev);
541
542 /* When hotplug for bridges is enabled, bridges are
543 * described in ACPI separately (see build_pci_bus_end).
544 * In this case they aren't themselves hot-pluggable.
545 * Hotplugged bridges *are* hot-pluggable.
546 */
547 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
548 !DEVICE(pdev)->hotplugged;
549
550 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
551
552 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
553 continue;
554 }
555
556 /* start to compose PCI slot descriptor */
557 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
558 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
559
560 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
561 /* add VGA specific AML methods */
562 int s3d;
563
564 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
565 s3d = 3;
566 } else {
567 s3d = 0;
568 }
569
570 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
571 aml_append(method, aml_return(aml_int(0)));
572 aml_append(dev, method);
573
574 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
575 aml_append(method, aml_return(aml_int(0)));
576 aml_append(dev, method);
577
578 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
579 aml_append(method, aml_return(aml_int(s3d)));
580 aml_append(dev, method);
581 } else if (hotplug_enabled_dev) {
582 /* add _SUN/_EJ0 to make slot hotpluggable */
583 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
584
585 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
586 aml_append(method,
587 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
588 );
589 aml_append(dev, method);
590
591 if (bsel) {
592 build_append_pcihp_notify_entry(notify_method, slot);
593 }
594 } else if (bridge_in_acpi) {
595 /*
596 * device is coldplugged bridge,
597 * add child device descriptions into its scope
598 */
599 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
600
601 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
602 }
603 /* slot descriptor has been composed, add it into parent context */
604 aml_append(parent_scope, dev);
605 }
606
607 if (bsel) {
608 aml_append(parent_scope, notify_method);
609 }
610
611 /* Append PCNT method to notify about events on local and child buses.
612 * Add unconditionally for root since DSDT expects it.
613 */
614 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
615
616 /* If bus supports hotplug select it and notify about local events */
617 if (bsel) {
618 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
619 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
620 aml_append(method,
621 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
622 );
623 aml_append(method,
624 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
625 );
626 }
627
628 /* Notify about child bus events in any case */
629 if (pcihp_bridge_en) {
630 QLIST_FOREACH(sec, &bus->child, sibling) {
631 int32_t devfn = sec->parent_dev->devfn;
632
633 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
634 continue;
635 }
636
637 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
638 }
639 }
640 aml_append(parent_scope, method);
641 qobject_decref(bsel);
642 }
643
644 /**
645 * build_prt_entry:
646 * @link_name: link name for PCI route entry
647 *
648 * build AML package containing a PCI route entry for @link_name
649 */
650 static Aml *build_prt_entry(const char *link_name)
651 {
652 Aml *a_zero = aml_int(0);
653 Aml *pkg = aml_package(4);
654 aml_append(pkg, a_zero);
655 aml_append(pkg, a_zero);
656 aml_append(pkg, aml_name("%s", link_name));
657 aml_append(pkg, a_zero);
658 return pkg;
659 }
660
661 /*
662 * initialize_route - Initialize the interrupt routing rule
663 * through a specific LINK:
664 * if (lnk_idx == idx)
665 * route using link 'link_name'
666 */
667 static Aml *initialize_route(Aml *route, const char *link_name,
668 Aml *lnk_idx, int idx)
669 {
670 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
671 Aml *pkg = build_prt_entry(link_name);
672
673 aml_append(if_ctx, aml_store(pkg, route));
674
675 return if_ctx;
676 }
677
678 /*
679 * build_prt - Define interrupt rounting rules
680 *
681 * Returns an array of 128 routes, one for each device,
682 * based on device location.
683 * The main goal is to equaly distribute the interrupts
684 * over the 4 existing ACPI links (works only for i440fx).
685 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
686 *
687 */
688 static Aml *build_prt(bool is_pci0_prt)
689 {
690 Aml *method, *while_ctx, *pin, *res;
691
692 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
693 res = aml_local(0);
694 pin = aml_local(1);
695 aml_append(method, aml_store(aml_package(128), res));
696 aml_append(method, aml_store(aml_int(0), pin));
697
698 /* while (pin < 128) */
699 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
700 {
701 Aml *slot = aml_local(2);
702 Aml *lnk_idx = aml_local(3);
703 Aml *route = aml_local(4);
704
705 /* slot = pin >> 2 */
706 aml_append(while_ctx,
707 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
708 /* lnk_idx = (slot + pin) & 3 */
709 aml_append(while_ctx,
710 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
711 lnk_idx));
712
713 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
714 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
715 if (is_pci0_prt) {
716 Aml *if_device_1, *if_pin_4, *else_pin_4;
717
718 /* device 1 is the power-management device, needs SCI */
719 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
720 {
721 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
722 {
723 aml_append(if_pin_4,
724 aml_store(build_prt_entry("LNKS"), route));
725 }
726 aml_append(if_device_1, if_pin_4);
727 else_pin_4 = aml_else();
728 {
729 aml_append(else_pin_4,
730 aml_store(build_prt_entry("LNKA"), route));
731 }
732 aml_append(if_device_1, else_pin_4);
733 }
734 aml_append(while_ctx, if_device_1);
735 } else {
736 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
737 }
738 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
739 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
740
741 /* route[0] = 0x[slot]FFFF */
742 aml_append(while_ctx,
743 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
744 NULL),
745 aml_index(route, aml_int(0))));
746 /* route[1] = pin & 3 */
747 aml_append(while_ctx,
748 aml_store(aml_and(pin, aml_int(3), NULL),
749 aml_index(route, aml_int(1))));
750 /* res[pin] = route */
751 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
752 /* pin++ */
753 aml_append(while_ctx, aml_increment(pin));
754 }
755 aml_append(method, while_ctx);
756 /* return res*/
757 aml_append(method, aml_return(res));
758
759 return method;
760 }
761
762 typedef struct CrsRangeEntry {
763 uint64_t base;
764 uint64_t limit;
765 } CrsRangeEntry;
766
767 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
768 {
769 CrsRangeEntry *entry;
770
771 entry = g_malloc(sizeof(*entry));
772 entry->base = base;
773 entry->limit = limit;
774
775 g_ptr_array_add(ranges, entry);
776 }
777
778 static void crs_range_free(gpointer data)
779 {
780 CrsRangeEntry *entry = (CrsRangeEntry *)data;
781 g_free(entry);
782 }
783
784 typedef struct CrsRangeSet {
785 GPtrArray *io_ranges;
786 GPtrArray *mem_ranges;
787 GPtrArray *mem_64bit_ranges;
788 } CrsRangeSet;
789
790 static void crs_range_set_init(CrsRangeSet *range_set)
791 {
792 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
793 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
794 range_set->mem_64bit_ranges =
795 g_ptr_array_new_with_free_func(crs_range_free);
796 }
797
798 static void crs_range_set_free(CrsRangeSet *range_set)
799 {
800 g_ptr_array_free(range_set->io_ranges, true);
801 g_ptr_array_free(range_set->mem_ranges, true);
802 g_ptr_array_free(range_set->mem_64bit_ranges, true);
803 }
804
805 static gint crs_range_compare(gconstpointer a, gconstpointer b)
806 {
807 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
808 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
809
810 return (int64_t)entry_a->base - (int64_t)entry_b->base;
811 }
812
813 /*
814 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
815 * interval, computes the 'free' ranges from the same interval.
816 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
817 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
818 */
819 static void crs_replace_with_free_ranges(GPtrArray *ranges,
820 uint64_t start, uint64_t end)
821 {
822 GPtrArray *free_ranges = g_ptr_array_new();
823 uint64_t free_base = start;
824 int i;
825
826 g_ptr_array_sort(ranges, crs_range_compare);
827 for (i = 0; i < ranges->len; i++) {
828 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
829
830 if (free_base < used->base) {
831 crs_range_insert(free_ranges, free_base, used->base - 1);
832 }
833
834 free_base = used->limit + 1;
835 }
836
837 if (free_base < end) {
838 crs_range_insert(free_ranges, free_base, end);
839 }
840
841 g_ptr_array_set_size(ranges, 0);
842 for (i = 0; i < free_ranges->len; i++) {
843 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
844 }
845
846 g_ptr_array_free(free_ranges, true);
847 }
848
849 /*
850 * crs_range_merge - merges adjacent ranges in the given array.
851 * Array elements are deleted and replaced with the merged ranges.
852 */
853 static void crs_range_merge(GPtrArray *range)
854 {
855 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
856 CrsRangeEntry *entry;
857 uint64_t range_base, range_limit;
858 int i;
859
860 if (!range->len) {
861 return;
862 }
863
864 g_ptr_array_sort(range, crs_range_compare);
865
866 entry = g_ptr_array_index(range, 0);
867 range_base = entry->base;
868 range_limit = entry->limit;
869 for (i = 1; i < range->len; i++) {
870 entry = g_ptr_array_index(range, i);
871 if (entry->base - 1 == range_limit) {
872 range_limit = entry->limit;
873 } else {
874 crs_range_insert(tmp, range_base, range_limit);
875 range_base = entry->base;
876 range_limit = entry->limit;
877 }
878 }
879 crs_range_insert(tmp, range_base, range_limit);
880
881 g_ptr_array_set_size(range, 0);
882 for (i = 0; i < tmp->len; i++) {
883 entry = g_ptr_array_index(tmp, i);
884 crs_range_insert(range, entry->base, entry->limit);
885 }
886 g_ptr_array_free(tmp, true);
887 }
888
889 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
890 {
891 Aml *crs = aml_resource_template();
892 CrsRangeSet temp_range_set;
893 CrsRangeEntry *entry;
894 uint8_t max_bus = pci_bus_num(host->bus);
895 uint8_t type;
896 int devfn;
897 int i;
898
899 crs_range_set_init(&temp_range_set);
900 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
901 uint64_t range_base, range_limit;
902 PCIDevice *dev = host->bus->devices[devfn];
903
904 if (!dev) {
905 continue;
906 }
907
908 for (i = 0; i < PCI_NUM_REGIONS; i++) {
909 PCIIORegion *r = &dev->io_regions[i];
910
911 range_base = r->addr;
912 range_limit = r->addr + r->size - 1;
913
914 /*
915 * Work-around for old bioses
916 * that do not support multiple root buses
917 */
918 if (!range_base || range_base > range_limit) {
919 continue;
920 }
921
922 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
923 crs_range_insert(temp_range_set.io_ranges,
924 range_base, range_limit);
925 } else { /* "memory" */
926 crs_range_insert(temp_range_set.mem_ranges,
927 range_base, range_limit);
928 }
929 }
930
931 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
932 if (type == PCI_HEADER_TYPE_BRIDGE) {
933 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
934 if (subordinate > max_bus) {
935 max_bus = subordinate;
936 }
937
938 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
939 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
940
941 /*
942 * Work-around for old bioses
943 * that do not support multiple root buses
944 */
945 if (range_base && range_base <= range_limit) {
946 crs_range_insert(temp_range_set.io_ranges,
947 range_base, range_limit);
948 }
949
950 range_base =
951 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
952 range_limit =
953 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
954
955 /*
956 * Work-around for old bioses
957 * that do not support multiple root buses
958 */
959 if (range_base && range_base <= range_limit) {
960 uint64_t length = range_limit - range_base + 1;
961 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
962 crs_range_insert(temp_range_set.mem_ranges,
963 range_base, range_limit);
964 } else {
965 crs_range_insert(temp_range_set.mem_64bit_ranges,
966 range_base, range_limit);
967 }
968 }
969
970 range_base =
971 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
972 range_limit =
973 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
974
975 /*
976 * Work-around for old bioses
977 * that do not support multiple root buses
978 */
979 if (range_base && range_base <= range_limit) {
980 uint64_t length = range_limit - range_base + 1;
981 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
982 crs_range_insert(temp_range_set.mem_ranges,
983 range_base, range_limit);
984 } else {
985 crs_range_insert(temp_range_set.mem_64bit_ranges,
986 range_base, range_limit);
987 }
988 }
989 }
990 }
991
992 crs_range_merge(temp_range_set.io_ranges);
993 for (i = 0; i < temp_range_set.io_ranges->len; i++) {
994 entry = g_ptr_array_index(temp_range_set.io_ranges, i);
995 aml_append(crs,
996 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
997 AML_POS_DECODE, AML_ENTIRE_RANGE,
998 0, entry->base, entry->limit, 0,
999 entry->limit - entry->base + 1));
1000 crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
1001 }
1002
1003 crs_range_merge(temp_range_set.mem_ranges);
1004 for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
1005 entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
1006 aml_append(crs,
1007 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1008 AML_MAX_FIXED, AML_NON_CACHEABLE,
1009 AML_READ_WRITE,
1010 0, entry->base, entry->limit, 0,
1011 entry->limit - entry->base + 1));
1012 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
1013 }
1014
1015 crs_range_merge(temp_range_set.mem_64bit_ranges);
1016 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
1017 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
1018 aml_append(crs,
1019 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1020 AML_MAX_FIXED, AML_NON_CACHEABLE,
1021 AML_READ_WRITE,
1022 0, entry->base, entry->limit, 0,
1023 entry->limit - entry->base + 1));
1024 crs_range_insert(range_set->mem_64bit_ranges,
1025 entry->base, entry->limit);
1026 }
1027
1028 crs_range_set_free(&temp_range_set);
1029
1030 aml_append(crs,
1031 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1032 0,
1033 pci_bus_num(host->bus),
1034 max_bus,
1035 0,
1036 max_bus - pci_bus_num(host->bus) + 1));
1037
1038 return crs;
1039 }
1040
1041 static void build_memory_devices(Aml *sb_scope, int nr_mem,
1042 uint16_t io_base, uint16_t io_len)
1043 {
1044 int i;
1045 Aml *scope;
1046 Aml *crs;
1047 Aml *field;
1048 Aml *dev;
1049 Aml *method;
1050 Aml *ifctx;
1051
1052 /* build memory devices */
1053 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
1054 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE);
1055 aml_append(scope,
1056 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem))
1057 );
1058
1059 crs = aml_resource_template();
1060 aml_append(crs,
1061 aml_io(AML_DECODE16, io_base, io_base, 0, io_len)
1062 );
1063 aml_append(scope, aml_name_decl("_CRS", crs));
1064
1065 aml_append(scope, aml_operation_region(
1066 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO,
1067 aml_int(io_base), io_len)
1068 );
1069
1070 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1071 AML_NOLOCK, AML_PRESERVE);
1072 aml_append(field, /* read only */
1073 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32));
1074 aml_append(field, /* read only */
1075 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32));
1076 aml_append(field, /* read only */
1077 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32));
1078 aml_append(field, /* read only */
1079 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32));
1080 aml_append(field, /* read only */
1081 aml_named_field(MEMORY_SLOT_PROXIMITY, 32));
1082 aml_append(scope, field);
1083
1084 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC,
1085 AML_NOLOCK, AML_WRITE_AS_ZEROS);
1086 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1087 aml_append(field, /* 1 if enabled, read only */
1088 aml_named_field(MEMORY_SLOT_ENABLED, 1));
1089 aml_append(field,
1090 /*(read) 1 if has a insert event. (write) 1 to clear event */
1091 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1));
1092 aml_append(field,
1093 /* (read) 1 if has a remove event. (write) 1 to clear event */
1094 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1));
1095 aml_append(field,
1096 /* initiates device eject, write only */
1097 aml_named_field(MEMORY_SLOT_EJECT, 1));
1098 aml_append(scope, field);
1099
1100 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1101 AML_NOLOCK, AML_PRESERVE);
1102 aml_append(field, /* DIMM selector, write only */
1103 aml_named_field(MEMORY_SLOT_SLECTOR, 32));
1104 aml_append(field, /* _OST event code, write only */
1105 aml_named_field(MEMORY_SLOT_OST_EVENT, 32));
1106 aml_append(field, /* _OST status code, write only */
1107 aml_named_field(MEMORY_SLOT_OST_STATUS, 32));
1108 aml_append(scope, field);
1109 aml_append(sb_scope, scope);
1110
1111 for (i = 0; i < nr_mem; i++) {
1112 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
1113 const char *s;
1114
1115 dev = aml_device("MP%02X", i);
1116 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1117 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1118
1119 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1120 s = BASEPATH MEMORY_SLOT_CRS_METHOD;
1121 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1122 aml_append(dev, method);
1123
1124 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1125 s = BASEPATH MEMORY_SLOT_STATUS_METHOD;
1126 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1127 aml_append(dev, method);
1128
1129 method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
1130 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD;
1131 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1132 aml_append(dev, method);
1133
1134 method = aml_method("_OST", 3, AML_NOTSERIALIZED);
1135 s = BASEPATH MEMORY_SLOT_OST_METHOD;
1136
1137 aml_append(method, aml_return(aml_call4(
1138 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1139 )));
1140 aml_append(dev, method);
1141
1142 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1143 s = BASEPATH MEMORY_SLOT_EJECT_METHOD;
1144 aml_append(method, aml_return(aml_call2(
1145 s, aml_name("_UID"), aml_arg(0))));
1146 aml_append(dev, method);
1147
1148 aml_append(sb_scope, dev);
1149 }
1150
1151 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1152 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1153 */
1154 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1155 for (i = 0; i < nr_mem; i++) {
1156 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1157 aml_append(ifctx,
1158 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1159 );
1160 aml_append(method, ifctx);
1161 }
1162 aml_append(sb_scope, method);
1163 }
1164
1165 static void build_hpet_aml(Aml *table)
1166 {
1167 Aml *crs;
1168 Aml *field;
1169 Aml *method;
1170 Aml *if_ctx;
1171 Aml *scope = aml_scope("_SB");
1172 Aml *dev = aml_device("HPET");
1173 Aml *zero = aml_int(0);
1174 Aml *id = aml_local(0);
1175 Aml *period = aml_local(1);
1176
1177 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1178 aml_append(dev, aml_name_decl("_UID", zero));
1179
1180 aml_append(dev,
1181 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1182 HPET_LEN));
1183 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1184 aml_append(field, aml_named_field("VEND", 32));
1185 aml_append(field, aml_named_field("PRD", 32));
1186 aml_append(dev, field);
1187
1188 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1189 aml_append(method, aml_store(aml_name("VEND"), id));
1190 aml_append(method, aml_store(aml_name("PRD"), period));
1191 aml_append(method, aml_shiftright(id, aml_int(16), id));
1192 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1193 aml_equal(id, aml_int(0xffff))));
1194 {
1195 aml_append(if_ctx, aml_return(zero));
1196 }
1197 aml_append(method, if_ctx);
1198
1199 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1200 aml_lgreater(period, aml_int(100000000))));
1201 {
1202 aml_append(if_ctx, aml_return(zero));
1203 }
1204 aml_append(method, if_ctx);
1205
1206 aml_append(method, aml_return(aml_int(0x0F)));
1207 aml_append(dev, method);
1208
1209 crs = aml_resource_template();
1210 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1211 aml_append(dev, aml_name_decl("_CRS", crs));
1212
1213 aml_append(scope, dev);
1214 aml_append(table, scope);
1215 }
1216
1217 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
1218 {
1219 Aml *dev, *fdi;
1220 uint8_t maxc, maxh, maxs;
1221
1222 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1223
1224 dev = aml_device("FLP%c", 'A' + idx);
1225
1226 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1227
1228 fdi = aml_package(16);
1229 aml_append(fdi, aml_int(idx)); /* Drive Number */
1230 aml_append(fdi,
1231 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1232 /*
1233 * the values below are the limits of the drive, and are thus independent
1234 * of the inserted media
1235 */
1236 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1237 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1238 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1239 /*
1240 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1241 * the drive type, so shall we
1242 */
1243 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1244 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1245 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1246 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1247 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1248 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1249 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1250 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1251 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1252 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1253 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1254
1255 aml_append(dev, aml_name_decl("_FDI", fdi));
1256 return dev;
1257 }
1258
1259 static Aml *build_fdc_device_aml(ISADevice *fdc)
1260 {
1261 int i;
1262 Aml *dev;
1263 Aml *crs;
1264
1265 #define ACPI_FDE_MAX_FD 4
1266 uint32_t fde_buf[5] = {
1267 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1268 cpu_to_le32(2) /* tape presence (2 == never present) */
1269 };
1270
1271 dev = aml_device("FDC0");
1272 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1273
1274 crs = aml_resource_template();
1275 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1276 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1277 aml_append(crs, aml_irq_no_flags(6));
1278 aml_append(crs,
1279 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1280 aml_append(dev, aml_name_decl("_CRS", crs));
1281
1282 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1283 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1284
1285 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1286 fde_buf[i] = cpu_to_le32(1); /* drive present */
1287 aml_append(dev, build_fdinfo_aml(i, type));
1288 }
1289 }
1290 aml_append(dev, aml_name_decl("_FDE",
1291 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1292
1293 return dev;
1294 }
1295
1296 static Aml *build_rtc_device_aml(void)
1297 {
1298 Aml *dev;
1299 Aml *crs;
1300
1301 dev = aml_device("RTC");
1302 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1303 crs = aml_resource_template();
1304 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1305 aml_append(crs, aml_irq_no_flags(8));
1306 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1307 aml_append(dev, aml_name_decl("_CRS", crs));
1308
1309 return dev;
1310 }
1311
1312 static Aml *build_kbd_device_aml(void)
1313 {
1314 Aml *dev;
1315 Aml *crs;
1316 Aml *method;
1317
1318 dev = aml_device("KBD");
1319 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1320
1321 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1322 aml_append(method, aml_return(aml_int(0x0f)));
1323 aml_append(dev, method);
1324
1325 crs = aml_resource_template();
1326 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1327 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1328 aml_append(crs, aml_irq_no_flags(1));
1329 aml_append(dev, aml_name_decl("_CRS", crs));
1330
1331 return dev;
1332 }
1333
1334 static Aml *build_mouse_device_aml(void)
1335 {
1336 Aml *dev;
1337 Aml *crs;
1338 Aml *method;
1339
1340 dev = aml_device("MOU");
1341 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1342
1343 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1344 aml_append(method, aml_return(aml_int(0x0f)));
1345 aml_append(dev, method);
1346
1347 crs = aml_resource_template();
1348 aml_append(crs, aml_irq_no_flags(12));
1349 aml_append(dev, aml_name_decl("_CRS", crs));
1350
1351 return dev;
1352 }
1353
1354 static Aml *build_lpt_device_aml(void)
1355 {
1356 Aml *dev;
1357 Aml *crs;
1358 Aml *method;
1359 Aml *if_ctx;
1360 Aml *else_ctx;
1361 Aml *zero = aml_int(0);
1362 Aml *is_present = aml_local(0);
1363
1364 dev = aml_device("LPT");
1365 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1366
1367 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1368 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1369 if_ctx = aml_if(aml_equal(is_present, zero));
1370 {
1371 aml_append(if_ctx, aml_return(aml_int(0x00)));
1372 }
1373 aml_append(method, if_ctx);
1374 else_ctx = aml_else();
1375 {
1376 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1377 }
1378 aml_append(method, else_ctx);
1379 aml_append(dev, method);
1380
1381 crs = aml_resource_template();
1382 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1383 aml_append(crs, aml_irq_no_flags(7));
1384 aml_append(dev, aml_name_decl("_CRS", crs));
1385
1386 return dev;
1387 }
1388
1389 static Aml *build_com_device_aml(uint8_t uid)
1390 {
1391 Aml *dev;
1392 Aml *crs;
1393 Aml *method;
1394 Aml *if_ctx;
1395 Aml *else_ctx;
1396 Aml *zero = aml_int(0);
1397 Aml *is_present = aml_local(0);
1398 const char *enabled_field = "CAEN";
1399 uint8_t irq = 4;
1400 uint16_t io_port = 0x03F8;
1401
1402 assert(uid == 1 || uid == 2);
1403 if (uid == 2) {
1404 enabled_field = "CBEN";
1405 irq = 3;
1406 io_port = 0x02F8;
1407 }
1408
1409 dev = aml_device("COM%d", uid);
1410 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1411 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1412
1413 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1414 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1415 if_ctx = aml_if(aml_equal(is_present, zero));
1416 {
1417 aml_append(if_ctx, aml_return(aml_int(0x00)));
1418 }
1419 aml_append(method, if_ctx);
1420 else_ctx = aml_else();
1421 {
1422 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1423 }
1424 aml_append(method, else_ctx);
1425 aml_append(dev, method);
1426
1427 crs = aml_resource_template();
1428 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1429 aml_append(crs, aml_irq_no_flags(irq));
1430 aml_append(dev, aml_name_decl("_CRS", crs));
1431
1432 return dev;
1433 }
1434
1435 static void build_isa_devices_aml(Aml *table)
1436 {
1437 ISADevice *fdc = pc_find_fdc0();
1438 bool ambiguous;
1439
1440 Aml *scope = aml_scope("_SB.PCI0.ISA");
1441 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
1442
1443 aml_append(scope, build_rtc_device_aml());
1444 aml_append(scope, build_kbd_device_aml());
1445 aml_append(scope, build_mouse_device_aml());
1446 if (fdc) {
1447 aml_append(scope, build_fdc_device_aml(fdc));
1448 }
1449 aml_append(scope, build_lpt_device_aml());
1450 aml_append(scope, build_com_device_aml(1));
1451 aml_append(scope, build_com_device_aml(2));
1452
1453 if (ambiguous) {
1454 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1455 } else if (!obj) {
1456 error_report("No ISA bus, unable to define IPMI ACPI data");
1457 } else {
1458 build_acpi_ipmi_devices(scope, BUS(obj));
1459 }
1460
1461 aml_append(table, scope);
1462 }
1463
1464 static void build_dbg_aml(Aml *table)
1465 {
1466 Aml *field;
1467 Aml *method;
1468 Aml *while_ctx;
1469 Aml *scope = aml_scope("\\");
1470 Aml *buf = aml_local(0);
1471 Aml *len = aml_local(1);
1472 Aml *idx = aml_local(2);
1473
1474 aml_append(scope,
1475 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1476 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1477 aml_append(field, aml_named_field("DBGB", 8));
1478 aml_append(scope, field);
1479
1480 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1481
1482 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1483 aml_append(method, aml_to_buffer(buf, buf));
1484 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1485 aml_append(method, aml_store(aml_int(0), idx));
1486
1487 while_ctx = aml_while(aml_lless(idx, len));
1488 aml_append(while_ctx,
1489 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1490 aml_append(while_ctx, aml_increment(idx));
1491 aml_append(method, while_ctx);
1492
1493 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1494 aml_append(scope, method);
1495
1496 aml_append(table, scope);
1497 }
1498
1499 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1500 {
1501 Aml *dev;
1502 Aml *crs;
1503 Aml *method;
1504 uint32_t irqs[] = {5, 10, 11};
1505
1506 dev = aml_device("%s", name);
1507 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1508 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1509
1510 crs = aml_resource_template();
1511 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1512 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1513 aml_append(dev, aml_name_decl("_PRS", crs));
1514
1515 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1516 aml_append(method, aml_return(aml_call1("IQST", reg)));
1517 aml_append(dev, method);
1518
1519 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1520 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1521 aml_append(dev, method);
1522
1523 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1524 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1525 aml_append(dev, method);
1526
1527 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1528 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1529 aml_append(method, aml_store(aml_name("PRRI"), reg));
1530 aml_append(dev, method);
1531
1532 return dev;
1533 }
1534
1535 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1536 {
1537 Aml *dev;
1538 Aml *crs;
1539 Aml *method;
1540 uint32_t irqs;
1541
1542 dev = aml_device("%s", name);
1543 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1544 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1545
1546 crs = aml_resource_template();
1547 irqs = gsi;
1548 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1549 AML_SHARED, &irqs, 1));
1550 aml_append(dev, aml_name_decl("_PRS", crs));
1551
1552 aml_append(dev, aml_name_decl("_CRS", crs));
1553
1554 /*
1555 * _DIS can be no-op because the interrupt cannot be disabled.
1556 */
1557 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1558 aml_append(dev, method);
1559
1560 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1561 aml_append(dev, method);
1562
1563 return dev;
1564 }
1565
1566 /* _CRS method - get current settings */
1567 static Aml *build_iqcr_method(bool is_piix4)
1568 {
1569 Aml *if_ctx;
1570 uint32_t irqs;
1571 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1572 Aml *crs = aml_resource_template();
1573
1574 irqs = 0;
1575 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1576 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1577 aml_append(method, aml_name_decl("PRR0", crs));
1578
1579 aml_append(method,
1580 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1581
1582 if (is_piix4) {
1583 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1584 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1585 aml_append(method, if_ctx);
1586 } else {
1587 aml_append(method,
1588 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1589 aml_name("PRRI")));
1590 }
1591
1592 aml_append(method, aml_return(aml_name("PRR0")));
1593 return method;
1594 }
1595
1596 /* _STA method - get status */
1597 static Aml *build_irq_status_method(void)
1598 {
1599 Aml *if_ctx;
1600 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1601
1602 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1603 aml_append(if_ctx, aml_return(aml_int(0x09)));
1604 aml_append(method, if_ctx);
1605 aml_append(method, aml_return(aml_int(0x0B)));
1606 return method;
1607 }
1608
1609 static void build_piix4_pci0_int(Aml *table)
1610 {
1611 Aml *dev;
1612 Aml *crs;
1613 Aml *field;
1614 Aml *method;
1615 uint32_t irqs;
1616 Aml *sb_scope = aml_scope("_SB");
1617 Aml *pci0_scope = aml_scope("PCI0");
1618
1619 aml_append(pci0_scope, build_prt(true));
1620 aml_append(sb_scope, pci0_scope);
1621
1622 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1623 aml_append(field, aml_named_field("PRQ0", 8));
1624 aml_append(field, aml_named_field("PRQ1", 8));
1625 aml_append(field, aml_named_field("PRQ2", 8));
1626 aml_append(field, aml_named_field("PRQ3", 8));
1627 aml_append(sb_scope, field);
1628
1629 aml_append(sb_scope, build_irq_status_method());
1630 aml_append(sb_scope, build_iqcr_method(true));
1631
1632 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1633 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1634 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1635 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1636
1637 dev = aml_device("LNKS");
1638 {
1639 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1640 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1641
1642 crs = aml_resource_template();
1643 irqs = 9;
1644 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1645 AML_ACTIVE_HIGH, AML_SHARED,
1646 &irqs, 1));
1647 aml_append(dev, aml_name_decl("_PRS", crs));
1648
1649 /* The SCI cannot be disabled and is always attached to GSI 9,
1650 * so these are no-ops. We only need this link to override the
1651 * polarity to active high and match the content of the MADT.
1652 */
1653 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1654 aml_append(method, aml_return(aml_int(0x0b)));
1655 aml_append(dev, method);
1656
1657 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1658 aml_append(dev, method);
1659
1660 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1661 aml_append(method, aml_return(aml_name("_PRS")));
1662 aml_append(dev, method);
1663
1664 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1665 aml_append(dev, method);
1666 }
1667 aml_append(sb_scope, dev);
1668
1669 aml_append(table, sb_scope);
1670 }
1671
1672 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1673 {
1674 int i;
1675 int head;
1676 Aml *pkg;
1677 char base = name[3] < 'E' ? 'A' : 'E';
1678 char *s = g_strdup(name);
1679 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1680
1681 assert(strlen(s) == 4);
1682
1683 head = name[3] - base;
1684 for (i = 0; i < 4; i++) {
1685 if (head + i > 3) {
1686 head = i * -1;
1687 }
1688 s[3] = base + head + i;
1689 pkg = aml_package(4);
1690 aml_append(pkg, a_nr);
1691 aml_append(pkg, aml_int(i));
1692 aml_append(pkg, aml_name("%s", s));
1693 aml_append(pkg, aml_int(0));
1694 aml_append(ctx, pkg);
1695 }
1696 g_free(s);
1697 }
1698
1699 static Aml *build_q35_routing_table(const char *str)
1700 {
1701 int i;
1702 Aml *pkg;
1703 char *name = g_strdup_printf("%s ", str);
1704
1705 pkg = aml_package(128);
1706 for (i = 0; i < 0x18; i++) {
1707 name[3] = 'E' + (i & 0x3);
1708 append_q35_prt_entry(pkg, i, name);
1709 }
1710
1711 name[3] = 'E';
1712 append_q35_prt_entry(pkg, 0x18, name);
1713
1714 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1715 for (i = 0x0019; i < 0x1e; i++) {
1716 name[3] = 'A';
1717 append_q35_prt_entry(pkg, i, name);
1718 }
1719
1720 /* PCIe->PCI bridge. use PIRQ[E-H] */
1721 name[3] = 'E';
1722 append_q35_prt_entry(pkg, 0x1e, name);
1723 name[3] = 'A';
1724 append_q35_prt_entry(pkg, 0x1f, name);
1725
1726 g_free(name);
1727 return pkg;
1728 }
1729
1730 static void build_q35_pci0_int(Aml *table)
1731 {
1732 Aml *field;
1733 Aml *method;
1734 Aml *sb_scope = aml_scope("_SB");
1735 Aml *pci0_scope = aml_scope("PCI0");
1736
1737 /* Zero => PIC mode, One => APIC Mode */
1738 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1739 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1740 {
1741 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1742 }
1743 aml_append(table, method);
1744
1745 aml_append(pci0_scope,
1746 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1747 aml_append(pci0_scope,
1748 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1749
1750 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1751 {
1752 Aml *if_ctx;
1753 Aml *else_ctx;
1754
1755 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1756 section 6.2.8.1 */
1757 /* Note: we provide the same info as the PCI routing
1758 table of the Bochs BIOS */
1759 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1760 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1761 aml_append(method, if_ctx);
1762 else_ctx = aml_else();
1763 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1764 aml_append(method, else_ctx);
1765 }
1766 aml_append(pci0_scope, method);
1767 aml_append(sb_scope, pci0_scope);
1768
1769 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1770 aml_append(field, aml_named_field("PRQA", 8));
1771 aml_append(field, aml_named_field("PRQB", 8));
1772 aml_append(field, aml_named_field("PRQC", 8));
1773 aml_append(field, aml_named_field("PRQD", 8));
1774 aml_append(field, aml_reserved_field(0x20));
1775 aml_append(field, aml_named_field("PRQE", 8));
1776 aml_append(field, aml_named_field("PRQF", 8));
1777 aml_append(field, aml_named_field("PRQG", 8));
1778 aml_append(field, aml_named_field("PRQH", 8));
1779 aml_append(sb_scope, field);
1780
1781 aml_append(sb_scope, build_irq_status_method());
1782 aml_append(sb_scope, build_iqcr_method(false));
1783
1784 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1785 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1786 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1787 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1788 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1789 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1790 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1791 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1792
1793 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1794 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1795 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1796 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1797 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1798 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1799 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1800 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1801
1802 aml_append(table, sb_scope);
1803 }
1804
1805 static void build_q35_isa_bridge(Aml *table)
1806 {
1807 Aml *dev;
1808 Aml *scope;
1809 Aml *field;
1810
1811 scope = aml_scope("_SB.PCI0");
1812 dev = aml_device("ISA");
1813 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1814
1815 /* ICH9 PCI to ISA irq remapping */
1816 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1817 aml_int(0x60), 0x0C));
1818
1819 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1820 aml_int(0x80), 0x02));
1821 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1822 aml_append(field, aml_named_field("COMA", 3));
1823 aml_append(field, aml_reserved_field(1));
1824 aml_append(field, aml_named_field("COMB", 3));
1825 aml_append(field, aml_reserved_field(1));
1826 aml_append(field, aml_named_field("LPTD", 2));
1827 aml_append(dev, field);
1828
1829 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1830 aml_int(0x82), 0x02));
1831 /* enable bits */
1832 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1833 aml_append(field, aml_named_field("CAEN", 1));
1834 aml_append(field, aml_named_field("CBEN", 1));
1835 aml_append(field, aml_named_field("LPEN", 1));
1836 aml_append(dev, field);
1837
1838 aml_append(scope, dev);
1839 aml_append(table, scope);
1840 }
1841
1842 static void build_piix4_pm(Aml *table)
1843 {
1844 Aml *dev;
1845 Aml *scope;
1846
1847 scope = aml_scope("_SB.PCI0");
1848 dev = aml_device("PX13");
1849 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1850
1851 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1852 aml_int(0x00), 0xff));
1853 aml_append(scope, dev);
1854 aml_append(table, scope);
1855 }
1856
1857 static void build_piix4_isa_bridge(Aml *table)
1858 {
1859 Aml *dev;
1860 Aml *scope;
1861 Aml *field;
1862
1863 scope = aml_scope("_SB.PCI0");
1864 dev = aml_device("ISA");
1865 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1866
1867 /* PIIX PCI to ISA irq remapping */
1868 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1869 aml_int(0x60), 0x04));
1870 /* enable bits */
1871 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1872 /* Offset(0x5f),, 7, */
1873 aml_append(field, aml_reserved_field(0x2f8));
1874 aml_append(field, aml_reserved_field(7));
1875 aml_append(field, aml_named_field("LPEN", 1));
1876 /* Offset(0x67),, 3, */
1877 aml_append(field, aml_reserved_field(0x38));
1878 aml_append(field, aml_reserved_field(3));
1879 aml_append(field, aml_named_field("CAEN", 1));
1880 aml_append(field, aml_reserved_field(3));
1881 aml_append(field, aml_named_field("CBEN", 1));
1882 aml_append(dev, field);
1883
1884 aml_append(scope, dev);
1885 aml_append(table, scope);
1886 }
1887
1888 static void build_piix4_pci_hotplug(Aml *table)
1889 {
1890 Aml *scope;
1891 Aml *field;
1892 Aml *method;
1893
1894 scope = aml_scope("_SB.PCI0");
1895
1896 aml_append(scope,
1897 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1898 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1899 aml_append(field, aml_named_field("PCIU", 32));
1900 aml_append(field, aml_named_field("PCID", 32));
1901 aml_append(scope, field);
1902
1903 aml_append(scope,
1904 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1905 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1906 aml_append(field, aml_named_field("B0EJ", 32));
1907 aml_append(scope, field);
1908
1909 aml_append(scope,
1910 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1911 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1912 aml_append(field, aml_named_field("BNUM", 32));
1913 aml_append(scope, field);
1914
1915 aml_append(scope, aml_mutex("BLCK", 0));
1916
1917 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1918 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1919 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1920 aml_append(method,
1921 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1922 aml_append(method, aml_release(aml_name("BLCK")));
1923 aml_append(method, aml_return(aml_int(0)));
1924 aml_append(scope, method);
1925
1926 aml_append(table, scope);
1927 }
1928
1929 static Aml *build_q35_osc_method(void)
1930 {
1931 Aml *if_ctx;
1932 Aml *if_ctx2;
1933 Aml *else_ctx;
1934 Aml *method;
1935 Aml *a_cwd1 = aml_name("CDW1");
1936 Aml *a_ctrl = aml_name("CTRL");
1937
1938 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1939 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1940
1941 if_ctx = aml_if(aml_equal(
1942 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1943 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1944 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1945
1946 aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1947 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1948
1949 /*
1950 * Always allow native PME, AER (no dependencies)
1951 * Never allow SHPC (no SHPC controller in this system)
1952 */
1953 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
1954
1955 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1956 /* Unknown revision */
1957 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1958 aml_append(if_ctx, if_ctx2);
1959
1960 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1961 /* Capabilities bits were masked */
1962 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1963 aml_append(if_ctx, if_ctx2);
1964
1965 /* Update DWORD3 in the buffer */
1966 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1967 aml_append(method, if_ctx);
1968
1969 else_ctx = aml_else();
1970 /* Unrecognized UUID */
1971 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1972 aml_append(method, else_ctx);
1973
1974 aml_append(method, aml_return(aml_arg(3)));
1975 return method;
1976 }
1977
1978 static void
1979 build_dsdt(GArray *table_data, BIOSLinker *linker,
1980 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1981 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1982 {
1983 CrsRangeEntry *entry;
1984 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1985 CrsRangeSet crs_range_set;
1986 PCMachineState *pcms = PC_MACHINE(machine);
1987 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1988 uint32_t nr_mem = machine->ram_slots;
1989 int root_bus_limit = 0xFF;
1990 PCIBus *bus = NULL;
1991 int i;
1992
1993 dsdt = init_aml_allocator();
1994
1995 /* Reserve space for header */
1996 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1997
1998 build_dbg_aml(dsdt);
1999 if (misc->is_piix4) {
2000 sb_scope = aml_scope("_SB");
2001 dev = aml_device("PCI0");
2002 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
2003 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
2004 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
2005 aml_append(sb_scope, dev);
2006 aml_append(dsdt, sb_scope);
2007
2008 build_hpet_aml(dsdt);
2009 build_piix4_pm(dsdt);
2010 build_piix4_isa_bridge(dsdt);
2011 build_isa_devices_aml(dsdt);
2012 build_piix4_pci_hotplug(dsdt);
2013 build_piix4_pci0_int(dsdt);
2014 } else {
2015 sb_scope = aml_scope("_SB");
2016 aml_append(sb_scope,
2017 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c));
2018 aml_append(sb_scope,
2019 aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01));
2020 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
2021 aml_append(field, aml_named_field("PCIB", 8));
2022 aml_append(sb_scope, field);
2023 aml_append(dsdt, sb_scope);
2024
2025 sb_scope = aml_scope("_SB");
2026 dev = aml_device("PCI0");
2027 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
2028 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
2029 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
2030 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
2031 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
2032 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
2033 aml_append(dev, build_q35_osc_method());
2034 aml_append(sb_scope, dev);
2035 aml_append(dsdt, sb_scope);
2036
2037 build_hpet_aml(dsdt);
2038 build_q35_isa_bridge(dsdt);
2039 build_isa_devices_aml(dsdt);
2040 build_q35_pci0_int(dsdt);
2041 }
2042
2043 if (pcmc->legacy_cpu_hotplug) {
2044 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
2045 } else {
2046 CPUHotplugFeatures opts = {
2047 .apci_1_compatible = true, .has_legacy_cphp = true
2048 };
2049 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
2050 "\\_SB.PCI0", "\\_GPE._E02");
2051 }
2052 build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base,
2053 pm->mem_hp_io_len);
2054
2055 scope = aml_scope("_GPE");
2056 {
2057 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
2058
2059 if (misc->is_piix4) {
2060 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
2061 aml_append(method,
2062 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
2063 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
2064 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
2065 aml_append(scope, method);
2066 }
2067
2068 method = aml_method("_E03", 0, AML_NOTSERIALIZED);
2069 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
2070 aml_append(scope, method);
2071 }
2072 aml_append(dsdt, scope);
2073
2074 crs_range_set_init(&crs_range_set);
2075 bus = PC_MACHINE(machine)->bus;
2076 if (bus) {
2077 QLIST_FOREACH(bus, &bus->child, sibling) {
2078 uint8_t bus_num = pci_bus_num(bus);
2079 uint8_t numa_node = pci_bus_numa_node(bus);
2080
2081 /* look only for expander root buses */
2082 if (!pci_bus_is_root(bus)) {
2083 continue;
2084 }
2085
2086 if (bus_num < root_bus_limit) {
2087 root_bus_limit = bus_num - 1;
2088 }
2089
2090 scope = aml_scope("\\_SB");
2091 dev = aml_device("PC%.02X", bus_num);
2092 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
2093 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
2094 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
2095
2096 if (numa_node != NUMA_NODE_UNASSIGNED) {
2097 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
2098 }
2099
2100 aml_append(dev, build_prt(false));
2101 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
2102 aml_append(dev, aml_name_decl("_CRS", crs));
2103 aml_append(scope, dev);
2104 aml_append(dsdt, scope);
2105 }
2106 }
2107
2108 scope = aml_scope("\\_SB.PCI0");
2109 /* build PCI0._CRS */
2110 crs = aml_resource_template();
2111 aml_append(crs,
2112 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
2113 0x0000, 0x0, root_bus_limit,
2114 0x0000, root_bus_limit + 1));
2115 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
2116
2117 aml_append(crs,
2118 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2119 AML_POS_DECODE, AML_ENTIRE_RANGE,
2120 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
2121
2122 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
2123 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
2124 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
2125 aml_append(crs,
2126 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2127 AML_POS_DECODE, AML_ENTIRE_RANGE,
2128 0x0000, entry->base, entry->limit,
2129 0x0000, entry->limit - entry->base + 1));
2130 }
2131
2132 aml_append(crs,
2133 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2134 AML_CACHEABLE, AML_READ_WRITE,
2135 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2136
2137 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
2138 range_lob(pci_hole),
2139 range_upb(pci_hole));
2140 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
2141 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
2142 aml_append(crs,
2143 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2144 AML_NON_CACHEABLE, AML_READ_WRITE,
2145 0, entry->base, entry->limit,
2146 0, entry->limit - entry->base + 1));
2147 }
2148
2149 if (!range_is_empty(pci_hole64)) {
2150 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
2151 range_lob(pci_hole64),
2152 range_upb(pci_hole64));
2153 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
2154 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
2155 aml_append(crs,
2156 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
2157 AML_MAX_FIXED,
2158 AML_CACHEABLE, AML_READ_WRITE,
2159 0, entry->base, entry->limit,
2160 0, entry->limit - entry->base + 1));
2161 }
2162 }
2163
2164 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2165 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2166 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2167 }
2168 aml_append(scope, aml_name_decl("_CRS", crs));
2169
2170 /* reserve GPE0 block resources */
2171 dev = aml_device("GPE0");
2172 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2173 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2174 /* device present, functioning, decoding, not shown in UI */
2175 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2176 crs = aml_resource_template();
2177 aml_append(crs,
2178 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
2179 );
2180 aml_append(dev, aml_name_decl("_CRS", crs));
2181 aml_append(scope, dev);
2182
2183 crs_range_set_free(&crs_range_set);
2184
2185 /* reserve PCIHP resources */
2186 if (pm->pcihp_io_len) {
2187 dev = aml_device("PHPR");
2188 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2189 aml_append(dev,
2190 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2191 /* device present, functioning, decoding, not shown in UI */
2192 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2193 crs = aml_resource_template();
2194 aml_append(crs,
2195 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2196 pm->pcihp_io_len)
2197 );
2198 aml_append(dev, aml_name_decl("_CRS", crs));
2199 aml_append(scope, dev);
2200 }
2201 aml_append(dsdt, scope);
2202
2203 /* create S3_ / S4_ / S5_ packages if necessary */
2204 scope = aml_scope("\\");
2205 if (!pm->s3_disabled) {
2206 pkg = aml_package(4);
2207 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2208 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2209 aml_append(pkg, aml_int(0)); /* reserved */
2210 aml_append(pkg, aml_int(0)); /* reserved */
2211 aml_append(scope, aml_name_decl("_S3", pkg));
2212 }
2213
2214 if (!pm->s4_disabled) {
2215 pkg = aml_package(4);
2216 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2217 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2218 aml_append(pkg, aml_int(pm->s4_val));
2219 aml_append(pkg, aml_int(0)); /* reserved */
2220 aml_append(pkg, aml_int(0)); /* reserved */
2221 aml_append(scope, aml_name_decl("_S4", pkg));
2222 }
2223
2224 pkg = aml_package(4);
2225 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2226 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2227 aml_append(pkg, aml_int(0)); /* reserved */
2228 aml_append(pkg, aml_int(0)); /* reserved */
2229 aml_append(scope, aml_name_decl("_S5", pkg));
2230 aml_append(dsdt, scope);
2231
2232 /* create fw_cfg node, unconditionally */
2233 {
2234 /* when using port i/o, the 8-bit data register *always* overlaps
2235 * with half of the 16-bit control register. Hence, the total size
2236 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2237 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2238 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2239 "dma_enabled", NULL) ?
2240 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2241 FW_CFG_CTL_SIZE;
2242
2243 scope = aml_scope("\\_SB.PCI0");
2244 dev = aml_device("FWCF");
2245
2246 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2247
2248 /* device present, functioning, decoding, not shown in UI */
2249 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2250
2251 crs = aml_resource_template();
2252 aml_append(crs,
2253 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2254 );
2255 aml_append(dev, aml_name_decl("_CRS", crs));
2256
2257 aml_append(scope, dev);
2258 aml_append(dsdt, scope);
2259 }
2260
2261 if (misc->applesmc_io_base) {
2262 scope = aml_scope("\\_SB.PCI0.ISA");
2263 dev = aml_device("SMC");
2264
2265 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2266 /* device present, functioning, decoding, not shown in UI */
2267 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2268
2269 crs = aml_resource_template();
2270 aml_append(crs,
2271 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2272 0x01, APPLESMC_MAX_DATA_LENGTH)
2273 );
2274 aml_append(crs, aml_irq_no_flags(6));
2275 aml_append(dev, aml_name_decl("_CRS", crs));
2276
2277 aml_append(scope, dev);
2278 aml_append(dsdt, scope);
2279 }
2280
2281 if (misc->pvpanic_port) {
2282 scope = aml_scope("\\_SB.PCI0.ISA");
2283
2284 dev = aml_device("PEVT");
2285 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2286
2287 crs = aml_resource_template();
2288 aml_append(crs,
2289 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2290 );
2291 aml_append(dev, aml_name_decl("_CRS", crs));
2292
2293 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2294 aml_int(misc->pvpanic_port), 1));
2295 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2296 aml_append(field, aml_named_field("PEPT", 8));
2297 aml_append(dev, field);
2298
2299 /* device present, functioning, decoding, shown in UI */
2300 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2301
2302 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2303 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2304 aml_append(method, aml_return(aml_local(0)));
2305 aml_append(dev, method);
2306
2307 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2308 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2309 aml_append(dev, method);
2310
2311 aml_append(scope, dev);
2312 aml_append(dsdt, scope);
2313 }
2314
2315 sb_scope = aml_scope("\\_SB");
2316 {
2317 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base,
2318 pm->mem_hp_io_len);
2319
2320 {
2321 Object *pci_host;
2322 PCIBus *bus = NULL;
2323
2324 pci_host = acpi_get_i386_pci_host();
2325 if (pci_host) {
2326 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2327 }
2328
2329 if (bus) {
2330 Aml *scope = aml_scope("PCI0");
2331 /* Scan all PCI buses. Generate tables to support hotplug. */
2332 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2333
2334 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2335 dev = aml_device("ISA.TPM");
2336 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2337 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2338 crs = aml_resource_template();
2339 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2340 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2341 /*
2342 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2343 Rewrite to take IRQ from TPM device model and
2344 fix default IRQ value there to use some unused IRQ
2345 */
2346 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2347 aml_append(dev, aml_name_decl("_CRS", crs));
2348 aml_append(scope, dev);
2349 }
2350
2351 aml_append(sb_scope, scope);
2352 }
2353 }
2354 aml_append(dsdt, sb_scope);
2355 }
2356
2357 /* copy AML table into ACPI tables blob and patch header there */
2358 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
2359 build_header(linker, table_data,
2360 (void *)(table_data->data + table_data->len - dsdt->buf->len),
2361 "DSDT", dsdt->buf->len, 1, NULL, NULL);
2362 free_aml_allocator();
2363 }
2364
2365 static void
2366 build_hpet(GArray *table_data, BIOSLinker *linker)
2367 {
2368 Acpi20Hpet *hpet;
2369
2370 hpet = acpi_data_push(table_data, sizeof(*hpet));
2371 /* Note timer_block_id value must be kept in sync with value advertised by
2372 * emulated hpet
2373 */
2374 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2375 hpet->addr.address = cpu_to_le64(HPET_BASE);
2376 build_header(linker, table_data,
2377 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
2378 }
2379
2380 static void
2381 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2382 {
2383 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2384 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
2385 unsigned log_addr_offset =
2386 (char *)&tcpa->log_area_start_address - table_data->data;
2387
2388 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2389 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2390 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
2391
2392 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
2393 false /* high memory */);
2394
2395 /* log area start address to be filled by Guest linker */
2396 bios_linker_loader_add_pointer(linker,
2397 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
2398 ACPI_BUILD_TPMLOG_FILE, 0);
2399
2400 build_header(linker, table_data,
2401 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
2402 }
2403
2404 static void
2405 build_tpm2(GArray *table_data, BIOSLinker *linker)
2406 {
2407 Acpi20TPM2 *tpm2_ptr;
2408
2409 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2410
2411 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2412 tpm2_ptr->control_area_address = cpu_to_le64(0);
2413 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2414
2415 build_header(linker, table_data,
2416 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
2417 }
2418
2419 static void
2420 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
2421 {
2422 AcpiSystemResourceAffinityTable *srat;
2423 AcpiSratMemoryAffinity *numamem;
2424
2425 int i;
2426 int srat_start, numa_start, slots;
2427 uint64_t mem_len, mem_base, next_base;
2428 MachineClass *mc = MACHINE_GET_CLASS(machine);
2429 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
2430 PCMachineState *pcms = PC_MACHINE(machine);
2431 ram_addr_t hotplugabble_address_space_size =
2432 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
2433 NULL);
2434
2435 srat_start = table_data->len;
2436
2437 srat = acpi_data_push(table_data, sizeof *srat);
2438 srat->reserved1 = cpu_to_le32(1);
2439
2440 for (i = 0; i < apic_ids->len; i++) {
2441 int j = numa_get_node_for_cpu(i);
2442 uint32_t apic_id = apic_ids->cpus[i].arch_id;
2443
2444 if (apic_id < 255) {
2445 AcpiSratProcessorAffinity *core;
2446
2447 core = acpi_data_push(table_data, sizeof *core);
2448 core->type = ACPI_SRAT_PROCESSOR_APIC;
2449 core->length = sizeof(*core);
2450 core->local_apic_id = apic_id;
2451 if (j < nb_numa_nodes) {
2452 core->proximity_lo = j;
2453 }
2454 memset(core->proximity_hi, 0, 3);
2455 core->local_sapic_eid = 0;
2456 core->flags = cpu_to_le32(1);
2457 } else {
2458 AcpiSratProcessorX2ApicAffinity *core;
2459
2460 core = acpi_data_push(table_data, sizeof *core);
2461 core->type = ACPI_SRAT_PROCESSOR_x2APIC;
2462 core->length = sizeof(*core);
2463 core->x2apic_id = cpu_to_le32(apic_id);
2464 if (j < nb_numa_nodes) {
2465 core->proximity_domain = cpu_to_le32(j);
2466 }
2467 core->flags = cpu_to_le32(1);
2468 }
2469 }
2470
2471
2472 /* the memory map is a bit tricky, it contains at least one hole
2473 * from 640k-1M and possibly another one from 3.5G-4G.
2474 */
2475 next_base = 0;
2476 numa_start = table_data->len;
2477
2478 numamem = acpi_data_push(table_data, sizeof *numamem);
2479 build_srat_memory(numamem, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED);
2480 next_base = 1024 * 1024;
2481 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2482 mem_base = next_base;
2483 mem_len = pcms->node_mem[i - 1];
2484 if (i == 1) {
2485 mem_len -= 1024 * 1024;
2486 }
2487 next_base = mem_base + mem_len;
2488
2489 /* Cut out the ACPI_PCI hole */
2490 if (mem_base <= pcms->below_4g_mem_size &&
2491 next_base > pcms->below_4g_mem_size) {
2492 mem_len -= next_base - pcms->below_4g_mem_size;
2493 if (mem_len > 0) {
2494 numamem = acpi_data_push(table_data, sizeof *numamem);
2495 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2496 MEM_AFFINITY_ENABLED);
2497 }
2498 mem_base = 1ULL << 32;
2499 mem_len = next_base - pcms->below_4g_mem_size;
2500 next_base += (1ULL << 32) - pcms->below_4g_mem_size;
2501 }
2502 numamem = acpi_data_push(table_data, sizeof *numamem);
2503 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2504 MEM_AFFINITY_ENABLED);
2505 }
2506 slots = (table_data->len - numa_start) / sizeof *numamem;
2507 for (; slots < pcms->numa_nodes + 2; slots++) {
2508 numamem = acpi_data_push(table_data, sizeof *numamem);
2509 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2510 }
2511
2512 /*
2513 * Entry is required for Windows to enable memory hotplug in OS.
2514 * Memory devices may override proximity set by this entry,
2515 * providing _PXM method if necessary.
2516 */
2517 if (hotplugabble_address_space_size) {
2518 numamem = acpi_data_push(table_data, sizeof *numamem);
2519 build_srat_memory(numamem, pcms->hotplug_memory.base,
2520 hotplugabble_address_space_size, 0,
2521 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2522 }
2523
2524 build_header(linker, table_data,
2525 (void *)(table_data->data + srat_start),
2526 "SRAT",
2527 table_data->len - srat_start, 1, NULL, NULL);
2528 g_free(apic_ids);
2529 }
2530
2531 static void
2532 build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info)
2533 {
2534 AcpiTableMcfg *mcfg;
2535 const char *sig;
2536 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2537
2538 mcfg = acpi_data_push(table_data, len);
2539 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2540 /* Only a single allocation so no need to play with segments */
2541 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2542 mcfg->allocation[0].start_bus_number = 0;
2543 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2544
2545 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2546 * To avoid table size changes (which create migration issues),
2547 * always create the table even if there are no allocations,
2548 * but set the signature to a reserved value in this case.
2549 * ACPI spec requires OSPMs to ignore such tables.
2550 */
2551 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
2552 /* Reserved signature: ignored by OSPM */
2553 sig = "QEMU";
2554 } else {
2555 sig = "MCFG";
2556 }
2557 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
2558 }
2559
2560 /*
2561 * VT-d spec 8.1 DMA Remapping Reporting Structure
2562 * (version Oct. 2014 or later)
2563 */
2564 static void
2565 build_dmar_q35(GArray *table_data, BIOSLinker *linker)
2566 {
2567 int dmar_start = table_data->len;
2568
2569 AcpiTableDmar *dmar;
2570 AcpiDmarHardwareUnit *drhd;
2571 uint8_t dmar_flags = 0;
2572 X86IOMMUState *iommu = x86_iommu_get_default();
2573 AcpiDmarDeviceScope *scope = NULL;
2574 /* Root complex IOAPIC use one path[0] only */
2575 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
2576
2577 assert(iommu);
2578 if (iommu->intr_supported) {
2579 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2580 }
2581
2582 dmar = acpi_data_push(table_data, sizeof(*dmar));
2583 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
2584 dmar->flags = dmar_flags;
2585
2586 /* DMAR Remapping Hardware Unit Definition structure */
2587 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
2588 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2589 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
2590 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2591 drhd->pci_segment = cpu_to_le16(0);
2592 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2593
2594 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2595 * 8.3.1 (version Oct. 2014 or later). */
2596 scope = &drhd->scope[0];
2597 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
2598 scope->length = ioapic_scope_size;
2599 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2600 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
2601 scope->path[0] = cpu_to_le16(Q35_PSEUDO_DEVFN_IOAPIC);
2602
2603 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2604 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2605 }
2606 /*
2607 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2608 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2609 */
2610 static void
2611 build_amd_iommu(GArray *table_data, BIOSLinker *linker)
2612 {
2613 int iommu_start = table_data->len;
2614 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2615
2616 /* IVRS header */
2617 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2618 /* IVinfo - IO virtualization information common to all
2619 * IOMMU units in a system
2620 */
2621 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2622 /* reserved */
2623 build_append_int_noprefix(table_data, 0, 8);
2624
2625 /* IVHD definition - type 10h */
2626 build_append_int_noprefix(table_data, 0x10, 1);
2627 /* virtualization flags */
2628 build_append_int_noprefix(table_data,
2629 (1UL << 0) | /* HtTunEn */
2630 (1UL << 4) | /* iotblSup */
2631 (1UL << 6) | /* PrefSup */
2632 (1UL << 7), /* PPRSup */
2633 1);
2634 /* IVHD length */
2635 build_append_int_noprefix(table_data, 0x24, 2);
2636 /* DeviceID */
2637 build_append_int_noprefix(table_data, s->devid, 2);
2638 /* Capability offset */
2639 build_append_int_noprefix(table_data, s->capab_offset, 2);
2640 /* IOMMU base address */
2641 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2642 /* PCI Segment Group */
2643 build_append_int_noprefix(table_data, 0, 2);
2644 /* IOMMU info */
2645 build_append_int_noprefix(table_data, 0, 2);
2646 /* IOMMU Feature Reporting */
2647 build_append_int_noprefix(table_data,
2648 (48UL << 30) | /* HATS */
2649 (48UL << 28) | /* GATS */
2650 (1UL << 2), /* GTSup */
2651 4);
2652 /*
2653 * Type 1 device entry reporting all devices
2654 * These are 4-byte device entries currently reporting the range of
2655 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2656 */
2657 build_append_int_noprefix(table_data, 0x0000001, 4);
2658
2659 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2660 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2661 }
2662
2663 static GArray *
2664 build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset)
2665 {
2666 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2667 unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address);
2668 unsigned rsdt_pa_offset =
2669 (char *)&rsdp->rsdt_physical_address - rsdp_table->data;
2670
2671 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16,
2672 true /* fseg memory */);
2673
2674 memcpy(&rsdp->signature, "RSD PTR ", 8);
2675 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
2676 /* Address to be filled by Guest linker */
2677 bios_linker_loader_add_pointer(linker,
2678 ACPI_BUILD_RSDP_FILE, rsdt_pa_offset, rsdt_pa_size,
2679 ACPI_BUILD_TABLE_FILE, rsdt_tbl_offset);
2680
2681 /* Checksum to be filled by Guest linker */
2682 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
2683 (char *)rsdp - rsdp_table->data, sizeof *rsdp,
2684 (char *)&rsdp->checksum - rsdp_table->data);
2685
2686 return rsdp_table;
2687 }
2688
2689 typedef
2690 struct AcpiBuildState {
2691 /* Copy of table in RAM (for patching). */
2692 MemoryRegion *table_mr;
2693 /* Is table patched? */
2694 uint8_t patched;
2695 void *rsdp;
2696 MemoryRegion *rsdp_mr;
2697 MemoryRegion *linker_mr;
2698 } AcpiBuildState;
2699
2700 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2701 {
2702 Object *pci_host;
2703 QObject *o;
2704
2705 pci_host = acpi_get_i386_pci_host();
2706 g_assert(pci_host);
2707
2708 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2709 if (!o) {
2710 return false;
2711 }
2712 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
2713 qobject_decref(o);
2714
2715 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2716 assert(o);
2717 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
2718 qobject_decref(o);
2719 return true;
2720 }
2721
2722 static
2723 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2724 {
2725 PCMachineState *pcms = PC_MACHINE(machine);
2726 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2727 GArray *table_offsets;
2728 unsigned facs, dsdt, rsdt, fadt;
2729 AcpiPmInfo pm;
2730 AcpiMiscInfo misc;
2731 AcpiMcfgInfo mcfg;
2732 Range pci_hole, pci_hole64;
2733 uint8_t *u;
2734 size_t aml_len = 0;
2735 GArray *tables_blob = tables->table_data;
2736 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2737
2738 acpi_get_pm_info(&pm);
2739 acpi_get_misc_info(&misc);
2740 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2741 acpi_get_slic_oem(&slic_oem);
2742
2743 table_offsets = g_array_new(false, true /* clear */,
2744 sizeof(uint32_t));
2745 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2746
2747 bios_linker_loader_alloc(tables->linker,
2748 ACPI_BUILD_TABLE_FILE, tables_blob,
2749 64 /* Ensure FACS is aligned */,
2750 false /* high memory */);
2751
2752 /*
2753 * FACS is pointed to by FADT.
2754 * We place it first since it's the only table that has alignment
2755 * requirements.
2756 */
2757 facs = tables_blob->len;
2758 build_facs(tables_blob, tables->linker);
2759
2760 /* DSDT is pointed to by FADT */
2761 dsdt = tables_blob->len;
2762 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2763 &pci_hole, &pci_hole64, machine);
2764
2765 /* Count the size of the DSDT and SSDT, we will need it for legacy
2766 * sizing of ACPI tables.
2767 */
2768 aml_len += tables_blob->len - dsdt;
2769
2770 /* ACPI tables pointed to by RSDT */
2771 fadt = tables_blob->len;
2772 acpi_add_table(table_offsets, tables_blob);
2773 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt,
2774 slic_oem.id, slic_oem.table_id);
2775 aml_len += tables_blob->len - fadt;
2776
2777 acpi_add_table(table_offsets, tables_blob);
2778 build_madt(tables_blob, tables->linker, pcms);
2779
2780 if (misc.has_hpet) {
2781 acpi_add_table(table_offsets, tables_blob);
2782 build_hpet(tables_blob, tables->linker);
2783 }
2784 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2785 acpi_add_table(table_offsets, tables_blob);
2786 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2787
2788 if (misc.tpm_version == TPM_VERSION_2_0) {
2789 acpi_add_table(table_offsets, tables_blob);
2790 build_tpm2(tables_blob, tables->linker);
2791 }
2792 }
2793 if (pcms->numa_nodes) {
2794 acpi_add_table(table_offsets, tables_blob);
2795 build_srat(tables_blob, tables->linker, machine);
2796 }
2797 if (acpi_get_mcfg(&mcfg)) {
2798 acpi_add_table(table_offsets, tables_blob);
2799 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2800 }
2801 if (x86_iommu_get_default()) {
2802 IommuType IOMMUType = x86_iommu_get_type();
2803 if (IOMMUType == TYPE_AMD) {
2804 acpi_add_table(table_offsets, tables_blob);
2805 build_amd_iommu(tables_blob, tables->linker);
2806 } else if (IOMMUType == TYPE_INTEL) {
2807 acpi_add_table(table_offsets, tables_blob);
2808 build_dmar_q35(tables_blob, tables->linker);
2809 }
2810 }
2811 if (pcms->acpi_nvdimm_state.is_enabled) {
2812 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2813 pcms->acpi_nvdimm_state.dsm_mem);
2814 }
2815
2816 /* Add tables supplied by user (if any) */
2817 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2818 unsigned len = acpi_table_len(u);
2819
2820 acpi_add_table(table_offsets, tables_blob);
2821 g_array_append_vals(tables_blob, u, len);
2822 }
2823
2824 /* RSDT is pointed to by RSDP */
2825 rsdt = tables_blob->len;
2826 build_rsdt(tables_blob, tables->linker, table_offsets,
2827 slic_oem.id, slic_oem.table_id);
2828
2829 /* RSDP is in FSEG memory, so allocate it separately */
2830 build_rsdp(tables->rsdp, tables->linker, rsdt);
2831
2832 /* We'll expose it all to Guest so we want to reduce
2833 * chance of size changes.
2834 *
2835 * We used to align the tables to 4k, but of course this would
2836 * too simple to be enough. 4k turned out to be too small an
2837 * alignment very soon, and in fact it is almost impossible to
2838 * keep the table size stable for all (max_cpus, max_memory_slots)
2839 * combinations. So the table size is always 64k for pc-i440fx-2.1
2840 * and we give an error if the table grows beyond that limit.
2841 *
2842 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2843 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2844 * than 2.0 and we can always pad the smaller tables with zeros. We can
2845 * then use the exact size of the 2.0 tables.
2846 *
2847 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2848 */
2849 if (pcmc->legacy_acpi_table_size) {
2850 /* Subtracting aml_len gives the size of fixed tables. Then add the
2851 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2852 */
2853 int legacy_aml_len =
2854 pcmc->legacy_acpi_table_size +
2855 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
2856 int legacy_table_size =
2857 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2858 ACPI_BUILD_ALIGN_SIZE);
2859 if (tables_blob->len > legacy_table_size) {
2860 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2861 error_report("Warning: migration may not work.");
2862 }
2863 g_array_set_size(tables_blob, legacy_table_size);
2864 } else {
2865 /* Make sure we have a buffer in case we need to resize the tables. */
2866 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2867 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2868 error_report("Warning: ACPI tables are larger than 64k.");
2869 error_report("Warning: migration may not work.");
2870 error_report("Warning: please remove CPUs, NUMA nodes, "
2871 "memory slots or PCI bridges.");
2872 }
2873 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2874 }
2875
2876 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2877
2878 /* Cleanup memory that's no longer used. */
2879 g_array_free(table_offsets, true);
2880 }
2881
2882 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2883 {
2884 uint32_t size = acpi_data_len(data);
2885
2886 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2887 memory_region_ram_resize(mr, size, &error_abort);
2888
2889 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2890 memory_region_set_dirty(mr, 0, size);
2891 }
2892
2893 static void acpi_build_update(void *build_opaque)
2894 {
2895 AcpiBuildState *build_state = build_opaque;
2896 AcpiBuildTables tables;
2897
2898 /* No state to update or already patched? Nothing to do. */
2899 if (!build_state || build_state->patched) {
2900 return;
2901 }
2902 build_state->patched = 1;
2903
2904 acpi_build_tables_init(&tables);
2905
2906 acpi_build(&tables, MACHINE(qdev_get_machine()));
2907
2908 acpi_ram_update(build_state->table_mr, tables.table_data);
2909
2910 if (build_state->rsdp) {
2911 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2912 } else {
2913 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2914 }
2915
2916 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2917 acpi_build_tables_cleanup(&tables, true);
2918 }
2919
2920 static void acpi_build_reset(void *build_opaque)
2921 {
2922 AcpiBuildState *build_state = build_opaque;
2923 build_state->patched = 0;
2924 }
2925
2926 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2927 GArray *blob, const char *name,
2928 uint64_t max_size)
2929 {
2930 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2931 name, acpi_build_update, build_state);
2932 }
2933
2934 static const VMStateDescription vmstate_acpi_build = {
2935 .name = "acpi_build",
2936 .version_id = 1,
2937 .minimum_version_id = 1,
2938 .fields = (VMStateField[]) {
2939 VMSTATE_UINT8(patched, AcpiBuildState),
2940 VMSTATE_END_OF_LIST()
2941 },
2942 };
2943
2944 void acpi_setup(void)
2945 {
2946 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2947 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2948 AcpiBuildTables tables;
2949 AcpiBuildState *build_state;
2950
2951 if (!pcms->fw_cfg) {
2952 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2953 return;
2954 }
2955
2956 if (!pcmc->has_acpi_build) {
2957 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2958 return;
2959 }
2960
2961 if (!acpi_enabled) {
2962 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2963 return;
2964 }
2965
2966 build_state = g_malloc0(sizeof *build_state);
2967
2968 acpi_set_pci_info();
2969
2970 acpi_build_tables_init(&tables);
2971 acpi_build(&tables, MACHINE(pcms));
2972
2973 /* Now expose it all to Guest */
2974 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
2975 ACPI_BUILD_TABLE_FILE,
2976 ACPI_BUILD_TABLE_MAX_SIZE);
2977 assert(build_state->table_mr != NULL);
2978
2979 build_state->linker_mr =
2980 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
2981 "etc/table-loader", 0);
2982
2983 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2984 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2985
2986 if (!pcmc->rsdp_in_ram) {
2987 /*
2988 * Keep for compatibility with old machine types.
2989 * Though RSDP is small, its contents isn't immutable, so
2990 * we'll update it along with the rest of tables on guest access.
2991 */
2992 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2993
2994 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2995 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2996 acpi_build_update, build_state,
2997 build_state->rsdp, rsdp_size);
2998 build_state->rsdp_mr = NULL;
2999 } else {
3000 build_state->rsdp = NULL;
3001 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
3002 ACPI_BUILD_RSDP_FILE, 0);
3003 }
3004
3005 qemu_register_reset(acpi_build_reset, build_state);
3006 acpi_build_reset(build_state);
3007 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
3008
3009 /* Cleanup tables but don't free the memory: we track it
3010 * in build_state.
3011 */
3012 acpi_build_tables_cleanup(&tables, false);
3013 }
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