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[mirror_qemu.git] / hw / i386 / acpi-build.c
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "acpi-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "hw/core/cpu.h"
32 #include "target/i386/cpu.h"
33 #include "hw/misc/pvpanic.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "sysemu/tpm_backend.h"
47 #include "hw/rtc/mc146818rtc_regs.h"
48 #include "migration/vmstate.h"
49 #include "hw/mem/memory-device.h"
50 #include "hw/mem/nvdimm.h"
51 #include "sysemu/numa.h"
52 #include "sysemu/reset.h"
53 #include "hw/hyperv/vmbus-bridge.h"
54
55 /* Supported chipsets: */
56 #include "hw/southbridge/piix.h"
57 #include "hw/acpi/pcihp.h"
58 #include "hw/i386/fw_cfg.h"
59 #include "hw/i386/ich9.h"
60 #include "hw/pci/pci_bus.h"
61 #include "hw/pci-host/q35.h"
62 #include "hw/i386/x86-iommu.h"
63
64 #include "hw/acpi/aml-build.h"
65 #include "hw/acpi/utils.h"
66 #include "hw/acpi/pci.h"
67
68 #include "qom/qom-qobject.h"
69 #include "hw/i386/amd_iommu.h"
70 #include "hw/i386/intel_iommu.h"
71
72 #include "hw/acpi/ipmi.h"
73 #include "hw/acpi/hmat.h"
74
75 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
76 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
77 * a little bit, there should be plenty of free space since the DSDT
78 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
79 */
80 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
81 #define ACPI_BUILD_ALIGN_SIZE 0x1000
82
83 #define ACPI_BUILD_TABLE_SIZE 0x20000
84
85 /* #define DEBUG_ACPI_BUILD */
86 #ifdef DEBUG_ACPI_BUILD
87 #define ACPI_BUILD_DPRINTF(fmt, ...) \
88 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
89 #else
90 #define ACPI_BUILD_DPRINTF(fmt, ...)
91 #endif
92
93 typedef struct AcpiPmInfo {
94 bool s3_disabled;
95 bool s4_disabled;
96 bool pcihp_bridge_en;
97 bool smi_on_cpuhp;
98 bool smi_on_cpu_unplug;
99 bool pcihp_root_en;
100 uint8_t s4_val;
101 AcpiFadtData fadt;
102 uint16_t cpu_hp_io_base;
103 uint16_t pcihp_io_base;
104 uint16_t pcihp_io_len;
105 } AcpiPmInfo;
106
107 typedef struct AcpiMiscInfo {
108 bool is_piix4;
109 bool has_hpet;
110 TPMVersion tpm_version;
111 const unsigned char *dsdt_code;
112 unsigned dsdt_size;
113 uint16_t pvpanic_port;
114 uint16_t applesmc_io_base;
115 } AcpiMiscInfo;
116
117 typedef struct AcpiBuildPciBusHotplugState {
118 GArray *device_table;
119 GArray *notify_table;
120 struct AcpiBuildPciBusHotplugState *parent;
121 bool pcihp_bridge_en;
122 } AcpiBuildPciBusHotplugState;
123
124 typedef struct FwCfgTPMConfig {
125 uint32_t tpmppi_address;
126 uint8_t tpm_version;
127 uint8_t tpmppi_version;
128 } QEMU_PACKED FwCfgTPMConfig;
129
130 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
131
132 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = {
133 .space_id = AML_AS_SYSTEM_IO,
134 .address = NVDIMM_ACPI_IO_BASE,
135 .bit_width = NVDIMM_ACPI_IO_LEN << 3
136 };
137
138 static void init_common_fadt_data(MachineState *ms, Object *o,
139 AcpiFadtData *data)
140 {
141 X86MachineState *x86ms = X86_MACHINE(ms);
142 /*
143 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old
144 * behavior for compatibility irrelevant to smm_enabled, which doesn't
145 * comforms to ACPI spec.
146 */
147 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ?
148 true : x86_machine_is_smm_enabled(x86ms);
149 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
150 AmlAddressSpace as = AML_AS_SYSTEM_IO;
151 AcpiFadtData fadt = {
152 .rev = 3,
153 .flags =
154 (1 << ACPI_FADT_F_WBINVD) |
155 (1 << ACPI_FADT_F_PROC_C1) |
156 (1 << ACPI_FADT_F_SLP_BUTTON) |
157 (1 << ACPI_FADT_F_RTC_S4) |
158 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
159 /* APIC destination mode ("Flat Logical") has an upper limit of 8
160 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
161 * used
162 */
163 ((ms->smp.max_cpus > 8) ?
164 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
165 .int_model = 1 /* Multiple APIC */,
166 .rtc_century = RTC_CENTURY,
167 .plvl2_lat = 0xfff /* C2 state not supported */,
168 .plvl3_lat = 0xfff /* C3 state not supported */,
169 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0,
170 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
171 .acpi_enable_cmd =
172 smm_enabled ?
173 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) :
174 0,
175 .acpi_disable_cmd =
176 smm_enabled ?
177 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) :
178 0,
179 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
180 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
181 .address = io + 0x04 },
182 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
183 .gpe0_blk = { .space_id = as, .bit_width =
184 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
185 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
186 },
187 };
188 *data = fadt;
189 }
190
191 static Object *object_resolve_type_unambiguous(const char *typename)
192 {
193 bool ambig;
194 Object *o = object_resolve_path_type("", typename, &ambig);
195
196 if (ambig || !o) {
197 return NULL;
198 }
199 return o;
200 }
201
202 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
203 {
204 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
205 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
206 Object *obj = piix ? piix : lpc;
207 QObject *o;
208 pm->cpu_hp_io_base = 0;
209 pm->pcihp_io_base = 0;
210 pm->pcihp_io_len = 0;
211 pm->smi_on_cpuhp = false;
212 pm->smi_on_cpu_unplug = false;
213
214 assert(obj);
215 init_common_fadt_data(machine, obj, &pm->fadt);
216 if (piix) {
217 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
218 pm->fadt.rev = 1;
219 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
220 pm->pcihp_io_base =
221 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
222 pm->pcihp_io_len =
223 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
224 }
225 if (lpc) {
226 uint64_t smi_features = object_property_get_uint(lpc,
227 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL);
228 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
229 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
230 pm->fadt.reset_reg = r;
231 pm->fadt.reset_val = 0xf;
232 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
233 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
234 pm->smi_on_cpuhp =
235 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT));
236 pm->smi_on_cpu_unplug =
237 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT));
238 }
239
240 /* The above need not be conditional on machine type because the reset port
241 * happens to be the same on PIIX (pc) and ICH9 (q35). */
242 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);
243
244 /* Fill in optional s3/s4 related properties */
245 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
246 if (o) {
247 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
248 } else {
249 pm->s3_disabled = false;
250 }
251 qobject_unref(o);
252 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
253 if (o) {
254 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
255 } else {
256 pm->s4_disabled = false;
257 }
258 qobject_unref(o);
259 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
260 if (o) {
261 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
262 } else {
263 pm->s4_val = false;
264 }
265 qobject_unref(o);
266
267 pm->pcihp_bridge_en =
268 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
269 NULL);
270 pm->pcihp_root_en =
271 object_property_get_bool(obj, "acpi-root-pci-hotplug",
272 NULL);
273 }
274
275 static void acpi_get_misc_info(AcpiMiscInfo *info)
276 {
277 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
278 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
279 assert(!!piix != !!lpc);
280
281 if (piix) {
282 info->is_piix4 = true;
283 }
284 if (lpc) {
285 info->is_piix4 = false;
286 }
287
288 info->has_hpet = hpet_find();
289 info->tpm_version = tpm_get_version(tpm_find());
290 info->pvpanic_port = pvpanic_port();
291 info->applesmc_io_base = applesmc_port();
292 }
293
294 /*
295 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
296 * On i386 arch we only have two pci hosts, so we can look only for them.
297 */
298 static Object *acpi_get_i386_pci_host(void)
299 {
300 PCIHostState *host;
301
302 host = OBJECT_CHECK(PCIHostState,
303 object_resolve_path("/machine/i440fx", NULL),
304 TYPE_PCI_HOST_BRIDGE);
305 if (!host) {
306 host = OBJECT_CHECK(PCIHostState,
307 object_resolve_path("/machine/q35", NULL),
308 TYPE_PCI_HOST_BRIDGE);
309 }
310
311 return OBJECT(host);
312 }
313
314 static void acpi_get_pci_holes(Range *hole, Range *hole64)
315 {
316 Object *pci_host;
317
318 pci_host = acpi_get_i386_pci_host();
319 g_assert(pci_host);
320
321 range_set_bounds1(hole,
322 object_property_get_uint(pci_host,
323 PCI_HOST_PROP_PCI_HOLE_START,
324 NULL),
325 object_property_get_uint(pci_host,
326 PCI_HOST_PROP_PCI_HOLE_END,
327 NULL));
328 range_set_bounds1(hole64,
329 object_property_get_uint(pci_host,
330 PCI_HOST_PROP_PCI_HOLE64_START,
331 NULL),
332 object_property_get_uint(pci_host,
333 PCI_HOST_PROP_PCI_HOLE64_END,
334 NULL));
335 }
336
337 static void acpi_align_size(GArray *blob, unsigned align)
338 {
339 /* Align size to multiple of given size. This reduces the chance
340 * we need to change size in the future (breaking cross version migration).
341 */
342 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
343 }
344
345 /* FACS */
346 static void
347 build_facs(GArray *table_data)
348 {
349 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
350 memcpy(&facs->signature, "FACS", 4);
351 facs->length = cpu_to_le32(sizeof(*facs));
352 }
353
354 static void build_append_pcihp_notify_entry(Aml *method, int slot)
355 {
356 Aml *if_ctx;
357 int32_t devfn = PCI_DEVFN(slot, 0);
358
359 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
360 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
361 aml_append(method, if_ctx);
362 }
363
364 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
365 bool pcihp_bridge_en)
366 {
367 Aml *dev, *notify_method = NULL, *method;
368 QObject *bsel;
369 PCIBus *sec;
370 int i;
371
372 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
373 if (bsel) {
374 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
375
376 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
377 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
378 }
379
380 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
381 DeviceClass *dc;
382 PCIDeviceClass *pc;
383 PCIDevice *pdev = bus->devices[i];
384 int slot = PCI_SLOT(i);
385 bool hotplug_enabled_dev;
386 bool bridge_in_acpi;
387 bool cold_plugged_bridge;
388
389 if (!pdev) {
390 if (bsel) { /* add hotplug slots for non present devices */
391 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
392 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
393 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
394 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
395 aml_append(method,
396 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
397 );
398 aml_append(dev, method);
399 method = aml_method("_DSM", 4, AML_SERIALIZED);
400 aml_append(method,
401 aml_return(aml_call6("PDSM", aml_arg(0), aml_arg(1),
402 aml_arg(2), aml_arg(3),
403 aml_name("BSEL"), aml_name("_SUN")))
404 );
405 aml_append(dev, method);
406 aml_append(parent_scope, dev);
407
408 build_append_pcihp_notify_entry(notify_method, slot);
409 }
410 continue;
411 }
412
413 pc = PCI_DEVICE_GET_CLASS(pdev);
414 dc = DEVICE_GET_CLASS(pdev);
415
416 /*
417 * Cold plugged bridges aren't themselves hot-pluggable.
418 * Hotplugged bridges *are* hot-pluggable.
419 */
420 cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged;
421 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en;
422
423 hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge;
424
425 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
426 continue;
427 }
428
429 /* start to compose PCI slot descriptor */
430 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
431 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
432
433 if (bsel) {
434 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
435 method = aml_method("_DSM", 4, AML_SERIALIZED);
436 aml_append(method, aml_return(
437 aml_call6("PDSM", aml_arg(0), aml_arg(1), aml_arg(2),
438 aml_arg(3), aml_name("BSEL"), aml_name("_SUN"))
439 ));
440 aml_append(dev, method);
441 }
442
443 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
444 /* add VGA specific AML methods */
445 int s3d;
446
447 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
448 s3d = 3;
449 } else {
450 s3d = 0;
451 }
452
453 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
454 aml_append(method, aml_return(aml_int(0)));
455 aml_append(dev, method);
456
457 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
458 aml_append(method, aml_return(aml_int(0)));
459 aml_append(dev, method);
460
461 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
462 aml_append(method, aml_return(aml_int(s3d)));
463 aml_append(dev, method);
464 } else if (hotplug_enabled_dev) {
465 /* add _EJ0 to make slot hotpluggable */
466 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
467 aml_append(method,
468 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
469 );
470 aml_append(dev, method);
471
472 if (bsel) {
473 build_append_pcihp_notify_entry(notify_method, slot);
474 }
475 } else if (bridge_in_acpi) {
476 /*
477 * device is coldplugged bridge,
478 * add child device descriptions into its scope
479 */
480 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
481
482 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
483 }
484 /* slot descriptor has been composed, add it into parent context */
485 aml_append(parent_scope, dev);
486 }
487
488 if (bsel) {
489 aml_append(parent_scope, notify_method);
490 }
491
492 /* Append PCNT method to notify about events on local and child buses.
493 * Add this method for root bus only when hotplug is enabled since DSDT
494 * expects it.
495 */
496 if (bsel || pcihp_bridge_en) {
497 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
498
499 /* If bus supports hotplug select it and notify about local events */
500 if (bsel) {
501 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
502
503 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
504 aml_append(method, aml_call2("DVNT", aml_name("PCIU"),
505 aml_int(1))); /* Device Check */
506 aml_append(method, aml_call2("DVNT", aml_name("PCID"),
507 aml_int(3))); /* Eject Request */
508 }
509
510 /* Notify about child bus events in any case */
511 if (pcihp_bridge_en) {
512 QLIST_FOREACH(sec, &bus->child, sibling) {
513 int32_t devfn = sec->parent_dev->devfn;
514
515 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
516 continue;
517 }
518
519 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
520 }
521 }
522
523 aml_append(parent_scope, method);
524 }
525 qobject_unref(bsel);
526 }
527
528 Aml *aml_pci_device_dsm(void)
529 {
530 Aml *method, *UUID, *ifctx, *ifctx1, *ifctx2, *ifctx3, *elsectx;
531 Aml *acpi_index = aml_local(0);
532 Aml *zero = aml_int(0);
533 Aml *bnum = aml_arg(4);
534 Aml *func = aml_arg(2);
535 Aml *rev = aml_arg(1);
536 Aml *sun = aml_arg(5);
537
538 method = aml_method("PDSM", 6, AML_SERIALIZED);
539
540 /*
541 * PCI Firmware Specification 3.1
542 * 4.6. _DSM Definitions for PCI
543 */
544 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
545 ifctx = aml_if(aml_equal(aml_arg(0), UUID));
546 {
547 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sun), acpi_index));
548 ifctx1 = aml_if(aml_equal(func, zero));
549 {
550 uint8_t byte_list[1];
551
552 ifctx2 = aml_if(aml_equal(rev, aml_int(2)));
553 {
554 /*
555 * advertise function 7 if device has acpi-index
556 * acpi_index values:
557 * 0: not present (default value)
558 * FFFFFFFF: not supported (old QEMU without PIDX reg)
559 * other: device's acpi-index
560 */
561 ifctx3 = aml_if(aml_lnot(
562 aml_or(aml_equal(acpi_index, zero),
563 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL)
564 ));
565 {
566 byte_list[0] =
567 1 /* have supported functions */ |
568 1 << 7 /* support for function 7 */
569 ;
570 aml_append(ifctx3, aml_return(aml_buffer(1, byte_list)));
571 }
572 aml_append(ifctx2, ifctx3);
573 }
574 aml_append(ifctx1, ifctx2);
575
576 byte_list[0] = 0; /* nothing supported */
577 aml_append(ifctx1, aml_return(aml_buffer(1, byte_list)));
578 }
579 aml_append(ifctx, ifctx1);
580 elsectx = aml_else();
581 /*
582 * PCI Firmware Specification 3.1
583 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
584 * Operating Systems
585 */
586 ifctx1 = aml_if(aml_equal(func, aml_int(7)));
587 {
588 Aml *pkg = aml_package(2);
589 Aml *ret = aml_local(1);
590
591 aml_append(pkg, zero);
592 /*
593 * optional, if not impl. should return null string
594 */
595 aml_append(pkg, aml_string("%s", ""));
596 aml_append(ifctx1, aml_store(pkg, ret));
597 /*
598 * update acpi-index to actual value
599 */
600 aml_append(ifctx1, aml_store(acpi_index, aml_index(ret, zero)));
601 aml_append(ifctx1, aml_return(ret));
602 }
603 aml_append(elsectx, ifctx1);
604 aml_append(ifctx, elsectx);
605 }
606 aml_append(method, ifctx);
607 return method;
608 }
609
610 /**
611 * build_prt_entry:
612 * @link_name: link name for PCI route entry
613 *
614 * build AML package containing a PCI route entry for @link_name
615 */
616 static Aml *build_prt_entry(const char *link_name)
617 {
618 Aml *a_zero = aml_int(0);
619 Aml *pkg = aml_package(4);
620 aml_append(pkg, a_zero);
621 aml_append(pkg, a_zero);
622 aml_append(pkg, aml_name("%s", link_name));
623 aml_append(pkg, a_zero);
624 return pkg;
625 }
626
627 /*
628 * initialize_route - Initialize the interrupt routing rule
629 * through a specific LINK:
630 * if (lnk_idx == idx)
631 * route using link 'link_name'
632 */
633 static Aml *initialize_route(Aml *route, const char *link_name,
634 Aml *lnk_idx, int idx)
635 {
636 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
637 Aml *pkg = build_prt_entry(link_name);
638
639 aml_append(if_ctx, aml_store(pkg, route));
640
641 return if_ctx;
642 }
643
644 /*
645 * build_prt - Define interrupt rounting rules
646 *
647 * Returns an array of 128 routes, one for each device,
648 * based on device location.
649 * The main goal is to equaly distribute the interrupts
650 * over the 4 existing ACPI links (works only for i440fx).
651 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
652 *
653 */
654 static Aml *build_prt(bool is_pci0_prt)
655 {
656 Aml *method, *while_ctx, *pin, *res;
657
658 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
659 res = aml_local(0);
660 pin = aml_local(1);
661 aml_append(method, aml_store(aml_package(128), res));
662 aml_append(method, aml_store(aml_int(0), pin));
663
664 /* while (pin < 128) */
665 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
666 {
667 Aml *slot = aml_local(2);
668 Aml *lnk_idx = aml_local(3);
669 Aml *route = aml_local(4);
670
671 /* slot = pin >> 2 */
672 aml_append(while_ctx,
673 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
674 /* lnk_idx = (slot + pin) & 3 */
675 aml_append(while_ctx,
676 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
677 lnk_idx));
678
679 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
680 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
681 if (is_pci0_prt) {
682 Aml *if_device_1, *if_pin_4, *else_pin_4;
683
684 /* device 1 is the power-management device, needs SCI */
685 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
686 {
687 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
688 {
689 aml_append(if_pin_4,
690 aml_store(build_prt_entry("LNKS"), route));
691 }
692 aml_append(if_device_1, if_pin_4);
693 else_pin_4 = aml_else();
694 {
695 aml_append(else_pin_4,
696 aml_store(build_prt_entry("LNKA"), route));
697 }
698 aml_append(if_device_1, else_pin_4);
699 }
700 aml_append(while_ctx, if_device_1);
701 } else {
702 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
703 }
704 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
705 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
706
707 /* route[0] = 0x[slot]FFFF */
708 aml_append(while_ctx,
709 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
710 NULL),
711 aml_index(route, aml_int(0))));
712 /* route[1] = pin & 3 */
713 aml_append(while_ctx,
714 aml_store(aml_and(pin, aml_int(3), NULL),
715 aml_index(route, aml_int(1))));
716 /* res[pin] = route */
717 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
718 /* pin++ */
719 aml_append(while_ctx, aml_increment(pin));
720 }
721 aml_append(method, while_ctx);
722 /* return res*/
723 aml_append(method, aml_return(res));
724
725 return method;
726 }
727
728 static void build_hpet_aml(Aml *table)
729 {
730 Aml *crs;
731 Aml *field;
732 Aml *method;
733 Aml *if_ctx;
734 Aml *scope = aml_scope("_SB");
735 Aml *dev = aml_device("HPET");
736 Aml *zero = aml_int(0);
737 Aml *id = aml_local(0);
738 Aml *period = aml_local(1);
739
740 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
741 aml_append(dev, aml_name_decl("_UID", zero));
742
743 aml_append(dev,
744 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
745 HPET_LEN));
746 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
747 aml_append(field, aml_named_field("VEND", 32));
748 aml_append(field, aml_named_field("PRD", 32));
749 aml_append(dev, field);
750
751 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
752 aml_append(method, aml_store(aml_name("VEND"), id));
753 aml_append(method, aml_store(aml_name("PRD"), period));
754 aml_append(method, aml_shiftright(id, aml_int(16), id));
755 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
756 aml_equal(id, aml_int(0xffff))));
757 {
758 aml_append(if_ctx, aml_return(zero));
759 }
760 aml_append(method, if_ctx);
761
762 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
763 aml_lgreater(period, aml_int(100000000))));
764 {
765 aml_append(if_ctx, aml_return(zero));
766 }
767 aml_append(method, if_ctx);
768
769 aml_append(method, aml_return(aml_int(0x0F)));
770 aml_append(dev, method);
771
772 crs = aml_resource_template();
773 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
774 aml_append(dev, aml_name_decl("_CRS", crs));
775
776 aml_append(scope, dev);
777 aml_append(table, scope);
778 }
779
780 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge)
781 {
782 Aml *dev;
783 Aml *method;
784 Aml *crs;
785
786 dev = aml_device("VMBS");
787 aml_append(dev, aml_name_decl("STA", aml_int(0xF)));
788 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus")));
789 aml_append(dev, aml_name_decl("_UID", aml_int(0x0)));
790 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS")));
791
792 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
793 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL),
794 aml_name("STA")));
795 aml_append(dev, method);
796
797 method = aml_method("_PS0", 0, AML_NOTSERIALIZED);
798 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL),
799 aml_name("STA")));
800 aml_append(dev, method);
801
802 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
803 aml_append(method, aml_return(aml_name("STA")));
804 aml_append(dev, method);
805
806 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0)));
807
808 crs = aml_resource_template();
809 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq));
810 aml_append(dev, aml_name_decl("_CRS", crs));
811
812 return dev;
813 }
814
815 static void build_isa_devices_aml(Aml *table)
816 {
817 bool ambiguous;
818 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
819 Aml *scope;
820
821 assert(obj && !ambiguous);
822
823 scope = aml_scope("_SB.PCI0.ISA");
824 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA");
825 isa_build_aml(ISA_BUS(obj), scope);
826
827 aml_append(table, scope);
828 }
829
830 static void build_dbg_aml(Aml *table)
831 {
832 Aml *field;
833 Aml *method;
834 Aml *while_ctx;
835 Aml *scope = aml_scope("\\");
836 Aml *buf = aml_local(0);
837 Aml *len = aml_local(1);
838 Aml *idx = aml_local(2);
839
840 aml_append(scope,
841 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
842 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
843 aml_append(field, aml_named_field("DBGB", 8));
844 aml_append(scope, field);
845
846 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
847
848 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
849 aml_append(method, aml_to_buffer(buf, buf));
850 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
851 aml_append(method, aml_store(aml_int(0), idx));
852
853 while_ctx = aml_while(aml_lless(idx, len));
854 aml_append(while_ctx,
855 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
856 aml_append(while_ctx, aml_increment(idx));
857 aml_append(method, while_ctx);
858
859 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
860 aml_append(scope, method);
861
862 aml_append(table, scope);
863 }
864
865 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
866 {
867 Aml *dev;
868 Aml *crs;
869 Aml *method;
870 uint32_t irqs[] = {5, 10, 11};
871
872 dev = aml_device("%s", name);
873 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
874 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
875
876 crs = aml_resource_template();
877 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
878 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
879 aml_append(dev, aml_name_decl("_PRS", crs));
880
881 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
882 aml_append(method, aml_return(aml_call1("IQST", reg)));
883 aml_append(dev, method);
884
885 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
886 aml_append(method, aml_or(reg, aml_int(0x80), reg));
887 aml_append(dev, method);
888
889 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
890 aml_append(method, aml_return(aml_call1("IQCR", reg)));
891 aml_append(dev, method);
892
893 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
894 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
895 aml_append(method, aml_store(aml_name("PRRI"), reg));
896 aml_append(dev, method);
897
898 return dev;
899 }
900
901 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
902 {
903 Aml *dev;
904 Aml *crs;
905 Aml *method;
906 uint32_t irqs;
907
908 dev = aml_device("%s", name);
909 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
910 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
911
912 crs = aml_resource_template();
913 irqs = gsi;
914 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
915 AML_SHARED, &irqs, 1));
916 aml_append(dev, aml_name_decl("_PRS", crs));
917
918 aml_append(dev, aml_name_decl("_CRS", crs));
919
920 /*
921 * _DIS can be no-op because the interrupt cannot be disabled.
922 */
923 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
924 aml_append(dev, method);
925
926 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
927 aml_append(dev, method);
928
929 return dev;
930 }
931
932 /* _CRS method - get current settings */
933 static Aml *build_iqcr_method(bool is_piix4)
934 {
935 Aml *if_ctx;
936 uint32_t irqs;
937 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
938 Aml *crs = aml_resource_template();
939
940 irqs = 0;
941 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
942 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
943 aml_append(method, aml_name_decl("PRR0", crs));
944
945 aml_append(method,
946 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
947
948 if (is_piix4) {
949 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
950 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
951 aml_append(method, if_ctx);
952 } else {
953 aml_append(method,
954 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
955 aml_name("PRRI")));
956 }
957
958 aml_append(method, aml_return(aml_name("PRR0")));
959 return method;
960 }
961
962 /* _STA method - get status */
963 static Aml *build_irq_status_method(void)
964 {
965 Aml *if_ctx;
966 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
967
968 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
969 aml_append(if_ctx, aml_return(aml_int(0x09)));
970 aml_append(method, if_ctx);
971 aml_append(method, aml_return(aml_int(0x0B)));
972 return method;
973 }
974
975 static void build_piix4_pci0_int(Aml *table)
976 {
977 Aml *dev;
978 Aml *crs;
979 Aml *field;
980 Aml *method;
981 uint32_t irqs;
982 Aml *sb_scope = aml_scope("_SB");
983 Aml *pci0_scope = aml_scope("PCI0");
984
985 aml_append(pci0_scope, build_prt(true));
986 aml_append(sb_scope, pci0_scope);
987
988 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
989 aml_append(field, aml_named_field("PRQ0", 8));
990 aml_append(field, aml_named_field("PRQ1", 8));
991 aml_append(field, aml_named_field("PRQ2", 8));
992 aml_append(field, aml_named_field("PRQ3", 8));
993 aml_append(sb_scope, field);
994
995 aml_append(sb_scope, build_irq_status_method());
996 aml_append(sb_scope, build_iqcr_method(true));
997
998 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
999 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1000 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1001 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1002
1003 dev = aml_device("LNKS");
1004 {
1005 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1006 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1007
1008 crs = aml_resource_template();
1009 irqs = 9;
1010 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1011 AML_ACTIVE_HIGH, AML_SHARED,
1012 &irqs, 1));
1013 aml_append(dev, aml_name_decl("_PRS", crs));
1014
1015 /* The SCI cannot be disabled and is always attached to GSI 9,
1016 * so these are no-ops. We only need this link to override the
1017 * polarity to active high and match the content of the MADT.
1018 */
1019 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1020 aml_append(method, aml_return(aml_int(0x0b)));
1021 aml_append(dev, method);
1022
1023 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1024 aml_append(dev, method);
1025
1026 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1027 aml_append(method, aml_return(aml_name("_PRS")));
1028 aml_append(dev, method);
1029
1030 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1031 aml_append(dev, method);
1032 }
1033 aml_append(sb_scope, dev);
1034
1035 aml_append(table, sb_scope);
1036 }
1037
1038 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1039 {
1040 int i;
1041 int head;
1042 Aml *pkg;
1043 char base = name[3] < 'E' ? 'A' : 'E';
1044 char *s = g_strdup(name);
1045 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1046
1047 assert(strlen(s) == 4);
1048
1049 head = name[3] - base;
1050 for (i = 0; i < 4; i++) {
1051 if (head + i > 3) {
1052 head = i * -1;
1053 }
1054 s[3] = base + head + i;
1055 pkg = aml_package(4);
1056 aml_append(pkg, a_nr);
1057 aml_append(pkg, aml_int(i));
1058 aml_append(pkg, aml_name("%s", s));
1059 aml_append(pkg, aml_int(0));
1060 aml_append(ctx, pkg);
1061 }
1062 g_free(s);
1063 }
1064
1065 static Aml *build_q35_routing_table(const char *str)
1066 {
1067 int i;
1068 Aml *pkg;
1069 char *name = g_strdup_printf("%s ", str);
1070
1071 pkg = aml_package(128);
1072 for (i = 0; i < 0x18; i++) {
1073 name[3] = 'E' + (i & 0x3);
1074 append_q35_prt_entry(pkg, i, name);
1075 }
1076
1077 name[3] = 'E';
1078 append_q35_prt_entry(pkg, 0x18, name);
1079
1080 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1081 for (i = 0x0019; i < 0x1e; i++) {
1082 name[3] = 'A';
1083 append_q35_prt_entry(pkg, i, name);
1084 }
1085
1086 /* PCIe->PCI bridge. use PIRQ[E-H] */
1087 name[3] = 'E';
1088 append_q35_prt_entry(pkg, 0x1e, name);
1089 name[3] = 'A';
1090 append_q35_prt_entry(pkg, 0x1f, name);
1091
1092 g_free(name);
1093 return pkg;
1094 }
1095
1096 static void build_q35_pci0_int(Aml *table)
1097 {
1098 Aml *field;
1099 Aml *method;
1100 Aml *sb_scope = aml_scope("_SB");
1101 Aml *pci0_scope = aml_scope("PCI0");
1102
1103 /* Zero => PIC mode, One => APIC Mode */
1104 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1105 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1106 {
1107 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1108 }
1109 aml_append(table, method);
1110
1111 aml_append(pci0_scope,
1112 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1113 aml_append(pci0_scope,
1114 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1115
1116 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1117 {
1118 Aml *if_ctx;
1119 Aml *else_ctx;
1120
1121 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1122 section 6.2.8.1 */
1123 /* Note: we provide the same info as the PCI routing
1124 table of the Bochs BIOS */
1125 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1126 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1127 aml_append(method, if_ctx);
1128 else_ctx = aml_else();
1129 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1130 aml_append(method, else_ctx);
1131 }
1132 aml_append(pci0_scope, method);
1133 aml_append(sb_scope, pci0_scope);
1134
1135 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1136 aml_append(field, aml_named_field("PRQA", 8));
1137 aml_append(field, aml_named_field("PRQB", 8));
1138 aml_append(field, aml_named_field("PRQC", 8));
1139 aml_append(field, aml_named_field("PRQD", 8));
1140 aml_append(field, aml_reserved_field(0x20));
1141 aml_append(field, aml_named_field("PRQE", 8));
1142 aml_append(field, aml_named_field("PRQF", 8));
1143 aml_append(field, aml_named_field("PRQG", 8));
1144 aml_append(field, aml_named_field("PRQH", 8));
1145 aml_append(sb_scope, field);
1146
1147 aml_append(sb_scope, build_irq_status_method());
1148 aml_append(sb_scope, build_iqcr_method(false));
1149
1150 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1151 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1152 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1153 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1154 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1155 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1156 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1157 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1158
1159 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1160 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1161 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1162 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1163 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1164 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1165 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1166 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1167
1168 aml_append(table, sb_scope);
1169 }
1170
1171 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg)
1172 {
1173 Aml *dev;
1174 Aml *resource_template;
1175
1176 /* DRAM controller */
1177 dev = aml_device("DRAC");
1178 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01")));
1179
1180 resource_template = aml_resource_template();
1181 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) {
1182 aml_append(resource_template,
1183 aml_qword_memory(AML_POS_DECODE,
1184 AML_MIN_FIXED,
1185 AML_MAX_FIXED,
1186 AML_NON_CACHEABLE,
1187 AML_READ_WRITE,
1188 0x0000000000000000,
1189 mcfg->base,
1190 mcfg->base + mcfg->size - 1,
1191 0x0000000000000000,
1192 mcfg->size));
1193 } else {
1194 aml_append(resource_template,
1195 aml_dword_memory(AML_POS_DECODE,
1196 AML_MIN_FIXED,
1197 AML_MAX_FIXED,
1198 AML_NON_CACHEABLE,
1199 AML_READ_WRITE,
1200 0x0000000000000000,
1201 mcfg->base,
1202 mcfg->base + mcfg->size - 1,
1203 0x0000000000000000,
1204 mcfg->size));
1205 }
1206 aml_append(dev, aml_name_decl("_CRS", resource_template));
1207
1208 return dev;
1209 }
1210
1211 static void build_q35_isa_bridge(Aml *table)
1212 {
1213 Aml *dev;
1214 Aml *scope;
1215
1216 scope = aml_scope("_SB.PCI0");
1217 dev = aml_device("ISA");
1218 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1219
1220 /* ICH9 PCI to ISA irq remapping */
1221 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1222 aml_int(0x60), 0x0C));
1223
1224 aml_append(scope, dev);
1225 aml_append(table, scope);
1226 }
1227
1228 static void build_piix4_isa_bridge(Aml *table)
1229 {
1230 Aml *dev;
1231 Aml *scope;
1232
1233 scope = aml_scope("_SB.PCI0");
1234 dev = aml_device("ISA");
1235 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1236
1237 /* PIIX PCI to ISA irq remapping */
1238 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1239 aml_int(0x60), 0x04));
1240
1241 aml_append(scope, dev);
1242 aml_append(table, scope);
1243 }
1244
1245 static void build_piix4_pci_hotplug(Aml *table)
1246 {
1247 Aml *scope;
1248 Aml *field;
1249 Aml *method;
1250
1251 scope = aml_scope("_SB.PCI0");
1252
1253 aml_append(scope,
1254 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1255 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1256 aml_append(field, aml_named_field("PCIU", 32));
1257 aml_append(field, aml_named_field("PCID", 32));
1258 aml_append(scope, field);
1259
1260 aml_append(scope,
1261 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1262 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1263 aml_append(field, aml_named_field("B0EJ", 32));
1264 aml_append(scope, field);
1265
1266 aml_append(scope,
1267 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x08));
1268 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1269 aml_append(field, aml_named_field("BNUM", 32));
1270 aml_append(field, aml_named_field("PIDX", 32));
1271 aml_append(scope, field);
1272
1273 aml_append(scope, aml_mutex("BLCK", 0));
1274
1275 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1276 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1277 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1278 aml_append(method,
1279 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1280 aml_append(method, aml_release(aml_name("BLCK")));
1281 aml_append(method, aml_return(aml_int(0)));
1282 aml_append(scope, method);
1283
1284 method = aml_method("AIDX", 2, AML_NOTSERIALIZED);
1285 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1286 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1287 aml_append(method,
1288 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX")));
1289 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0)));
1290 aml_append(method, aml_release(aml_name("BLCK")));
1291 aml_append(method, aml_return(aml_local(0)));
1292 aml_append(scope, method);
1293
1294 aml_append(scope, aml_pci_device_dsm());
1295
1296 aml_append(table, scope);
1297 }
1298
1299 static Aml *build_q35_osc_method(void)
1300 {
1301 Aml *if_ctx;
1302 Aml *if_ctx2;
1303 Aml *else_ctx;
1304 Aml *method;
1305 Aml *a_cwd1 = aml_name("CDW1");
1306 Aml *a_ctrl = aml_local(0);
1307
1308 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1309 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1310
1311 if_ctx = aml_if(aml_equal(
1312 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1313 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1314 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1315
1316 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1317
1318 /*
1319 * Always allow native PME, AER (no dependencies)
1320 * Allow SHPC (PCI bridges can have SHPC controller)
1321 */
1322 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
1323
1324 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1325 /* Unknown revision */
1326 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1327 aml_append(if_ctx, if_ctx2);
1328
1329 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1330 /* Capabilities bits were masked */
1331 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1332 aml_append(if_ctx, if_ctx2);
1333
1334 /* Update DWORD3 in the buffer */
1335 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1336 aml_append(method, if_ctx);
1337
1338 else_ctx = aml_else();
1339 /* Unrecognized UUID */
1340 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1341 aml_append(method, else_ctx);
1342
1343 aml_append(method, aml_return(aml_arg(3)));
1344 return method;
1345 }
1346
1347 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func)
1348 {
1349 Aml *scope = aml_scope("_SB.PCI0");
1350 Aml *dev = aml_device("SMB0");
1351
1352 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func)));
1353 build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0");
1354 aml_append(scope, dev);
1355 aml_append(table, scope);
1356 }
1357
1358 static void
1359 build_dsdt(GArray *table_data, BIOSLinker *linker,
1360 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1361 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1362 {
1363 CrsRangeEntry *entry;
1364 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1365 CrsRangeSet crs_range_set;
1366 PCMachineState *pcms = PC_MACHINE(machine);
1367 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1368 X86MachineState *x86ms = X86_MACHINE(machine);
1369 AcpiMcfgInfo mcfg;
1370 bool mcfg_valid = !!acpi_get_mcfg(&mcfg);
1371 uint32_t nr_mem = machine->ram_slots;
1372 int root_bus_limit = 0xFF;
1373 PCIBus *bus = NULL;
1374 TPMIf *tpm = tpm_find();
1375 int i;
1376 VMBusBridge *vmbus_bridge = vmbus_bridge_find();
1377
1378 dsdt = init_aml_allocator();
1379
1380 /* Reserve space for header */
1381 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1382
1383 build_dbg_aml(dsdt);
1384 if (misc->is_piix4) {
1385 sb_scope = aml_scope("_SB");
1386 dev = aml_device("PCI0");
1387 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1388 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1389 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
1390 aml_append(sb_scope, dev);
1391 aml_append(dsdt, sb_scope);
1392
1393 if (misc->has_hpet) {
1394 build_hpet_aml(dsdt);
1395 }
1396 build_piix4_isa_bridge(dsdt);
1397 build_isa_devices_aml(dsdt);
1398 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1399 build_piix4_pci_hotplug(dsdt);
1400 }
1401 build_piix4_pci0_int(dsdt);
1402 } else {
1403 sb_scope = aml_scope("_SB");
1404 dev = aml_device("PCI0");
1405 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1406 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1407 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1408 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
1409 aml_append(dev, build_q35_osc_method());
1410 aml_append(sb_scope, dev);
1411 if (mcfg_valid) {
1412 aml_append(sb_scope, build_q35_dram_controller(&mcfg));
1413 }
1414
1415 if (pm->smi_on_cpuhp) {
1416 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */
1417 dev = aml_device("PCI0.SMI0");
1418 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1419 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources")));
1420 crs = aml_resource_template();
1421 aml_append(crs,
1422 aml_io(
1423 AML_DECODE16,
1424 ACPI_PORT_SMI_CMD,
1425 ACPI_PORT_SMI_CMD,
1426 1,
1427 2)
1428 );
1429 aml_append(dev, aml_name_decl("_CRS", crs));
1430 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO,
1431 aml_int(ACPI_PORT_SMI_CMD), 2));
1432 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK,
1433 AML_WRITE_AS_ZEROS);
1434 aml_append(field, aml_named_field("SMIC", 8));
1435 aml_append(field, aml_reserved_field(8));
1436 aml_append(dev, field);
1437 aml_append(sb_scope, dev);
1438 }
1439
1440 aml_append(dsdt, sb_scope);
1441
1442 if (misc->has_hpet) {
1443 build_hpet_aml(dsdt);
1444 }
1445 build_q35_isa_bridge(dsdt);
1446 build_isa_devices_aml(dsdt);
1447 build_q35_pci0_int(dsdt);
1448 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) {
1449 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC);
1450 }
1451 }
1452
1453 if (vmbus_bridge) {
1454 sb_scope = aml_scope("_SB");
1455 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge));
1456 aml_append(dsdt, sb_scope);
1457 }
1458
1459 if (pcmc->legacy_cpu_hotplug) {
1460 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1461 } else {
1462 CPUHotplugFeatures opts = {
1463 .acpi_1_compatible = true, .has_legacy_cphp = true,
1464 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL,
1465 .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
1466 };
1467 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1468 "\\_SB.PCI0", "\\_GPE._E02");
1469 }
1470
1471 if (pcms->memhp_io_base && nr_mem) {
1472 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
1473 "\\_GPE._E03", AML_SYSTEM_IO,
1474 pcms->memhp_io_base);
1475 }
1476
1477 scope = aml_scope("_GPE");
1478 {
1479 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1480
1481 if (misc->is_piix4 && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
1482 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1483 aml_append(method,
1484 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1485 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1486 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1487 aml_append(scope, method);
1488 }
1489
1490 if (machine->nvdimms_state->is_enabled) {
1491 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1492 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1493 aml_int(0x80)));
1494 aml_append(scope, method);
1495 }
1496 }
1497 aml_append(dsdt, scope);
1498
1499 crs_range_set_init(&crs_range_set);
1500 bus = PC_MACHINE(machine)->bus;
1501 if (bus) {
1502 QLIST_FOREACH(bus, &bus->child, sibling) {
1503 uint8_t bus_num = pci_bus_num(bus);
1504 uint8_t numa_node = pci_bus_numa_node(bus);
1505
1506 /* look only for expander root buses */
1507 if (!pci_bus_is_root(bus)) {
1508 continue;
1509 }
1510
1511 if (bus_num < root_bus_limit) {
1512 root_bus_limit = bus_num - 1;
1513 }
1514
1515 scope = aml_scope("\\_SB");
1516 dev = aml_device("PC%.02X", bus_num);
1517 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1518 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1519 if (pci_bus_is_express(bus)) {
1520 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1521 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1522 aml_append(dev, build_q35_osc_method());
1523 } else {
1524 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1525 }
1526
1527 if (numa_node != NUMA_NODE_UNASSIGNED) {
1528 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1529 }
1530
1531 aml_append(dev, build_prt(false));
1532 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
1533 0, 0, 0, 0);
1534 aml_append(dev, aml_name_decl("_CRS", crs));
1535 aml_append(scope, dev);
1536 aml_append(dsdt, scope);
1537 }
1538 }
1539
1540 /*
1541 * At this point crs_range_set has all the ranges used by pci
1542 * busses *other* than PCI0. These ranges will be excluded from
1543 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1544 * too.
1545 */
1546 if (mcfg_valid) {
1547 crs_range_insert(crs_range_set.mem_ranges,
1548 mcfg.base, mcfg.base + mcfg.size - 1);
1549 }
1550
1551 scope = aml_scope("\\_SB.PCI0");
1552 /* build PCI0._CRS */
1553 crs = aml_resource_template();
1554 aml_append(crs,
1555 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1556 0x0000, 0x0, root_bus_limit,
1557 0x0000, root_bus_limit + 1));
1558 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1559
1560 aml_append(crs,
1561 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1562 AML_POS_DECODE, AML_ENTIRE_RANGE,
1563 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1564
1565 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1566 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1567 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1568 aml_append(crs,
1569 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1570 AML_POS_DECODE, AML_ENTIRE_RANGE,
1571 0x0000, entry->base, entry->limit,
1572 0x0000, entry->limit - entry->base + 1));
1573 }
1574
1575 aml_append(crs,
1576 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1577 AML_CACHEABLE, AML_READ_WRITE,
1578 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1579
1580 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
1581 range_lob(pci_hole),
1582 range_upb(pci_hole));
1583 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1584 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
1585 aml_append(crs,
1586 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1587 AML_NON_CACHEABLE, AML_READ_WRITE,
1588 0, entry->base, entry->limit,
1589 0, entry->limit - entry->base + 1));
1590 }
1591
1592 if (!range_is_empty(pci_hole64)) {
1593 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1594 range_lob(pci_hole64),
1595 range_upb(pci_hole64));
1596 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1597 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1598 aml_append(crs,
1599 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1600 AML_MAX_FIXED,
1601 AML_CACHEABLE, AML_READ_WRITE,
1602 0, entry->base, entry->limit,
1603 0, entry->limit - entry->base + 1));
1604 }
1605 }
1606
1607 if (TPM_IS_TIS_ISA(tpm_find())) {
1608 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1609 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1610 }
1611 aml_append(scope, aml_name_decl("_CRS", crs));
1612
1613 /* reserve GPE0 block resources */
1614 dev = aml_device("GPE0");
1615 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1616 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1617 /* device present, functioning, decoding, not shown in UI */
1618 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1619 crs = aml_resource_template();
1620 aml_append(crs,
1621 aml_io(
1622 AML_DECODE16,
1623 pm->fadt.gpe0_blk.address,
1624 pm->fadt.gpe0_blk.address,
1625 1,
1626 pm->fadt.gpe0_blk.bit_width / 8)
1627 );
1628 aml_append(dev, aml_name_decl("_CRS", crs));
1629 aml_append(scope, dev);
1630
1631 crs_range_set_free(&crs_range_set);
1632
1633 /* reserve PCIHP resources */
1634 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
1635 dev = aml_device("PHPR");
1636 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1637 aml_append(dev,
1638 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1639 /* device present, functioning, decoding, not shown in UI */
1640 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1641 crs = aml_resource_template();
1642 aml_append(crs,
1643 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
1644 pm->pcihp_io_len)
1645 );
1646 aml_append(dev, aml_name_decl("_CRS", crs));
1647 aml_append(scope, dev);
1648 }
1649 aml_append(dsdt, scope);
1650
1651 /* create S3_ / S4_ / S5_ packages if necessary */
1652 scope = aml_scope("\\");
1653 if (!pm->s3_disabled) {
1654 pkg = aml_package(4);
1655 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1656 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1657 aml_append(pkg, aml_int(0)); /* reserved */
1658 aml_append(pkg, aml_int(0)); /* reserved */
1659 aml_append(scope, aml_name_decl("_S3", pkg));
1660 }
1661
1662 if (!pm->s4_disabled) {
1663 pkg = aml_package(4);
1664 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1665 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1666 aml_append(pkg, aml_int(pm->s4_val));
1667 aml_append(pkg, aml_int(0)); /* reserved */
1668 aml_append(pkg, aml_int(0)); /* reserved */
1669 aml_append(scope, aml_name_decl("_S4", pkg));
1670 }
1671
1672 pkg = aml_package(4);
1673 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1674 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1675 aml_append(pkg, aml_int(0)); /* reserved */
1676 aml_append(pkg, aml_int(0)); /* reserved */
1677 aml_append(scope, aml_name_decl("_S5", pkg));
1678 aml_append(dsdt, scope);
1679
1680 /* create fw_cfg node, unconditionally */
1681 {
1682 scope = aml_scope("\\_SB.PCI0");
1683 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg);
1684 aml_append(dsdt, scope);
1685 }
1686
1687 if (misc->applesmc_io_base) {
1688 scope = aml_scope("\\_SB.PCI0.ISA");
1689 dev = aml_device("SMC");
1690
1691 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
1692 /* device present, functioning, decoding, not shown in UI */
1693 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1694
1695 crs = aml_resource_template();
1696 aml_append(crs,
1697 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
1698 0x01, APPLESMC_MAX_DATA_LENGTH)
1699 );
1700 aml_append(crs, aml_irq_no_flags(6));
1701 aml_append(dev, aml_name_decl("_CRS", crs));
1702
1703 aml_append(scope, dev);
1704 aml_append(dsdt, scope);
1705 }
1706
1707 if (misc->pvpanic_port) {
1708 scope = aml_scope("\\_SB.PCI0.ISA");
1709
1710 dev = aml_device("PEVT");
1711 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
1712
1713 crs = aml_resource_template();
1714 aml_append(crs,
1715 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
1716 );
1717 aml_append(dev, aml_name_decl("_CRS", crs));
1718
1719 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
1720 aml_int(misc->pvpanic_port), 1));
1721 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1722 aml_append(field, aml_named_field("PEPT", 8));
1723 aml_append(dev, field);
1724
1725 /* device present, functioning, decoding, shown in UI */
1726 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1727
1728 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
1729 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
1730 aml_append(method, aml_return(aml_local(0)));
1731 aml_append(dev, method);
1732
1733 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
1734 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
1735 aml_append(dev, method);
1736
1737 aml_append(scope, dev);
1738 aml_append(dsdt, scope);
1739 }
1740
1741 sb_scope = aml_scope("\\_SB");
1742 {
1743 Object *pci_host;
1744 PCIBus *bus = NULL;
1745
1746 pci_host = acpi_get_i386_pci_host();
1747 if (pci_host) {
1748 bus = PCI_HOST_BRIDGE(pci_host)->bus;
1749 }
1750
1751 if (bus) {
1752 Aml *scope = aml_scope("PCI0");
1753 /* Scan all PCI buses. Generate tables to support hotplug. */
1754 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
1755
1756 if (TPM_IS_TIS_ISA(tpm)) {
1757 if (misc->tpm_version == TPM_VERSION_2_0) {
1758 dev = aml_device("TPM");
1759 aml_append(dev, aml_name_decl("_HID",
1760 aml_string("MSFT0101")));
1761 } else {
1762 dev = aml_device("ISA.TPM");
1763 aml_append(dev, aml_name_decl("_HID",
1764 aml_eisaid("PNP0C31")));
1765 }
1766
1767 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1768 crs = aml_resource_template();
1769 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1770 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1771 /*
1772 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
1773 Rewrite to take IRQ from TPM device model and
1774 fix default IRQ value there to use some unused IRQ
1775 */
1776 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
1777 aml_append(dev, aml_name_decl("_CRS", crs));
1778
1779 tpm_build_ppi_acpi(tpm, dev);
1780
1781 aml_append(scope, dev);
1782 }
1783
1784 aml_append(sb_scope, scope);
1785 }
1786 }
1787
1788 if (TPM_IS_CRB(tpm)) {
1789 dev = aml_device("TPM");
1790 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
1791 crs = aml_resource_template();
1792 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
1793 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
1794 aml_append(dev, aml_name_decl("_CRS", crs));
1795
1796 aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
1797
1798 tpm_build_ppi_acpi(tpm, dev);
1799
1800 aml_append(sb_scope, dev);
1801 }
1802
1803 aml_append(dsdt, sb_scope);
1804
1805 /* copy AML table into ACPI tables blob and patch header there */
1806 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
1807 build_header(linker, table_data,
1808 (void *)(table_data->data + table_data->len - dsdt->buf->len),
1809 "DSDT", dsdt->buf->len, 1, x86ms->oem_id, x86ms->oem_table_id);
1810 free_aml_allocator();
1811 }
1812
1813 static void
1814 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
1815 const char *oem_table_id)
1816 {
1817 Acpi20Hpet *hpet;
1818 int hpet_start = table_data->len;
1819
1820 hpet = acpi_data_push(table_data, sizeof(*hpet));
1821 /* Note timer_block_id value must be kept in sync with value advertised by
1822 * emulated hpet
1823 */
1824 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1825 hpet->addr.address = cpu_to_le64(HPET_BASE);
1826 build_header(linker, table_data,
1827 (void *)(table_data->data + hpet_start),
1828 "HPET", sizeof(*hpet), 1, oem_id, oem_table_id);
1829 }
1830
1831 static void
1832 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
1833 const char *oem_id, const char *oem_table_id)
1834 {
1835 int tcpa_start = table_data->len;
1836 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
1837 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
1838 unsigned log_addr_offset =
1839 (char *)&tcpa->log_area_start_address - table_data->data;
1840
1841 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
1842 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
1843 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
1844
1845 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
1846 false /* high memory */);
1847
1848 /* log area start address to be filled by Guest linker */
1849 bios_linker_loader_add_pointer(linker,
1850 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
1851 ACPI_BUILD_TPMLOG_FILE, 0);
1852
1853 build_header(linker, table_data,
1854 (void *)(table_data->data + tcpa_start),
1855 "TCPA", sizeof(*tcpa), 2, oem_id, oem_table_id);
1856 }
1857
1858 #define HOLE_640K_START (640 * KiB)
1859 #define HOLE_640K_END (1 * MiB)
1860
1861 static void
1862 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
1863 {
1864 AcpiSystemResourceAffinityTable *srat;
1865 AcpiSratMemoryAffinity *numamem;
1866
1867 int i;
1868 int srat_start, numa_start, slots;
1869 uint64_t mem_len, mem_base, next_base;
1870 MachineClass *mc = MACHINE_GET_CLASS(machine);
1871 X86MachineState *x86ms = X86_MACHINE(machine);
1872 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
1873 PCMachineState *pcms = PC_MACHINE(machine);
1874 ram_addr_t hotplugabble_address_space_size =
1875 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
1876 NULL);
1877
1878 srat_start = table_data->len;
1879
1880 srat = acpi_data_push(table_data, sizeof *srat);
1881 srat->reserved1 = cpu_to_le32(1);
1882
1883 for (i = 0; i < apic_ids->len; i++) {
1884 int node_id = apic_ids->cpus[i].props.node_id;
1885 uint32_t apic_id = apic_ids->cpus[i].arch_id;
1886
1887 if (apic_id < 255) {
1888 AcpiSratProcessorAffinity *core;
1889
1890 core = acpi_data_push(table_data, sizeof *core);
1891 core->type = ACPI_SRAT_PROCESSOR_APIC;
1892 core->length = sizeof(*core);
1893 core->local_apic_id = apic_id;
1894 core->proximity_lo = node_id;
1895 memset(core->proximity_hi, 0, 3);
1896 core->local_sapic_eid = 0;
1897 core->flags = cpu_to_le32(1);
1898 } else {
1899 AcpiSratProcessorX2ApicAffinity *core;
1900
1901 core = acpi_data_push(table_data, sizeof *core);
1902 core->type = ACPI_SRAT_PROCESSOR_x2APIC;
1903 core->length = sizeof(*core);
1904 core->x2apic_id = cpu_to_le32(apic_id);
1905 core->proximity_domain = cpu_to_le32(node_id);
1906 core->flags = cpu_to_le32(1);
1907 }
1908 }
1909
1910
1911 /* the memory map is a bit tricky, it contains at least one hole
1912 * from 640k-1M and possibly another one from 3.5G-4G.
1913 */
1914 next_base = 0;
1915 numa_start = table_data->len;
1916
1917 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
1918 mem_base = next_base;
1919 mem_len = pcms->node_mem[i - 1];
1920 next_base = mem_base + mem_len;
1921
1922 /* Cut out the 640K hole */
1923 if (mem_base <= HOLE_640K_START &&
1924 next_base > HOLE_640K_START) {
1925 mem_len -= next_base - HOLE_640K_START;
1926 if (mem_len > 0) {
1927 numamem = acpi_data_push(table_data, sizeof *numamem);
1928 build_srat_memory(numamem, mem_base, mem_len, i - 1,
1929 MEM_AFFINITY_ENABLED);
1930 }
1931
1932 /* Check for the rare case: 640K < RAM < 1M */
1933 if (next_base <= HOLE_640K_END) {
1934 next_base = HOLE_640K_END;
1935 continue;
1936 }
1937 mem_base = HOLE_640K_END;
1938 mem_len = next_base - HOLE_640K_END;
1939 }
1940
1941 /* Cut out the ACPI_PCI hole */
1942 if (mem_base <= x86ms->below_4g_mem_size &&
1943 next_base > x86ms->below_4g_mem_size) {
1944 mem_len -= next_base - x86ms->below_4g_mem_size;
1945 if (mem_len > 0) {
1946 numamem = acpi_data_push(table_data, sizeof *numamem);
1947 build_srat_memory(numamem, mem_base, mem_len, i - 1,
1948 MEM_AFFINITY_ENABLED);
1949 }
1950 mem_base = 1ULL << 32;
1951 mem_len = next_base - x86ms->below_4g_mem_size;
1952 next_base = mem_base + mem_len;
1953 }
1954
1955 if (mem_len > 0) {
1956 numamem = acpi_data_push(table_data, sizeof *numamem);
1957 build_srat_memory(numamem, mem_base, mem_len, i - 1,
1958 MEM_AFFINITY_ENABLED);
1959 }
1960 }
1961
1962 if (machine->nvdimms_state->is_enabled) {
1963 nvdimm_build_srat(table_data);
1964 }
1965
1966 slots = (table_data->len - numa_start) / sizeof *numamem;
1967 for (; slots < pcms->numa_nodes + 2; slots++) {
1968 numamem = acpi_data_push(table_data, sizeof *numamem);
1969 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
1970 }
1971
1972 /*
1973 * Entry is required for Windows to enable memory hotplug in OS
1974 * and for Linux to enable SWIOTLB when booted with less than
1975 * 4G of RAM. Windows works better if the entry sets proximity
1976 * to the highest NUMA node in the machine.
1977 * Memory devices may override proximity set by this entry,
1978 * providing _PXM method if necessary.
1979 */
1980 if (hotplugabble_address_space_size) {
1981 numamem = acpi_data_push(table_data, sizeof *numamem);
1982 build_srat_memory(numamem, machine->device_memory->base,
1983 hotplugabble_address_space_size, pcms->numa_nodes - 1,
1984 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
1985 }
1986
1987 build_header(linker, table_data,
1988 (void *)(table_data->data + srat_start),
1989 "SRAT",
1990 table_data->len - srat_start, 1, x86ms->oem_id,
1991 x86ms->oem_table_id);
1992 }
1993
1994 /*
1995 * VT-d spec 8.1 DMA Remapping Reporting Structure
1996 * (version Oct. 2014 or later)
1997 */
1998 static void
1999 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2000 const char *oem_table_id)
2001 {
2002 int dmar_start = table_data->len;
2003
2004 AcpiTableDmar *dmar;
2005 AcpiDmarHardwareUnit *drhd;
2006 AcpiDmarRootPortATS *atsr;
2007 uint8_t dmar_flags = 0;
2008 X86IOMMUState *iommu = x86_iommu_get_default();
2009 AcpiDmarDeviceScope *scope = NULL;
2010 /* Root complex IOAPIC use one path[0] only */
2011 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
2012 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2013
2014 assert(iommu);
2015 if (x86_iommu_ir_supported(iommu)) {
2016 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2017 }
2018
2019 dmar = acpi_data_push(table_data, sizeof(*dmar));
2020 dmar->host_address_width = intel_iommu->aw_bits - 1;
2021 dmar->flags = dmar_flags;
2022
2023 /* DMAR Remapping Hardware Unit Definition structure */
2024 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
2025 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2026 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
2027 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2028 drhd->pci_segment = cpu_to_le16(0);
2029 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2030
2031 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2032 * 8.3.1 (version Oct. 2014 or later). */
2033 scope = &drhd->scope[0];
2034 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
2035 scope->length = ioapic_scope_size;
2036 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2037 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
2038 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
2039 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
2040
2041 if (iommu->dt_supported) {
2042 atsr = acpi_data_push(table_data, sizeof(*atsr));
2043 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
2044 atsr->length = cpu_to_le16(sizeof(*atsr));
2045 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
2046 atsr->pci_segment = cpu_to_le16(0);
2047 }
2048
2049 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2050 "DMAR", table_data->len - dmar_start, 1, oem_id, oem_table_id);
2051 }
2052
2053 /*
2054 * Windows ACPI Emulated Devices Table
2055 * (Version 1.0 - April 6, 2009)
2056 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
2057 *
2058 * Helpful to speedup Windows guests and ignored by others.
2059 */
2060 static void
2061 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2062 const char *oem_table_id)
2063 {
2064 int waet_start = table_data->len;
2065
2066 /* WAET header */
2067 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2068 /*
2069 * Set "ACPI PM timer good" flag.
2070 *
2071 * Tells Windows guests that our ACPI PM timer is reliable in the
2072 * sense that guest can read it only once to obtain a reliable value.
2073 * Which avoids costly VMExits caused by guest re-reading it unnecessarily.
2074 */
2075 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4);
2076
2077 build_header(linker, table_data, (void *)(table_data->data + waet_start),
2078 "WAET", table_data->len - waet_start, 1, oem_id, oem_table_id);
2079 }
2080
2081 /*
2082 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2083 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2084 */
2085 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2086
2087 /*
2088 * Insert IVHD entry for device and recurse, insert alias, or insert range as
2089 * necessary for the PCI topology.
2090 */
2091 static void
2092 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque)
2093 {
2094 GArray *table_data = opaque;
2095 uint32_t entry;
2096
2097 /* "Select" IVHD entry, type 0x2 */
2098 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2;
2099 build_append_int_noprefix(table_data, entry, 4);
2100
2101 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2102 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
2103 uint8_t sec = pci_bus_num(sec_bus);
2104 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS];
2105
2106 if (pci_bus_is_express(sec_bus)) {
2107 /*
2108 * Walk the bus if there are subordinates, otherwise use a range
2109 * to cover an entire leaf bus. We could potentially also use a
2110 * range for traversed buses, but we'd need to take care not to
2111 * create both Select and Range entries covering the same device.
2112 * This is easier and potentially more compact.
2113 *
2114 * An example bare metal system seems to use Select entries for
2115 * root ports without a slot (ie. built-ins) and Range entries
2116 * when there is a slot. The same system also only hard-codes
2117 * the alias range for an onboard PCIe-to-PCI bridge, apparently
2118 * making no effort to support nested bridges. We attempt to
2119 * be more thorough here.
2120 */
2121 if (sec == sub) { /* leaf bus */
2122 /* "Start of Range" IVHD entry, type 0x3 */
2123 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3;
2124 build_append_int_noprefix(table_data, entry, 4);
2125 /* "End of Range" IVHD entry, type 0x4 */
2126 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2127 build_append_int_noprefix(table_data, entry, 4);
2128 } else {
2129 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data);
2130 }
2131 } else {
2132 /*
2133 * If the secondary bus is conventional, then we need to create an
2134 * Alias range for everything downstream. The range covers the
2135 * first devfn on the secondary bus to the last devfn on the
2136 * subordinate bus. The alias target depends on legacy versus
2137 * express bridges, just as in pci_device_iommu_address_space().
2138 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
2139 */
2140 uint16_t dev_id_a, dev_id_b;
2141
2142 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0));
2143
2144 if (pci_is_express(dev) &&
2145 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
2146 dev_id_b = dev_id_a;
2147 } else {
2148 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn);
2149 }
2150
2151 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
2152 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4);
2153 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4);
2154
2155 /* "End of Range" IVHD entry, type 0x4 */
2156 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2157 build_append_int_noprefix(table_data, entry, 4);
2158 }
2159 }
2160 }
2161
2162 /* For all PCI host bridges, walk and insert IVHD entries */
2163 static int
2164 ivrs_host_bridges(Object *obj, void *opaque)
2165 {
2166 GArray *ivhd_blob = opaque;
2167
2168 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2169 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2170
2171 if (bus) {
2172 pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob);
2173 }
2174 }
2175
2176 return 0;
2177 }
2178
2179 static void
2180 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2181 const char *oem_table_id)
2182 {
2183 int ivhd_table_len = 24;
2184 int iommu_start = table_data->len;
2185 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2186 GArray *ivhd_blob = g_array_new(false, true, 1);
2187
2188 /* IVRS header */
2189 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2190 /* IVinfo - IO virtualization information common to all
2191 * IOMMU units in a system
2192 */
2193 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2194 /* reserved */
2195 build_append_int_noprefix(table_data, 0, 8);
2196
2197 /* IVHD definition - type 10h */
2198 build_append_int_noprefix(table_data, 0x10, 1);
2199 /* virtualization flags */
2200 build_append_int_noprefix(table_data,
2201 (1UL << 0) | /* HtTunEn */
2202 (1UL << 4) | /* iotblSup */
2203 (1UL << 6) | /* PrefSup */
2204 (1UL << 7), /* PPRSup */
2205 1);
2206
2207 /*
2208 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2209 * complete set of IVHD entries. Do this into a separate blob so that we
2210 * can calculate the total IVRS table length here and then append the new
2211 * blob further below. Fall back to an entry covering all devices, which
2212 * is sufficient when no aliases are present.
2213 */
2214 object_child_foreach_recursive(object_get_root(),
2215 ivrs_host_bridges, ivhd_blob);
2216
2217 if (!ivhd_blob->len) {
2218 /*
2219 * Type 1 device entry reporting all devices
2220 * These are 4-byte device entries currently reporting the range of
2221 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2222 */
2223 build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
2224 }
2225
2226 ivhd_table_len += ivhd_blob->len;
2227
2228 /*
2229 * When interrupt remapping is supported, we add a special IVHD device
2230 * for type IO-APIC.
2231 */
2232 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2233 ivhd_table_len += 8;
2234 }
2235
2236 /* IVHD length */
2237 build_append_int_noprefix(table_data, ivhd_table_len, 2);
2238 /* DeviceID */
2239 build_append_int_noprefix(table_data, s->devid, 2);
2240 /* Capability offset */
2241 build_append_int_noprefix(table_data, s->capab_offset, 2);
2242 /* IOMMU base address */
2243 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2244 /* PCI Segment Group */
2245 build_append_int_noprefix(table_data, 0, 2);
2246 /* IOMMU info */
2247 build_append_int_noprefix(table_data, 0, 2);
2248 /* IOMMU Feature Reporting */
2249 build_append_int_noprefix(table_data,
2250 (48UL << 30) | /* HATS */
2251 (48UL << 28) | /* GATS */
2252 (1UL << 2) | /* GTSup */
2253 (1UL << 6), /* GASup */
2254 4);
2255
2256 /* IVHD entries as found above */
2257 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
2258 g_array_free(ivhd_blob, TRUE);
2259
2260 /*
2261 * Add a special IVHD device type.
2262 * Refer to spec - Table 95: IVHD device entry type codes
2263 *
2264 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2265 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2266 */
2267 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2268 build_append_int_noprefix(table_data,
2269 (0x1ull << 56) | /* type IOAPIC */
2270 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
2271 0x48, /* special device */
2272 8);
2273 }
2274
2275 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2276 "IVRS", table_data->len - iommu_start, 1, oem_id,
2277 oem_table_id);
2278 }
2279
2280 typedef
2281 struct AcpiBuildState {
2282 /* Copy of table in RAM (for patching). */
2283 MemoryRegion *table_mr;
2284 /* Is table patched? */
2285 uint8_t patched;
2286 void *rsdp;
2287 MemoryRegion *rsdp_mr;
2288 MemoryRegion *linker_mr;
2289 } AcpiBuildState;
2290
2291 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2292 {
2293 Object *pci_host;
2294 QObject *o;
2295
2296 pci_host = acpi_get_i386_pci_host();
2297 g_assert(pci_host);
2298
2299 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2300 if (!o) {
2301 return false;
2302 }
2303 mcfg->base = qnum_get_uint(qobject_to(QNum, o));
2304 qobject_unref(o);
2305 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
2306 return false;
2307 }
2308
2309 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2310 assert(o);
2311 mcfg->size = qnum_get_uint(qobject_to(QNum, o));
2312 qobject_unref(o);
2313 return true;
2314 }
2315
2316 static
2317 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2318 {
2319 PCMachineState *pcms = PC_MACHINE(machine);
2320 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2321 X86MachineState *x86ms = X86_MACHINE(machine);
2322 GArray *table_offsets;
2323 unsigned facs, dsdt, rsdt, fadt;
2324 AcpiPmInfo pm;
2325 AcpiMiscInfo misc;
2326 AcpiMcfgInfo mcfg;
2327 Range pci_hole, pci_hole64;
2328 uint8_t *u;
2329 size_t aml_len = 0;
2330 GArray *tables_blob = tables->table_data;
2331 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2332 Object *vmgenid_dev;
2333 char *oem_id;
2334 char *oem_table_id;
2335
2336 acpi_get_pm_info(machine, &pm);
2337 acpi_get_misc_info(&misc);
2338 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2339 acpi_get_slic_oem(&slic_oem);
2340
2341 if (slic_oem.id) {
2342 oem_id = slic_oem.id;
2343 } else {
2344 oem_id = x86ms->oem_id;
2345 }
2346
2347 if (slic_oem.table_id) {
2348 oem_table_id = slic_oem.table_id;
2349 } else {
2350 oem_table_id = x86ms->oem_table_id;
2351 }
2352
2353 table_offsets = g_array_new(false, true /* clear */,
2354 sizeof(uint32_t));
2355 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2356
2357 bios_linker_loader_alloc(tables->linker,
2358 ACPI_BUILD_TABLE_FILE, tables_blob,
2359 64 /* Ensure FACS is aligned */,
2360 false /* high memory */);
2361
2362 /*
2363 * FACS is pointed to by FADT.
2364 * We place it first since it's the only table that has alignment
2365 * requirements.
2366 */
2367 facs = tables_blob->len;
2368 build_facs(tables_blob);
2369
2370 /* DSDT is pointed to by FADT */
2371 dsdt = tables_blob->len;
2372 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2373 &pci_hole, &pci_hole64, machine);
2374
2375 /* Count the size of the DSDT and SSDT, we will need it for legacy
2376 * sizing of ACPI tables.
2377 */
2378 aml_len += tables_blob->len - dsdt;
2379
2380 /* ACPI tables pointed to by RSDT */
2381 fadt = tables_blob->len;
2382 acpi_add_table(table_offsets, tables_blob);
2383 pm.fadt.facs_tbl_offset = &facs;
2384 pm.fadt.dsdt_tbl_offset = &dsdt;
2385 pm.fadt.xdsdt_tbl_offset = &dsdt;
2386 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id);
2387 aml_len += tables_blob->len - fadt;
2388
2389 acpi_add_table(table_offsets, tables_blob);
2390 acpi_build_madt(tables_blob, tables->linker, x86ms,
2391 ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id,
2392 x86ms->oem_table_id);
2393
2394 vmgenid_dev = find_vmgenid_dev();
2395 if (vmgenid_dev) {
2396 acpi_add_table(table_offsets, tables_blob);
2397 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2398 tables->vmgenid, tables->linker, x86ms->oem_id);
2399 }
2400
2401 if (misc.has_hpet) {
2402 acpi_add_table(table_offsets, tables_blob);
2403 build_hpet(tables_blob, tables->linker, x86ms->oem_id,
2404 x86ms->oem_table_id);
2405 }
2406 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2407 if (misc.tpm_version == TPM_VERSION_1_2) {
2408 acpi_add_table(table_offsets, tables_blob);
2409 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog,
2410 x86ms->oem_id, x86ms->oem_table_id);
2411 } else { /* TPM_VERSION_2_0 */
2412 acpi_add_table(table_offsets, tables_blob);
2413 build_tpm2(tables_blob, tables->linker, tables->tcpalog,
2414 x86ms->oem_id, x86ms->oem_table_id);
2415 }
2416 }
2417 if (pcms->numa_nodes) {
2418 acpi_add_table(table_offsets, tables_blob);
2419 build_srat(tables_blob, tables->linker, machine);
2420 if (machine->numa_state->have_numa_distance) {
2421 acpi_add_table(table_offsets, tables_blob);
2422 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id,
2423 x86ms->oem_table_id);
2424 }
2425 if (machine->numa_state->hmat_enabled) {
2426 acpi_add_table(table_offsets, tables_blob);
2427 build_hmat(tables_blob, tables->linker, machine->numa_state,
2428 x86ms->oem_id, x86ms->oem_table_id);
2429 }
2430 }
2431 if (acpi_get_mcfg(&mcfg)) {
2432 acpi_add_table(table_offsets, tables_blob);
2433 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id,
2434 x86ms->oem_table_id);
2435 }
2436 if (x86_iommu_get_default()) {
2437 IommuType IOMMUType = x86_iommu_get_type();
2438 if (IOMMUType == TYPE_AMD) {
2439 acpi_add_table(table_offsets, tables_blob);
2440 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id,
2441 x86ms->oem_table_id);
2442 } else if (IOMMUType == TYPE_INTEL) {
2443 acpi_add_table(table_offsets, tables_blob);
2444 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id,
2445 x86ms->oem_table_id);
2446 }
2447 }
2448 if (machine->nvdimms_state->is_enabled) {
2449 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2450 machine->nvdimms_state, machine->ram_slots,
2451 x86ms->oem_id, x86ms->oem_table_id);
2452 }
2453
2454 acpi_add_table(table_offsets, tables_blob);
2455 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id);
2456
2457 /* Add tables supplied by user (if any) */
2458 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2459 unsigned len = acpi_table_len(u);
2460
2461 acpi_add_table(table_offsets, tables_blob);
2462 g_array_append_vals(tables_blob, u, len);
2463 }
2464
2465 /* RSDT is pointed to by RSDP */
2466 rsdt = tables_blob->len;
2467 build_rsdt(tables_blob, tables->linker, table_offsets,
2468 oem_id, oem_table_id);
2469
2470 /* RSDP is in FSEG memory, so allocate it separately */
2471 {
2472 AcpiRsdpData rsdp_data = {
2473 .revision = 0,
2474 .oem_id = x86ms->oem_id,
2475 .xsdt_tbl_offset = NULL,
2476 .rsdt_tbl_offset = &rsdt,
2477 };
2478 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2479 if (!pcmc->rsdp_in_ram) {
2480 /* We used to allocate some extra space for RSDP revision 2 but
2481 * only used the RSDP revision 0 space. The extra bytes were
2482 * zeroed out and not used.
2483 * Here we continue wasting those extra 16 bytes to make sure we
2484 * don't break migration for machine types 2.2 and older due to
2485 * RSDP blob size mismatch.
2486 */
2487 build_append_int_noprefix(tables->rsdp, 0, 16);
2488 }
2489 }
2490
2491 /* We'll expose it all to Guest so we want to reduce
2492 * chance of size changes.
2493 *
2494 * We used to align the tables to 4k, but of course this would
2495 * too simple to be enough. 4k turned out to be too small an
2496 * alignment very soon, and in fact it is almost impossible to
2497 * keep the table size stable for all (max_cpus, max_memory_slots)
2498 * combinations. So the table size is always 64k for pc-i440fx-2.1
2499 * and we give an error if the table grows beyond that limit.
2500 *
2501 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2502 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2503 * than 2.0 and we can always pad the smaller tables with zeros. We can
2504 * then use the exact size of the 2.0 tables.
2505 *
2506 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2507 */
2508 if (pcmc->legacy_acpi_table_size) {
2509 /* Subtracting aml_len gives the size of fixed tables. Then add the
2510 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2511 */
2512 int legacy_aml_len =
2513 pcmc->legacy_acpi_table_size +
2514 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit;
2515 int legacy_table_size =
2516 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2517 ACPI_BUILD_ALIGN_SIZE);
2518 if (tables_blob->len > legacy_table_size) {
2519 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2520 warn_report("ACPI table size %u exceeds %d bytes,"
2521 " migration may not work",
2522 tables_blob->len, legacy_table_size);
2523 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2524 " or PCI bridges.");
2525 }
2526 g_array_set_size(tables_blob, legacy_table_size);
2527 } else {
2528 /* Make sure we have a buffer in case we need to resize the tables. */
2529 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2530 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2531 warn_report("ACPI table size %u exceeds %d bytes,"
2532 " migration may not work",
2533 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2534 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2535 " or PCI bridges.");
2536 }
2537 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2538 }
2539
2540 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2541
2542 /* Cleanup memory that's no longer used. */
2543 g_array_free(table_offsets, true);
2544 }
2545
2546 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2547 {
2548 uint32_t size = acpi_data_len(data);
2549
2550 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2551 memory_region_ram_resize(mr, size, &error_abort);
2552
2553 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2554 memory_region_set_dirty(mr, 0, size);
2555 }
2556
2557 static void acpi_build_update(void *build_opaque)
2558 {
2559 AcpiBuildState *build_state = build_opaque;
2560 AcpiBuildTables tables;
2561
2562 /* No state to update or already patched? Nothing to do. */
2563 if (!build_state || build_state->patched) {
2564 return;
2565 }
2566 build_state->patched = 1;
2567
2568 acpi_build_tables_init(&tables);
2569
2570 acpi_build(&tables, MACHINE(qdev_get_machine()));
2571
2572 acpi_ram_update(build_state->table_mr, tables.table_data);
2573
2574 if (build_state->rsdp) {
2575 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2576 } else {
2577 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2578 }
2579
2580 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2581 acpi_build_tables_cleanup(&tables, true);
2582 }
2583
2584 static void acpi_build_reset(void *build_opaque)
2585 {
2586 AcpiBuildState *build_state = build_opaque;
2587 build_state->patched = 0;
2588 }
2589
2590 static const VMStateDescription vmstate_acpi_build = {
2591 .name = "acpi_build",
2592 .version_id = 1,
2593 .minimum_version_id = 1,
2594 .fields = (VMStateField[]) {
2595 VMSTATE_UINT8(patched, AcpiBuildState),
2596 VMSTATE_END_OF_LIST()
2597 },
2598 };
2599
2600 void acpi_setup(void)
2601 {
2602 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2603 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2604 X86MachineState *x86ms = X86_MACHINE(pcms);
2605 AcpiBuildTables tables;
2606 AcpiBuildState *build_state;
2607 Object *vmgenid_dev;
2608 TPMIf *tpm;
2609 static FwCfgTPMConfig tpm_config;
2610
2611 if (!x86ms->fw_cfg) {
2612 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2613 return;
2614 }
2615
2616 if (!pcms->acpi_build_enabled) {
2617 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2618 return;
2619 }
2620
2621 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
2622 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2623 return;
2624 }
2625
2626 build_state = g_malloc0(sizeof *build_state);
2627
2628 acpi_build_tables_init(&tables);
2629 acpi_build(&tables, MACHINE(pcms));
2630
2631 /* Now expose it all to Guest */
2632 build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
2633 build_state, tables.table_data,
2634 ACPI_BUILD_TABLE_FILE);
2635 assert(build_state->table_mr != NULL);
2636
2637 build_state->linker_mr =
2638 acpi_add_rom_blob(acpi_build_update, build_state,
2639 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE);
2640
2641 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2642 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2643
2644 tpm = tpm_find();
2645 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
2646 tpm_config = (FwCfgTPMConfig) {
2647 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2648 .tpm_version = tpm_get_version(tpm),
2649 .tpmppi_version = TPM_PPI_VERSION_1_30
2650 };
2651 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
2652 &tpm_config, sizeof tpm_config);
2653 }
2654
2655 vmgenid_dev = find_vmgenid_dev();
2656 if (vmgenid_dev) {
2657 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
2658 tables.vmgenid);
2659 }
2660
2661 if (!pcmc->rsdp_in_ram) {
2662 /*
2663 * Keep for compatibility with old machine types.
2664 * Though RSDP is small, its contents isn't immutable, so
2665 * we'll update it along with the rest of tables on guest access.
2666 */
2667 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2668
2669 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2670 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2671 acpi_build_update, NULL, build_state,
2672 build_state->rsdp, rsdp_size, true);
2673 build_state->rsdp_mr = NULL;
2674 } else {
2675 build_state->rsdp = NULL;
2676 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
2677 build_state, tables.rsdp,
2678 ACPI_BUILD_RSDP_FILE);
2679 }
2680
2681 qemu_register_reset(acpi_build_reset, build_state);
2682 acpi_build_reset(build_state);
2683 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2684
2685 /* Cleanup tables but don't free the memory: we track it
2686 * in build_state.
2687 */
2688 acpi_build_tables_cleanup(&tables, false);
2689 }
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