]> git.proxmox.com Git - mirror_qemu.git/blob - hw/i386/acpi-build.c
projects / mirror_qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
target-sparc: Use tcg_gen_atomic_cmpxchg_tl
[mirror_qemu.git] / hw / i386 / acpi-build.c
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "acpi-build.h"
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
30 #include "qom/cpu.h"
31 #include "hw/i386/pc.h"
32 #include "target-i386/cpu.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/acpi/cpu.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "sysemu/tpm_backend.h"
46 #include "hw/timer/mc146818rtc_regs.h"
47 #include "sysemu/numa.h"
48
49 /* Supported chipsets: */
50 #include "hw/acpi/piix4.h"
51 #include "hw/acpi/pcihp.h"
52 #include "hw/i386/ich9.h"
53 #include "hw/pci/pci_bus.h"
54 #include "hw/pci-host/q35.h"
55 #include "hw/i386/x86-iommu.h"
56 #include "hw/timer/hpet.h"
57
58 #include "hw/acpi/aml-build.h"
59
60 #include "qapi/qmp/qint.h"
61 #include "qom/qom-qobject.h"
62 #include "hw/i386/amd_iommu.h"
63 #include "hw/i386/intel_iommu.h"
64
65 #include "hw/acpi/ipmi.h"
66
67 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
68 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
69 * a little bit, there should be plenty of free space since the DSDT
70 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
71 */
72 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
73 #define ACPI_BUILD_ALIGN_SIZE 0x1000
74
75 #define ACPI_BUILD_TABLE_SIZE 0x20000
76
77 /* #define DEBUG_ACPI_BUILD */
78 #ifdef DEBUG_ACPI_BUILD
79 #define ACPI_BUILD_DPRINTF(fmt, ...) \
80 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
81 #else
82 #define ACPI_BUILD_DPRINTF(fmt, ...)
83 #endif
84
85 /* Default IOAPIC ID */
86 #define ACPI_BUILD_IOAPIC_ID 0x0
87
88 typedef struct AcpiMcfgInfo {
89 uint64_t mcfg_base;
90 uint32_t mcfg_size;
91 } AcpiMcfgInfo;
92
93 typedef struct AcpiPmInfo {
94 bool s3_disabled;
95 bool s4_disabled;
96 bool pcihp_bridge_en;
97 uint8_t s4_val;
98 uint16_t sci_int;
99 uint8_t acpi_enable_cmd;
100 uint8_t acpi_disable_cmd;
101 uint32_t gpe0_blk;
102 uint32_t gpe0_blk_len;
103 uint32_t io_base;
104 uint16_t cpu_hp_io_base;
105 uint16_t mem_hp_io_base;
106 uint16_t mem_hp_io_len;
107 uint16_t pcihp_io_base;
108 uint16_t pcihp_io_len;
109 } AcpiPmInfo;
110
111 typedef struct AcpiMiscInfo {
112 bool is_piix4;
113 bool has_hpet;
114 TPMVersion tpm_version;
115 const unsigned char *dsdt_code;
116 unsigned dsdt_size;
117 uint16_t pvpanic_port;
118 uint16_t applesmc_io_base;
119 } AcpiMiscInfo;
120
121 typedef struct AcpiBuildPciBusHotplugState {
122 GArray *device_table;
123 GArray *notify_table;
124 struct AcpiBuildPciBusHotplugState *parent;
125 bool pcihp_bridge_en;
126 } AcpiBuildPciBusHotplugState;
127
128 static void acpi_get_pm_info(AcpiPmInfo *pm)
129 {
130 Object *piix = piix4_pm_find();
131 Object *lpc = ich9_lpc_find();
132 Object *obj = NULL;
133 QObject *o;
134
135 pm->cpu_hp_io_base = 0;
136 pm->pcihp_io_base = 0;
137 pm->pcihp_io_len = 0;
138 if (piix) {
139 obj = piix;
140 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
141 pm->pcihp_io_base =
142 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
143 pm->pcihp_io_len =
144 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
145 }
146 if (lpc) {
147 obj = lpc;
148 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
149 }
150 assert(obj);
151
152 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
153 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
154
155 /* Fill in optional s3/s4 related properties */
156 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
157 if (o) {
158 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
159 } else {
160 pm->s3_disabled = false;
161 }
162 qobject_decref(o);
163 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
164 if (o) {
165 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
166 } else {
167 pm->s4_disabled = false;
168 }
169 qobject_decref(o);
170 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
171 if (o) {
172 pm->s4_val = qint_get_int(qobject_to_qint(o));
173 } else {
174 pm->s4_val = false;
175 }
176 qobject_decref(o);
177
178 /* Fill in mandatory properties */
179 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
180
181 pm->acpi_enable_cmd = object_property_get_int(obj,
182 ACPI_PM_PROP_ACPI_ENABLE_CMD,
183 NULL);
184 pm->acpi_disable_cmd = object_property_get_int(obj,
185 ACPI_PM_PROP_ACPI_DISABLE_CMD,
186 NULL);
187 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
188 NULL);
189 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
190 NULL);
191 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
192 NULL);
193 pm->pcihp_bridge_en =
194 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
195 NULL);
196 }
197
198 static void acpi_get_misc_info(AcpiMiscInfo *info)
199 {
200 Object *piix = piix4_pm_find();
201 Object *lpc = ich9_lpc_find();
202 assert(!!piix != !!lpc);
203
204 if (piix) {
205 info->is_piix4 = true;
206 }
207 if (lpc) {
208 info->is_piix4 = false;
209 }
210
211 info->has_hpet = hpet_find();
212 info->tpm_version = tpm_get_version();
213 info->pvpanic_port = pvpanic_port();
214 info->applesmc_io_base = applesmc_port();
215 }
216
217 /*
218 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
219 * On i386 arch we only have two pci hosts, so we can look only for them.
220 */
221 static Object *acpi_get_i386_pci_host(void)
222 {
223 PCIHostState *host;
224
225 host = OBJECT_CHECK(PCIHostState,
226 object_resolve_path("/machine/i440fx", NULL),
227 TYPE_PCI_HOST_BRIDGE);
228 if (!host) {
229 host = OBJECT_CHECK(PCIHostState,
230 object_resolve_path("/machine/q35", NULL),
231 TYPE_PCI_HOST_BRIDGE);
232 }
233
234 return OBJECT(host);
235 }
236
237 static void acpi_get_pci_holes(Range *hole, Range *hole64)
238 {
239 Object *pci_host;
240
241 pci_host = acpi_get_i386_pci_host();
242 g_assert(pci_host);
243
244 range_set_bounds1(hole,
245 object_property_get_int(pci_host,
246 PCI_HOST_PROP_PCI_HOLE_START,
247 NULL),
248 object_property_get_int(pci_host,
249 PCI_HOST_PROP_PCI_HOLE_END,
250 NULL));
251 range_set_bounds1(hole64,
252 object_property_get_int(pci_host,
253 PCI_HOST_PROP_PCI_HOLE64_START,
254 NULL),
255 object_property_get_int(pci_host,
256 PCI_HOST_PROP_PCI_HOLE64_END,
257 NULL));
258 }
259
260 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
261
262 static void acpi_align_size(GArray *blob, unsigned align)
263 {
264 /* Align size to multiple of given size. This reduces the chance
265 * we need to change size in the future (breaking cross version migration).
266 */
267 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
268 }
269
270 /* FACS */
271 static void
272 build_facs(GArray *table_data, BIOSLinker *linker)
273 {
274 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
275 memcpy(&facs->signature, "FACS", 4);
276 facs->length = cpu_to_le32(sizeof(*facs));
277 }
278
279 /* Load chipset information in FADT */
280 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
281 {
282 fadt->model = 1;
283 fadt->reserved1 = 0;
284 fadt->sci_int = cpu_to_le16(pm->sci_int);
285 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
286 fadt->acpi_enable = pm->acpi_enable_cmd;
287 fadt->acpi_disable = pm->acpi_disable_cmd;
288 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
289 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
290 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
291 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
292 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
293 /* EVT, CNT, TMR length matches hw/acpi/core.c */
294 fadt->pm1_evt_len = 4;
295 fadt->pm1_cnt_len = 2;
296 fadt->pm_tmr_len = 4;
297 fadt->gpe0_blk_len = pm->gpe0_blk_len;
298 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
299 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
300 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
301 (1 << ACPI_FADT_F_PROC_C1) |
302 (1 << ACPI_FADT_F_SLP_BUTTON) |
303 (1 << ACPI_FADT_F_RTC_S4));
304 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
305 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
306 * For more than 8 CPUs, "Clustered Logical" mode has to be used
307 */
308 if (max_cpus > 8) {
309 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
310 }
311 fadt->century = RTC_CENTURY;
312 }
313
314
315 /* FADT */
316 static void
317 build_fadt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm,
318 unsigned facs_tbl_offset, unsigned dsdt_tbl_offset,
319 const char *oem_id, const char *oem_table_id)
320 {
321 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
322 unsigned fw_ctrl_offset = (char *)&fadt->firmware_ctrl - table_data->data;
323 unsigned dsdt_entry_offset = (char *)&fadt->dsdt - table_data->data;
324
325 /* FACS address to be filled by Guest linker */
326 bios_linker_loader_add_pointer(linker,
327 ACPI_BUILD_TABLE_FILE, fw_ctrl_offset, sizeof(fadt->firmware_ctrl),
328 ACPI_BUILD_TABLE_FILE, facs_tbl_offset);
329
330 /* DSDT address to be filled by Guest linker */
331 fadt_setup(fadt, pm);
332 bios_linker_loader_add_pointer(linker,
333 ACPI_BUILD_TABLE_FILE, dsdt_entry_offset, sizeof(fadt->dsdt),
334 ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset);
335
336 build_header(linker, table_data,
337 (void *)fadt, "FACP", sizeof(*fadt), 1, oem_id, oem_table_id);
338 }
339
340 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
341 CPUArchIdList *apic_ids, GArray *entry)
342 {
343 uint32_t apic_id = apic_ids->cpus[uid].arch_id;
344
345 /* ACPI spec says that LAPIC entry for non present
346 * CPU may be omitted from MADT or it must be marked
347 * as disabled. However omitting non present CPU from
348 * MADT breaks hotplug on linux. So possible CPUs
349 * should be put in MADT but kept disabled.
350 */
351 if (apic_id < 255) {
352 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
353
354 apic->type = ACPI_APIC_PROCESSOR;
355 apic->length = sizeof(*apic);
356 apic->processor_id = uid;
357 apic->local_apic_id = apic_id;
358 if (apic_ids->cpus[uid].cpu != NULL) {
359 apic->flags = cpu_to_le32(1);
360 } else {
361 apic->flags = cpu_to_le32(0);
362 }
363 } else {
364 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic);
365
366 apic->type = ACPI_APIC_LOCAL_X2APIC;
367 apic->length = sizeof(*apic);
368 apic->uid = cpu_to_le32(uid);
369 apic->x2apic_id = cpu_to_le32(apic_id);
370 if (apic_ids->cpus[uid].cpu != NULL) {
371 apic->flags = cpu_to_le32(1);
372 } else {
373 apic->flags = cpu_to_le32(0);
374 }
375 }
376 }
377
378 static void
379 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
380 {
381 MachineClass *mc = MACHINE_GET_CLASS(pcms);
382 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
383 int madt_start = table_data->len;
384 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
385 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
386 bool x2apic_mode = false;
387
388 AcpiMultipleApicTable *madt;
389 AcpiMadtIoApic *io_apic;
390 AcpiMadtIntsrcovr *intsrcovr;
391 int i;
392
393 madt = acpi_data_push(table_data, sizeof *madt);
394 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
395 madt->flags = cpu_to_le32(1);
396
397 for (i = 0; i < apic_ids->len; i++) {
398 adevc->madt_cpu(adev, i, apic_ids, table_data);
399 if (apic_ids->cpus[i].arch_id > 254) {
400 x2apic_mode = true;
401 }
402 }
403 g_free(apic_ids);
404
405 io_apic = acpi_data_push(table_data, sizeof *io_apic);
406 io_apic->type = ACPI_APIC_IO;
407 io_apic->length = sizeof(*io_apic);
408 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
409 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
410 io_apic->interrupt = cpu_to_le32(0);
411
412 if (pcms->apic_xrupt_override) {
413 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
414 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
415 intsrcovr->length = sizeof(*intsrcovr);
416 intsrcovr->source = 0;
417 intsrcovr->gsi = cpu_to_le32(2);
418 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
419 }
420 for (i = 1; i < 16; i++) {
421 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
422 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
423 /* No need for a INT source override structure. */
424 continue;
425 }
426 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
427 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
428 intsrcovr->length = sizeof(*intsrcovr);
429 intsrcovr->source = i;
430 intsrcovr->gsi = cpu_to_le32(i);
431 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
432 }
433
434 if (x2apic_mode) {
435 AcpiMadtLocalX2ApicNmi *local_nmi;
436
437 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
438 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI;
439 local_nmi->length = sizeof(*local_nmi);
440 local_nmi->uid = 0xFFFFFFFF; /* all processors */
441 local_nmi->flags = cpu_to_le16(0);
442 local_nmi->lint = 1; /* ACPI_LINT1 */
443 } else {
444 AcpiMadtLocalNmi *local_nmi;
445
446 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
447 local_nmi->type = ACPI_APIC_LOCAL_NMI;
448 local_nmi->length = sizeof(*local_nmi);
449 local_nmi->processor_id = 0xff; /* all processors */
450 local_nmi->flags = cpu_to_le16(0);
451 local_nmi->lint = 1; /* ACPI_LINT1 */
452 }
453
454 build_header(linker, table_data,
455 (void *)(table_data->data + madt_start), "APIC",
456 table_data->len - madt_start, 1, NULL, NULL);
457 }
458
459 /* Assign BSEL property to all buses. In the future, this can be changed
460 * to only assign to buses that support hotplug.
461 */
462 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
463 {
464 unsigned *bsel_alloc = opaque;
465 unsigned *bus_bsel;
466
467 if (qbus_is_hotpluggable(BUS(bus))) {
468 bus_bsel = g_malloc(sizeof *bus_bsel);
469
470 *bus_bsel = (*bsel_alloc)++;
471 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
472 bus_bsel, NULL);
473 }
474
475 return bsel_alloc;
476 }
477
478 static void acpi_set_pci_info(void)
479 {
480 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
481 unsigned bsel_alloc = 0;
482
483 if (bus) {
484 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
485 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
486 }
487 }
488
489 static void build_append_pcihp_notify_entry(Aml *method, int slot)
490 {
491 Aml *if_ctx;
492 int32_t devfn = PCI_DEVFN(slot, 0);
493
494 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
495 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
496 aml_append(method, if_ctx);
497 }
498
499 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
500 bool pcihp_bridge_en)
501 {
502 Aml *dev, *notify_method, *method;
503 QObject *bsel;
504 PCIBus *sec;
505 int i;
506
507 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
508 if (bsel) {
509 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
510
511 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
512 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
513 }
514
515 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
516 DeviceClass *dc;
517 PCIDeviceClass *pc;
518 PCIDevice *pdev = bus->devices[i];
519 int slot = PCI_SLOT(i);
520 bool hotplug_enabled_dev;
521 bool bridge_in_acpi;
522
523 if (!pdev) {
524 if (bsel) { /* add hotplug slots for non present devices */
525 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
526 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
527 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
528 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
529 aml_append(method,
530 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
531 );
532 aml_append(dev, method);
533 aml_append(parent_scope, dev);
534
535 build_append_pcihp_notify_entry(notify_method, slot);
536 }
537 continue;
538 }
539
540 pc = PCI_DEVICE_GET_CLASS(pdev);
541 dc = DEVICE_GET_CLASS(pdev);
542
543 /* When hotplug for bridges is enabled, bridges are
544 * described in ACPI separately (see build_pci_bus_end).
545 * In this case they aren't themselves hot-pluggable.
546 * Hotplugged bridges *are* hot-pluggable.
547 */
548 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
549 !DEVICE(pdev)->hotplugged;
550
551 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
552
553 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
554 continue;
555 }
556
557 /* start to compose PCI slot descriptor */
558 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
559 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
560
561 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
562 /* add VGA specific AML methods */
563 int s3d;
564
565 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
566 s3d = 3;
567 } else {
568 s3d = 0;
569 }
570
571 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
572 aml_append(method, aml_return(aml_int(0)));
573 aml_append(dev, method);
574
575 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
576 aml_append(method, aml_return(aml_int(0)));
577 aml_append(dev, method);
578
579 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
580 aml_append(method, aml_return(aml_int(s3d)));
581 aml_append(dev, method);
582 } else if (hotplug_enabled_dev) {
583 /* add _SUN/_EJ0 to make slot hotpluggable */
584 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
585
586 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
587 aml_append(method,
588 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
589 );
590 aml_append(dev, method);
591
592 if (bsel) {
593 build_append_pcihp_notify_entry(notify_method, slot);
594 }
595 } else if (bridge_in_acpi) {
596 /*
597 * device is coldplugged bridge,
598 * add child device descriptions into its scope
599 */
600 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
601
602 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
603 }
604 /* slot descriptor has been composed, add it into parent context */
605 aml_append(parent_scope, dev);
606 }
607
608 if (bsel) {
609 aml_append(parent_scope, notify_method);
610 }
611
612 /* Append PCNT method to notify about events on local and child buses.
613 * Add unconditionally for root since DSDT expects it.
614 */
615 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
616
617 /* If bus supports hotplug select it and notify about local events */
618 if (bsel) {
619 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
620 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
621 aml_append(method,
622 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
623 );
624 aml_append(method,
625 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
626 );
627 }
628
629 /* Notify about child bus events in any case */
630 if (pcihp_bridge_en) {
631 QLIST_FOREACH(sec, &bus->child, sibling) {
632 int32_t devfn = sec->parent_dev->devfn;
633
634 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
635 continue;
636 }
637
638 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
639 }
640 }
641 aml_append(parent_scope, method);
642 qobject_decref(bsel);
643 }
644
645 /**
646 * build_prt_entry:
647 * @link_name: link name for PCI route entry
648 *
649 * build AML package containing a PCI route entry for @link_name
650 */
651 static Aml *build_prt_entry(const char *link_name)
652 {
653 Aml *a_zero = aml_int(0);
654 Aml *pkg = aml_package(4);
655 aml_append(pkg, a_zero);
656 aml_append(pkg, a_zero);
657 aml_append(pkg, aml_name("%s", link_name));
658 aml_append(pkg, a_zero);
659 return pkg;
660 }
661
662 /*
663 * initialize_route - Initialize the interrupt routing rule
664 * through a specific LINK:
665 * if (lnk_idx == idx)
666 * route using link 'link_name'
667 */
668 static Aml *initialize_route(Aml *route, const char *link_name,
669 Aml *lnk_idx, int idx)
670 {
671 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
672 Aml *pkg = build_prt_entry(link_name);
673
674 aml_append(if_ctx, aml_store(pkg, route));
675
676 return if_ctx;
677 }
678
679 /*
680 * build_prt - Define interrupt rounting rules
681 *
682 * Returns an array of 128 routes, one for each device,
683 * based on device location.
684 * The main goal is to equaly distribute the interrupts
685 * over the 4 existing ACPI links (works only for i440fx).
686 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
687 *
688 */
689 static Aml *build_prt(bool is_pci0_prt)
690 {
691 Aml *method, *while_ctx, *pin, *res;
692
693 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
694 res = aml_local(0);
695 pin = aml_local(1);
696 aml_append(method, aml_store(aml_package(128), res));
697 aml_append(method, aml_store(aml_int(0), pin));
698
699 /* while (pin < 128) */
700 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
701 {
702 Aml *slot = aml_local(2);
703 Aml *lnk_idx = aml_local(3);
704 Aml *route = aml_local(4);
705
706 /* slot = pin >> 2 */
707 aml_append(while_ctx,
708 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
709 /* lnk_idx = (slot + pin) & 3 */
710 aml_append(while_ctx,
711 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
712 lnk_idx));
713
714 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
715 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
716 if (is_pci0_prt) {
717 Aml *if_device_1, *if_pin_4, *else_pin_4;
718
719 /* device 1 is the power-management device, needs SCI */
720 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
721 {
722 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
723 {
724 aml_append(if_pin_4,
725 aml_store(build_prt_entry("LNKS"), route));
726 }
727 aml_append(if_device_1, if_pin_4);
728 else_pin_4 = aml_else();
729 {
730 aml_append(else_pin_4,
731 aml_store(build_prt_entry("LNKA"), route));
732 }
733 aml_append(if_device_1, else_pin_4);
734 }
735 aml_append(while_ctx, if_device_1);
736 } else {
737 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
738 }
739 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
740 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
741
742 /* route[0] = 0x[slot]FFFF */
743 aml_append(while_ctx,
744 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
745 NULL),
746 aml_index(route, aml_int(0))));
747 /* route[1] = pin & 3 */
748 aml_append(while_ctx,
749 aml_store(aml_and(pin, aml_int(3), NULL),
750 aml_index(route, aml_int(1))));
751 /* res[pin] = route */
752 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
753 /* pin++ */
754 aml_append(while_ctx, aml_increment(pin));
755 }
756 aml_append(method, while_ctx);
757 /* return res*/
758 aml_append(method, aml_return(res));
759
760 return method;
761 }
762
763 typedef struct CrsRangeEntry {
764 uint64_t base;
765 uint64_t limit;
766 } CrsRangeEntry;
767
768 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
769 {
770 CrsRangeEntry *entry;
771
772 entry = g_malloc(sizeof(*entry));
773 entry->base = base;
774 entry->limit = limit;
775
776 g_ptr_array_add(ranges, entry);
777 }
778
779 static void crs_range_free(gpointer data)
780 {
781 CrsRangeEntry *entry = (CrsRangeEntry *)data;
782 g_free(entry);
783 }
784
785 typedef struct CrsRangeSet {
786 GPtrArray *io_ranges;
787 GPtrArray *mem_ranges;
788 GPtrArray *mem_64bit_ranges;
789 } CrsRangeSet;
790
791 static void crs_range_set_init(CrsRangeSet *range_set)
792 {
793 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
794 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
795 range_set->mem_64bit_ranges =
796 g_ptr_array_new_with_free_func(crs_range_free);
797 }
798
799 static void crs_range_set_free(CrsRangeSet *range_set)
800 {
801 g_ptr_array_free(range_set->io_ranges, true);
802 g_ptr_array_free(range_set->mem_ranges, true);
803 g_ptr_array_free(range_set->mem_64bit_ranges, true);
804 }
805
806 static gint crs_range_compare(gconstpointer a, gconstpointer b)
807 {
808 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
809 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
810
811 return (int64_t)entry_a->base - (int64_t)entry_b->base;
812 }
813
814 /*
815 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
816 * interval, computes the 'free' ranges from the same interval.
817 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
818 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
819 */
820 static void crs_replace_with_free_ranges(GPtrArray *ranges,
821 uint64_t start, uint64_t end)
822 {
823 GPtrArray *free_ranges = g_ptr_array_new();
824 uint64_t free_base = start;
825 int i;
826
827 g_ptr_array_sort(ranges, crs_range_compare);
828 for (i = 0; i < ranges->len; i++) {
829 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
830
831 if (free_base < used->base) {
832 crs_range_insert(free_ranges, free_base, used->base - 1);
833 }
834
835 free_base = used->limit + 1;
836 }
837
838 if (free_base < end) {
839 crs_range_insert(free_ranges, free_base, end);
840 }
841
842 g_ptr_array_set_size(ranges, 0);
843 for (i = 0; i < free_ranges->len; i++) {
844 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
845 }
846
847 g_ptr_array_free(free_ranges, true);
848 }
849
850 /*
851 * crs_range_merge - merges adjacent ranges in the given array.
852 * Array elements are deleted and replaced with the merged ranges.
853 */
854 static void crs_range_merge(GPtrArray *range)
855 {
856 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
857 CrsRangeEntry *entry;
858 uint64_t range_base, range_limit;
859 int i;
860
861 if (!range->len) {
862 return;
863 }
864
865 g_ptr_array_sort(range, crs_range_compare);
866
867 entry = g_ptr_array_index(range, 0);
868 range_base = entry->base;
869 range_limit = entry->limit;
870 for (i = 1; i < range->len; i++) {
871 entry = g_ptr_array_index(range, i);
872 if (entry->base - 1 == range_limit) {
873 range_limit = entry->limit;
874 } else {
875 crs_range_insert(tmp, range_base, range_limit);
876 range_base = entry->base;
877 range_limit = entry->limit;
878 }
879 }
880 crs_range_insert(tmp, range_base, range_limit);
881
882 g_ptr_array_set_size(range, 0);
883 for (i = 0; i < tmp->len; i++) {
884 entry = g_ptr_array_index(tmp, i);
885 crs_range_insert(range, entry->base, entry->limit);
886 }
887 g_ptr_array_free(tmp, true);
888 }
889
890 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
891 {
892 Aml *crs = aml_resource_template();
893 CrsRangeSet temp_range_set;
894 CrsRangeEntry *entry;
895 uint8_t max_bus = pci_bus_num(host->bus);
896 uint8_t type;
897 int devfn;
898 int i;
899
900 crs_range_set_init(&temp_range_set);
901 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
902 uint64_t range_base, range_limit;
903 PCIDevice *dev = host->bus->devices[devfn];
904
905 if (!dev) {
906 continue;
907 }
908
909 for (i = 0; i < PCI_NUM_REGIONS; i++) {
910 PCIIORegion *r = &dev->io_regions[i];
911
912 range_base = r->addr;
913 range_limit = r->addr + r->size - 1;
914
915 /*
916 * Work-around for old bioses
917 * that do not support multiple root buses
918 */
919 if (!range_base || range_base > range_limit) {
920 continue;
921 }
922
923 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
924 crs_range_insert(temp_range_set.io_ranges,
925 range_base, range_limit);
926 } else { /* "memory" */
927 crs_range_insert(temp_range_set.mem_ranges,
928 range_base, range_limit);
929 }
930 }
931
932 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
933 if (type == PCI_HEADER_TYPE_BRIDGE) {
934 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
935 if (subordinate > max_bus) {
936 max_bus = subordinate;
937 }
938
939 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
940 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
941
942 /*
943 * Work-around for old bioses
944 * that do not support multiple root buses
945 */
946 if (range_base && range_base <= range_limit) {
947 crs_range_insert(temp_range_set.io_ranges,
948 range_base, range_limit);
949 }
950
951 range_base =
952 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
953 range_limit =
954 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
955
956 /*
957 * Work-around for old bioses
958 * that do not support multiple root buses
959 */
960 if (range_base && range_base <= range_limit) {
961 uint64_t length = range_limit - range_base + 1;
962 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
963 crs_range_insert(temp_range_set.mem_ranges,
964 range_base, range_limit);
965 } else {
966 crs_range_insert(temp_range_set.mem_64bit_ranges,
967 range_base, range_limit);
968 }
969 }
970
971 range_base =
972 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
973 range_limit =
974 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
975
976 /*
977 * Work-around for old bioses
978 * that do not support multiple root buses
979 */
980 if (range_base && range_base <= range_limit) {
981 uint64_t length = range_limit - range_base + 1;
982 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
983 crs_range_insert(temp_range_set.mem_ranges,
984 range_base, range_limit);
985 } else {
986 crs_range_insert(temp_range_set.mem_64bit_ranges,
987 range_base, range_limit);
988 }
989 }
990 }
991 }
992
993 crs_range_merge(temp_range_set.io_ranges);
994 for (i = 0; i < temp_range_set.io_ranges->len; i++) {
995 entry = g_ptr_array_index(temp_range_set.io_ranges, i);
996 aml_append(crs,
997 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
998 AML_POS_DECODE, AML_ENTIRE_RANGE,
999 0, entry->base, entry->limit, 0,
1000 entry->limit - entry->base + 1));
1001 crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
1002 }
1003
1004 crs_range_merge(temp_range_set.mem_ranges);
1005 for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
1006 entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
1007 aml_append(crs,
1008 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1009 AML_MAX_FIXED, AML_NON_CACHEABLE,
1010 AML_READ_WRITE,
1011 0, entry->base, entry->limit, 0,
1012 entry->limit - entry->base + 1));
1013 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
1014 }
1015
1016 crs_range_merge(temp_range_set.mem_64bit_ranges);
1017 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
1018 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
1019 aml_append(crs,
1020 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1021 AML_MAX_FIXED, AML_NON_CACHEABLE,
1022 AML_READ_WRITE,
1023 0, entry->base, entry->limit, 0,
1024 entry->limit - entry->base + 1));
1025 crs_range_insert(range_set->mem_64bit_ranges,
1026 entry->base, entry->limit);
1027 }
1028
1029 crs_range_set_free(&temp_range_set);
1030
1031 aml_append(crs,
1032 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1033 0,
1034 pci_bus_num(host->bus),
1035 max_bus,
1036 0,
1037 max_bus - pci_bus_num(host->bus) + 1));
1038
1039 return crs;
1040 }
1041
1042 static void build_memory_devices(Aml *sb_scope, int nr_mem,
1043 uint16_t io_base, uint16_t io_len)
1044 {
1045 int i;
1046 Aml *scope;
1047 Aml *crs;
1048 Aml *field;
1049 Aml *dev;
1050 Aml *method;
1051 Aml *ifctx;
1052
1053 /* build memory devices */
1054 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
1055 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE);
1056 aml_append(scope,
1057 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem))
1058 );
1059
1060 crs = aml_resource_template();
1061 aml_append(crs,
1062 aml_io(AML_DECODE16, io_base, io_base, 0, io_len)
1063 );
1064 aml_append(scope, aml_name_decl("_CRS", crs));
1065
1066 aml_append(scope, aml_operation_region(
1067 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO,
1068 aml_int(io_base), io_len)
1069 );
1070
1071 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1072 AML_NOLOCK, AML_PRESERVE);
1073 aml_append(field, /* read only */
1074 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32));
1075 aml_append(field, /* read only */
1076 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32));
1077 aml_append(field, /* read only */
1078 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32));
1079 aml_append(field, /* read only */
1080 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32));
1081 aml_append(field, /* read only */
1082 aml_named_field(MEMORY_SLOT_PROXIMITY, 32));
1083 aml_append(scope, field);
1084
1085 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC,
1086 AML_NOLOCK, AML_WRITE_AS_ZEROS);
1087 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1088 aml_append(field, /* 1 if enabled, read only */
1089 aml_named_field(MEMORY_SLOT_ENABLED, 1));
1090 aml_append(field,
1091 /*(read) 1 if has a insert event. (write) 1 to clear event */
1092 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1));
1093 aml_append(field,
1094 /* (read) 1 if has a remove event. (write) 1 to clear event */
1095 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1));
1096 aml_append(field,
1097 /* initiates device eject, write only */
1098 aml_named_field(MEMORY_SLOT_EJECT, 1));
1099 aml_append(scope, field);
1100
1101 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1102 AML_NOLOCK, AML_PRESERVE);
1103 aml_append(field, /* DIMM selector, write only */
1104 aml_named_field(MEMORY_SLOT_SLECTOR, 32));
1105 aml_append(field, /* _OST event code, write only */
1106 aml_named_field(MEMORY_SLOT_OST_EVENT, 32));
1107 aml_append(field, /* _OST status code, write only */
1108 aml_named_field(MEMORY_SLOT_OST_STATUS, 32));
1109 aml_append(scope, field);
1110 aml_append(sb_scope, scope);
1111
1112 for (i = 0; i < nr_mem; i++) {
1113 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
1114 const char *s;
1115
1116 dev = aml_device("MP%02X", i);
1117 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1118 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1119
1120 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1121 s = BASEPATH MEMORY_SLOT_CRS_METHOD;
1122 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1123 aml_append(dev, method);
1124
1125 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1126 s = BASEPATH MEMORY_SLOT_STATUS_METHOD;
1127 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1128 aml_append(dev, method);
1129
1130 method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
1131 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD;
1132 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1133 aml_append(dev, method);
1134
1135 method = aml_method("_OST", 3, AML_NOTSERIALIZED);
1136 s = BASEPATH MEMORY_SLOT_OST_METHOD;
1137
1138 aml_append(method, aml_return(aml_call4(
1139 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1140 )));
1141 aml_append(dev, method);
1142
1143 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1144 s = BASEPATH MEMORY_SLOT_EJECT_METHOD;
1145 aml_append(method, aml_return(aml_call2(
1146 s, aml_name("_UID"), aml_arg(0))));
1147 aml_append(dev, method);
1148
1149 aml_append(sb_scope, dev);
1150 }
1151
1152 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1153 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1154 */
1155 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1156 for (i = 0; i < nr_mem; i++) {
1157 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1158 aml_append(ifctx,
1159 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1160 );
1161 aml_append(method, ifctx);
1162 }
1163 aml_append(sb_scope, method);
1164 }
1165
1166 static void build_hpet_aml(Aml *table)
1167 {
1168 Aml *crs;
1169 Aml *field;
1170 Aml *method;
1171 Aml *if_ctx;
1172 Aml *scope = aml_scope("_SB");
1173 Aml *dev = aml_device("HPET");
1174 Aml *zero = aml_int(0);
1175 Aml *id = aml_local(0);
1176 Aml *period = aml_local(1);
1177
1178 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1179 aml_append(dev, aml_name_decl("_UID", zero));
1180
1181 aml_append(dev,
1182 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1183 HPET_LEN));
1184 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1185 aml_append(field, aml_named_field("VEND", 32));
1186 aml_append(field, aml_named_field("PRD", 32));
1187 aml_append(dev, field);
1188
1189 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1190 aml_append(method, aml_store(aml_name("VEND"), id));
1191 aml_append(method, aml_store(aml_name("PRD"), period));
1192 aml_append(method, aml_shiftright(id, aml_int(16), id));
1193 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1194 aml_equal(id, aml_int(0xffff))));
1195 {
1196 aml_append(if_ctx, aml_return(zero));
1197 }
1198 aml_append(method, if_ctx);
1199
1200 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1201 aml_lgreater(period, aml_int(100000000))));
1202 {
1203 aml_append(if_ctx, aml_return(zero));
1204 }
1205 aml_append(method, if_ctx);
1206
1207 aml_append(method, aml_return(aml_int(0x0F)));
1208 aml_append(dev, method);
1209
1210 crs = aml_resource_template();
1211 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1212 aml_append(dev, aml_name_decl("_CRS", crs));
1213
1214 aml_append(scope, dev);
1215 aml_append(table, scope);
1216 }
1217
1218 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
1219 {
1220 Aml *dev, *fdi;
1221 uint8_t maxc, maxh, maxs;
1222
1223 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1224
1225 dev = aml_device("FLP%c", 'A' + idx);
1226
1227 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1228
1229 fdi = aml_package(16);
1230 aml_append(fdi, aml_int(idx)); /* Drive Number */
1231 aml_append(fdi,
1232 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1233 /*
1234 * the values below are the limits of the drive, and are thus independent
1235 * of the inserted media
1236 */
1237 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1238 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1239 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1240 /*
1241 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1242 * the drive type, so shall we
1243 */
1244 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1245 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1246 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1247 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1248 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1249 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1250 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1251 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1252 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1253 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1254 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1255
1256 aml_append(dev, aml_name_decl("_FDI", fdi));
1257 return dev;
1258 }
1259
1260 static Aml *build_fdc_device_aml(ISADevice *fdc)
1261 {
1262 int i;
1263 Aml *dev;
1264 Aml *crs;
1265
1266 #define ACPI_FDE_MAX_FD 4
1267 uint32_t fde_buf[5] = {
1268 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1269 cpu_to_le32(2) /* tape presence (2 == never present) */
1270 };
1271
1272 dev = aml_device("FDC0");
1273 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1274
1275 crs = aml_resource_template();
1276 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1277 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1278 aml_append(crs, aml_irq_no_flags(6));
1279 aml_append(crs,
1280 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1281 aml_append(dev, aml_name_decl("_CRS", crs));
1282
1283 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1284 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1285
1286 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1287 fde_buf[i] = cpu_to_le32(1); /* drive present */
1288 aml_append(dev, build_fdinfo_aml(i, type));
1289 }
1290 }
1291 aml_append(dev, aml_name_decl("_FDE",
1292 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1293
1294 return dev;
1295 }
1296
1297 static Aml *build_rtc_device_aml(void)
1298 {
1299 Aml *dev;
1300 Aml *crs;
1301
1302 dev = aml_device("RTC");
1303 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1304 crs = aml_resource_template();
1305 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1306 aml_append(crs, aml_irq_no_flags(8));
1307 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1308 aml_append(dev, aml_name_decl("_CRS", crs));
1309
1310 return dev;
1311 }
1312
1313 static Aml *build_kbd_device_aml(void)
1314 {
1315 Aml *dev;
1316 Aml *crs;
1317 Aml *method;
1318
1319 dev = aml_device("KBD");
1320 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1321
1322 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1323 aml_append(method, aml_return(aml_int(0x0f)));
1324 aml_append(dev, method);
1325
1326 crs = aml_resource_template();
1327 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1328 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1329 aml_append(crs, aml_irq_no_flags(1));
1330 aml_append(dev, aml_name_decl("_CRS", crs));
1331
1332 return dev;
1333 }
1334
1335 static Aml *build_mouse_device_aml(void)
1336 {
1337 Aml *dev;
1338 Aml *crs;
1339 Aml *method;
1340
1341 dev = aml_device("MOU");
1342 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1343
1344 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1345 aml_append(method, aml_return(aml_int(0x0f)));
1346 aml_append(dev, method);
1347
1348 crs = aml_resource_template();
1349 aml_append(crs, aml_irq_no_flags(12));
1350 aml_append(dev, aml_name_decl("_CRS", crs));
1351
1352 return dev;
1353 }
1354
1355 static Aml *build_lpt_device_aml(void)
1356 {
1357 Aml *dev;
1358 Aml *crs;
1359 Aml *method;
1360 Aml *if_ctx;
1361 Aml *else_ctx;
1362 Aml *zero = aml_int(0);
1363 Aml *is_present = aml_local(0);
1364
1365 dev = aml_device("LPT");
1366 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1367
1368 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1369 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1370 if_ctx = aml_if(aml_equal(is_present, zero));
1371 {
1372 aml_append(if_ctx, aml_return(aml_int(0x00)));
1373 }
1374 aml_append(method, if_ctx);
1375 else_ctx = aml_else();
1376 {
1377 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1378 }
1379 aml_append(method, else_ctx);
1380 aml_append(dev, method);
1381
1382 crs = aml_resource_template();
1383 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1384 aml_append(crs, aml_irq_no_flags(7));
1385 aml_append(dev, aml_name_decl("_CRS", crs));
1386
1387 return dev;
1388 }
1389
1390 static Aml *build_com_device_aml(uint8_t uid)
1391 {
1392 Aml *dev;
1393 Aml *crs;
1394 Aml *method;
1395 Aml *if_ctx;
1396 Aml *else_ctx;
1397 Aml *zero = aml_int(0);
1398 Aml *is_present = aml_local(0);
1399 const char *enabled_field = "CAEN";
1400 uint8_t irq = 4;
1401 uint16_t io_port = 0x03F8;
1402
1403 assert(uid == 1 || uid == 2);
1404 if (uid == 2) {
1405 enabled_field = "CBEN";
1406 irq = 3;
1407 io_port = 0x02F8;
1408 }
1409
1410 dev = aml_device("COM%d", uid);
1411 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1412 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1413
1414 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1415 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1416 if_ctx = aml_if(aml_equal(is_present, zero));
1417 {
1418 aml_append(if_ctx, aml_return(aml_int(0x00)));
1419 }
1420 aml_append(method, if_ctx);
1421 else_ctx = aml_else();
1422 {
1423 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1424 }
1425 aml_append(method, else_ctx);
1426 aml_append(dev, method);
1427
1428 crs = aml_resource_template();
1429 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1430 aml_append(crs, aml_irq_no_flags(irq));
1431 aml_append(dev, aml_name_decl("_CRS", crs));
1432
1433 return dev;
1434 }
1435
1436 static void build_isa_devices_aml(Aml *table)
1437 {
1438 ISADevice *fdc = pc_find_fdc0();
1439 bool ambiguous;
1440
1441 Aml *scope = aml_scope("_SB.PCI0.ISA");
1442 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
1443
1444 aml_append(scope, build_rtc_device_aml());
1445 aml_append(scope, build_kbd_device_aml());
1446 aml_append(scope, build_mouse_device_aml());
1447 if (fdc) {
1448 aml_append(scope, build_fdc_device_aml(fdc));
1449 }
1450 aml_append(scope, build_lpt_device_aml());
1451 aml_append(scope, build_com_device_aml(1));
1452 aml_append(scope, build_com_device_aml(2));
1453
1454 if (ambiguous) {
1455 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1456 } else if (!obj) {
1457 error_report("No ISA bus, unable to define IPMI ACPI data");
1458 } else {
1459 build_acpi_ipmi_devices(scope, BUS(obj));
1460 }
1461
1462 aml_append(table, scope);
1463 }
1464
1465 static void build_dbg_aml(Aml *table)
1466 {
1467 Aml *field;
1468 Aml *method;
1469 Aml *while_ctx;
1470 Aml *scope = aml_scope("\\");
1471 Aml *buf = aml_local(0);
1472 Aml *len = aml_local(1);
1473 Aml *idx = aml_local(2);
1474
1475 aml_append(scope,
1476 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1477 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1478 aml_append(field, aml_named_field("DBGB", 8));
1479 aml_append(scope, field);
1480
1481 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1482
1483 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1484 aml_append(method, aml_to_buffer(buf, buf));
1485 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1486 aml_append(method, aml_store(aml_int(0), idx));
1487
1488 while_ctx = aml_while(aml_lless(idx, len));
1489 aml_append(while_ctx,
1490 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1491 aml_append(while_ctx, aml_increment(idx));
1492 aml_append(method, while_ctx);
1493
1494 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1495 aml_append(scope, method);
1496
1497 aml_append(table, scope);
1498 }
1499
1500 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1501 {
1502 Aml *dev;
1503 Aml *crs;
1504 Aml *method;
1505 uint32_t irqs[] = {5, 10, 11};
1506
1507 dev = aml_device("%s", name);
1508 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1509 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1510
1511 crs = aml_resource_template();
1512 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1513 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1514 aml_append(dev, aml_name_decl("_PRS", crs));
1515
1516 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1517 aml_append(method, aml_return(aml_call1("IQST", reg)));
1518 aml_append(dev, method);
1519
1520 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1521 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1522 aml_append(dev, method);
1523
1524 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1525 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1526 aml_append(dev, method);
1527
1528 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1529 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1530 aml_append(method, aml_store(aml_name("PRRI"), reg));
1531 aml_append(dev, method);
1532
1533 return dev;
1534 }
1535
1536 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1537 {
1538 Aml *dev;
1539 Aml *crs;
1540 Aml *method;
1541 uint32_t irqs;
1542
1543 dev = aml_device("%s", name);
1544 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1545 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1546
1547 crs = aml_resource_template();
1548 irqs = gsi;
1549 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1550 AML_SHARED, &irqs, 1));
1551 aml_append(dev, aml_name_decl("_PRS", crs));
1552
1553 aml_append(dev, aml_name_decl("_CRS", crs));
1554
1555 /*
1556 * _DIS can be no-op because the interrupt cannot be disabled.
1557 */
1558 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1559 aml_append(dev, method);
1560
1561 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1562 aml_append(dev, method);
1563
1564 return dev;
1565 }
1566
1567 /* _CRS method - get current settings */
1568 static Aml *build_iqcr_method(bool is_piix4)
1569 {
1570 Aml *if_ctx;
1571 uint32_t irqs;
1572 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1573 Aml *crs = aml_resource_template();
1574
1575 irqs = 0;
1576 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1577 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1578 aml_append(method, aml_name_decl("PRR0", crs));
1579
1580 aml_append(method,
1581 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1582
1583 if (is_piix4) {
1584 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1585 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1586 aml_append(method, if_ctx);
1587 } else {
1588 aml_append(method,
1589 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1590 aml_name("PRRI")));
1591 }
1592
1593 aml_append(method, aml_return(aml_name("PRR0")));
1594 return method;
1595 }
1596
1597 /* _STA method - get status */
1598 static Aml *build_irq_status_method(void)
1599 {
1600 Aml *if_ctx;
1601 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1602
1603 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1604 aml_append(if_ctx, aml_return(aml_int(0x09)));
1605 aml_append(method, if_ctx);
1606 aml_append(method, aml_return(aml_int(0x0B)));
1607 return method;
1608 }
1609
1610 static void build_piix4_pci0_int(Aml *table)
1611 {
1612 Aml *dev;
1613 Aml *crs;
1614 Aml *field;
1615 Aml *method;
1616 uint32_t irqs;
1617 Aml *sb_scope = aml_scope("_SB");
1618 Aml *pci0_scope = aml_scope("PCI0");
1619
1620 aml_append(pci0_scope, build_prt(true));
1621 aml_append(sb_scope, pci0_scope);
1622
1623 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1624 aml_append(field, aml_named_field("PRQ0", 8));
1625 aml_append(field, aml_named_field("PRQ1", 8));
1626 aml_append(field, aml_named_field("PRQ2", 8));
1627 aml_append(field, aml_named_field("PRQ3", 8));
1628 aml_append(sb_scope, field);
1629
1630 aml_append(sb_scope, build_irq_status_method());
1631 aml_append(sb_scope, build_iqcr_method(true));
1632
1633 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1634 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1635 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1636 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1637
1638 dev = aml_device("LNKS");
1639 {
1640 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1641 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1642
1643 crs = aml_resource_template();
1644 irqs = 9;
1645 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1646 AML_ACTIVE_HIGH, AML_SHARED,
1647 &irqs, 1));
1648 aml_append(dev, aml_name_decl("_PRS", crs));
1649
1650 /* The SCI cannot be disabled and is always attached to GSI 9,
1651 * so these are no-ops. We only need this link to override the
1652 * polarity to active high and match the content of the MADT.
1653 */
1654 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1655 aml_append(method, aml_return(aml_int(0x0b)));
1656 aml_append(dev, method);
1657
1658 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1659 aml_append(dev, method);
1660
1661 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1662 aml_append(method, aml_return(aml_name("_PRS")));
1663 aml_append(dev, method);
1664
1665 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1666 aml_append(dev, method);
1667 }
1668 aml_append(sb_scope, dev);
1669
1670 aml_append(table, sb_scope);
1671 }
1672
1673 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1674 {
1675 int i;
1676 int head;
1677 Aml *pkg;
1678 char base = name[3] < 'E' ? 'A' : 'E';
1679 char *s = g_strdup(name);
1680 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1681
1682 assert(strlen(s) == 4);
1683
1684 head = name[3] - base;
1685 for (i = 0; i < 4; i++) {
1686 if (head + i > 3) {
1687 head = i * -1;
1688 }
1689 s[3] = base + head + i;
1690 pkg = aml_package(4);
1691 aml_append(pkg, a_nr);
1692 aml_append(pkg, aml_int(i));
1693 aml_append(pkg, aml_name("%s", s));
1694 aml_append(pkg, aml_int(0));
1695 aml_append(ctx, pkg);
1696 }
1697 g_free(s);
1698 }
1699
1700 static Aml *build_q35_routing_table(const char *str)
1701 {
1702 int i;
1703 Aml *pkg;
1704 char *name = g_strdup_printf("%s ", str);
1705
1706 pkg = aml_package(128);
1707 for (i = 0; i < 0x18; i++) {
1708 name[3] = 'E' + (i & 0x3);
1709 append_q35_prt_entry(pkg, i, name);
1710 }
1711
1712 name[3] = 'E';
1713 append_q35_prt_entry(pkg, 0x18, name);
1714
1715 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1716 for (i = 0x0019; i < 0x1e; i++) {
1717 name[3] = 'A';
1718 append_q35_prt_entry(pkg, i, name);
1719 }
1720
1721 /* PCIe->PCI bridge. use PIRQ[E-H] */
1722 name[3] = 'E';
1723 append_q35_prt_entry(pkg, 0x1e, name);
1724 name[3] = 'A';
1725 append_q35_prt_entry(pkg, 0x1f, name);
1726
1727 g_free(name);
1728 return pkg;
1729 }
1730
1731 static void build_q35_pci0_int(Aml *table)
1732 {
1733 Aml *field;
1734 Aml *method;
1735 Aml *sb_scope = aml_scope("_SB");
1736 Aml *pci0_scope = aml_scope("PCI0");
1737
1738 /* Zero => PIC mode, One => APIC Mode */
1739 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1740 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1741 {
1742 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1743 }
1744 aml_append(table, method);
1745
1746 aml_append(pci0_scope,
1747 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1748 aml_append(pci0_scope,
1749 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1750
1751 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1752 {
1753 Aml *if_ctx;
1754 Aml *else_ctx;
1755
1756 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1757 section 6.2.8.1 */
1758 /* Note: we provide the same info as the PCI routing
1759 table of the Bochs BIOS */
1760 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1761 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1762 aml_append(method, if_ctx);
1763 else_ctx = aml_else();
1764 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1765 aml_append(method, else_ctx);
1766 }
1767 aml_append(pci0_scope, method);
1768 aml_append(sb_scope, pci0_scope);
1769
1770 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1771 aml_append(field, aml_named_field("PRQA", 8));
1772 aml_append(field, aml_named_field("PRQB", 8));
1773 aml_append(field, aml_named_field("PRQC", 8));
1774 aml_append(field, aml_named_field("PRQD", 8));
1775 aml_append(field, aml_reserved_field(0x20));
1776 aml_append(field, aml_named_field("PRQE", 8));
1777 aml_append(field, aml_named_field("PRQF", 8));
1778 aml_append(field, aml_named_field("PRQG", 8));
1779 aml_append(field, aml_named_field("PRQH", 8));
1780 aml_append(sb_scope, field);
1781
1782 aml_append(sb_scope, build_irq_status_method());
1783 aml_append(sb_scope, build_iqcr_method(false));
1784
1785 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1786 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1787 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1788 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1789 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1790 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1791 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1792 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1793
1794 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1795 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1796 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1797 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1798 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1799 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1800 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1801 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1802
1803 aml_append(table, sb_scope);
1804 }
1805
1806 static void build_q35_isa_bridge(Aml *table)
1807 {
1808 Aml *dev;
1809 Aml *scope;
1810 Aml *field;
1811
1812 scope = aml_scope("_SB.PCI0");
1813 dev = aml_device("ISA");
1814 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1815
1816 /* ICH9 PCI to ISA irq remapping */
1817 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1818 aml_int(0x60), 0x0C));
1819
1820 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1821 aml_int(0x80), 0x02));
1822 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1823 aml_append(field, aml_named_field("COMA", 3));
1824 aml_append(field, aml_reserved_field(1));
1825 aml_append(field, aml_named_field("COMB", 3));
1826 aml_append(field, aml_reserved_field(1));
1827 aml_append(field, aml_named_field("LPTD", 2));
1828 aml_append(dev, field);
1829
1830 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1831 aml_int(0x82), 0x02));
1832 /* enable bits */
1833 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1834 aml_append(field, aml_named_field("CAEN", 1));
1835 aml_append(field, aml_named_field("CBEN", 1));
1836 aml_append(field, aml_named_field("LPEN", 1));
1837 aml_append(dev, field);
1838
1839 aml_append(scope, dev);
1840 aml_append(table, scope);
1841 }
1842
1843 static void build_piix4_pm(Aml *table)
1844 {
1845 Aml *dev;
1846 Aml *scope;
1847
1848 scope = aml_scope("_SB.PCI0");
1849 dev = aml_device("PX13");
1850 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1851
1852 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1853 aml_int(0x00), 0xff));
1854 aml_append(scope, dev);
1855 aml_append(table, scope);
1856 }
1857
1858 static void build_piix4_isa_bridge(Aml *table)
1859 {
1860 Aml *dev;
1861 Aml *scope;
1862 Aml *field;
1863
1864 scope = aml_scope("_SB.PCI0");
1865 dev = aml_device("ISA");
1866 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1867
1868 /* PIIX PCI to ISA irq remapping */
1869 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1870 aml_int(0x60), 0x04));
1871 /* enable bits */
1872 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1873 /* Offset(0x5f),, 7, */
1874 aml_append(field, aml_reserved_field(0x2f8));
1875 aml_append(field, aml_reserved_field(7));
1876 aml_append(field, aml_named_field("LPEN", 1));
1877 /* Offset(0x67),, 3, */
1878 aml_append(field, aml_reserved_field(0x38));
1879 aml_append(field, aml_reserved_field(3));
1880 aml_append(field, aml_named_field("CAEN", 1));
1881 aml_append(field, aml_reserved_field(3));
1882 aml_append(field, aml_named_field("CBEN", 1));
1883 aml_append(dev, field);
1884
1885 aml_append(scope, dev);
1886 aml_append(table, scope);
1887 }
1888
1889 static void build_piix4_pci_hotplug(Aml *table)
1890 {
1891 Aml *scope;
1892 Aml *field;
1893 Aml *method;
1894
1895 scope = aml_scope("_SB.PCI0");
1896
1897 aml_append(scope,
1898 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1899 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1900 aml_append(field, aml_named_field("PCIU", 32));
1901 aml_append(field, aml_named_field("PCID", 32));
1902 aml_append(scope, field);
1903
1904 aml_append(scope,
1905 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1906 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1907 aml_append(field, aml_named_field("B0EJ", 32));
1908 aml_append(scope, field);
1909
1910 aml_append(scope,
1911 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1912 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1913 aml_append(field, aml_named_field("BNUM", 32));
1914 aml_append(scope, field);
1915
1916 aml_append(scope, aml_mutex("BLCK", 0));
1917
1918 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1919 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1920 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1921 aml_append(method,
1922 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1923 aml_append(method, aml_release(aml_name("BLCK")));
1924 aml_append(method, aml_return(aml_int(0)));
1925 aml_append(scope, method);
1926
1927 aml_append(table, scope);
1928 }
1929
1930 static Aml *build_q35_osc_method(void)
1931 {
1932 Aml *if_ctx;
1933 Aml *if_ctx2;
1934 Aml *else_ctx;
1935 Aml *method;
1936 Aml *a_cwd1 = aml_name("CDW1");
1937 Aml *a_ctrl = aml_name("CTRL");
1938
1939 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1940 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1941
1942 if_ctx = aml_if(aml_equal(
1943 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1944 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1945 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1946
1947 aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1948 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1949
1950 /*
1951 * Always allow native PME, AER (no dependencies)
1952 * Never allow SHPC (no SHPC controller in this system)
1953 */
1954 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
1955
1956 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1957 /* Unknown revision */
1958 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1959 aml_append(if_ctx, if_ctx2);
1960
1961 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1962 /* Capabilities bits were masked */
1963 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1964 aml_append(if_ctx, if_ctx2);
1965
1966 /* Update DWORD3 in the buffer */
1967 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1968 aml_append(method, if_ctx);
1969
1970 else_ctx = aml_else();
1971 /* Unrecognized UUID */
1972 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1973 aml_append(method, else_ctx);
1974
1975 aml_append(method, aml_return(aml_arg(3)));
1976 return method;
1977 }
1978
1979 static void
1980 build_dsdt(GArray *table_data, BIOSLinker *linker,
1981 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1982 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1983 {
1984 CrsRangeEntry *entry;
1985 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1986 CrsRangeSet crs_range_set;
1987 PCMachineState *pcms = PC_MACHINE(machine);
1988 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1989 uint32_t nr_mem = machine->ram_slots;
1990 int root_bus_limit = 0xFF;
1991 PCIBus *bus = NULL;
1992 int i;
1993
1994 dsdt = init_aml_allocator();
1995
1996 /* Reserve space for header */
1997 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1998
1999 build_dbg_aml(dsdt);
2000 if (misc->is_piix4) {
2001 sb_scope = aml_scope("_SB");
2002 dev = aml_device("PCI0");
2003 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
2004 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
2005 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
2006 aml_append(sb_scope, dev);
2007 aml_append(dsdt, sb_scope);
2008
2009 build_hpet_aml(dsdt);
2010 build_piix4_pm(dsdt);
2011 build_piix4_isa_bridge(dsdt);
2012 build_isa_devices_aml(dsdt);
2013 build_piix4_pci_hotplug(dsdt);
2014 build_piix4_pci0_int(dsdt);
2015 } else {
2016 sb_scope = aml_scope("_SB");
2017 aml_append(sb_scope,
2018 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c));
2019 aml_append(sb_scope,
2020 aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01));
2021 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
2022 aml_append(field, aml_named_field("PCIB", 8));
2023 aml_append(sb_scope, field);
2024 aml_append(dsdt, sb_scope);
2025
2026 sb_scope = aml_scope("_SB");
2027 dev = aml_device("PCI0");
2028 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
2029 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
2030 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
2031 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
2032 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
2033 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
2034 aml_append(dev, build_q35_osc_method());
2035 aml_append(sb_scope, dev);
2036 aml_append(dsdt, sb_scope);
2037
2038 build_hpet_aml(dsdt);
2039 build_q35_isa_bridge(dsdt);
2040 build_isa_devices_aml(dsdt);
2041 build_q35_pci0_int(dsdt);
2042 }
2043
2044 if (pcmc->legacy_cpu_hotplug) {
2045 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
2046 } else {
2047 CPUHotplugFeatures opts = {
2048 .apci_1_compatible = true, .has_legacy_cphp = true
2049 };
2050 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
2051 "\\_SB.PCI0", "\\_GPE._E02");
2052 }
2053 build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base,
2054 pm->mem_hp_io_len);
2055
2056 scope = aml_scope("_GPE");
2057 {
2058 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
2059
2060 if (misc->is_piix4) {
2061 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
2062 aml_append(method,
2063 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
2064 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
2065 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
2066 aml_append(scope, method);
2067 }
2068
2069 method = aml_method("_E03", 0, AML_NOTSERIALIZED);
2070 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
2071 aml_append(scope, method);
2072 }
2073 aml_append(dsdt, scope);
2074
2075 crs_range_set_init(&crs_range_set);
2076 bus = PC_MACHINE(machine)->bus;
2077 if (bus) {
2078 QLIST_FOREACH(bus, &bus->child, sibling) {
2079 uint8_t bus_num = pci_bus_num(bus);
2080 uint8_t numa_node = pci_bus_numa_node(bus);
2081
2082 /* look only for expander root buses */
2083 if (!pci_bus_is_root(bus)) {
2084 continue;
2085 }
2086
2087 if (bus_num < root_bus_limit) {
2088 root_bus_limit = bus_num - 1;
2089 }
2090
2091 scope = aml_scope("\\_SB");
2092 dev = aml_device("PC%.02X", bus_num);
2093 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
2094 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
2095 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
2096
2097 if (numa_node != NUMA_NODE_UNASSIGNED) {
2098 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
2099 }
2100
2101 aml_append(dev, build_prt(false));
2102 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
2103 aml_append(dev, aml_name_decl("_CRS", crs));
2104 aml_append(scope, dev);
2105 aml_append(dsdt, scope);
2106 }
2107 }
2108
2109 scope = aml_scope("\\_SB.PCI0");
2110 /* build PCI0._CRS */
2111 crs = aml_resource_template();
2112 aml_append(crs,
2113 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
2114 0x0000, 0x0, root_bus_limit,
2115 0x0000, root_bus_limit + 1));
2116 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
2117
2118 aml_append(crs,
2119 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2120 AML_POS_DECODE, AML_ENTIRE_RANGE,
2121 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
2122
2123 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
2124 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
2125 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
2126 aml_append(crs,
2127 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2128 AML_POS_DECODE, AML_ENTIRE_RANGE,
2129 0x0000, entry->base, entry->limit,
2130 0x0000, entry->limit - entry->base + 1));
2131 }
2132
2133 aml_append(crs,
2134 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2135 AML_CACHEABLE, AML_READ_WRITE,
2136 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2137
2138 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
2139 range_lob(pci_hole),
2140 range_upb(pci_hole));
2141 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
2142 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
2143 aml_append(crs,
2144 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2145 AML_NON_CACHEABLE, AML_READ_WRITE,
2146 0, entry->base, entry->limit,
2147 0, entry->limit - entry->base + 1));
2148 }
2149
2150 if (!range_is_empty(pci_hole64)) {
2151 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
2152 range_lob(pci_hole64),
2153 range_upb(pci_hole64));
2154 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
2155 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
2156 aml_append(crs,
2157 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
2158 AML_MAX_FIXED,
2159 AML_CACHEABLE, AML_READ_WRITE,
2160 0, entry->base, entry->limit,
2161 0, entry->limit - entry->base + 1));
2162 }
2163 }
2164
2165 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2166 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2167 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2168 }
2169 aml_append(scope, aml_name_decl("_CRS", crs));
2170
2171 /* reserve GPE0 block resources */
2172 dev = aml_device("GPE0");
2173 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2174 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2175 /* device present, functioning, decoding, not shown in UI */
2176 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2177 crs = aml_resource_template();
2178 aml_append(crs,
2179 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
2180 );
2181 aml_append(dev, aml_name_decl("_CRS", crs));
2182 aml_append(scope, dev);
2183
2184 crs_range_set_free(&crs_range_set);
2185
2186 /* reserve PCIHP resources */
2187 if (pm->pcihp_io_len) {
2188 dev = aml_device("PHPR");
2189 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2190 aml_append(dev,
2191 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2192 /* device present, functioning, decoding, not shown in UI */
2193 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2194 crs = aml_resource_template();
2195 aml_append(crs,
2196 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2197 pm->pcihp_io_len)
2198 );
2199 aml_append(dev, aml_name_decl("_CRS", crs));
2200 aml_append(scope, dev);
2201 }
2202 aml_append(dsdt, scope);
2203
2204 /* create S3_ / S4_ / S5_ packages if necessary */
2205 scope = aml_scope("\\");
2206 if (!pm->s3_disabled) {
2207 pkg = aml_package(4);
2208 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2209 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2210 aml_append(pkg, aml_int(0)); /* reserved */
2211 aml_append(pkg, aml_int(0)); /* reserved */
2212 aml_append(scope, aml_name_decl("_S3", pkg));
2213 }
2214
2215 if (!pm->s4_disabled) {
2216 pkg = aml_package(4);
2217 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2218 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2219 aml_append(pkg, aml_int(pm->s4_val));
2220 aml_append(pkg, aml_int(0)); /* reserved */
2221 aml_append(pkg, aml_int(0)); /* reserved */
2222 aml_append(scope, aml_name_decl("_S4", pkg));
2223 }
2224
2225 pkg = aml_package(4);
2226 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2227 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2228 aml_append(pkg, aml_int(0)); /* reserved */
2229 aml_append(pkg, aml_int(0)); /* reserved */
2230 aml_append(scope, aml_name_decl("_S5", pkg));
2231 aml_append(dsdt, scope);
2232
2233 /* create fw_cfg node, unconditionally */
2234 {
2235 /* when using port i/o, the 8-bit data register *always* overlaps
2236 * with half of the 16-bit control register. Hence, the total size
2237 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2238 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2239 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2240 "dma_enabled", NULL) ?
2241 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2242 FW_CFG_CTL_SIZE;
2243
2244 scope = aml_scope("\\_SB.PCI0");
2245 dev = aml_device("FWCF");
2246
2247 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2248
2249 /* device present, functioning, decoding, not shown in UI */
2250 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2251
2252 crs = aml_resource_template();
2253 aml_append(crs,
2254 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2255 );
2256 aml_append(dev, aml_name_decl("_CRS", crs));
2257
2258 aml_append(scope, dev);
2259 aml_append(dsdt, scope);
2260 }
2261
2262 if (misc->applesmc_io_base) {
2263 scope = aml_scope("\\_SB.PCI0.ISA");
2264 dev = aml_device("SMC");
2265
2266 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2267 /* device present, functioning, decoding, not shown in UI */
2268 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2269
2270 crs = aml_resource_template();
2271 aml_append(crs,
2272 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2273 0x01, APPLESMC_MAX_DATA_LENGTH)
2274 );
2275 aml_append(crs, aml_irq_no_flags(6));
2276 aml_append(dev, aml_name_decl("_CRS", crs));
2277
2278 aml_append(scope, dev);
2279 aml_append(dsdt, scope);
2280 }
2281
2282 if (misc->pvpanic_port) {
2283 scope = aml_scope("\\_SB.PCI0.ISA");
2284
2285 dev = aml_device("PEVT");
2286 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2287
2288 crs = aml_resource_template();
2289 aml_append(crs,
2290 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2291 );
2292 aml_append(dev, aml_name_decl("_CRS", crs));
2293
2294 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2295 aml_int(misc->pvpanic_port), 1));
2296 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2297 aml_append(field, aml_named_field("PEPT", 8));
2298 aml_append(dev, field);
2299
2300 /* device present, functioning, decoding, shown in UI */
2301 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2302
2303 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2304 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2305 aml_append(method, aml_return(aml_local(0)));
2306 aml_append(dev, method);
2307
2308 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2309 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2310 aml_append(dev, method);
2311
2312 aml_append(scope, dev);
2313 aml_append(dsdt, scope);
2314 }
2315
2316 sb_scope = aml_scope("\\_SB");
2317 {
2318 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base,
2319 pm->mem_hp_io_len);
2320
2321 {
2322 Object *pci_host;
2323 PCIBus *bus = NULL;
2324
2325 pci_host = acpi_get_i386_pci_host();
2326 if (pci_host) {
2327 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2328 }
2329
2330 if (bus) {
2331 Aml *scope = aml_scope("PCI0");
2332 /* Scan all PCI buses. Generate tables to support hotplug. */
2333 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2334
2335 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2336 dev = aml_device("ISA.TPM");
2337 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2338 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2339 crs = aml_resource_template();
2340 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2341 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2342 /*
2343 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2344 Rewrite to take IRQ from TPM device model and
2345 fix default IRQ value there to use some unused IRQ
2346 */
2347 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2348 aml_append(dev, aml_name_decl("_CRS", crs));
2349 aml_append(scope, dev);
2350 }
2351
2352 aml_append(sb_scope, scope);
2353 }
2354 }
2355 aml_append(dsdt, sb_scope);
2356 }
2357
2358 /* copy AML table into ACPI tables blob and patch header there */
2359 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
2360 build_header(linker, table_data,
2361 (void *)(table_data->data + table_data->len - dsdt->buf->len),
2362 "DSDT", dsdt->buf->len, 1, NULL, NULL);
2363 free_aml_allocator();
2364 }
2365
2366 static void
2367 build_hpet(GArray *table_data, BIOSLinker *linker)
2368 {
2369 Acpi20Hpet *hpet;
2370
2371 hpet = acpi_data_push(table_data, sizeof(*hpet));
2372 /* Note timer_block_id value must be kept in sync with value advertised by
2373 * emulated hpet
2374 */
2375 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2376 hpet->addr.address = cpu_to_le64(HPET_BASE);
2377 build_header(linker, table_data,
2378 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
2379 }
2380
2381 static void
2382 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2383 {
2384 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2385 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
2386 unsigned log_addr_offset =
2387 (char *)&tcpa->log_area_start_address - table_data->data;
2388
2389 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2390 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2391 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
2392
2393 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
2394 false /* high memory */);
2395
2396 /* log area start address to be filled by Guest linker */
2397 bios_linker_loader_add_pointer(linker,
2398 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
2399 ACPI_BUILD_TPMLOG_FILE, 0);
2400
2401 build_header(linker, table_data,
2402 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
2403 }
2404
2405 static void
2406 build_tpm2(GArray *table_data, BIOSLinker *linker)
2407 {
2408 Acpi20TPM2 *tpm2_ptr;
2409
2410 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2411
2412 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2413 tpm2_ptr->control_area_address = cpu_to_le64(0);
2414 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2415
2416 build_header(linker, table_data,
2417 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
2418 }
2419
2420 static void
2421 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
2422 {
2423 AcpiSystemResourceAffinityTable *srat;
2424 AcpiSratMemoryAffinity *numamem;
2425
2426 int i;
2427 int srat_start, numa_start, slots;
2428 uint64_t mem_len, mem_base, next_base;
2429 MachineClass *mc = MACHINE_GET_CLASS(machine);
2430 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
2431 PCMachineState *pcms = PC_MACHINE(machine);
2432 ram_addr_t hotplugabble_address_space_size =
2433 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
2434 NULL);
2435
2436 srat_start = table_data->len;
2437
2438 srat = acpi_data_push(table_data, sizeof *srat);
2439 srat->reserved1 = cpu_to_le32(1);
2440
2441 for (i = 0; i < apic_ids->len; i++) {
2442 int j = numa_get_node_for_cpu(i);
2443 uint32_t apic_id = apic_ids->cpus[i].arch_id;
2444
2445 if (apic_id < 255) {
2446 AcpiSratProcessorAffinity *core;
2447
2448 core = acpi_data_push(table_data, sizeof *core);
2449 core->type = ACPI_SRAT_PROCESSOR_APIC;
2450 core->length = sizeof(*core);
2451 core->local_apic_id = apic_id;
2452 if (j < nb_numa_nodes) {
2453 core->proximity_lo = j;
2454 }
2455 memset(core->proximity_hi, 0, 3);
2456 core->local_sapic_eid = 0;
2457 core->flags = cpu_to_le32(1);
2458 } else {
2459 AcpiSratProcessorX2ApicAffinity *core;
2460
2461 core = acpi_data_push(table_data, sizeof *core);
2462 core->type = ACPI_SRAT_PROCESSOR_x2APIC;
2463 core->length = sizeof(*core);
2464 core->x2apic_id = cpu_to_le32(apic_id);
2465 if (j < nb_numa_nodes) {
2466 core->proximity_domain = cpu_to_le32(j);
2467 }
2468 core->flags = cpu_to_le32(1);
2469 }
2470 }
2471
2472
2473 /* the memory map is a bit tricky, it contains at least one hole
2474 * from 640k-1M and possibly another one from 3.5G-4G.
2475 */
2476 next_base = 0;
2477 numa_start = table_data->len;
2478
2479 numamem = acpi_data_push(table_data, sizeof *numamem);
2480 build_srat_memory(numamem, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED);
2481 next_base = 1024 * 1024;
2482 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2483 mem_base = next_base;
2484 mem_len = pcms->node_mem[i - 1];
2485 if (i == 1) {
2486 mem_len -= 1024 * 1024;
2487 }
2488 next_base = mem_base + mem_len;
2489
2490 /* Cut out the ACPI_PCI hole */
2491 if (mem_base <= pcms->below_4g_mem_size &&
2492 next_base > pcms->below_4g_mem_size) {
2493 mem_len -= next_base - pcms->below_4g_mem_size;
2494 if (mem_len > 0) {
2495 numamem = acpi_data_push(table_data, sizeof *numamem);
2496 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2497 MEM_AFFINITY_ENABLED);
2498 }
2499 mem_base = 1ULL << 32;
2500 mem_len = next_base - pcms->below_4g_mem_size;
2501 next_base += (1ULL << 32) - pcms->below_4g_mem_size;
2502 }
2503 numamem = acpi_data_push(table_data, sizeof *numamem);
2504 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2505 MEM_AFFINITY_ENABLED);
2506 }
2507 slots = (table_data->len - numa_start) / sizeof *numamem;
2508 for (; slots < pcms->numa_nodes + 2; slots++) {
2509 numamem = acpi_data_push(table_data, sizeof *numamem);
2510 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2511 }
2512
2513 /*
2514 * Entry is required for Windows to enable memory hotplug in OS.
2515 * Memory devices may override proximity set by this entry,
2516 * providing _PXM method if necessary.
2517 */
2518 if (hotplugabble_address_space_size) {
2519 numamem = acpi_data_push(table_data, sizeof *numamem);
2520 build_srat_memory(numamem, pcms->hotplug_memory.base,
2521 hotplugabble_address_space_size, 0,
2522 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2523 }
2524
2525 build_header(linker, table_data,
2526 (void *)(table_data->data + srat_start),
2527 "SRAT",
2528 table_data->len - srat_start, 1, NULL, NULL);
2529 g_free(apic_ids);
2530 }
2531
2532 static void
2533 build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info)
2534 {
2535 AcpiTableMcfg *mcfg;
2536 const char *sig;
2537 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2538
2539 mcfg = acpi_data_push(table_data, len);
2540 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2541 /* Only a single allocation so no need to play with segments */
2542 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2543 mcfg->allocation[0].start_bus_number = 0;
2544 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2545
2546 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2547 * To avoid table size changes (which create migration issues),
2548 * always create the table even if there are no allocations,
2549 * but set the signature to a reserved value in this case.
2550 * ACPI spec requires OSPMs to ignore such tables.
2551 */
2552 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
2553 /* Reserved signature: ignored by OSPM */
2554 sig = "QEMU";
2555 } else {
2556 sig = "MCFG";
2557 }
2558 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
2559 }
2560
2561 /*
2562 * VT-d spec 8.1 DMA Remapping Reporting Structure
2563 * (version Oct. 2014 or later)
2564 */
2565 static void
2566 build_dmar_q35(GArray *table_data, BIOSLinker *linker)
2567 {
2568 int dmar_start = table_data->len;
2569
2570 AcpiTableDmar *dmar;
2571 AcpiDmarHardwareUnit *drhd;
2572 uint8_t dmar_flags = 0;
2573 X86IOMMUState *iommu = x86_iommu_get_default();
2574 AcpiDmarDeviceScope *scope = NULL;
2575 /* Root complex IOAPIC use one path[0] only */
2576 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
2577
2578 assert(iommu);
2579 if (iommu->intr_supported) {
2580 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2581 }
2582
2583 dmar = acpi_data_push(table_data, sizeof(*dmar));
2584 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
2585 dmar->flags = dmar_flags;
2586
2587 /* DMAR Remapping Hardware Unit Definition structure */
2588 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
2589 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2590 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
2591 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2592 drhd->pci_segment = cpu_to_le16(0);
2593 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2594
2595 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2596 * 8.3.1 (version Oct. 2014 or later). */
2597 scope = &drhd->scope[0];
2598 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
2599 scope->length = ioapic_scope_size;
2600 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2601 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
2602 scope->path[0] = cpu_to_le16(Q35_PSEUDO_DEVFN_IOAPIC);
2603
2604 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2605 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2606 }
2607 /*
2608 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2609 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2610 */
2611 static void
2612 build_amd_iommu(GArray *table_data, BIOSLinker *linker)
2613 {
2614 int iommu_start = table_data->len;
2615 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2616
2617 /* IVRS header */
2618 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2619 /* IVinfo - IO virtualization information common to all
2620 * IOMMU units in a system
2621 */
2622 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2623 /* reserved */
2624 build_append_int_noprefix(table_data, 0, 8);
2625
2626 /* IVHD definition - type 10h */
2627 build_append_int_noprefix(table_data, 0x10, 1);
2628 /* virtualization flags */
2629 build_append_int_noprefix(table_data,
2630 (1UL << 0) | /* HtTunEn */
2631 (1UL << 4) | /* iotblSup */
2632 (1UL << 6) | /* PrefSup */
2633 (1UL << 7), /* PPRSup */
2634 1);
2635 /* IVHD length */
2636 build_append_int_noprefix(table_data, 0x24, 2);
2637 /* DeviceID */
2638 build_append_int_noprefix(table_data, s->devid, 2);
2639 /* Capability offset */
2640 build_append_int_noprefix(table_data, s->capab_offset, 2);
2641 /* IOMMU base address */
2642 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2643 /* PCI Segment Group */
2644 build_append_int_noprefix(table_data, 0, 2);
2645 /* IOMMU info */
2646 build_append_int_noprefix(table_data, 0, 2);
2647 /* IOMMU Feature Reporting */
2648 build_append_int_noprefix(table_data,
2649 (48UL << 30) | /* HATS */
2650 (48UL << 28) | /* GATS */
2651 (1UL << 2), /* GTSup */
2652 4);
2653 /*
2654 * Type 1 device entry reporting all devices
2655 * These are 4-byte device entries currently reporting the range of
2656 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2657 */
2658 build_append_int_noprefix(table_data, 0x0000001, 4);
2659
2660 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2661 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2662 }
2663
2664 static GArray *
2665 build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset)
2666 {
2667 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2668 unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address);
2669 unsigned rsdt_pa_offset =
2670 (char *)&rsdp->rsdt_physical_address - rsdp_table->data;
2671
2672 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16,
2673 true /* fseg memory */);
2674
2675 memcpy(&rsdp->signature, "RSD PTR ", 8);
2676 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
2677 /* Address to be filled by Guest linker */
2678 bios_linker_loader_add_pointer(linker,
2679 ACPI_BUILD_RSDP_FILE, rsdt_pa_offset, rsdt_pa_size,
2680 ACPI_BUILD_TABLE_FILE, rsdt_tbl_offset);
2681
2682 /* Checksum to be filled by Guest linker */
2683 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
2684 (char *)rsdp - rsdp_table->data, sizeof *rsdp,
2685 (char *)&rsdp->checksum - rsdp_table->data);
2686
2687 return rsdp_table;
2688 }
2689
2690 typedef
2691 struct AcpiBuildState {
2692 /* Copy of table in RAM (for patching). */
2693 MemoryRegion *table_mr;
2694 /* Is table patched? */
2695 uint8_t patched;
2696 void *rsdp;
2697 MemoryRegion *rsdp_mr;
2698 MemoryRegion *linker_mr;
2699 } AcpiBuildState;
2700
2701 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2702 {
2703 Object *pci_host;
2704 QObject *o;
2705
2706 pci_host = acpi_get_i386_pci_host();
2707 g_assert(pci_host);
2708
2709 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2710 if (!o) {
2711 return false;
2712 }
2713 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
2714 qobject_decref(o);
2715
2716 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2717 assert(o);
2718 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
2719 qobject_decref(o);
2720 return true;
2721 }
2722
2723 static
2724 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2725 {
2726 PCMachineState *pcms = PC_MACHINE(machine);
2727 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2728 GArray *table_offsets;
2729 unsigned facs, dsdt, rsdt, fadt;
2730 AcpiPmInfo pm;
2731 AcpiMiscInfo misc;
2732 AcpiMcfgInfo mcfg;
2733 Range pci_hole, pci_hole64;
2734 uint8_t *u;
2735 size_t aml_len = 0;
2736 GArray *tables_blob = tables->table_data;
2737 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2738
2739 acpi_get_pm_info(&pm);
2740 acpi_get_misc_info(&misc);
2741 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2742 acpi_get_slic_oem(&slic_oem);
2743
2744 table_offsets = g_array_new(false, true /* clear */,
2745 sizeof(uint32_t));
2746 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2747
2748 bios_linker_loader_alloc(tables->linker,
2749 ACPI_BUILD_TABLE_FILE, tables_blob,
2750 64 /* Ensure FACS is aligned */,
2751 false /* high memory */);
2752
2753 /*
2754 * FACS is pointed to by FADT.
2755 * We place it first since it's the only table that has alignment
2756 * requirements.
2757 */
2758 facs = tables_blob->len;
2759 build_facs(tables_blob, tables->linker);
2760
2761 /* DSDT is pointed to by FADT */
2762 dsdt = tables_blob->len;
2763 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2764 &pci_hole, &pci_hole64, machine);
2765
2766 /* Count the size of the DSDT and SSDT, we will need it for legacy
2767 * sizing of ACPI tables.
2768 */
2769 aml_len += tables_blob->len - dsdt;
2770
2771 /* ACPI tables pointed to by RSDT */
2772 fadt = tables_blob->len;
2773 acpi_add_table(table_offsets, tables_blob);
2774 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt,
2775 slic_oem.id, slic_oem.table_id);
2776 aml_len += tables_blob->len - fadt;
2777
2778 acpi_add_table(table_offsets, tables_blob);
2779 build_madt(tables_blob, tables->linker, pcms);
2780
2781 if (misc.has_hpet) {
2782 acpi_add_table(table_offsets, tables_blob);
2783 build_hpet(tables_blob, tables->linker);
2784 }
2785 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2786 acpi_add_table(table_offsets, tables_blob);
2787 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2788
2789 if (misc.tpm_version == TPM_VERSION_2_0) {
2790 acpi_add_table(table_offsets, tables_blob);
2791 build_tpm2(tables_blob, tables->linker);
2792 }
2793 }
2794 if (pcms->numa_nodes) {
2795 acpi_add_table(table_offsets, tables_blob);
2796 build_srat(tables_blob, tables->linker, machine);
2797 }
2798 if (acpi_get_mcfg(&mcfg)) {
2799 acpi_add_table(table_offsets, tables_blob);
2800 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2801 }
2802 if (x86_iommu_get_default()) {
2803 IommuType IOMMUType = x86_iommu_get_type();
2804 if (IOMMUType == TYPE_AMD) {
2805 acpi_add_table(table_offsets, tables_blob);
2806 build_amd_iommu(tables_blob, tables->linker);
2807 } else if (IOMMUType == TYPE_INTEL) {
2808 acpi_add_table(table_offsets, tables_blob);
2809 build_dmar_q35(tables_blob, tables->linker);
2810 }
2811 }
2812 if (pcms->acpi_nvdimm_state.is_enabled) {
2813 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2814 pcms->acpi_nvdimm_state.dsm_mem);
2815 }
2816
2817 /* Add tables supplied by user (if any) */
2818 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2819 unsigned len = acpi_table_len(u);
2820
2821 acpi_add_table(table_offsets, tables_blob);
2822 g_array_append_vals(tables_blob, u, len);
2823 }
2824
2825 /* RSDT is pointed to by RSDP */
2826 rsdt = tables_blob->len;
2827 build_rsdt(tables_blob, tables->linker, table_offsets,
2828 slic_oem.id, slic_oem.table_id);
2829
2830 /* RSDP is in FSEG memory, so allocate it separately */
2831 build_rsdp(tables->rsdp, tables->linker, rsdt);
2832
2833 /* We'll expose it all to Guest so we want to reduce
2834 * chance of size changes.
2835 *
2836 * We used to align the tables to 4k, but of course this would
2837 * too simple to be enough. 4k turned out to be too small an
2838 * alignment very soon, and in fact it is almost impossible to
2839 * keep the table size stable for all (max_cpus, max_memory_slots)
2840 * combinations. So the table size is always 64k for pc-i440fx-2.1
2841 * and we give an error if the table grows beyond that limit.
2842 *
2843 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2844 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2845 * than 2.0 and we can always pad the smaller tables with zeros. We can
2846 * then use the exact size of the 2.0 tables.
2847 *
2848 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2849 */
2850 if (pcmc->legacy_acpi_table_size) {
2851 /* Subtracting aml_len gives the size of fixed tables. Then add the
2852 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2853 */
2854 int legacy_aml_len =
2855 pcmc->legacy_acpi_table_size +
2856 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
2857 int legacy_table_size =
2858 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2859 ACPI_BUILD_ALIGN_SIZE);
2860 if (tables_blob->len > legacy_table_size) {
2861 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2862 error_report("Warning: migration may not work.");
2863 }
2864 g_array_set_size(tables_blob, legacy_table_size);
2865 } else {
2866 /* Make sure we have a buffer in case we need to resize the tables. */
2867 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2868 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2869 error_report("Warning: ACPI tables are larger than 64k.");
2870 error_report("Warning: migration may not work.");
2871 error_report("Warning: please remove CPUs, NUMA nodes, "
2872 "memory slots or PCI bridges.");
2873 }
2874 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2875 }
2876
2877 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2878
2879 /* Cleanup memory that's no longer used. */
2880 g_array_free(table_offsets, true);
2881 }
2882
2883 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2884 {
2885 uint32_t size = acpi_data_len(data);
2886
2887 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2888 memory_region_ram_resize(mr, size, &error_abort);
2889
2890 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2891 memory_region_set_dirty(mr, 0, size);
2892 }
2893
2894 static void acpi_build_update(void *build_opaque)
2895 {
2896 AcpiBuildState *build_state = build_opaque;
2897 AcpiBuildTables tables;
2898
2899 /* No state to update or already patched? Nothing to do. */
2900 if (!build_state || build_state->patched) {
2901 return;
2902 }
2903 build_state->patched = 1;
2904
2905 acpi_build_tables_init(&tables);
2906
2907 acpi_build(&tables, MACHINE(qdev_get_machine()));
2908
2909 acpi_ram_update(build_state->table_mr, tables.table_data);
2910
2911 if (build_state->rsdp) {
2912 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2913 } else {
2914 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2915 }
2916
2917 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2918 acpi_build_tables_cleanup(&tables, true);
2919 }
2920
2921 static void acpi_build_reset(void *build_opaque)
2922 {
2923 AcpiBuildState *build_state = build_opaque;
2924 build_state->patched = 0;
2925 }
2926
2927 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2928 GArray *blob, const char *name,
2929 uint64_t max_size)
2930 {
2931 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2932 name, acpi_build_update, build_state);
2933 }
2934
2935 static const VMStateDescription vmstate_acpi_build = {
2936 .name = "acpi_build",
2937 .version_id = 1,
2938 .minimum_version_id = 1,
2939 .fields = (VMStateField[]) {
2940 VMSTATE_UINT8(patched, AcpiBuildState),
2941 VMSTATE_END_OF_LIST()
2942 },
2943 };
2944
2945 void acpi_setup(void)
2946 {
2947 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2948 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2949 AcpiBuildTables tables;
2950 AcpiBuildState *build_state;
2951
2952 if (!pcms->fw_cfg) {
2953 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2954 return;
2955 }
2956
2957 if (!pcmc->has_acpi_build) {
2958 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2959 return;
2960 }
2961
2962 if (!acpi_enabled) {
2963 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2964 return;
2965 }
2966
2967 build_state = g_malloc0(sizeof *build_state);
2968
2969 acpi_set_pci_info();
2970
2971 acpi_build_tables_init(&tables);
2972 acpi_build(&tables, MACHINE(pcms));
2973
2974 /* Now expose it all to Guest */
2975 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
2976 ACPI_BUILD_TABLE_FILE,
2977 ACPI_BUILD_TABLE_MAX_SIZE);
2978 assert(build_state->table_mr != NULL);
2979
2980 build_state->linker_mr =
2981 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
2982 "etc/table-loader", 0);
2983
2984 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2985 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2986
2987 if (!pcmc->rsdp_in_ram) {
2988 /*
2989 * Keep for compatibility with old machine types.
2990 * Though RSDP is small, its contents isn't immutable, so
2991 * we'll update it along with the rest of tables on guest access.
2992 */
2993 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2994
2995 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2996 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2997 acpi_build_update, build_state,
2998 build_state->rsdp, rsdp_size);
2999 build_state->rsdp_mr = NULL;
3000 } else {
3001 build_state->rsdp = NULL;
3002 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
3003 ACPI_BUILD_RSDP_FILE, 0);
3004 }
3005
3006 qemu_register_reset(acpi_build_reset, build_state);
3007 acpi_build_reset(build_state);
3008 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
3009
3010 /* Cleanup tables but don't free the memory: we track it
3011 * in build_state.
3012 */
3013 acpi_build_tables_cleanup(&tables, false);
3014 }
QEMU mirror