1 /* Support for generating ACPI tables and passing them to Guests
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
7 * Author: Michael S. Tsirkin <mst@redhat.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "acpi-build.h"
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
31 #include "hw/i386/pc.h"
32 #include "target-i386/cpu.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/acpi/cpu.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "sysemu/tpm_backend.h"
46 #include "hw/timer/mc146818rtc_regs.h"
47 #include "sysemu/numa.h"
49 /* Supported chipsets: */
50 #include "hw/acpi/piix4.h"
51 #include "hw/acpi/pcihp.h"
52 #include "hw/i386/ich9.h"
53 #include "hw/pci/pci_bus.h"
54 #include "hw/pci-host/q35.h"
55 #include "hw/i386/x86-iommu.h"
56 #include "hw/timer/hpet.h"
58 #include "hw/acpi/aml-build.h"
60 #include "qapi/qmp/qint.h"
61 #include "qom/qom-qobject.h"
62 #include "hw/i386/amd_iommu.h"
63 #include "hw/i386/intel_iommu.h"
65 #include "hw/acpi/ipmi.h"
67 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
68 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
69 * a little bit, there should be plenty of free space since the DSDT
70 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
72 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
73 #define ACPI_BUILD_ALIGN_SIZE 0x1000
75 #define ACPI_BUILD_TABLE_SIZE 0x20000
77 /* #define DEBUG_ACPI_BUILD */
78 #ifdef DEBUG_ACPI_BUILD
79 #define ACPI_BUILD_DPRINTF(fmt, ...) \
80 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
82 #define ACPI_BUILD_DPRINTF(fmt, ...)
85 /* Default IOAPIC ID */
86 #define ACPI_BUILD_IOAPIC_ID 0x0
88 typedef struct AcpiMcfgInfo
{
93 typedef struct AcpiPmInfo
{
99 uint8_t acpi_enable_cmd
;
100 uint8_t acpi_disable_cmd
;
102 uint32_t gpe0_blk_len
;
104 uint16_t cpu_hp_io_base
;
105 uint16_t mem_hp_io_base
;
106 uint16_t mem_hp_io_len
;
107 uint16_t pcihp_io_base
;
108 uint16_t pcihp_io_len
;
111 typedef struct AcpiMiscInfo
{
114 TPMVersion tpm_version
;
115 const unsigned char *dsdt_code
;
117 uint16_t pvpanic_port
;
118 uint16_t applesmc_io_base
;
121 typedef struct AcpiBuildPciBusHotplugState
{
122 GArray
*device_table
;
123 GArray
*notify_table
;
124 struct AcpiBuildPciBusHotplugState
*parent
;
125 bool pcihp_bridge_en
;
126 } AcpiBuildPciBusHotplugState
;
128 static void acpi_get_pm_info(AcpiPmInfo
*pm
)
130 Object
*piix
= piix4_pm_find();
131 Object
*lpc
= ich9_lpc_find();
135 pm
->cpu_hp_io_base
= 0;
136 pm
->pcihp_io_base
= 0;
137 pm
->pcihp_io_len
= 0;
140 pm
->cpu_hp_io_base
= PIIX4_CPU_HOTPLUG_IO_BASE
;
142 object_property_get_int(obj
, ACPI_PCIHP_IO_BASE_PROP
, NULL
);
144 object_property_get_int(obj
, ACPI_PCIHP_IO_LEN_PROP
, NULL
);
148 pm
->cpu_hp_io_base
= ICH9_CPU_HOTPLUG_IO_BASE
;
152 pm
->mem_hp_io_base
= ACPI_MEMORY_HOTPLUG_BASE
;
153 pm
->mem_hp_io_len
= ACPI_MEMORY_HOTPLUG_IO_LEN
;
155 /* Fill in optional s3/s4 related properties */
156 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S3_DISABLED
, NULL
);
158 pm
->s3_disabled
= qint_get_int(qobject_to_qint(o
));
160 pm
->s3_disabled
= false;
163 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_DISABLED
, NULL
);
165 pm
->s4_disabled
= qint_get_int(qobject_to_qint(o
));
167 pm
->s4_disabled
= false;
170 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_VAL
, NULL
);
172 pm
->s4_val
= qint_get_int(qobject_to_qint(o
));
178 /* Fill in mandatory properties */
179 pm
->sci_int
= object_property_get_int(obj
, ACPI_PM_PROP_SCI_INT
, NULL
);
181 pm
->acpi_enable_cmd
= object_property_get_int(obj
,
182 ACPI_PM_PROP_ACPI_ENABLE_CMD
,
184 pm
->acpi_disable_cmd
= object_property_get_int(obj
,
185 ACPI_PM_PROP_ACPI_DISABLE_CMD
,
187 pm
->io_base
= object_property_get_int(obj
, ACPI_PM_PROP_PM_IO_BASE
,
189 pm
->gpe0_blk
= object_property_get_int(obj
, ACPI_PM_PROP_GPE0_BLK
,
191 pm
->gpe0_blk_len
= object_property_get_int(obj
, ACPI_PM_PROP_GPE0_BLK_LEN
,
193 pm
->pcihp_bridge_en
=
194 object_property_get_bool(obj
, "acpi-pci-hotplug-with-bridge-support",
198 static void acpi_get_misc_info(AcpiMiscInfo
*info
)
200 Object
*piix
= piix4_pm_find();
201 Object
*lpc
= ich9_lpc_find();
202 assert(!!piix
!= !!lpc
);
205 info
->is_piix4
= true;
208 info
->is_piix4
= false;
211 info
->has_hpet
= hpet_find();
212 info
->tpm_version
= tpm_get_version();
213 info
->pvpanic_port
= pvpanic_port();
214 info
->applesmc_io_base
= applesmc_port();
218 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
219 * On i386 arch we only have two pci hosts, so we can look only for them.
221 static Object
*acpi_get_i386_pci_host(void)
225 host
= OBJECT_CHECK(PCIHostState
,
226 object_resolve_path("/machine/i440fx", NULL
),
227 TYPE_PCI_HOST_BRIDGE
);
229 host
= OBJECT_CHECK(PCIHostState
,
230 object_resolve_path("/machine/q35", NULL
),
231 TYPE_PCI_HOST_BRIDGE
);
237 static void acpi_get_pci_holes(Range
*hole
, Range
*hole64
)
241 pci_host
= acpi_get_i386_pci_host();
244 range_set_bounds1(hole
,
245 object_property_get_int(pci_host
,
246 PCI_HOST_PROP_PCI_HOLE_START
,
248 object_property_get_int(pci_host
,
249 PCI_HOST_PROP_PCI_HOLE_END
,
251 range_set_bounds1(hole64
,
252 object_property_get_int(pci_host
,
253 PCI_HOST_PROP_PCI_HOLE64_START
,
255 object_property_get_int(pci_host
,
256 PCI_HOST_PROP_PCI_HOLE64_END
,
260 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
262 static void acpi_align_size(GArray
*blob
, unsigned align
)
264 /* Align size to multiple of given size. This reduces the chance
265 * we need to change size in the future (breaking cross version migration).
267 g_array_set_size(blob
, ROUND_UP(acpi_data_len(blob
), align
));
272 build_facs(GArray
*table_data
, BIOSLinker
*linker
)
274 AcpiFacsDescriptorRev1
*facs
= acpi_data_push(table_data
, sizeof *facs
);
275 memcpy(&facs
->signature
, "FACS", 4);
276 facs
->length
= cpu_to_le32(sizeof(*facs
));
279 /* Load chipset information in FADT */
280 static void fadt_setup(AcpiFadtDescriptorRev1
*fadt
, AcpiPmInfo
*pm
)
284 fadt
->sci_int
= cpu_to_le16(pm
->sci_int
);
285 fadt
->smi_cmd
= cpu_to_le32(ACPI_PORT_SMI_CMD
);
286 fadt
->acpi_enable
= pm
->acpi_enable_cmd
;
287 fadt
->acpi_disable
= pm
->acpi_disable_cmd
;
288 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
289 fadt
->pm1a_evt_blk
= cpu_to_le32(pm
->io_base
);
290 fadt
->pm1a_cnt_blk
= cpu_to_le32(pm
->io_base
+ 0x04);
291 fadt
->pm_tmr_blk
= cpu_to_le32(pm
->io_base
+ 0x08);
292 fadt
->gpe0_blk
= cpu_to_le32(pm
->gpe0_blk
);
293 /* EVT, CNT, TMR length matches hw/acpi/core.c */
294 fadt
->pm1_evt_len
= 4;
295 fadt
->pm1_cnt_len
= 2;
296 fadt
->pm_tmr_len
= 4;
297 fadt
->gpe0_blk_len
= pm
->gpe0_blk_len
;
298 fadt
->plvl2_lat
= cpu_to_le16(0xfff); /* C2 state not supported */
299 fadt
->plvl3_lat
= cpu_to_le16(0xfff); /* C3 state not supported */
300 fadt
->flags
= cpu_to_le32((1 << ACPI_FADT_F_WBINVD
) |
301 (1 << ACPI_FADT_F_PROC_C1
) |
302 (1 << ACPI_FADT_F_SLP_BUTTON
) |
303 (1 << ACPI_FADT_F_RTC_S4
));
304 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK
);
305 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
306 * For more than 8 CPUs, "Clustered Logical" mode has to be used
309 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL
);
311 fadt
->century
= RTC_CENTURY
;
317 build_fadt(GArray
*table_data
, BIOSLinker
*linker
, AcpiPmInfo
*pm
,
318 unsigned facs_tbl_offset
, unsigned dsdt_tbl_offset
,
319 const char *oem_id
, const char *oem_table_id
)
321 AcpiFadtDescriptorRev1
*fadt
= acpi_data_push(table_data
, sizeof(*fadt
));
322 unsigned fw_ctrl_offset
= (char *)&fadt
->firmware_ctrl
- table_data
->data
;
323 unsigned dsdt_entry_offset
= (char *)&fadt
->dsdt
- table_data
->data
;
325 /* FACS address to be filled by Guest linker */
326 bios_linker_loader_add_pointer(linker
,
327 ACPI_BUILD_TABLE_FILE
, fw_ctrl_offset
, sizeof(fadt
->firmware_ctrl
),
328 ACPI_BUILD_TABLE_FILE
, facs_tbl_offset
);
330 /* DSDT address to be filled by Guest linker */
331 fadt_setup(fadt
, pm
);
332 bios_linker_loader_add_pointer(linker
,
333 ACPI_BUILD_TABLE_FILE
, dsdt_entry_offset
, sizeof(fadt
->dsdt
),
334 ACPI_BUILD_TABLE_FILE
, dsdt_tbl_offset
);
336 build_header(linker
, table_data
,
337 (void *)fadt
, "FACP", sizeof(*fadt
), 1, oem_id
, oem_table_id
);
340 void pc_madt_cpu_entry(AcpiDeviceIf
*adev
, int uid
,
341 CPUArchIdList
*apic_ids
, GArray
*entry
)
344 AcpiMadtProcessorApic
*apic
= acpi_data_push(entry
, sizeof *apic
);
346 apic_id
= apic_ids
->cpus
[uid
].arch_id
;
347 apic
->type
= ACPI_APIC_PROCESSOR
;
348 apic
->length
= sizeof(*apic
);
349 apic
->processor_id
= uid
;
350 apic
->local_apic_id
= apic_id
;
351 if (apic_ids
->cpus
[uid
].cpu
!= NULL
) {
352 apic
->flags
= cpu_to_le32(1);
354 /* ACPI spec says that LAPIC entry for non present
355 * CPU may be omitted from MADT or it must be marked
356 * as disabled. However omitting non present CPU from
357 * MADT breaks hotplug on linux. So possible CPUs
358 * should be put in MADT but kept disabled.
360 apic
->flags
= cpu_to_le32(0);
365 build_madt(GArray
*table_data
, BIOSLinker
*linker
, PCMachineState
*pcms
)
367 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
368 CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(MACHINE(pcms
));
369 int madt_start
= table_data
->len
;
370 AcpiDeviceIfClass
*adevc
= ACPI_DEVICE_IF_GET_CLASS(pcms
->acpi_dev
);
371 AcpiDeviceIf
*adev
= ACPI_DEVICE_IF(pcms
->acpi_dev
);
373 AcpiMultipleApicTable
*madt
;
374 AcpiMadtIoApic
*io_apic
;
375 AcpiMadtIntsrcovr
*intsrcovr
;
376 AcpiMadtLocalNmi
*local_nmi
;
379 madt
= acpi_data_push(table_data
, sizeof *madt
);
380 madt
->local_apic_address
= cpu_to_le32(APIC_DEFAULT_ADDRESS
);
381 madt
->flags
= cpu_to_le32(1);
383 for (i
= 0; i
< apic_ids
->len
; i
++) {
384 adevc
->madt_cpu(adev
, i
, apic_ids
, table_data
);
388 io_apic
= acpi_data_push(table_data
, sizeof *io_apic
);
389 io_apic
->type
= ACPI_APIC_IO
;
390 io_apic
->length
= sizeof(*io_apic
);
391 io_apic
->io_apic_id
= ACPI_BUILD_IOAPIC_ID
;
392 io_apic
->address
= cpu_to_le32(IO_APIC_DEFAULT_ADDRESS
);
393 io_apic
->interrupt
= cpu_to_le32(0);
395 if (pcms
->apic_xrupt_override
) {
396 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
397 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
398 intsrcovr
->length
= sizeof(*intsrcovr
);
399 intsrcovr
->source
= 0;
400 intsrcovr
->gsi
= cpu_to_le32(2);
401 intsrcovr
->flags
= cpu_to_le16(0); /* conforms to bus specifications */
403 for (i
= 1; i
< 16; i
++) {
404 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
405 if (!(ACPI_BUILD_PCI_IRQS
& (1 << i
))) {
406 /* No need for a INT source override structure. */
409 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
410 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
411 intsrcovr
->length
= sizeof(*intsrcovr
);
412 intsrcovr
->source
= i
;
413 intsrcovr
->gsi
= cpu_to_le32(i
);
414 intsrcovr
->flags
= cpu_to_le16(0xd); /* active high, level triggered */
417 local_nmi
= acpi_data_push(table_data
, sizeof *local_nmi
);
418 local_nmi
->type
= ACPI_APIC_LOCAL_NMI
;
419 local_nmi
->length
= sizeof(*local_nmi
);
420 local_nmi
->processor_id
= 0xff; /* all processors */
421 local_nmi
->flags
= cpu_to_le16(0);
422 local_nmi
->lint
= 1; /* ACPI_LINT1 */
424 build_header(linker
, table_data
,
425 (void *)(table_data
->data
+ madt_start
), "APIC",
426 table_data
->len
- madt_start
, 1, NULL
, NULL
);
429 /* Assign BSEL property to all buses. In the future, this can be changed
430 * to only assign to buses that support hotplug.
432 static void *acpi_set_bsel(PCIBus
*bus
, void *opaque
)
434 unsigned *bsel_alloc
= opaque
;
437 if (qbus_is_hotpluggable(BUS(bus
))) {
438 bus_bsel
= g_malloc(sizeof *bus_bsel
);
440 *bus_bsel
= (*bsel_alloc
)++;
441 object_property_add_uint32_ptr(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
,
448 static void acpi_set_pci_info(void)
450 PCIBus
*bus
= find_i440fx(); /* TODO: Q35 support */
451 unsigned bsel_alloc
= 0;
454 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
455 pci_for_each_bus_depth_first(bus
, acpi_set_bsel
, NULL
, &bsel_alloc
);
459 static void build_append_pcihp_notify_entry(Aml
*method
, int slot
)
462 int32_t devfn
= PCI_DEVFN(slot
, 0);
464 if_ctx
= aml_if(aml_and(aml_arg(0), aml_int(0x1U
<< slot
), NULL
));
465 aml_append(if_ctx
, aml_notify(aml_name("S%.02X", devfn
), aml_arg(1)));
466 aml_append(method
, if_ctx
);
469 static void build_append_pci_bus_devices(Aml
*parent_scope
, PCIBus
*bus
,
470 bool pcihp_bridge_en
)
472 Aml
*dev
, *notify_method
, *method
;
477 bsel
= object_property_get_qobject(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
, NULL
);
479 int64_t bsel_val
= qint_get_int(qobject_to_qint(bsel
));
481 aml_append(parent_scope
, aml_name_decl("BSEL", aml_int(bsel_val
)));
482 notify_method
= aml_method("DVNT", 2, AML_NOTSERIALIZED
);
485 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); i
+= PCI_FUNC_MAX
) {
488 PCIDevice
*pdev
= bus
->devices
[i
];
489 int slot
= PCI_SLOT(i
);
490 bool hotplug_enabled_dev
;
494 if (bsel
) { /* add hotplug slots for non present devices */
495 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
496 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
497 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
498 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
500 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
502 aml_append(dev
, method
);
503 aml_append(parent_scope
, dev
);
505 build_append_pcihp_notify_entry(notify_method
, slot
);
510 pc
= PCI_DEVICE_GET_CLASS(pdev
);
511 dc
= DEVICE_GET_CLASS(pdev
);
513 /* When hotplug for bridges is enabled, bridges are
514 * described in ACPI separately (see build_pci_bus_end).
515 * In this case they aren't themselves hot-pluggable.
516 * Hotplugged bridges *are* hot-pluggable.
518 bridge_in_acpi
= pc
->is_bridge
&& pcihp_bridge_en
&&
519 !DEVICE(pdev
)->hotplugged
;
521 hotplug_enabled_dev
= bsel
&& dc
->hotpluggable
&& !bridge_in_acpi
;
523 if (pc
->class_id
== PCI_CLASS_BRIDGE_ISA
) {
527 /* start to compose PCI slot descriptor */
528 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
529 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
531 if (pc
->class_id
== PCI_CLASS_DISPLAY_VGA
) {
532 /* add VGA specific AML methods */
535 if (object_dynamic_cast(OBJECT(pdev
), "qxl-vga")) {
541 method
= aml_method("_S1D", 0, AML_NOTSERIALIZED
);
542 aml_append(method
, aml_return(aml_int(0)));
543 aml_append(dev
, method
);
545 method
= aml_method("_S2D", 0, AML_NOTSERIALIZED
);
546 aml_append(method
, aml_return(aml_int(0)));
547 aml_append(dev
, method
);
549 method
= aml_method("_S3D", 0, AML_NOTSERIALIZED
);
550 aml_append(method
, aml_return(aml_int(s3d
)));
551 aml_append(dev
, method
);
552 } else if (hotplug_enabled_dev
) {
553 /* add _SUN/_EJ0 to make slot hotpluggable */
554 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
556 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
558 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
560 aml_append(dev
, method
);
563 build_append_pcihp_notify_entry(notify_method
, slot
);
565 } else if (bridge_in_acpi
) {
567 * device is coldplugged bridge,
568 * add child device descriptions into its scope
570 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
572 build_append_pci_bus_devices(dev
, sec_bus
, pcihp_bridge_en
);
574 /* slot descriptor has been composed, add it into parent context */
575 aml_append(parent_scope
, dev
);
579 aml_append(parent_scope
, notify_method
);
582 /* Append PCNT method to notify about events on local and child buses.
583 * Add unconditionally for root since DSDT expects it.
585 method
= aml_method("PCNT", 0, AML_NOTSERIALIZED
);
587 /* If bus supports hotplug select it and notify about local events */
589 int64_t bsel_val
= qint_get_int(qobject_to_qint(bsel
));
590 aml_append(method
, aml_store(aml_int(bsel_val
), aml_name("BNUM")));
592 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
595 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
599 /* Notify about child bus events in any case */
600 if (pcihp_bridge_en
) {
601 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
602 int32_t devfn
= sec
->parent_dev
->devfn
;
604 if (pci_bus_is_root(sec
) || pci_bus_is_express(sec
)) {
608 aml_append(method
, aml_name("^S%.02X.PCNT", devfn
));
611 aml_append(parent_scope
, method
);
612 qobject_decref(bsel
);
617 * @link_name: link name for PCI route entry
619 * build AML package containing a PCI route entry for @link_name
621 static Aml
*build_prt_entry(const char *link_name
)
623 Aml
*a_zero
= aml_int(0);
624 Aml
*pkg
= aml_package(4);
625 aml_append(pkg
, a_zero
);
626 aml_append(pkg
, a_zero
);
627 aml_append(pkg
, aml_name("%s", link_name
));
628 aml_append(pkg
, a_zero
);
633 * initialize_route - Initialize the interrupt routing rule
634 * through a specific LINK:
635 * if (lnk_idx == idx)
636 * route using link 'link_name'
638 static Aml
*initialize_route(Aml
*route
, const char *link_name
,
639 Aml
*lnk_idx
, int idx
)
641 Aml
*if_ctx
= aml_if(aml_equal(lnk_idx
, aml_int(idx
)));
642 Aml
*pkg
= build_prt_entry(link_name
);
644 aml_append(if_ctx
, aml_store(pkg
, route
));
650 * build_prt - Define interrupt rounting rules
652 * Returns an array of 128 routes, one for each device,
653 * based on device location.
654 * The main goal is to equaly distribute the interrupts
655 * over the 4 existing ACPI links (works only for i440fx).
656 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
659 static Aml
*build_prt(bool is_pci0_prt
)
661 Aml
*method
, *while_ctx
, *pin
, *res
;
663 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
666 aml_append(method
, aml_store(aml_package(128), res
));
667 aml_append(method
, aml_store(aml_int(0), pin
));
669 /* while (pin < 128) */
670 while_ctx
= aml_while(aml_lless(pin
, aml_int(128)));
672 Aml
*slot
= aml_local(2);
673 Aml
*lnk_idx
= aml_local(3);
674 Aml
*route
= aml_local(4);
676 /* slot = pin >> 2 */
677 aml_append(while_ctx
,
678 aml_store(aml_shiftright(pin
, aml_int(2), NULL
), slot
));
679 /* lnk_idx = (slot + pin) & 3 */
680 aml_append(while_ctx
,
681 aml_store(aml_and(aml_add(pin
, slot
, NULL
), aml_int(3), NULL
),
684 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
685 aml_append(while_ctx
, initialize_route(route
, "LNKD", lnk_idx
, 0));
687 Aml
*if_device_1
, *if_pin_4
, *else_pin_4
;
689 /* device 1 is the power-management device, needs SCI */
690 if_device_1
= aml_if(aml_equal(lnk_idx
, aml_int(1)));
692 if_pin_4
= aml_if(aml_equal(pin
, aml_int(4)));
695 aml_store(build_prt_entry("LNKS"), route
));
697 aml_append(if_device_1
, if_pin_4
);
698 else_pin_4
= aml_else();
700 aml_append(else_pin_4
,
701 aml_store(build_prt_entry("LNKA"), route
));
703 aml_append(if_device_1
, else_pin_4
);
705 aml_append(while_ctx
, if_device_1
);
707 aml_append(while_ctx
, initialize_route(route
, "LNKA", lnk_idx
, 1));
709 aml_append(while_ctx
, initialize_route(route
, "LNKB", lnk_idx
, 2));
710 aml_append(while_ctx
, initialize_route(route
, "LNKC", lnk_idx
, 3));
712 /* route[0] = 0x[slot]FFFF */
713 aml_append(while_ctx
,
714 aml_store(aml_or(aml_shiftleft(slot
, aml_int(16)), aml_int(0xFFFF),
716 aml_index(route
, aml_int(0))));
717 /* route[1] = pin & 3 */
718 aml_append(while_ctx
,
719 aml_store(aml_and(pin
, aml_int(3), NULL
),
720 aml_index(route
, aml_int(1))));
721 /* res[pin] = route */
722 aml_append(while_ctx
, aml_store(route
, aml_index(res
, pin
)));
724 aml_append(while_ctx
, aml_increment(pin
));
726 aml_append(method
, while_ctx
);
728 aml_append(method
, aml_return(res
));
733 typedef struct CrsRangeEntry
{
738 static void crs_range_insert(GPtrArray
*ranges
, uint64_t base
, uint64_t limit
)
740 CrsRangeEntry
*entry
;
742 entry
= g_malloc(sizeof(*entry
));
744 entry
->limit
= limit
;
746 g_ptr_array_add(ranges
, entry
);
749 static void crs_range_free(gpointer data
)
751 CrsRangeEntry
*entry
= (CrsRangeEntry
*)data
;
755 typedef struct CrsRangeSet
{
756 GPtrArray
*io_ranges
;
757 GPtrArray
*mem_ranges
;
758 GPtrArray
*mem_64bit_ranges
;
761 static void crs_range_set_init(CrsRangeSet
*range_set
)
763 range_set
->io_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
764 range_set
->mem_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
765 range_set
->mem_64bit_ranges
=
766 g_ptr_array_new_with_free_func(crs_range_free
);
769 static void crs_range_set_free(CrsRangeSet
*range_set
)
771 g_ptr_array_free(range_set
->io_ranges
, true);
772 g_ptr_array_free(range_set
->mem_ranges
, true);
773 g_ptr_array_free(range_set
->mem_64bit_ranges
, true);
776 static gint
crs_range_compare(gconstpointer a
, gconstpointer b
)
778 CrsRangeEntry
*entry_a
= *(CrsRangeEntry
**)a
;
779 CrsRangeEntry
*entry_b
= *(CrsRangeEntry
**)b
;
781 return (int64_t)entry_a
->base
- (int64_t)entry_b
->base
;
785 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
786 * interval, computes the 'free' ranges from the same interval.
787 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
788 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
790 static void crs_replace_with_free_ranges(GPtrArray
*ranges
,
791 uint64_t start
, uint64_t end
)
793 GPtrArray
*free_ranges
= g_ptr_array_new();
794 uint64_t free_base
= start
;
797 g_ptr_array_sort(ranges
, crs_range_compare
);
798 for (i
= 0; i
< ranges
->len
; i
++) {
799 CrsRangeEntry
*used
= g_ptr_array_index(ranges
, i
);
801 if (free_base
< used
->base
) {
802 crs_range_insert(free_ranges
, free_base
, used
->base
- 1);
805 free_base
= used
->limit
+ 1;
808 if (free_base
< end
) {
809 crs_range_insert(free_ranges
, free_base
, end
);
812 g_ptr_array_set_size(ranges
, 0);
813 for (i
= 0; i
< free_ranges
->len
; i
++) {
814 g_ptr_array_add(ranges
, g_ptr_array_index(free_ranges
, i
));
817 g_ptr_array_free(free_ranges
, true);
821 * crs_range_merge - merges adjacent ranges in the given array.
822 * Array elements are deleted and replaced with the merged ranges.
824 static void crs_range_merge(GPtrArray
*range
)
826 GPtrArray
*tmp
= g_ptr_array_new_with_free_func(crs_range_free
);
827 CrsRangeEntry
*entry
;
828 uint64_t range_base
, range_limit
;
835 g_ptr_array_sort(range
, crs_range_compare
);
837 entry
= g_ptr_array_index(range
, 0);
838 range_base
= entry
->base
;
839 range_limit
= entry
->limit
;
840 for (i
= 1; i
< range
->len
; i
++) {
841 entry
= g_ptr_array_index(range
, i
);
842 if (entry
->base
- 1 == range_limit
) {
843 range_limit
= entry
->limit
;
845 crs_range_insert(tmp
, range_base
, range_limit
);
846 range_base
= entry
->base
;
847 range_limit
= entry
->limit
;
850 crs_range_insert(tmp
, range_base
, range_limit
);
852 g_ptr_array_set_size(range
, 0);
853 for (i
= 0; i
< tmp
->len
; i
++) {
854 entry
= g_ptr_array_index(tmp
, i
);
855 crs_range_insert(range
, entry
->base
, entry
->limit
);
857 g_ptr_array_free(tmp
, true);
860 static Aml
*build_crs(PCIHostState
*host
, CrsRangeSet
*range_set
)
862 Aml
*crs
= aml_resource_template();
863 CrsRangeSet temp_range_set
;
864 CrsRangeEntry
*entry
;
865 uint8_t max_bus
= pci_bus_num(host
->bus
);
870 crs_range_set_init(&temp_range_set
);
871 for (devfn
= 0; devfn
< ARRAY_SIZE(host
->bus
->devices
); devfn
++) {
872 uint64_t range_base
, range_limit
;
873 PCIDevice
*dev
= host
->bus
->devices
[devfn
];
879 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
880 PCIIORegion
*r
= &dev
->io_regions
[i
];
882 range_base
= r
->addr
;
883 range_limit
= r
->addr
+ r
->size
- 1;
886 * Work-around for old bioses
887 * that do not support multiple root buses
889 if (!range_base
|| range_base
> range_limit
) {
893 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
894 crs_range_insert(temp_range_set
.io_ranges
,
895 range_base
, range_limit
);
896 } else { /* "memory" */
897 crs_range_insert(temp_range_set
.mem_ranges
,
898 range_base
, range_limit
);
902 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
903 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
904 uint8_t subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
905 if (subordinate
> max_bus
) {
906 max_bus
= subordinate
;
909 range_base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
910 range_limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
913 * Work-around for old bioses
914 * that do not support multiple root buses
916 if (range_base
&& range_base
<= range_limit
) {
917 crs_range_insert(temp_range_set
.io_ranges
,
918 range_base
, range_limit
);
922 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
924 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
927 * Work-around for old bioses
928 * that do not support multiple root buses
930 if (range_base
&& range_base
<= range_limit
) {
931 uint64_t length
= range_limit
- range_base
+ 1;
932 if (range_limit
<= UINT32_MAX
&& length
<= UINT32_MAX
) {
933 crs_range_insert(temp_range_set
.mem_ranges
,
934 range_base
, range_limit
);
936 crs_range_insert(temp_range_set
.mem_64bit_ranges
,
937 range_base
, range_limit
);
942 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
944 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
947 * Work-around for old bioses
948 * that do not support multiple root buses
950 if (range_base
&& range_base
<= range_limit
) {
951 uint64_t length
= range_limit
- range_base
+ 1;
952 if (range_limit
<= UINT32_MAX
&& length
<= UINT32_MAX
) {
953 crs_range_insert(temp_range_set
.mem_ranges
,
954 range_base
, range_limit
);
956 crs_range_insert(temp_range_set
.mem_64bit_ranges
,
957 range_base
, range_limit
);
963 crs_range_merge(temp_range_set
.io_ranges
);
964 for (i
= 0; i
< temp_range_set
.io_ranges
->len
; i
++) {
965 entry
= g_ptr_array_index(temp_range_set
.io_ranges
, i
);
967 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
968 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
969 0, entry
->base
, entry
->limit
, 0,
970 entry
->limit
- entry
->base
+ 1));
971 crs_range_insert(range_set
->io_ranges
, entry
->base
, entry
->limit
);
974 crs_range_merge(temp_range_set
.mem_ranges
);
975 for (i
= 0; i
< temp_range_set
.mem_ranges
->len
; i
++) {
976 entry
= g_ptr_array_index(temp_range_set
.mem_ranges
, i
);
978 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
979 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
981 0, entry
->base
, entry
->limit
, 0,
982 entry
->limit
- entry
->base
+ 1));
983 crs_range_insert(range_set
->mem_ranges
, entry
->base
, entry
->limit
);
986 crs_range_merge(temp_range_set
.mem_64bit_ranges
);
987 for (i
= 0; i
< temp_range_set
.mem_64bit_ranges
->len
; i
++) {
988 entry
= g_ptr_array_index(temp_range_set
.mem_64bit_ranges
, i
);
990 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
991 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
993 0, entry
->base
, entry
->limit
, 0,
994 entry
->limit
- entry
->base
+ 1));
995 crs_range_insert(range_set
->mem_64bit_ranges
,
996 entry
->base
, entry
->limit
);
999 crs_range_set_free(&temp_range_set
);
1002 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
1004 pci_bus_num(host
->bus
),
1007 max_bus
- pci_bus_num(host
->bus
) + 1));
1012 static void build_memory_devices(Aml
*sb_scope
, int nr_mem
,
1013 uint16_t io_base
, uint16_t io_len
)
1023 /* build memory devices */
1024 assert(nr_mem
<= ACPI_MAX_RAM_SLOTS
);
1025 scope
= aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE
);
1027 aml_name_decl(MEMORY_SLOTS_NUMBER
, aml_int(nr_mem
))
1030 crs
= aml_resource_template();
1032 aml_io(AML_DECODE16
, io_base
, io_base
, 0, io_len
)
1034 aml_append(scope
, aml_name_decl("_CRS", crs
));
1036 aml_append(scope
, aml_operation_region(
1037 MEMORY_HOTPLUG_IO_REGION
, AML_SYSTEM_IO
,
1038 aml_int(io_base
), io_len
)
1041 field
= aml_field(MEMORY_HOTPLUG_IO_REGION
, AML_DWORD_ACC
,
1042 AML_NOLOCK
, AML_PRESERVE
);
1043 aml_append(field
, /* read only */
1044 aml_named_field(MEMORY_SLOT_ADDR_LOW
, 32));
1045 aml_append(field
, /* read only */
1046 aml_named_field(MEMORY_SLOT_ADDR_HIGH
, 32));
1047 aml_append(field
, /* read only */
1048 aml_named_field(MEMORY_SLOT_SIZE_LOW
, 32));
1049 aml_append(field
, /* read only */
1050 aml_named_field(MEMORY_SLOT_SIZE_HIGH
, 32));
1051 aml_append(field
, /* read only */
1052 aml_named_field(MEMORY_SLOT_PROXIMITY
, 32));
1053 aml_append(scope
, field
);
1055 field
= aml_field(MEMORY_HOTPLUG_IO_REGION
, AML_BYTE_ACC
,
1056 AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1057 aml_append(field
, aml_reserved_field(160 /* bits, Offset(20) */));
1058 aml_append(field
, /* 1 if enabled, read only */
1059 aml_named_field(MEMORY_SLOT_ENABLED
, 1));
1061 /*(read) 1 if has a insert event. (write) 1 to clear event */
1062 aml_named_field(MEMORY_SLOT_INSERT_EVENT
, 1));
1064 /* (read) 1 if has a remove event. (write) 1 to clear event */
1065 aml_named_field(MEMORY_SLOT_REMOVE_EVENT
, 1));
1067 /* initiates device eject, write only */
1068 aml_named_field(MEMORY_SLOT_EJECT
, 1));
1069 aml_append(scope
, field
);
1071 field
= aml_field(MEMORY_HOTPLUG_IO_REGION
, AML_DWORD_ACC
,
1072 AML_NOLOCK
, AML_PRESERVE
);
1073 aml_append(field
, /* DIMM selector, write only */
1074 aml_named_field(MEMORY_SLOT_SLECTOR
, 32));
1075 aml_append(field
, /* _OST event code, write only */
1076 aml_named_field(MEMORY_SLOT_OST_EVENT
, 32));
1077 aml_append(field
, /* _OST status code, write only */
1078 aml_named_field(MEMORY_SLOT_OST_STATUS
, 32));
1079 aml_append(scope
, field
);
1080 aml_append(sb_scope
, scope
);
1082 for (i
= 0; i
< nr_mem
; i
++) {
1083 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
1086 dev
= aml_device("MP%02X", i
);
1087 aml_append(dev
, aml_name_decl("_UID", aml_string("0x%02X", i
)));
1088 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1090 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1091 s
= BASEPATH MEMORY_SLOT_CRS_METHOD
;
1092 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1093 aml_append(dev
, method
);
1095 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1096 s
= BASEPATH MEMORY_SLOT_STATUS_METHOD
;
1097 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1098 aml_append(dev
, method
);
1100 method
= aml_method("_PXM", 0, AML_NOTSERIALIZED
);
1101 s
= BASEPATH MEMORY_SLOT_PROXIMITY_METHOD
;
1102 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1103 aml_append(dev
, method
);
1105 method
= aml_method("_OST", 3, AML_NOTSERIALIZED
);
1106 s
= BASEPATH MEMORY_SLOT_OST_METHOD
;
1108 aml_append(method
, aml_return(aml_call4(
1109 s
, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1111 aml_append(dev
, method
);
1113 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
1114 s
= BASEPATH MEMORY_SLOT_EJECT_METHOD
;
1115 aml_append(method
, aml_return(aml_call2(
1116 s
, aml_name("_UID"), aml_arg(0))));
1117 aml_append(dev
, method
);
1119 aml_append(sb_scope
, dev
);
1122 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1123 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1125 method
= aml_method(MEMORY_SLOT_NOTIFY_METHOD
, 2, AML_NOTSERIALIZED
);
1126 for (i
= 0; i
< nr_mem
; i
++) {
1127 ifctx
= aml_if(aml_equal(aml_arg(0), aml_int(i
)));
1129 aml_notify(aml_name("MP%.02X", i
), aml_arg(1))
1131 aml_append(method
, ifctx
);
1133 aml_append(sb_scope
, method
);
1136 static void build_hpet_aml(Aml
*table
)
1142 Aml
*scope
= aml_scope("_SB");
1143 Aml
*dev
= aml_device("HPET");
1144 Aml
*zero
= aml_int(0);
1145 Aml
*id
= aml_local(0);
1146 Aml
*period
= aml_local(1);
1148 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1149 aml_append(dev
, aml_name_decl("_UID", zero
));
1152 aml_operation_region("HPTM", AML_SYSTEM_MEMORY
, aml_int(HPET_BASE
),
1154 field
= aml_field("HPTM", AML_DWORD_ACC
, AML_LOCK
, AML_PRESERVE
);
1155 aml_append(field
, aml_named_field("VEND", 32));
1156 aml_append(field
, aml_named_field("PRD", 32));
1157 aml_append(dev
, field
);
1159 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1160 aml_append(method
, aml_store(aml_name("VEND"), id
));
1161 aml_append(method
, aml_store(aml_name("PRD"), period
));
1162 aml_append(method
, aml_shiftright(id
, aml_int(16), id
));
1163 if_ctx
= aml_if(aml_lor(aml_equal(id
, zero
),
1164 aml_equal(id
, aml_int(0xffff))));
1166 aml_append(if_ctx
, aml_return(zero
));
1168 aml_append(method
, if_ctx
);
1170 if_ctx
= aml_if(aml_lor(aml_equal(period
, zero
),
1171 aml_lgreater(period
, aml_int(100000000))));
1173 aml_append(if_ctx
, aml_return(zero
));
1175 aml_append(method
, if_ctx
);
1177 aml_append(method
, aml_return(aml_int(0x0F)));
1178 aml_append(dev
, method
);
1180 crs
= aml_resource_template();
1181 aml_append(crs
, aml_memory32_fixed(HPET_BASE
, HPET_LEN
, AML_READ_ONLY
));
1182 aml_append(dev
, aml_name_decl("_CRS", crs
));
1184 aml_append(scope
, dev
);
1185 aml_append(table
, scope
);
1188 static Aml
*build_fdinfo_aml(int idx
, FloppyDriveType type
)
1191 uint8_t maxc
, maxh
, maxs
;
1193 isa_fdc_get_drive_max_chs(type
, &maxc
, &maxh
, &maxs
);
1195 dev
= aml_device("FLP%c", 'A' + idx
);
1197 aml_append(dev
, aml_name_decl("_ADR", aml_int(idx
)));
1199 fdi
= aml_package(16);
1200 aml_append(fdi
, aml_int(idx
)); /* Drive Number */
1202 aml_int(cmos_get_fd_drive_type(type
))); /* Device Type */
1204 * the values below are the limits of the drive, and are thus independent
1205 * of the inserted media
1207 aml_append(fdi
, aml_int(maxc
)); /* Maximum Cylinder Number */
1208 aml_append(fdi
, aml_int(maxs
)); /* Maximum Sector Number */
1209 aml_append(fdi
, aml_int(maxh
)); /* Maximum Head Number */
1211 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1212 * the drive type, so shall we
1214 aml_append(fdi
, aml_int(0xAF)); /* disk_specify_1 */
1215 aml_append(fdi
, aml_int(0x02)); /* disk_specify_2 */
1216 aml_append(fdi
, aml_int(0x25)); /* disk_motor_wait */
1217 aml_append(fdi
, aml_int(0x02)); /* disk_sector_siz */
1218 aml_append(fdi
, aml_int(0x12)); /* disk_eot */
1219 aml_append(fdi
, aml_int(0x1B)); /* disk_rw_gap */
1220 aml_append(fdi
, aml_int(0xFF)); /* disk_dtl */
1221 aml_append(fdi
, aml_int(0x6C)); /* disk_formt_gap */
1222 aml_append(fdi
, aml_int(0xF6)); /* disk_fill */
1223 aml_append(fdi
, aml_int(0x0F)); /* disk_head_sttl */
1224 aml_append(fdi
, aml_int(0x08)); /* disk_motor_strt */
1226 aml_append(dev
, aml_name_decl("_FDI", fdi
));
1230 static Aml
*build_fdc_device_aml(ISADevice
*fdc
)
1236 #define ACPI_FDE_MAX_FD 4
1237 uint32_t fde_buf
[5] = {
1238 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1239 cpu_to_le32(2) /* tape presence (2 == never present) */
1242 dev
= aml_device("FDC0");
1243 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1245 crs
= aml_resource_template();
1246 aml_append(crs
, aml_io(AML_DECODE16
, 0x03F2, 0x03F2, 0x00, 0x04));
1247 aml_append(crs
, aml_io(AML_DECODE16
, 0x03F7, 0x03F7, 0x00, 0x01));
1248 aml_append(crs
, aml_irq_no_flags(6));
1250 aml_dma(AML_COMPATIBILITY
, AML_NOTBUSMASTER
, AML_TRANSFER8
, 2));
1251 aml_append(dev
, aml_name_decl("_CRS", crs
));
1253 for (i
= 0; i
< MIN(MAX_FD
, ACPI_FDE_MAX_FD
); i
++) {
1254 FloppyDriveType type
= isa_fdc_get_drive_type(fdc
, i
);
1256 if (type
< FLOPPY_DRIVE_TYPE_NONE
) {
1257 fde_buf
[i
] = cpu_to_le32(1); /* drive present */
1258 aml_append(dev
, build_fdinfo_aml(i
, type
));
1261 aml_append(dev
, aml_name_decl("_FDE",
1262 aml_buffer(sizeof(fde_buf
), (uint8_t *)fde_buf
)));
1267 static Aml
*build_rtc_device_aml(void)
1272 dev
= aml_device("RTC");
1273 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1274 crs
= aml_resource_template();
1275 aml_append(crs
, aml_io(AML_DECODE16
, 0x0070, 0x0070, 0x10, 0x02));
1276 aml_append(crs
, aml_irq_no_flags(8));
1277 aml_append(crs
, aml_io(AML_DECODE16
, 0x0072, 0x0072, 0x02, 0x06));
1278 aml_append(dev
, aml_name_decl("_CRS", crs
));
1283 static Aml
*build_kbd_device_aml(void)
1289 dev
= aml_device("KBD");
1290 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1292 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1293 aml_append(method
, aml_return(aml_int(0x0f)));
1294 aml_append(dev
, method
);
1296 crs
= aml_resource_template();
1297 aml_append(crs
, aml_io(AML_DECODE16
, 0x0060, 0x0060, 0x01, 0x01));
1298 aml_append(crs
, aml_io(AML_DECODE16
, 0x0064, 0x0064, 0x01, 0x01));
1299 aml_append(crs
, aml_irq_no_flags(1));
1300 aml_append(dev
, aml_name_decl("_CRS", crs
));
1305 static Aml
*build_mouse_device_aml(void)
1311 dev
= aml_device("MOU");
1312 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1314 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1315 aml_append(method
, aml_return(aml_int(0x0f)));
1316 aml_append(dev
, method
);
1318 crs
= aml_resource_template();
1319 aml_append(crs
, aml_irq_no_flags(12));
1320 aml_append(dev
, aml_name_decl("_CRS", crs
));
1325 static Aml
*build_lpt_device_aml(void)
1332 Aml
*zero
= aml_int(0);
1333 Aml
*is_present
= aml_local(0);
1335 dev
= aml_device("LPT");
1336 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1338 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1339 aml_append(method
, aml_store(aml_name("LPEN"), is_present
));
1340 if_ctx
= aml_if(aml_equal(is_present
, zero
));
1342 aml_append(if_ctx
, aml_return(aml_int(0x00)));
1344 aml_append(method
, if_ctx
);
1345 else_ctx
= aml_else();
1347 aml_append(else_ctx
, aml_return(aml_int(0x0f)));
1349 aml_append(method
, else_ctx
);
1350 aml_append(dev
, method
);
1352 crs
= aml_resource_template();
1353 aml_append(crs
, aml_io(AML_DECODE16
, 0x0378, 0x0378, 0x08, 0x08));
1354 aml_append(crs
, aml_irq_no_flags(7));
1355 aml_append(dev
, aml_name_decl("_CRS", crs
));
1360 static Aml
*build_com_device_aml(uint8_t uid
)
1367 Aml
*zero
= aml_int(0);
1368 Aml
*is_present
= aml_local(0);
1369 const char *enabled_field
= "CAEN";
1371 uint16_t io_port
= 0x03F8;
1373 assert(uid
== 1 || uid
== 2);
1375 enabled_field
= "CBEN";
1380 dev
= aml_device("COM%d", uid
);
1381 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1382 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1384 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1385 aml_append(method
, aml_store(aml_name("%s", enabled_field
), is_present
));
1386 if_ctx
= aml_if(aml_equal(is_present
, zero
));
1388 aml_append(if_ctx
, aml_return(aml_int(0x00)));
1390 aml_append(method
, if_ctx
);
1391 else_ctx
= aml_else();
1393 aml_append(else_ctx
, aml_return(aml_int(0x0f)));
1395 aml_append(method
, else_ctx
);
1396 aml_append(dev
, method
);
1398 crs
= aml_resource_template();
1399 aml_append(crs
, aml_io(AML_DECODE16
, io_port
, io_port
, 0x00, 0x08));
1400 aml_append(crs
, aml_irq_no_flags(irq
));
1401 aml_append(dev
, aml_name_decl("_CRS", crs
));
1406 static void build_isa_devices_aml(Aml
*table
)
1408 ISADevice
*fdc
= pc_find_fdc0();
1411 Aml
*scope
= aml_scope("_SB.PCI0.ISA");
1412 Object
*obj
= object_resolve_path_type("", TYPE_ISA_BUS
, &ambiguous
);
1414 aml_append(scope
, build_rtc_device_aml());
1415 aml_append(scope
, build_kbd_device_aml());
1416 aml_append(scope
, build_mouse_device_aml());
1418 aml_append(scope
, build_fdc_device_aml(fdc
));
1420 aml_append(scope
, build_lpt_device_aml());
1421 aml_append(scope
, build_com_device_aml(1));
1422 aml_append(scope
, build_com_device_aml(2));
1425 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1427 error_report("No ISA bus, unable to define IPMI ACPI data");
1429 build_acpi_ipmi_devices(scope
, BUS(obj
));
1432 aml_append(table
, scope
);
1435 static void build_dbg_aml(Aml
*table
)
1440 Aml
*scope
= aml_scope("\\");
1441 Aml
*buf
= aml_local(0);
1442 Aml
*len
= aml_local(1);
1443 Aml
*idx
= aml_local(2);
1446 aml_operation_region("DBG", AML_SYSTEM_IO
, aml_int(0x0402), 0x01));
1447 field
= aml_field("DBG", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1448 aml_append(field
, aml_named_field("DBGB", 8));
1449 aml_append(scope
, field
);
1451 method
= aml_method("DBUG", 1, AML_NOTSERIALIZED
);
1453 aml_append(method
, aml_to_hexstring(aml_arg(0), buf
));
1454 aml_append(method
, aml_to_buffer(buf
, buf
));
1455 aml_append(method
, aml_subtract(aml_sizeof(buf
), aml_int(1), len
));
1456 aml_append(method
, aml_store(aml_int(0), idx
));
1458 while_ctx
= aml_while(aml_lless(idx
, len
));
1459 aml_append(while_ctx
,
1460 aml_store(aml_derefof(aml_index(buf
, idx
)), aml_name("DBGB")));
1461 aml_append(while_ctx
, aml_increment(idx
));
1462 aml_append(method
, while_ctx
);
1464 aml_append(method
, aml_store(aml_int(0x0A), aml_name("DBGB")));
1465 aml_append(scope
, method
);
1467 aml_append(table
, scope
);
1470 static Aml
*build_link_dev(const char *name
, uint8_t uid
, Aml
*reg
)
1475 uint32_t irqs
[] = {5, 10, 11};
1477 dev
= aml_device("%s", name
);
1478 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1479 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1481 crs
= aml_resource_template();
1482 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1483 AML_SHARED
, irqs
, ARRAY_SIZE(irqs
)));
1484 aml_append(dev
, aml_name_decl("_PRS", crs
));
1486 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1487 aml_append(method
, aml_return(aml_call1("IQST", reg
)));
1488 aml_append(dev
, method
);
1490 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1491 aml_append(method
, aml_or(reg
, aml_int(0x80), reg
));
1492 aml_append(dev
, method
);
1494 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1495 aml_append(method
, aml_return(aml_call1("IQCR", reg
)));
1496 aml_append(dev
, method
);
1498 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1499 aml_append(method
, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1500 aml_append(method
, aml_store(aml_name("PRRI"), reg
));
1501 aml_append(dev
, method
);
1506 static Aml
*build_gsi_link_dev(const char *name
, uint8_t uid
, uint8_t gsi
)
1513 dev
= aml_device("%s", name
);
1514 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1515 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1517 crs
= aml_resource_template();
1519 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1520 AML_SHARED
, &irqs
, 1));
1521 aml_append(dev
, aml_name_decl("_PRS", crs
));
1523 aml_append(dev
, aml_name_decl("_CRS", crs
));
1526 * _DIS can be no-op because the interrupt cannot be disabled.
1528 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1529 aml_append(dev
, method
);
1531 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1532 aml_append(dev
, method
);
1537 /* _CRS method - get current settings */
1538 static Aml
*build_iqcr_method(bool is_piix4
)
1542 Aml
*method
= aml_method("IQCR", 1, AML_SERIALIZED
);
1543 Aml
*crs
= aml_resource_template();
1546 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1547 AML_ACTIVE_HIGH
, AML_SHARED
, &irqs
, 1));
1548 aml_append(method
, aml_name_decl("PRR0", crs
));
1551 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1554 if_ctx
= aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1555 aml_append(if_ctx
, aml_store(aml_arg(0), aml_name("PRRI")));
1556 aml_append(method
, if_ctx
);
1559 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL
),
1563 aml_append(method
, aml_return(aml_name("PRR0")));
1567 /* _STA method - get status */
1568 static Aml
*build_irq_status_method(void)
1571 Aml
*method
= aml_method("IQST", 1, AML_NOTSERIALIZED
);
1573 if_ctx
= aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL
));
1574 aml_append(if_ctx
, aml_return(aml_int(0x09)));
1575 aml_append(method
, if_ctx
);
1576 aml_append(method
, aml_return(aml_int(0x0B)));
1580 static void build_piix4_pci0_int(Aml
*table
)
1587 Aml
*sb_scope
= aml_scope("_SB");
1588 Aml
*pci0_scope
= aml_scope("PCI0");
1590 aml_append(pci0_scope
, build_prt(true));
1591 aml_append(sb_scope
, pci0_scope
);
1593 field
= aml_field("PCI0.ISA.P40C", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1594 aml_append(field
, aml_named_field("PRQ0", 8));
1595 aml_append(field
, aml_named_field("PRQ1", 8));
1596 aml_append(field
, aml_named_field("PRQ2", 8));
1597 aml_append(field
, aml_named_field("PRQ3", 8));
1598 aml_append(sb_scope
, field
);
1600 aml_append(sb_scope
, build_irq_status_method());
1601 aml_append(sb_scope
, build_iqcr_method(true));
1603 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1604 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1605 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1606 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1608 dev
= aml_device("LNKS");
1610 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1611 aml_append(dev
, aml_name_decl("_UID", aml_int(4)));
1613 crs
= aml_resource_template();
1615 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1616 AML_ACTIVE_HIGH
, AML_SHARED
,
1618 aml_append(dev
, aml_name_decl("_PRS", crs
));
1620 /* The SCI cannot be disabled and is always attached to GSI 9,
1621 * so these are no-ops. We only need this link to override the
1622 * polarity to active high and match the content of the MADT.
1624 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1625 aml_append(method
, aml_return(aml_int(0x0b)));
1626 aml_append(dev
, method
);
1628 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1629 aml_append(dev
, method
);
1631 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1632 aml_append(method
, aml_return(aml_name("_PRS")));
1633 aml_append(dev
, method
);
1635 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1636 aml_append(dev
, method
);
1638 aml_append(sb_scope
, dev
);
1640 aml_append(table
, sb_scope
);
1643 static void append_q35_prt_entry(Aml
*ctx
, uint32_t nr
, const char *name
)
1648 char base
= name
[3] < 'E' ? 'A' : 'E';
1649 char *s
= g_strdup(name
);
1650 Aml
*a_nr
= aml_int((nr
<< 16) | 0xffff);
1652 assert(strlen(s
) == 4);
1654 head
= name
[3] - base
;
1655 for (i
= 0; i
< 4; i
++) {
1659 s
[3] = base
+ head
+ i
;
1660 pkg
= aml_package(4);
1661 aml_append(pkg
, a_nr
);
1662 aml_append(pkg
, aml_int(i
));
1663 aml_append(pkg
, aml_name("%s", s
));
1664 aml_append(pkg
, aml_int(0));
1665 aml_append(ctx
, pkg
);
1670 static Aml
*build_q35_routing_table(const char *str
)
1674 char *name
= g_strdup_printf("%s ", str
);
1676 pkg
= aml_package(128);
1677 for (i
= 0; i
< 0x18; i
++) {
1678 name
[3] = 'E' + (i
& 0x3);
1679 append_q35_prt_entry(pkg
, i
, name
);
1683 append_q35_prt_entry(pkg
, 0x18, name
);
1685 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1686 for (i
= 0x0019; i
< 0x1e; i
++) {
1688 append_q35_prt_entry(pkg
, i
, name
);
1691 /* PCIe->PCI bridge. use PIRQ[E-H] */
1693 append_q35_prt_entry(pkg
, 0x1e, name
);
1695 append_q35_prt_entry(pkg
, 0x1f, name
);
1701 static void build_q35_pci0_int(Aml
*table
)
1705 Aml
*sb_scope
= aml_scope("_SB");
1706 Aml
*pci0_scope
= aml_scope("PCI0");
1708 /* Zero => PIC mode, One => APIC Mode */
1709 aml_append(table
, aml_name_decl("PICF", aml_int(0)));
1710 method
= aml_method("_PIC", 1, AML_NOTSERIALIZED
);
1712 aml_append(method
, aml_store(aml_arg(0), aml_name("PICF")));
1714 aml_append(table
, method
);
1716 aml_append(pci0_scope
,
1717 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1718 aml_append(pci0_scope
,
1719 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1721 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
1726 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1728 /* Note: we provide the same info as the PCI routing
1729 table of the Bochs BIOS */
1730 if_ctx
= aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1731 aml_append(if_ctx
, aml_return(aml_name("PRTP")));
1732 aml_append(method
, if_ctx
);
1733 else_ctx
= aml_else();
1734 aml_append(else_ctx
, aml_return(aml_name("PRTA")));
1735 aml_append(method
, else_ctx
);
1737 aml_append(pci0_scope
, method
);
1738 aml_append(sb_scope
, pci0_scope
);
1740 field
= aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1741 aml_append(field
, aml_named_field("PRQA", 8));
1742 aml_append(field
, aml_named_field("PRQB", 8));
1743 aml_append(field
, aml_named_field("PRQC", 8));
1744 aml_append(field
, aml_named_field("PRQD", 8));
1745 aml_append(field
, aml_reserved_field(0x20));
1746 aml_append(field
, aml_named_field("PRQE", 8));
1747 aml_append(field
, aml_named_field("PRQF", 8));
1748 aml_append(field
, aml_named_field("PRQG", 8));
1749 aml_append(field
, aml_named_field("PRQH", 8));
1750 aml_append(sb_scope
, field
);
1752 aml_append(sb_scope
, build_irq_status_method());
1753 aml_append(sb_scope
, build_iqcr_method(false));
1755 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQA")));
1756 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQB")));
1757 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQC")));
1758 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQD")));
1759 aml_append(sb_scope
, build_link_dev("LNKE", 4, aml_name("PRQE")));
1760 aml_append(sb_scope
, build_link_dev("LNKF", 5, aml_name("PRQF")));
1761 aml_append(sb_scope
, build_link_dev("LNKG", 6, aml_name("PRQG")));
1762 aml_append(sb_scope
, build_link_dev("LNKH", 7, aml_name("PRQH")));
1764 aml_append(sb_scope
, build_gsi_link_dev("GSIA", 0x10, 0x10));
1765 aml_append(sb_scope
, build_gsi_link_dev("GSIB", 0x11, 0x11));
1766 aml_append(sb_scope
, build_gsi_link_dev("GSIC", 0x12, 0x12));
1767 aml_append(sb_scope
, build_gsi_link_dev("GSID", 0x13, 0x13));
1768 aml_append(sb_scope
, build_gsi_link_dev("GSIE", 0x14, 0x14));
1769 aml_append(sb_scope
, build_gsi_link_dev("GSIF", 0x15, 0x15));
1770 aml_append(sb_scope
, build_gsi_link_dev("GSIG", 0x16, 0x16));
1771 aml_append(sb_scope
, build_gsi_link_dev("GSIH", 0x17, 0x17));
1773 aml_append(table
, sb_scope
);
1776 static void build_q35_isa_bridge(Aml
*table
)
1782 scope
= aml_scope("_SB.PCI0");
1783 dev
= aml_device("ISA");
1784 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x001F0000)));
1786 /* ICH9 PCI to ISA irq remapping */
1787 aml_append(dev
, aml_operation_region("PIRQ", AML_PCI_CONFIG
,
1788 aml_int(0x60), 0x0C));
1790 aml_append(dev
, aml_operation_region("LPCD", AML_PCI_CONFIG
,
1791 aml_int(0x80), 0x02));
1792 field
= aml_field("LPCD", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1793 aml_append(field
, aml_named_field("COMA", 3));
1794 aml_append(field
, aml_reserved_field(1));
1795 aml_append(field
, aml_named_field("COMB", 3));
1796 aml_append(field
, aml_reserved_field(1));
1797 aml_append(field
, aml_named_field("LPTD", 2));
1798 aml_append(dev
, field
);
1800 aml_append(dev
, aml_operation_region("LPCE", AML_PCI_CONFIG
,
1801 aml_int(0x82), 0x02));
1803 field
= aml_field("LPCE", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1804 aml_append(field
, aml_named_field("CAEN", 1));
1805 aml_append(field
, aml_named_field("CBEN", 1));
1806 aml_append(field
, aml_named_field("LPEN", 1));
1807 aml_append(dev
, field
);
1809 aml_append(scope
, dev
);
1810 aml_append(table
, scope
);
1813 static void build_piix4_pm(Aml
*table
)
1818 scope
= aml_scope("_SB.PCI0");
1819 dev
= aml_device("PX13");
1820 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010003)));
1822 aml_append(dev
, aml_operation_region("P13C", AML_PCI_CONFIG
,
1823 aml_int(0x00), 0xff));
1824 aml_append(scope
, dev
);
1825 aml_append(table
, scope
);
1828 static void build_piix4_isa_bridge(Aml
*table
)
1834 scope
= aml_scope("_SB.PCI0");
1835 dev
= aml_device("ISA");
1836 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010000)));
1838 /* PIIX PCI to ISA irq remapping */
1839 aml_append(dev
, aml_operation_region("P40C", AML_PCI_CONFIG
,
1840 aml_int(0x60), 0x04));
1842 field
= aml_field("^PX13.P13C", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1843 /* Offset(0x5f),, 7, */
1844 aml_append(field
, aml_reserved_field(0x2f8));
1845 aml_append(field
, aml_reserved_field(7));
1846 aml_append(field
, aml_named_field("LPEN", 1));
1847 /* Offset(0x67),, 3, */
1848 aml_append(field
, aml_reserved_field(0x38));
1849 aml_append(field
, aml_reserved_field(3));
1850 aml_append(field
, aml_named_field("CAEN", 1));
1851 aml_append(field
, aml_reserved_field(3));
1852 aml_append(field
, aml_named_field("CBEN", 1));
1853 aml_append(dev
, field
);
1855 aml_append(scope
, dev
);
1856 aml_append(table
, scope
);
1859 static void build_piix4_pci_hotplug(Aml
*table
)
1865 scope
= aml_scope("_SB.PCI0");
1868 aml_operation_region("PCST", AML_SYSTEM_IO
, aml_int(0xae00), 0x08));
1869 field
= aml_field("PCST", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1870 aml_append(field
, aml_named_field("PCIU", 32));
1871 aml_append(field
, aml_named_field("PCID", 32));
1872 aml_append(scope
, field
);
1875 aml_operation_region("SEJ", AML_SYSTEM_IO
, aml_int(0xae08), 0x04));
1876 field
= aml_field("SEJ", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1877 aml_append(field
, aml_named_field("B0EJ", 32));
1878 aml_append(scope
, field
);
1881 aml_operation_region("BNMR", AML_SYSTEM_IO
, aml_int(0xae10), 0x04));
1882 field
= aml_field("BNMR", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1883 aml_append(field
, aml_named_field("BNUM", 32));
1884 aml_append(scope
, field
);
1886 aml_append(scope
, aml_mutex("BLCK", 0));
1888 method
= aml_method("PCEJ", 2, AML_NOTSERIALIZED
);
1889 aml_append(method
, aml_acquire(aml_name("BLCK"), 0xFFFF));
1890 aml_append(method
, aml_store(aml_arg(0), aml_name("BNUM")));
1892 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1893 aml_append(method
, aml_release(aml_name("BLCK")));
1894 aml_append(method
, aml_return(aml_int(0)));
1895 aml_append(scope
, method
);
1897 aml_append(table
, scope
);
1900 static Aml
*build_q35_osc_method(void)
1906 Aml
*a_cwd1
= aml_name("CDW1");
1907 Aml
*a_ctrl
= aml_name("CTRL");
1909 method
= aml_method("_OSC", 4, AML_NOTSERIALIZED
);
1910 aml_append(method
, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1912 if_ctx
= aml_if(aml_equal(
1913 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1914 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1915 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1917 aml_append(if_ctx
, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1918 aml_append(if_ctx
, aml_store(aml_name("CDW3"), a_ctrl
));
1921 * Always allow native PME, AER (no dependencies)
1922 * Never allow SHPC (no SHPC controller in this system)
1924 aml_append(if_ctx
, aml_and(a_ctrl
, aml_int(0x1D), a_ctrl
));
1926 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1927 /* Unknown revision */
1928 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x08), a_cwd1
));
1929 aml_append(if_ctx
, if_ctx2
);
1931 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl
)));
1932 /* Capabilities bits were masked */
1933 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x10), a_cwd1
));
1934 aml_append(if_ctx
, if_ctx2
);
1936 /* Update DWORD3 in the buffer */
1937 aml_append(if_ctx
, aml_store(a_ctrl
, aml_name("CDW3")));
1938 aml_append(method
, if_ctx
);
1940 else_ctx
= aml_else();
1941 /* Unrecognized UUID */
1942 aml_append(else_ctx
, aml_or(a_cwd1
, aml_int(4), a_cwd1
));
1943 aml_append(method
, else_ctx
);
1945 aml_append(method
, aml_return(aml_arg(3)));
1950 build_dsdt(GArray
*table_data
, BIOSLinker
*linker
,
1951 AcpiPmInfo
*pm
, AcpiMiscInfo
*misc
,
1952 Range
*pci_hole
, Range
*pci_hole64
, MachineState
*machine
)
1954 CrsRangeEntry
*entry
;
1955 Aml
*dsdt
, *sb_scope
, *scope
, *dev
, *method
, *field
, *pkg
, *crs
;
1956 CrsRangeSet crs_range_set
;
1957 PCMachineState
*pcms
= PC_MACHINE(machine
);
1958 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(machine
);
1959 uint32_t nr_mem
= machine
->ram_slots
;
1960 int root_bus_limit
= 0xFF;
1964 dsdt
= init_aml_allocator();
1966 /* Reserve space for header */
1967 acpi_data_push(dsdt
->buf
, sizeof(AcpiTableHeader
));
1969 build_dbg_aml(dsdt
);
1970 if (misc
->is_piix4
) {
1971 sb_scope
= aml_scope("_SB");
1972 dev
= aml_device("PCI0");
1973 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1974 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
1975 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
1976 aml_append(sb_scope
, dev
);
1977 aml_append(dsdt
, sb_scope
);
1979 build_hpet_aml(dsdt
);
1980 build_piix4_pm(dsdt
);
1981 build_piix4_isa_bridge(dsdt
);
1982 build_isa_devices_aml(dsdt
);
1983 build_piix4_pci_hotplug(dsdt
);
1984 build_piix4_pci0_int(dsdt
);
1986 sb_scope
= aml_scope("_SB");
1987 aml_append(sb_scope
,
1988 aml_operation_region("PCST", AML_SYSTEM_IO
, aml_int(0xae00), 0x0c));
1989 aml_append(sb_scope
,
1990 aml_operation_region("PCSB", AML_SYSTEM_IO
, aml_int(0xae0c), 0x01));
1991 field
= aml_field("PCSB", AML_ANY_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1992 aml_append(field
, aml_named_field("PCIB", 8));
1993 aml_append(sb_scope
, field
);
1994 aml_append(dsdt
, sb_scope
);
1996 sb_scope
= aml_scope("_SB");
1997 dev
= aml_device("PCI0");
1998 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1999 aml_append(dev
, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
2000 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
2001 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
2002 aml_append(dev
, aml_name_decl("SUPP", aml_int(0)));
2003 aml_append(dev
, aml_name_decl("CTRL", aml_int(0)));
2004 aml_append(dev
, build_q35_osc_method());
2005 aml_append(sb_scope
, dev
);
2006 aml_append(dsdt
, sb_scope
);
2008 build_hpet_aml(dsdt
);
2009 build_q35_isa_bridge(dsdt
);
2010 build_isa_devices_aml(dsdt
);
2011 build_q35_pci0_int(dsdt
);
2014 if (pcmc
->legacy_cpu_hotplug
) {
2015 build_legacy_cpu_hotplug_aml(dsdt
, machine
, pm
->cpu_hp_io_base
);
2017 CPUHotplugFeatures opts
= {
2018 .apci_1_compatible
= true, .has_legacy_cphp
= true
2020 build_cpus_aml(dsdt
, machine
, opts
, pm
->cpu_hp_io_base
,
2021 "\\_SB.PCI0", "\\_GPE._E02");
2023 build_memory_hotplug_aml(dsdt
, nr_mem
, pm
->mem_hp_io_base
,
2026 scope
= aml_scope("_GPE");
2028 aml_append(scope
, aml_name_decl("_HID", aml_string("ACPI0006")));
2030 if (misc
->is_piix4
) {
2031 method
= aml_method("_E01", 0, AML_NOTSERIALIZED
);
2033 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
2034 aml_append(method
, aml_call0("\\_SB.PCI0.PCNT"));
2035 aml_append(method
, aml_release(aml_name("\\_SB.PCI0.BLCK")));
2036 aml_append(scope
, method
);
2039 method
= aml_method("_E03", 0, AML_NOTSERIALIZED
);
2040 aml_append(method
, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH
));
2041 aml_append(scope
, method
);
2043 aml_append(dsdt
, scope
);
2045 crs_range_set_init(&crs_range_set
);
2046 bus
= PC_MACHINE(machine
)->bus
;
2048 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
2049 uint8_t bus_num
= pci_bus_num(bus
);
2050 uint8_t numa_node
= pci_bus_numa_node(bus
);
2052 /* look only for expander root buses */
2053 if (!pci_bus_is_root(bus
)) {
2057 if (bus_num
< root_bus_limit
) {
2058 root_bus_limit
= bus_num
- 1;
2061 scope
= aml_scope("\\_SB");
2062 dev
= aml_device("PC%.02X", bus_num
);
2063 aml_append(dev
, aml_name_decl("_UID", aml_int(bus_num
)));
2064 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
2065 aml_append(dev
, aml_name_decl("_BBN", aml_int(bus_num
)));
2067 if (numa_node
!= NUMA_NODE_UNASSIGNED
) {
2068 aml_append(dev
, aml_name_decl("_PXM", aml_int(numa_node
)));
2071 aml_append(dev
, build_prt(false));
2072 crs
= build_crs(PCI_HOST_BRIDGE(BUS(bus
)->parent
), &crs_range_set
);
2073 aml_append(dev
, aml_name_decl("_CRS", crs
));
2074 aml_append(scope
, dev
);
2075 aml_append(dsdt
, scope
);
2079 scope
= aml_scope("\\_SB.PCI0");
2080 /* build PCI0._CRS */
2081 crs
= aml_resource_template();
2083 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
2084 0x0000, 0x0, root_bus_limit
,
2085 0x0000, root_bus_limit
+ 1));
2086 aml_append(crs
, aml_io(AML_DECODE16
, 0x0CF8, 0x0CF8, 0x01, 0x08));
2089 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
2090 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
2091 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
2093 crs_replace_with_free_ranges(crs_range_set
.io_ranges
, 0x0D00, 0xFFFF);
2094 for (i
= 0; i
< crs_range_set
.io_ranges
->len
; i
++) {
2095 entry
= g_ptr_array_index(crs_range_set
.io_ranges
, i
);
2097 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
2098 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
2099 0x0000, entry
->base
, entry
->limit
,
2100 0x0000, entry
->limit
- entry
->base
+ 1));
2104 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
2105 AML_CACHEABLE
, AML_READ_WRITE
,
2106 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2108 crs_replace_with_free_ranges(crs_range_set
.mem_ranges
,
2109 range_lob(pci_hole
),
2110 range_upb(pci_hole
));
2111 for (i
= 0; i
< crs_range_set
.mem_ranges
->len
; i
++) {
2112 entry
= g_ptr_array_index(crs_range_set
.mem_ranges
, i
);
2114 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
2115 AML_NON_CACHEABLE
, AML_READ_WRITE
,
2116 0, entry
->base
, entry
->limit
,
2117 0, entry
->limit
- entry
->base
+ 1));
2120 if (!range_is_empty(pci_hole64
)) {
2121 crs_replace_with_free_ranges(crs_range_set
.mem_64bit_ranges
,
2122 range_lob(pci_hole64
),
2123 range_upb(pci_hole64
));
2124 for (i
= 0; i
< crs_range_set
.mem_64bit_ranges
->len
; i
++) {
2125 entry
= g_ptr_array_index(crs_range_set
.mem_64bit_ranges
, i
);
2127 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
2129 AML_CACHEABLE
, AML_READ_WRITE
,
2130 0, entry
->base
, entry
->limit
,
2131 0, entry
->limit
- entry
->base
+ 1));
2135 if (misc
->tpm_version
!= TPM_VERSION_UNSPEC
) {
2136 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
2137 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
2139 aml_append(scope
, aml_name_decl("_CRS", crs
));
2141 /* reserve GPE0 block resources */
2142 dev
= aml_device("GPE0");
2143 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
2144 aml_append(dev
, aml_name_decl("_UID", aml_string("GPE0 resources")));
2145 /* device present, functioning, decoding, not shown in UI */
2146 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2147 crs
= aml_resource_template();
2149 aml_io(AML_DECODE16
, pm
->gpe0_blk
, pm
->gpe0_blk
, 1, pm
->gpe0_blk_len
)
2151 aml_append(dev
, aml_name_decl("_CRS", crs
));
2152 aml_append(scope
, dev
);
2154 crs_range_set_free(&crs_range_set
);
2156 /* reserve PCIHP resources */
2157 if (pm
->pcihp_io_len
) {
2158 dev
= aml_device("PHPR");
2159 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
2161 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2162 /* device present, functioning, decoding, not shown in UI */
2163 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2164 crs
= aml_resource_template();
2166 aml_io(AML_DECODE16
, pm
->pcihp_io_base
, pm
->pcihp_io_base
, 1,
2169 aml_append(dev
, aml_name_decl("_CRS", crs
));
2170 aml_append(scope
, dev
);
2172 aml_append(dsdt
, scope
);
2174 /* create S3_ / S4_ / S5_ packages if necessary */
2175 scope
= aml_scope("\\");
2176 if (!pm
->s3_disabled
) {
2177 pkg
= aml_package(4);
2178 aml_append(pkg
, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2179 aml_append(pkg
, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2180 aml_append(pkg
, aml_int(0)); /* reserved */
2181 aml_append(pkg
, aml_int(0)); /* reserved */
2182 aml_append(scope
, aml_name_decl("_S3", pkg
));
2185 if (!pm
->s4_disabled
) {
2186 pkg
= aml_package(4);
2187 aml_append(pkg
, aml_int(pm
->s4_val
)); /* PM1a_CNT.SLP_TYP */
2188 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2189 aml_append(pkg
, aml_int(pm
->s4_val
));
2190 aml_append(pkg
, aml_int(0)); /* reserved */
2191 aml_append(pkg
, aml_int(0)); /* reserved */
2192 aml_append(scope
, aml_name_decl("_S4", pkg
));
2195 pkg
= aml_package(4);
2196 aml_append(pkg
, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2197 aml_append(pkg
, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2198 aml_append(pkg
, aml_int(0)); /* reserved */
2199 aml_append(pkg
, aml_int(0)); /* reserved */
2200 aml_append(scope
, aml_name_decl("_S5", pkg
));
2201 aml_append(dsdt
, scope
);
2203 /* create fw_cfg node, unconditionally */
2205 /* when using port i/o, the 8-bit data register *always* overlaps
2206 * with half of the 16-bit control register. Hence, the total size
2207 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2208 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2209 uint8_t io_size
= object_property_get_bool(OBJECT(pcms
->fw_cfg
),
2210 "dma_enabled", NULL
) ?
2211 ROUND_UP(FW_CFG_CTL_SIZE
, 4) + sizeof(dma_addr_t
) :
2214 scope
= aml_scope("\\_SB.PCI0");
2215 dev
= aml_device("FWCF");
2217 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0002")));
2219 /* device present, functioning, decoding, not shown in UI */
2220 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2222 crs
= aml_resource_template();
2224 aml_io(AML_DECODE16
, FW_CFG_IO_BASE
, FW_CFG_IO_BASE
, 0x01, io_size
)
2226 aml_append(dev
, aml_name_decl("_CRS", crs
));
2228 aml_append(scope
, dev
);
2229 aml_append(dsdt
, scope
);
2232 if (misc
->applesmc_io_base
) {
2233 scope
= aml_scope("\\_SB.PCI0.ISA");
2234 dev
= aml_device("SMC");
2236 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("APP0001")));
2237 /* device present, functioning, decoding, not shown in UI */
2238 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2240 crs
= aml_resource_template();
2242 aml_io(AML_DECODE16
, misc
->applesmc_io_base
, misc
->applesmc_io_base
,
2243 0x01, APPLESMC_MAX_DATA_LENGTH
)
2245 aml_append(crs
, aml_irq_no_flags(6));
2246 aml_append(dev
, aml_name_decl("_CRS", crs
));
2248 aml_append(scope
, dev
);
2249 aml_append(dsdt
, scope
);
2252 if (misc
->pvpanic_port
) {
2253 scope
= aml_scope("\\_SB.PCI0.ISA");
2255 dev
= aml_device("PEVT");
2256 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0001")));
2258 crs
= aml_resource_template();
2260 aml_io(AML_DECODE16
, misc
->pvpanic_port
, misc
->pvpanic_port
, 1, 1)
2262 aml_append(dev
, aml_name_decl("_CRS", crs
));
2264 aml_append(dev
, aml_operation_region("PEOR", AML_SYSTEM_IO
,
2265 aml_int(misc
->pvpanic_port
), 1));
2266 field
= aml_field("PEOR", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
2267 aml_append(field
, aml_named_field("PEPT", 8));
2268 aml_append(dev
, field
);
2270 /* device present, functioning, decoding, shown in UI */
2271 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
2273 method
= aml_method("RDPT", 0, AML_NOTSERIALIZED
);
2274 aml_append(method
, aml_store(aml_name("PEPT"), aml_local(0)));
2275 aml_append(method
, aml_return(aml_local(0)));
2276 aml_append(dev
, method
);
2278 method
= aml_method("WRPT", 1, AML_NOTSERIALIZED
);
2279 aml_append(method
, aml_store(aml_arg(0), aml_name("PEPT")));
2280 aml_append(dev
, method
);
2282 aml_append(scope
, dev
);
2283 aml_append(dsdt
, scope
);
2286 sb_scope
= aml_scope("\\_SB");
2288 build_memory_devices(sb_scope
, nr_mem
, pm
->mem_hp_io_base
,
2295 pci_host
= acpi_get_i386_pci_host();
2297 bus
= PCI_HOST_BRIDGE(pci_host
)->bus
;
2301 Aml
*scope
= aml_scope("PCI0");
2302 /* Scan all PCI buses. Generate tables to support hotplug. */
2303 build_append_pci_bus_devices(scope
, bus
, pm
->pcihp_bridge_en
);
2305 if (misc
->tpm_version
!= TPM_VERSION_UNSPEC
) {
2306 dev
= aml_device("ISA.TPM");
2307 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2308 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
2309 crs
= aml_resource_template();
2310 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
2311 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
2313 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2314 Rewrite to take IRQ from TPM device model and
2315 fix default IRQ value there to use some unused IRQ
2317 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2318 aml_append(dev
, aml_name_decl("_CRS", crs
));
2319 aml_append(scope
, dev
);
2322 aml_append(sb_scope
, scope
);
2325 aml_append(dsdt
, sb_scope
);
2328 /* copy AML table into ACPI tables blob and patch header there */
2329 g_array_append_vals(table_data
, dsdt
->buf
->data
, dsdt
->buf
->len
);
2330 build_header(linker
, table_data
,
2331 (void *)(table_data
->data
+ table_data
->len
- dsdt
->buf
->len
),
2332 "DSDT", dsdt
->buf
->len
, 1, NULL
, NULL
);
2333 free_aml_allocator();
2337 build_hpet(GArray
*table_data
, BIOSLinker
*linker
)
2341 hpet
= acpi_data_push(table_data
, sizeof(*hpet
));
2342 /* Note timer_block_id value must be kept in sync with value advertised by
2345 hpet
->timer_block_id
= cpu_to_le32(0x8086a201);
2346 hpet
->addr
.address
= cpu_to_le64(HPET_BASE
);
2347 build_header(linker
, table_data
,
2348 (void *)hpet
, "HPET", sizeof(*hpet
), 1, NULL
, NULL
);
2352 build_tpm_tcpa(GArray
*table_data
, BIOSLinker
*linker
, GArray
*tcpalog
)
2354 Acpi20Tcpa
*tcpa
= acpi_data_push(table_data
, sizeof *tcpa
);
2355 unsigned log_addr_size
= sizeof(tcpa
->log_area_start_address
);
2356 unsigned log_addr_offset
=
2357 (char *)&tcpa
->log_area_start_address
- table_data
->data
;
2359 tcpa
->platform_class
= cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT
);
2360 tcpa
->log_area_minimum_length
= cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE
);
2361 acpi_data_push(tcpalog
, le32_to_cpu(tcpa
->log_area_minimum_length
));
2363 bios_linker_loader_alloc(linker
, ACPI_BUILD_TPMLOG_FILE
, tcpalog
, 1,
2364 false /* high memory */);
2366 /* log area start address to be filled by Guest linker */
2367 bios_linker_loader_add_pointer(linker
,
2368 ACPI_BUILD_TABLE_FILE
, log_addr_offset
, log_addr_size
,
2369 ACPI_BUILD_TPMLOG_FILE
, 0);
2371 build_header(linker
, table_data
,
2372 (void *)tcpa
, "TCPA", sizeof(*tcpa
), 2, NULL
, NULL
);
2376 build_tpm2(GArray
*table_data
, BIOSLinker
*linker
)
2378 Acpi20TPM2
*tpm2_ptr
;
2380 tpm2_ptr
= acpi_data_push(table_data
, sizeof *tpm2_ptr
);
2382 tpm2_ptr
->platform_class
= cpu_to_le16(TPM2_ACPI_CLASS_CLIENT
);
2383 tpm2_ptr
->control_area_address
= cpu_to_le64(0);
2384 tpm2_ptr
->start_method
= cpu_to_le32(TPM2_START_METHOD_MMIO
);
2386 build_header(linker
, table_data
,
2387 (void *)tpm2_ptr
, "TPM2", sizeof(*tpm2_ptr
), 4, NULL
, NULL
);
2391 build_srat(GArray
*table_data
, BIOSLinker
*linker
, MachineState
*machine
)
2393 AcpiSystemResourceAffinityTable
*srat
;
2394 AcpiSratProcessorAffinity
*core
;
2395 AcpiSratMemoryAffinity
*numamem
;
2398 int srat_start
, numa_start
, slots
;
2399 uint64_t mem_len
, mem_base
, next_base
;
2400 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2401 CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(machine
);
2402 PCMachineState
*pcms
= PC_MACHINE(machine
);
2403 ram_addr_t hotplugabble_address_space_size
=
2404 object_property_get_int(OBJECT(pcms
), PC_MACHINE_MEMHP_REGION_SIZE
,
2407 srat_start
= table_data
->len
;
2409 srat
= acpi_data_push(table_data
, sizeof *srat
);
2410 srat
->reserved1
= cpu_to_le32(1);
2412 for (i
= 0; i
< apic_ids
->len
; i
++) {
2414 int apic_id
= apic_ids
->cpus
[i
].arch_id
;
2416 core
= acpi_data_push(table_data
, sizeof *core
);
2417 core
->type
= ACPI_SRAT_PROCESSOR_APIC
;
2418 core
->length
= sizeof(*core
);
2419 core
->local_apic_id
= apic_id
;
2420 for (j
= 0; j
< nb_numa_nodes
; j
++) {
2421 if (test_bit(i
, numa_info
[j
].node_cpu
)) {
2422 core
->proximity_lo
= j
;
2426 memset(core
->proximity_hi
, 0, 3);
2427 core
->local_sapic_eid
= 0;
2428 core
->flags
= cpu_to_le32(1);
2432 /* the memory map is a bit tricky, it contains at least one hole
2433 * from 640k-1M and possibly another one from 3.5G-4G.
2436 numa_start
= table_data
->len
;
2438 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2439 build_srat_memory(numamem
, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED
);
2440 next_base
= 1024 * 1024;
2441 for (i
= 1; i
< pcms
->numa_nodes
+ 1; ++i
) {
2442 mem_base
= next_base
;
2443 mem_len
= pcms
->node_mem
[i
- 1];
2445 mem_len
-= 1024 * 1024;
2447 next_base
= mem_base
+ mem_len
;
2449 /* Cut out the ACPI_PCI hole */
2450 if (mem_base
<= pcms
->below_4g_mem_size
&&
2451 next_base
> pcms
->below_4g_mem_size
) {
2452 mem_len
-= next_base
- pcms
->below_4g_mem_size
;
2454 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2455 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2456 MEM_AFFINITY_ENABLED
);
2458 mem_base
= 1ULL << 32;
2459 mem_len
= next_base
- pcms
->below_4g_mem_size
;
2460 next_base
+= (1ULL << 32) - pcms
->below_4g_mem_size
;
2462 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2463 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2464 MEM_AFFINITY_ENABLED
);
2466 slots
= (table_data
->len
- numa_start
) / sizeof *numamem
;
2467 for (; slots
< pcms
->numa_nodes
+ 2; slots
++) {
2468 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2469 build_srat_memory(numamem
, 0, 0, 0, MEM_AFFINITY_NOFLAGS
);
2473 * Entry is required for Windows to enable memory hotplug in OS.
2474 * Memory devices may override proximity set by this entry,
2475 * providing _PXM method if necessary.
2477 if (hotplugabble_address_space_size
) {
2478 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2479 build_srat_memory(numamem
, pcms
->hotplug_memory
.base
,
2480 hotplugabble_address_space_size
, 0,
2481 MEM_AFFINITY_HOTPLUGGABLE
| MEM_AFFINITY_ENABLED
);
2484 build_header(linker
, table_data
,
2485 (void *)(table_data
->data
+ srat_start
),
2487 table_data
->len
- srat_start
, 1, NULL
, NULL
);
2492 build_mcfg_q35(GArray
*table_data
, BIOSLinker
*linker
, AcpiMcfgInfo
*info
)
2494 AcpiTableMcfg
*mcfg
;
2496 int len
= sizeof(*mcfg
) + 1 * sizeof(mcfg
->allocation
[0]);
2498 mcfg
= acpi_data_push(table_data
, len
);
2499 mcfg
->allocation
[0].address
= cpu_to_le64(info
->mcfg_base
);
2500 /* Only a single allocation so no need to play with segments */
2501 mcfg
->allocation
[0].pci_segment
= cpu_to_le16(0);
2502 mcfg
->allocation
[0].start_bus_number
= 0;
2503 mcfg
->allocation
[0].end_bus_number
= PCIE_MMCFG_BUS(info
->mcfg_size
- 1);
2505 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2506 * To avoid table size changes (which create migration issues),
2507 * always create the table even if there are no allocations,
2508 * but set the signature to a reserved value in this case.
2509 * ACPI spec requires OSPMs to ignore such tables.
2511 if (info
->mcfg_base
== PCIE_BASE_ADDR_UNMAPPED
) {
2512 /* Reserved signature: ignored by OSPM */
2517 build_header(linker
, table_data
, (void *)mcfg
, sig
, len
, 1, NULL
, NULL
);
2521 * VT-d spec 8.1 DMA Remapping Reporting Structure
2522 * (version Oct. 2014 or later)
2525 build_dmar_q35(GArray
*table_data
, BIOSLinker
*linker
)
2527 int dmar_start
= table_data
->len
;
2529 AcpiTableDmar
*dmar
;
2530 AcpiDmarHardwareUnit
*drhd
;
2531 uint8_t dmar_flags
= 0;
2532 X86IOMMUState
*iommu
= x86_iommu_get_default();
2533 AcpiDmarDeviceScope
*scope
= NULL
;
2534 /* Root complex IOAPIC use one path[0] only */
2535 size_t ioapic_scope_size
= sizeof(*scope
) + sizeof(scope
->path
[0]);
2538 if (iommu
->intr_supported
) {
2539 dmar_flags
|= 0x1; /* Flags: 0x1: INT_REMAP */
2542 dmar
= acpi_data_push(table_data
, sizeof(*dmar
));
2543 dmar
->host_address_width
= VTD_HOST_ADDRESS_WIDTH
- 1;
2544 dmar
->flags
= dmar_flags
;
2546 /* DMAR Remapping Hardware Unit Definition structure */
2547 drhd
= acpi_data_push(table_data
, sizeof(*drhd
) + ioapic_scope_size
);
2548 drhd
->type
= cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT
);
2549 drhd
->length
= cpu_to_le16(sizeof(*drhd
) + ioapic_scope_size
);
2550 drhd
->flags
= ACPI_DMAR_INCLUDE_PCI_ALL
;
2551 drhd
->pci_segment
= cpu_to_le16(0);
2552 drhd
->address
= cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR
);
2554 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2555 * 8.3.1 (version Oct. 2014 or later). */
2556 scope
= &drhd
->scope
[0];
2557 scope
->entry_type
= 0x03; /* Type: 0x03 for IOAPIC */
2558 scope
->length
= ioapic_scope_size
;
2559 scope
->enumeration_id
= ACPI_BUILD_IOAPIC_ID
;
2560 scope
->bus
= Q35_PSEUDO_BUS_PLATFORM
;
2561 scope
->path
[0] = cpu_to_le16(Q35_PSEUDO_DEVFN_IOAPIC
);
2563 build_header(linker
, table_data
, (void *)(table_data
->data
+ dmar_start
),
2564 "DMAR", table_data
->len
- dmar_start
, 1, NULL
, NULL
);
2567 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2568 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2571 build_amd_iommu(GArray
*table_data
, BIOSLinker
*linker
)
2573 int iommu_start
= table_data
->len
;
2574 AMDVIState
*s
= AMD_IOMMU_DEVICE(x86_iommu_get_default());
2577 acpi_data_push(table_data
, sizeof(AcpiTableHeader
));
2578 /* IVinfo - IO virtualization information common to all
2579 * IOMMU units in a system
2581 build_append_int_noprefix(table_data
, 40UL << 8/* PASize */, 4);
2583 build_append_int_noprefix(table_data
, 0, 8);
2585 /* IVHD definition - type 10h */
2586 build_append_int_noprefix(table_data
, 0x10, 1);
2587 /* virtualization flags */
2588 build_append_int_noprefix(table_data
,
2589 (1UL << 0) | /* HtTunEn */
2590 (1UL << 4) | /* iotblSup */
2591 (1UL << 6) | /* PrefSup */
2592 (1UL << 7), /* PPRSup */
2595 build_append_int_noprefix(table_data
, 0x24, 2);
2597 build_append_int_noprefix(table_data
, s
->devid
, 2);
2598 /* Capability offset */
2599 build_append_int_noprefix(table_data
, s
->capab_offset
, 2);
2600 /* IOMMU base address */
2601 build_append_int_noprefix(table_data
, s
->mmio
.addr
, 8);
2602 /* PCI Segment Group */
2603 build_append_int_noprefix(table_data
, 0, 2);
2605 build_append_int_noprefix(table_data
, 0, 2);
2606 /* IOMMU Feature Reporting */
2607 build_append_int_noprefix(table_data
,
2608 (48UL << 30) | /* HATS */
2609 (48UL << 28) | /* GATS */
2610 (1UL << 2), /* GTSup */
2613 * Type 1 device entry reporting all devices
2614 * These are 4-byte device entries currently reporting the range of
2615 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2617 build_append_int_noprefix(table_data
, 0x0000001, 4);
2619 build_header(linker
, table_data
, (void *)(table_data
->data
+ iommu_start
),
2620 "IVRS", table_data
->len
- iommu_start
, 1, NULL
, NULL
);
2624 build_rsdp(GArray
*rsdp_table
, BIOSLinker
*linker
, unsigned rsdt_tbl_offset
)
2626 AcpiRsdpDescriptor
*rsdp
= acpi_data_push(rsdp_table
, sizeof *rsdp
);
2627 unsigned rsdt_pa_size
= sizeof(rsdp
->rsdt_physical_address
);
2628 unsigned rsdt_pa_offset
=
2629 (char *)&rsdp
->rsdt_physical_address
- rsdp_table
->data
;
2631 bios_linker_loader_alloc(linker
, ACPI_BUILD_RSDP_FILE
, rsdp_table
, 16,
2632 true /* fseg memory */);
2634 memcpy(&rsdp
->signature
, "RSD PTR ", 8);
2635 memcpy(rsdp
->oem_id
, ACPI_BUILD_APPNAME6
, 6);
2636 /* Address to be filled by Guest linker */
2637 bios_linker_loader_add_pointer(linker
,
2638 ACPI_BUILD_RSDP_FILE
, rsdt_pa_offset
, rsdt_pa_size
,
2639 ACPI_BUILD_TABLE_FILE
, rsdt_tbl_offset
);
2641 /* Checksum to be filled by Guest linker */
2642 bios_linker_loader_add_checksum(linker
, ACPI_BUILD_RSDP_FILE
,
2643 (char *)rsdp
- rsdp_table
->data
, sizeof *rsdp
,
2644 (char *)&rsdp
->checksum
- rsdp_table
->data
);
2650 struct AcpiBuildState
{
2651 /* Copy of table in RAM (for patching). */
2652 MemoryRegion
*table_mr
;
2653 /* Is table patched? */
2656 MemoryRegion
*rsdp_mr
;
2657 MemoryRegion
*linker_mr
;
2660 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
)
2665 pci_host
= acpi_get_i386_pci_host();
2668 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_BASE
, NULL
);
2672 mcfg
->mcfg_base
= qint_get_int(qobject_to_qint(o
));
2675 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_SIZE
, NULL
);
2677 mcfg
->mcfg_size
= qint_get_int(qobject_to_qint(o
));
2683 void acpi_build(AcpiBuildTables
*tables
, MachineState
*machine
)
2685 PCMachineState
*pcms
= PC_MACHINE(machine
);
2686 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2687 GArray
*table_offsets
;
2688 unsigned facs
, dsdt
, rsdt
, fadt
;
2692 Range pci_hole
, pci_hole64
;
2695 GArray
*tables_blob
= tables
->table_data
;
2696 AcpiSlicOem slic_oem
= { .id
= NULL
, .table_id
= NULL
};
2698 acpi_get_pm_info(&pm
);
2699 acpi_get_misc_info(&misc
);
2700 acpi_get_pci_holes(&pci_hole
, &pci_hole64
);
2701 acpi_get_slic_oem(&slic_oem
);
2703 table_offsets
= g_array_new(false, true /* clear */,
2705 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2707 bios_linker_loader_alloc(tables
->linker
,
2708 ACPI_BUILD_TABLE_FILE
, tables_blob
,
2709 64 /* Ensure FACS is aligned */,
2710 false /* high memory */);
2713 * FACS is pointed to by FADT.
2714 * We place it first since it's the only table that has alignment
2717 facs
= tables_blob
->len
;
2718 build_facs(tables_blob
, tables
->linker
);
2720 /* DSDT is pointed to by FADT */
2721 dsdt
= tables_blob
->len
;
2722 build_dsdt(tables_blob
, tables
->linker
, &pm
, &misc
,
2723 &pci_hole
, &pci_hole64
, machine
);
2725 /* Count the size of the DSDT and SSDT, we will need it for legacy
2726 * sizing of ACPI tables.
2728 aml_len
+= tables_blob
->len
- dsdt
;
2730 /* ACPI tables pointed to by RSDT */
2731 fadt
= tables_blob
->len
;
2732 acpi_add_table(table_offsets
, tables_blob
);
2733 build_fadt(tables_blob
, tables
->linker
, &pm
, facs
, dsdt
,
2734 slic_oem
.id
, slic_oem
.table_id
);
2735 aml_len
+= tables_blob
->len
- fadt
;
2737 acpi_add_table(table_offsets
, tables_blob
);
2738 build_madt(tables_blob
, tables
->linker
, pcms
);
2740 if (misc
.has_hpet
) {
2741 acpi_add_table(table_offsets
, tables_blob
);
2742 build_hpet(tables_blob
, tables
->linker
);
2744 if (misc
.tpm_version
!= TPM_VERSION_UNSPEC
) {
2745 acpi_add_table(table_offsets
, tables_blob
);
2746 build_tpm_tcpa(tables_blob
, tables
->linker
, tables
->tcpalog
);
2748 if (misc
.tpm_version
== TPM_VERSION_2_0
) {
2749 acpi_add_table(table_offsets
, tables_blob
);
2750 build_tpm2(tables_blob
, tables
->linker
);
2753 if (pcms
->numa_nodes
) {
2754 acpi_add_table(table_offsets
, tables_blob
);
2755 build_srat(tables_blob
, tables
->linker
, machine
);
2757 if (acpi_get_mcfg(&mcfg
)) {
2758 acpi_add_table(table_offsets
, tables_blob
);
2759 build_mcfg_q35(tables_blob
, tables
->linker
, &mcfg
);
2761 if (x86_iommu_get_default()) {
2762 IommuType IOMMUType
= x86_iommu_get_type();
2763 if (IOMMUType
== TYPE_AMD
) {
2764 acpi_add_table(table_offsets
, tables_blob
);
2765 build_amd_iommu(tables_blob
, tables
->linker
);
2766 } else if (IOMMUType
== TYPE_INTEL
) {
2767 acpi_add_table(table_offsets
, tables_blob
);
2768 build_dmar_q35(tables_blob
, tables
->linker
);
2771 if (pcms
->acpi_nvdimm_state
.is_enabled
) {
2772 nvdimm_build_acpi(table_offsets
, tables_blob
, tables
->linker
,
2773 pcms
->acpi_nvdimm_state
.dsm_mem
);
2776 /* Add tables supplied by user (if any) */
2777 for (u
= acpi_table_first(); u
; u
= acpi_table_next(u
)) {
2778 unsigned len
= acpi_table_len(u
);
2780 acpi_add_table(table_offsets
, tables_blob
);
2781 g_array_append_vals(tables_blob
, u
, len
);
2784 /* RSDT is pointed to by RSDP */
2785 rsdt
= tables_blob
->len
;
2786 build_rsdt(tables_blob
, tables
->linker
, table_offsets
,
2787 slic_oem
.id
, slic_oem
.table_id
);
2789 /* RSDP is in FSEG memory, so allocate it separately */
2790 build_rsdp(tables
->rsdp
, tables
->linker
, rsdt
);
2792 /* We'll expose it all to Guest so we want to reduce
2793 * chance of size changes.
2795 * We used to align the tables to 4k, but of course this would
2796 * too simple to be enough. 4k turned out to be too small an
2797 * alignment very soon, and in fact it is almost impossible to
2798 * keep the table size stable for all (max_cpus, max_memory_slots)
2799 * combinations. So the table size is always 64k for pc-i440fx-2.1
2800 * and we give an error if the table grows beyond that limit.
2802 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2803 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2804 * than 2.0 and we can always pad the smaller tables with zeros. We can
2805 * then use the exact size of the 2.0 tables.
2807 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2809 if (pcmc
->legacy_acpi_table_size
) {
2810 /* Subtracting aml_len gives the size of fixed tables. Then add the
2811 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2813 int legacy_aml_len
=
2814 pcmc
->legacy_acpi_table_size
+
2815 ACPI_BUILD_LEGACY_CPU_AML_SIZE
* max_cpus
;
2816 int legacy_table_size
=
2817 ROUND_UP(tables_blob
->len
- aml_len
+ legacy_aml_len
,
2818 ACPI_BUILD_ALIGN_SIZE
);
2819 if (tables_blob
->len
> legacy_table_size
) {
2820 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2821 error_report("Warning: migration may not work.");
2823 g_array_set_size(tables_blob
, legacy_table_size
);
2825 /* Make sure we have a buffer in case we need to resize the tables. */
2826 if (tables_blob
->len
> ACPI_BUILD_TABLE_SIZE
/ 2) {
2827 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2828 error_report("Warning: ACPI tables are larger than 64k.");
2829 error_report("Warning: migration may not work.");
2830 error_report("Warning: please remove CPUs, NUMA nodes, "
2831 "memory slots or PCI bridges.");
2833 acpi_align_size(tables_blob
, ACPI_BUILD_TABLE_SIZE
);
2836 acpi_align_size(tables
->linker
->cmd_blob
, ACPI_BUILD_ALIGN_SIZE
);
2838 /* Cleanup memory that's no longer used. */
2839 g_array_free(table_offsets
, true);
2842 static void acpi_ram_update(MemoryRegion
*mr
, GArray
*data
)
2844 uint32_t size
= acpi_data_len(data
);
2846 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2847 memory_region_ram_resize(mr
, size
, &error_abort
);
2849 memcpy(memory_region_get_ram_ptr(mr
), data
->data
, size
);
2850 memory_region_set_dirty(mr
, 0, size
);
2853 static void acpi_build_update(void *build_opaque
)
2855 AcpiBuildState
*build_state
= build_opaque
;
2856 AcpiBuildTables tables
;
2858 /* No state to update or already patched? Nothing to do. */
2859 if (!build_state
|| build_state
->patched
) {
2862 build_state
->patched
= 1;
2864 acpi_build_tables_init(&tables
);
2866 acpi_build(&tables
, MACHINE(qdev_get_machine()));
2868 acpi_ram_update(build_state
->table_mr
, tables
.table_data
);
2870 if (build_state
->rsdp
) {
2871 memcpy(build_state
->rsdp
, tables
.rsdp
->data
, acpi_data_len(tables
.rsdp
));
2873 acpi_ram_update(build_state
->rsdp_mr
, tables
.rsdp
);
2876 acpi_ram_update(build_state
->linker_mr
, tables
.linker
->cmd_blob
);
2877 acpi_build_tables_cleanup(&tables
, true);
2880 static void acpi_build_reset(void *build_opaque
)
2882 AcpiBuildState
*build_state
= build_opaque
;
2883 build_state
->patched
= 0;
2886 static MemoryRegion
*acpi_add_rom_blob(AcpiBuildState
*build_state
,
2887 GArray
*blob
, const char *name
,
2890 return rom_add_blob(name
, blob
->data
, acpi_data_len(blob
), max_size
, -1,
2891 name
, acpi_build_update
, build_state
);
2894 static const VMStateDescription vmstate_acpi_build
= {
2895 .name
= "acpi_build",
2897 .minimum_version_id
= 1,
2898 .fields
= (VMStateField
[]) {
2899 VMSTATE_UINT8(patched
, AcpiBuildState
),
2900 VMSTATE_END_OF_LIST()
2904 void acpi_setup(void)
2906 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
2907 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2908 AcpiBuildTables tables
;
2909 AcpiBuildState
*build_state
;
2911 if (!pcms
->fw_cfg
) {
2912 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2916 if (!pcmc
->has_acpi_build
) {
2917 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2921 if (!acpi_enabled
) {
2922 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2926 build_state
= g_malloc0(sizeof *build_state
);
2928 acpi_set_pci_info();
2930 acpi_build_tables_init(&tables
);
2931 acpi_build(&tables
, MACHINE(pcms
));
2933 /* Now expose it all to Guest */
2934 build_state
->table_mr
= acpi_add_rom_blob(build_state
, tables
.table_data
,
2935 ACPI_BUILD_TABLE_FILE
,
2936 ACPI_BUILD_TABLE_MAX_SIZE
);
2937 assert(build_state
->table_mr
!= NULL
);
2939 build_state
->linker_mr
=
2940 acpi_add_rom_blob(build_state
, tables
.linker
->cmd_blob
,
2941 "etc/table-loader", 0);
2943 fw_cfg_add_file(pcms
->fw_cfg
, ACPI_BUILD_TPMLOG_FILE
,
2944 tables
.tcpalog
->data
, acpi_data_len(tables
.tcpalog
));
2946 if (!pcmc
->rsdp_in_ram
) {
2948 * Keep for compatibility with old machine types.
2949 * Though RSDP is small, its contents isn't immutable, so
2950 * we'll update it along with the rest of tables on guest access.
2952 uint32_t rsdp_size
= acpi_data_len(tables
.rsdp
);
2954 build_state
->rsdp
= g_memdup(tables
.rsdp
->data
, rsdp_size
);
2955 fw_cfg_add_file_callback(pcms
->fw_cfg
, ACPI_BUILD_RSDP_FILE
,
2956 acpi_build_update
, build_state
,
2957 build_state
->rsdp
, rsdp_size
);
2958 build_state
->rsdp_mr
= NULL
;
2960 build_state
->rsdp
= NULL
;
2961 build_state
->rsdp_mr
= acpi_add_rom_blob(build_state
, tables
.rsdp
,
2962 ACPI_BUILD_RSDP_FILE
, 0);
2965 qemu_register_reset(acpi_build_reset
, build_state
);
2966 acpi_build_reset(build_state
);
2967 vmstate_register(NULL
, 0, &vmstate_acpi_build
, build_state
);
2969 /* Cleanup tables but don't free the memory: we track it
2972 acpi_build_tables_cleanup(&tables
, false);