]> git.proxmox.com Git - mirror_qemu.git/blob - hw/i386/acpi-build.c
projects / mirror_qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
pc: acpi: use build_append_foo() API to construct FADT
[mirror_qemu.git] / hw / i386 / acpi-build.c
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "qemu-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "qom/cpu.h"
32 #include "target/i386/cpu.h"
33 #include "hw/misc/pvpanic.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/loader.h"
41 #include "hw/isa/isa.h"
42 #include "hw/block/fdc.h"
43 #include "hw/acpi/memory_hotplug.h"
44 #include "sysemu/tpm.h"
45 #include "hw/acpi/tpm.h"
46 #include "hw/acpi/vmgenid.h"
47 #include "sysemu/tpm_backend.h"
48 #include "hw/timer/mc146818rtc_regs.h"
49 #include "sysemu/numa.h"
50
51 /* Supported chipsets: */
52 #include "hw/acpi/piix4.h"
53 #include "hw/acpi/pcihp.h"
54 #include "hw/i386/ich9.h"
55 #include "hw/pci/pci_bus.h"
56 #include "hw/pci-host/q35.h"
57 #include "hw/i386/x86-iommu.h"
58
59 #include "hw/acpi/aml-build.h"
60
61 #include "qom/qom-qobject.h"
62 #include "hw/i386/amd_iommu.h"
63 #include "hw/i386/intel_iommu.h"
64
65 #include "hw/acpi/ipmi.h"
66
67 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
68 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
69 * a little bit, there should be plenty of free space since the DSDT
70 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
71 */
72 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
73 #define ACPI_BUILD_ALIGN_SIZE 0x1000
74
75 #define ACPI_BUILD_TABLE_SIZE 0x20000
76
77 /* #define DEBUG_ACPI_BUILD */
78 #ifdef DEBUG_ACPI_BUILD
79 #define ACPI_BUILD_DPRINTF(fmt, ...) \
80 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
81 #else
82 #define ACPI_BUILD_DPRINTF(fmt, ...)
83 #endif
84
85 /* Default IOAPIC ID */
86 #define ACPI_BUILD_IOAPIC_ID 0x0
87
88 typedef struct AcpiMcfgInfo {
89 uint64_t mcfg_base;
90 uint32_t mcfg_size;
91 } AcpiMcfgInfo;
92
93 typedef struct AcpiPmInfo {
94 bool s3_disabled;
95 bool s4_disabled;
96 bool pcihp_bridge_en;
97 uint8_t s4_val;
98 AcpiFadtData fadt;
99 uint16_t cpu_hp_io_base;
100 uint16_t pcihp_io_base;
101 uint16_t pcihp_io_len;
102 } AcpiPmInfo;
103
104 typedef struct AcpiMiscInfo {
105 bool is_piix4;
106 bool has_hpet;
107 TPMVersion tpm_version;
108 const unsigned char *dsdt_code;
109 unsigned dsdt_size;
110 uint16_t pvpanic_port;
111 uint16_t applesmc_io_base;
112 } AcpiMiscInfo;
113
114 typedef struct AcpiBuildPciBusHotplugState {
115 GArray *device_table;
116 GArray *notify_table;
117 struct AcpiBuildPciBusHotplugState *parent;
118 bool pcihp_bridge_en;
119 } AcpiBuildPciBusHotplugState;
120
121 static void init_common_fadt_data(Object *o, AcpiFadtData *data)
122 {
123 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
124 AmlAddressSpace as = AML_AS_SYSTEM_IO;
125 AcpiFadtData fadt = {
126 .rev = 3,
127 .flags =
128 (1 << ACPI_FADT_F_WBINVD) |
129 (1 << ACPI_FADT_F_PROC_C1) |
130 (1 << ACPI_FADT_F_SLP_BUTTON) |
131 (1 << ACPI_FADT_F_RTC_S4) |
132 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
133 /* APIC destination mode ("Flat Logical") has an upper limit of 8
134 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
135 * used
136 */
137 ((max_cpus > 8) ? (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
138 .int_model = 1 /* Multiple APIC */,
139 .rtc_century = RTC_CENTURY,
140 .plvl2_lat = 0xfff /* C2 state not supported */,
141 .plvl3_lat = 0xfff /* C3 state not supported */,
142 .smi_cmd = ACPI_PORT_SMI_CMD,
143 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
144 .acpi_enable_cmd =
145 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL),
146 .acpi_disable_cmd =
147 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL),
148 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
149 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
150 .address = io + 0x04 },
151 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
152 .gpe0_blk = { .space_id = as, .bit_width =
153 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
154 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
155 },
156 };
157 *data = fadt;
158 }
159
160 static void acpi_get_pm_info(AcpiPmInfo *pm)
161 {
162 Object *piix = piix4_pm_find();
163 Object *lpc = ich9_lpc_find();
164 Object *obj = piix ? piix : lpc;
165 QObject *o;
166 pm->cpu_hp_io_base = 0;
167 pm->pcihp_io_base = 0;
168 pm->pcihp_io_len = 0;
169
170 init_common_fadt_data(obj, &pm->fadt);
171 if (piix) {
172 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
173 pm->fadt.rev = 1;
174 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
175 pm->pcihp_io_base =
176 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
177 pm->pcihp_io_len =
178 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
179 }
180 if (lpc) {
181 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
182 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
183 pm->fadt.reset_reg = r;
184 pm->fadt.reset_val = 0xf;
185 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
186 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
187 }
188 assert(obj);
189
190 /* The above need not be conditional on machine type because the reset port
191 * happens to be the same on PIIX (pc) and ICH9 (q35). */
192 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);
193
194 /* Fill in optional s3/s4 related properties */
195 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
196 if (o) {
197 pm->s3_disabled = qnum_get_uint(qobject_to_qnum(o));
198 } else {
199 pm->s3_disabled = false;
200 }
201 qobject_decref(o);
202 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
203 if (o) {
204 pm->s4_disabled = qnum_get_uint(qobject_to_qnum(o));
205 } else {
206 pm->s4_disabled = false;
207 }
208 qobject_decref(o);
209 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
210 if (o) {
211 pm->s4_val = qnum_get_uint(qobject_to_qnum(o));
212 } else {
213 pm->s4_val = false;
214 }
215 qobject_decref(o);
216
217 pm->pcihp_bridge_en =
218 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
219 NULL);
220 }
221
222 static void acpi_get_misc_info(AcpiMiscInfo *info)
223 {
224 Object *piix = piix4_pm_find();
225 Object *lpc = ich9_lpc_find();
226 assert(!!piix != !!lpc);
227
228 if (piix) {
229 info->is_piix4 = true;
230 }
231 if (lpc) {
232 info->is_piix4 = false;
233 }
234
235 info->has_hpet = hpet_find();
236 info->tpm_version = tpm_get_version(tpm_find());
237 info->pvpanic_port = pvpanic_port();
238 info->applesmc_io_base = applesmc_port();
239 }
240
241 /*
242 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
243 * On i386 arch we only have two pci hosts, so we can look only for them.
244 */
245 static Object *acpi_get_i386_pci_host(void)
246 {
247 PCIHostState *host;
248
249 host = OBJECT_CHECK(PCIHostState,
250 object_resolve_path("/machine/i440fx", NULL),
251 TYPE_PCI_HOST_BRIDGE);
252 if (!host) {
253 host = OBJECT_CHECK(PCIHostState,
254 object_resolve_path("/machine/q35", NULL),
255 TYPE_PCI_HOST_BRIDGE);
256 }
257
258 return OBJECT(host);
259 }
260
261 static void acpi_get_pci_holes(Range *hole, Range *hole64)
262 {
263 Object *pci_host;
264
265 pci_host = acpi_get_i386_pci_host();
266 g_assert(pci_host);
267
268 range_set_bounds1(hole,
269 object_property_get_uint(pci_host,
270 PCI_HOST_PROP_PCI_HOLE_START,
271 NULL),
272 object_property_get_uint(pci_host,
273 PCI_HOST_PROP_PCI_HOLE_END,
274 NULL));
275 range_set_bounds1(hole64,
276 object_property_get_uint(pci_host,
277 PCI_HOST_PROP_PCI_HOLE64_START,
278 NULL),
279 object_property_get_uint(pci_host,
280 PCI_HOST_PROP_PCI_HOLE64_END,
281 NULL));
282 }
283
284 static void acpi_align_size(GArray *blob, unsigned align)
285 {
286 /* Align size to multiple of given size. This reduces the chance
287 * we need to change size in the future (breaking cross version migration).
288 */
289 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
290 }
291
292 /* FACS */
293 static void
294 build_facs(GArray *table_data, BIOSLinker *linker)
295 {
296 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
297 memcpy(&facs->signature, "FACS", 4);
298 facs->length = cpu_to_le32(sizeof(*facs));
299 }
300
301 /* FADT */
302 static void
303 build_fadt(GArray *tbl, BIOSLinker *linker, AcpiFadtData *f,
304 const char *oem_id, const char *oem_table_id)
305 {
306 int off;
307 int fadt_start = tbl->len;
308
309 acpi_data_push(tbl, sizeof(AcpiTableHeader));
310
311 /* FACS address to be filled by Guest linker at runtime */
312 off = tbl->len;
313 build_append_int_noprefix(tbl, 0, 4); /* FIRMWARE_CTRL */
314 bios_linker_loader_add_pointer(linker,
315 ACPI_BUILD_TABLE_FILE, off, 4,
316 ACPI_BUILD_TABLE_FILE, *f->facs_tbl_offset);
317
318 /* DSDT address to be filled by Guest linker at runtime */
319 off = tbl->len;
320 build_append_int_noprefix(tbl, 0, 4); /* DSDT */
321 bios_linker_loader_add_pointer(linker,
322 ACPI_BUILD_TABLE_FILE, off, 4,
323 ACPI_BUILD_TABLE_FILE, *f->dsdt_tbl_offset);
324
325 /* ACPI1.0: INT_MODEL, ACPI2.0+: Reserved */
326 build_append_int_noprefix(tbl, f->int_model /* Multiple APIC */, 1);
327 /* Preferred_PM_Profile */
328 build_append_int_noprefix(tbl, 0 /* Unspecified */, 1);
329 build_append_int_noprefix(tbl, f->sci_int, 2); /* SCI_INT */
330 build_append_int_noprefix(tbl, f->smi_cmd, 4); /* SMI_CMD */
331 build_append_int_noprefix(tbl, f->acpi_enable_cmd, 1); /* ACPI_ENABLE */
332 build_append_int_noprefix(tbl, f->acpi_disable_cmd, 1); /* ACPI_DISABLE */
333 build_append_int_noprefix(tbl, 0 /* not supported */, 1); /* S4BIOS_REQ */
334 /* ACPI1.0: Reserved, ACPI2.0+: PSTATE_CNT */
335 build_append_int_noprefix(tbl, 0, 1);
336 build_append_int_noprefix(tbl, f->pm1a_evt.address, 4); /* PM1a_EVT_BLK */
337 build_append_int_noprefix(tbl, 0, 4); /* PM1b_EVT_BLK */
338 build_append_int_noprefix(tbl, f->pm1a_cnt.address, 4); /* PM1a_CNT_BLK */
339 build_append_int_noprefix(tbl, 0, 4); /* PM1b_CNT_BLK */
340 build_append_int_noprefix(tbl, 0, 4); /* PM2_CNT_BLK */
341 build_append_int_noprefix(tbl, f->pm_tmr.address, 4); /* PM_TMR_BLK */
342 build_append_int_noprefix(tbl, f->gpe0_blk.address, 4); /* GPE0_BLK */
343 build_append_int_noprefix(tbl, 0, 4); /* GPE1_BLK */
344 /* PM1_EVT_LEN */
345 build_append_int_noprefix(tbl, f->pm1a_evt.bit_width / 8, 1);
346 /* PM1_CNT_LEN */
347 build_append_int_noprefix(tbl, f->pm1a_cnt.bit_width / 8, 1);
348 build_append_int_noprefix(tbl, 0, 1); /* PM2_CNT_LEN */
349 build_append_int_noprefix(tbl, f->pm_tmr.bit_width / 8, 1); /* PM_TMR_LEN */
350 /* GPE0_BLK_LEN */
351 build_append_int_noprefix(tbl, f->gpe0_blk.bit_width / 8, 1);
352 build_append_int_noprefix(tbl, 0, 1); /* GPE1_BLK_LEN */
353 build_append_int_noprefix(tbl, 0, 1); /* GPE1_BASE */
354 build_append_int_noprefix(tbl, 0, 1); /* CST_CNT */
355 build_append_int_noprefix(tbl, f->plvl2_lat, 2); /* P_LVL2_LAT */
356 build_append_int_noprefix(tbl, f->plvl3_lat, 2); /* P_LVL3_LAT */
357 build_append_int_noprefix(tbl, 0, 2); /* FLUSH_SIZE */
358 build_append_int_noprefix(tbl, 0, 2); /* FLUSH_STRIDE */
359 build_append_int_noprefix(tbl, 0, 1); /* DUTY_OFFSET */
360 build_append_int_noprefix(tbl, 0, 1); /* DUTY_WIDTH */
361 build_append_int_noprefix(tbl, 0, 1); /* DAY_ALRM */
362 build_append_int_noprefix(tbl, 0, 1); /* MON_ALRM */
363 build_append_int_noprefix(tbl, f->rtc_century, 1); /* CENTURY */
364 build_append_int_noprefix(tbl, 0, 2); /* IAPC_BOOT_ARCH */
365 build_append_int_noprefix(tbl, 0, 1); /* Reserved */
366 build_append_int_noprefix(tbl, f->flags, 4); /* Flags */
367
368 if (f->rev == 1) {
369 goto build_hdr;
370 }
371
372 build_append_gas_from_struct(tbl, &f->reset_reg); /* RESET_REG */
373 build_append_int_noprefix(tbl, f->reset_val, 1); /* RESET_VALUE */
374 build_append_int_noprefix(tbl, 0, 3); /* Reserved, ACPI 3.0 */
375 build_append_int_noprefix(tbl, 0, 8); /* X_FIRMWARE_CTRL */
376
377 /* XDSDT address to be filled by Guest linker at runtime */
378 off = tbl->len;
379 build_append_int_noprefix(tbl, 0, 8); /* X_DSDT */
380 if (f->xdsdt_tbl_offset) {
381 bios_linker_loader_add_pointer(linker,
382 ACPI_BUILD_TABLE_FILE, off, 8,
383 ACPI_BUILD_TABLE_FILE, *f->xdsdt_tbl_offset);
384 }
385
386 build_append_gas_from_struct(tbl, &f->pm1a_evt); /* X_PM1a_EVT_BLK */
387 /* X_PM1b_EVT_BLK */
388 build_append_gas(tbl, AML_AS_SYSTEM_MEMORY, 0 , 0, 0, 0);
389 build_append_gas_from_struct(tbl, &f->pm1a_cnt); /* X_PM1a_CNT_BLK */
390 /* X_PM1b_CNT_BLK */
391 build_append_gas(tbl, AML_AS_SYSTEM_MEMORY, 0 , 0, 0, 0);
392 /* X_PM2_CNT_BLK */
393 build_append_gas(tbl, AML_AS_SYSTEM_MEMORY, 0 , 0, 0, 0);
394 build_append_gas_from_struct(tbl, &f->pm_tmr); /* X_PM_TMR_BLK */
395 build_append_gas_from_struct(tbl, &f->gpe0_blk); /* X_GPE0_BLK */
396 build_append_gas(tbl, AML_AS_SYSTEM_MEMORY, 0 , 0, 0, 0); /* X_GPE1_BLK */
397
398 build_hdr:
399 build_header(linker, tbl, (void *)(tbl->data + fadt_start),
400 "FACP", tbl->len - fadt_start, f->rev, oem_id, oem_table_id);
401 }
402
403 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
404 const CPUArchIdList *apic_ids, GArray *entry)
405 {
406 uint32_t apic_id = apic_ids->cpus[uid].arch_id;
407
408 /* ACPI spec says that LAPIC entry for non present
409 * CPU may be omitted from MADT or it must be marked
410 * as disabled. However omitting non present CPU from
411 * MADT breaks hotplug on linux. So possible CPUs
412 * should be put in MADT but kept disabled.
413 */
414 if (apic_id < 255) {
415 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
416
417 apic->type = ACPI_APIC_PROCESSOR;
418 apic->length = sizeof(*apic);
419 apic->processor_id = uid;
420 apic->local_apic_id = apic_id;
421 if (apic_ids->cpus[uid].cpu != NULL) {
422 apic->flags = cpu_to_le32(1);
423 } else {
424 apic->flags = cpu_to_le32(0);
425 }
426 } else {
427 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic);
428
429 apic->type = ACPI_APIC_LOCAL_X2APIC;
430 apic->length = sizeof(*apic);
431 apic->uid = cpu_to_le32(uid);
432 apic->x2apic_id = cpu_to_le32(apic_id);
433 if (apic_ids->cpus[uid].cpu != NULL) {
434 apic->flags = cpu_to_le32(1);
435 } else {
436 apic->flags = cpu_to_le32(0);
437 }
438 }
439 }
440
441 static void
442 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
443 {
444 MachineClass *mc = MACHINE_GET_CLASS(pcms);
445 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
446 int madt_start = table_data->len;
447 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
448 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
449 bool x2apic_mode = false;
450
451 AcpiMultipleApicTable *madt;
452 AcpiMadtIoApic *io_apic;
453 AcpiMadtIntsrcovr *intsrcovr;
454 int i;
455
456 madt = acpi_data_push(table_data, sizeof *madt);
457 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
458 madt->flags = cpu_to_le32(1);
459
460 for (i = 0; i < apic_ids->len; i++) {
461 adevc->madt_cpu(adev, i, apic_ids, table_data);
462 if (apic_ids->cpus[i].arch_id > 254) {
463 x2apic_mode = true;
464 }
465 }
466
467 io_apic = acpi_data_push(table_data, sizeof *io_apic);
468 io_apic->type = ACPI_APIC_IO;
469 io_apic->length = sizeof(*io_apic);
470 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
471 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
472 io_apic->interrupt = cpu_to_le32(0);
473
474 if (pcms->apic_xrupt_override) {
475 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
476 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
477 intsrcovr->length = sizeof(*intsrcovr);
478 intsrcovr->source = 0;
479 intsrcovr->gsi = cpu_to_le32(2);
480 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
481 }
482 for (i = 1; i < 16; i++) {
483 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
484 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
485 /* No need for a INT source override structure. */
486 continue;
487 }
488 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
489 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
490 intsrcovr->length = sizeof(*intsrcovr);
491 intsrcovr->source = i;
492 intsrcovr->gsi = cpu_to_le32(i);
493 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
494 }
495
496 if (x2apic_mode) {
497 AcpiMadtLocalX2ApicNmi *local_nmi;
498
499 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
500 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI;
501 local_nmi->length = sizeof(*local_nmi);
502 local_nmi->uid = 0xFFFFFFFF; /* all processors */
503 local_nmi->flags = cpu_to_le16(0);
504 local_nmi->lint = 1; /* ACPI_LINT1 */
505 } else {
506 AcpiMadtLocalNmi *local_nmi;
507
508 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
509 local_nmi->type = ACPI_APIC_LOCAL_NMI;
510 local_nmi->length = sizeof(*local_nmi);
511 local_nmi->processor_id = 0xff; /* all processors */
512 local_nmi->flags = cpu_to_le16(0);
513 local_nmi->lint = 1; /* ACPI_LINT1 */
514 }
515
516 build_header(linker, table_data,
517 (void *)(table_data->data + madt_start), "APIC",
518 table_data->len - madt_start, 1, NULL, NULL);
519 }
520
521 static void build_append_pcihp_notify_entry(Aml *method, int slot)
522 {
523 Aml *if_ctx;
524 int32_t devfn = PCI_DEVFN(slot, 0);
525
526 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
527 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
528 aml_append(method, if_ctx);
529 }
530
531 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
532 bool pcihp_bridge_en)
533 {
534 Aml *dev, *notify_method, *method;
535 QObject *bsel;
536 PCIBus *sec;
537 int i;
538
539 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
540 if (bsel) {
541 uint64_t bsel_val = qnum_get_uint(qobject_to_qnum(bsel));
542
543 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
544 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
545 }
546
547 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
548 DeviceClass *dc;
549 PCIDeviceClass *pc;
550 PCIDevice *pdev = bus->devices[i];
551 int slot = PCI_SLOT(i);
552 bool hotplug_enabled_dev;
553 bool bridge_in_acpi;
554
555 if (!pdev) {
556 if (bsel) { /* add hotplug slots for non present devices */
557 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
558 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
559 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
560 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
561 aml_append(method,
562 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
563 );
564 aml_append(dev, method);
565 aml_append(parent_scope, dev);
566
567 build_append_pcihp_notify_entry(notify_method, slot);
568 }
569 continue;
570 }
571
572 pc = PCI_DEVICE_GET_CLASS(pdev);
573 dc = DEVICE_GET_CLASS(pdev);
574
575 /* When hotplug for bridges is enabled, bridges are
576 * described in ACPI separately (see build_pci_bus_end).
577 * In this case they aren't themselves hot-pluggable.
578 * Hotplugged bridges *are* hot-pluggable.
579 */
580 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
581 !DEVICE(pdev)->hotplugged;
582
583 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
584
585 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
586 continue;
587 }
588
589 /* start to compose PCI slot descriptor */
590 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
591 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
592
593 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
594 /* add VGA specific AML methods */
595 int s3d;
596
597 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
598 s3d = 3;
599 } else {
600 s3d = 0;
601 }
602
603 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
604 aml_append(method, aml_return(aml_int(0)));
605 aml_append(dev, method);
606
607 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
608 aml_append(method, aml_return(aml_int(0)));
609 aml_append(dev, method);
610
611 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
612 aml_append(method, aml_return(aml_int(s3d)));
613 aml_append(dev, method);
614 } else if (hotplug_enabled_dev) {
615 /* add _SUN/_EJ0 to make slot hotpluggable */
616 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
617
618 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
619 aml_append(method,
620 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
621 );
622 aml_append(dev, method);
623
624 if (bsel) {
625 build_append_pcihp_notify_entry(notify_method, slot);
626 }
627 } else if (bridge_in_acpi) {
628 /*
629 * device is coldplugged bridge,
630 * add child device descriptions into its scope
631 */
632 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
633
634 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
635 }
636 /* slot descriptor has been composed, add it into parent context */
637 aml_append(parent_scope, dev);
638 }
639
640 if (bsel) {
641 aml_append(parent_scope, notify_method);
642 }
643
644 /* Append PCNT method to notify about events on local and child buses.
645 * Add unconditionally for root since DSDT expects it.
646 */
647 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
648
649 /* If bus supports hotplug select it and notify about local events */
650 if (bsel) {
651 uint64_t bsel_val = qnum_get_uint(qobject_to_qnum(bsel));
652
653 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
654 aml_append(method,
655 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
656 );
657 aml_append(method,
658 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
659 );
660 }
661
662 /* Notify about child bus events in any case */
663 if (pcihp_bridge_en) {
664 QLIST_FOREACH(sec, &bus->child, sibling) {
665 int32_t devfn = sec->parent_dev->devfn;
666
667 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
668 continue;
669 }
670
671 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
672 }
673 }
674 aml_append(parent_scope, method);
675 qobject_decref(bsel);
676 }
677
678 /**
679 * build_prt_entry:
680 * @link_name: link name for PCI route entry
681 *
682 * build AML package containing a PCI route entry for @link_name
683 */
684 static Aml *build_prt_entry(const char *link_name)
685 {
686 Aml *a_zero = aml_int(0);
687 Aml *pkg = aml_package(4);
688 aml_append(pkg, a_zero);
689 aml_append(pkg, a_zero);
690 aml_append(pkg, aml_name("%s", link_name));
691 aml_append(pkg, a_zero);
692 return pkg;
693 }
694
695 /*
696 * initialize_route - Initialize the interrupt routing rule
697 * through a specific LINK:
698 * if (lnk_idx == idx)
699 * route using link 'link_name'
700 */
701 static Aml *initialize_route(Aml *route, const char *link_name,
702 Aml *lnk_idx, int idx)
703 {
704 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
705 Aml *pkg = build_prt_entry(link_name);
706
707 aml_append(if_ctx, aml_store(pkg, route));
708
709 return if_ctx;
710 }
711
712 /*
713 * build_prt - Define interrupt rounting rules
714 *
715 * Returns an array of 128 routes, one for each device,
716 * based on device location.
717 * The main goal is to equaly distribute the interrupts
718 * over the 4 existing ACPI links (works only for i440fx).
719 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
720 *
721 */
722 static Aml *build_prt(bool is_pci0_prt)
723 {
724 Aml *method, *while_ctx, *pin, *res;
725
726 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
727 res = aml_local(0);
728 pin = aml_local(1);
729 aml_append(method, aml_store(aml_package(128), res));
730 aml_append(method, aml_store(aml_int(0), pin));
731
732 /* while (pin < 128) */
733 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
734 {
735 Aml *slot = aml_local(2);
736 Aml *lnk_idx = aml_local(3);
737 Aml *route = aml_local(4);
738
739 /* slot = pin >> 2 */
740 aml_append(while_ctx,
741 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
742 /* lnk_idx = (slot + pin) & 3 */
743 aml_append(while_ctx,
744 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
745 lnk_idx));
746
747 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
748 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
749 if (is_pci0_prt) {
750 Aml *if_device_1, *if_pin_4, *else_pin_4;
751
752 /* device 1 is the power-management device, needs SCI */
753 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
754 {
755 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
756 {
757 aml_append(if_pin_4,
758 aml_store(build_prt_entry("LNKS"), route));
759 }
760 aml_append(if_device_1, if_pin_4);
761 else_pin_4 = aml_else();
762 {
763 aml_append(else_pin_4,
764 aml_store(build_prt_entry("LNKA"), route));
765 }
766 aml_append(if_device_1, else_pin_4);
767 }
768 aml_append(while_ctx, if_device_1);
769 } else {
770 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
771 }
772 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
773 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
774
775 /* route[0] = 0x[slot]FFFF */
776 aml_append(while_ctx,
777 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
778 NULL),
779 aml_index(route, aml_int(0))));
780 /* route[1] = pin & 3 */
781 aml_append(while_ctx,
782 aml_store(aml_and(pin, aml_int(3), NULL),
783 aml_index(route, aml_int(1))));
784 /* res[pin] = route */
785 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
786 /* pin++ */
787 aml_append(while_ctx, aml_increment(pin));
788 }
789 aml_append(method, while_ctx);
790 /* return res*/
791 aml_append(method, aml_return(res));
792
793 return method;
794 }
795
796 typedef struct CrsRangeEntry {
797 uint64_t base;
798 uint64_t limit;
799 } CrsRangeEntry;
800
801 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
802 {
803 CrsRangeEntry *entry;
804
805 entry = g_malloc(sizeof(*entry));
806 entry->base = base;
807 entry->limit = limit;
808
809 g_ptr_array_add(ranges, entry);
810 }
811
812 static void crs_range_free(gpointer data)
813 {
814 CrsRangeEntry *entry = (CrsRangeEntry *)data;
815 g_free(entry);
816 }
817
818 typedef struct CrsRangeSet {
819 GPtrArray *io_ranges;
820 GPtrArray *mem_ranges;
821 GPtrArray *mem_64bit_ranges;
822 } CrsRangeSet;
823
824 static void crs_range_set_init(CrsRangeSet *range_set)
825 {
826 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
827 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
828 range_set->mem_64bit_ranges =
829 g_ptr_array_new_with_free_func(crs_range_free);
830 }
831
832 static void crs_range_set_free(CrsRangeSet *range_set)
833 {
834 g_ptr_array_free(range_set->io_ranges, true);
835 g_ptr_array_free(range_set->mem_ranges, true);
836 g_ptr_array_free(range_set->mem_64bit_ranges, true);
837 }
838
839 static gint crs_range_compare(gconstpointer a, gconstpointer b)
840 {
841 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
842 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
843
844 return (int64_t)entry_a->base - (int64_t)entry_b->base;
845 }
846
847 /*
848 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
849 * interval, computes the 'free' ranges from the same interval.
850 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
851 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
852 */
853 static void crs_replace_with_free_ranges(GPtrArray *ranges,
854 uint64_t start, uint64_t end)
855 {
856 GPtrArray *free_ranges = g_ptr_array_new();
857 uint64_t free_base = start;
858 int i;
859
860 g_ptr_array_sort(ranges, crs_range_compare);
861 for (i = 0; i < ranges->len; i++) {
862 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
863
864 if (free_base < used->base) {
865 crs_range_insert(free_ranges, free_base, used->base - 1);
866 }
867
868 free_base = used->limit + 1;
869 }
870
871 if (free_base < end) {
872 crs_range_insert(free_ranges, free_base, end);
873 }
874
875 g_ptr_array_set_size(ranges, 0);
876 for (i = 0; i < free_ranges->len; i++) {
877 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
878 }
879
880 g_ptr_array_free(free_ranges, true);
881 }
882
883 /*
884 * crs_range_merge - merges adjacent ranges in the given array.
885 * Array elements are deleted and replaced with the merged ranges.
886 */
887 static void crs_range_merge(GPtrArray *range)
888 {
889 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
890 CrsRangeEntry *entry;
891 uint64_t range_base, range_limit;
892 int i;
893
894 if (!range->len) {
895 return;
896 }
897
898 g_ptr_array_sort(range, crs_range_compare);
899
900 entry = g_ptr_array_index(range, 0);
901 range_base = entry->base;
902 range_limit = entry->limit;
903 for (i = 1; i < range->len; i++) {
904 entry = g_ptr_array_index(range, i);
905 if (entry->base - 1 == range_limit) {
906 range_limit = entry->limit;
907 } else {
908 crs_range_insert(tmp, range_base, range_limit);
909 range_base = entry->base;
910 range_limit = entry->limit;
911 }
912 }
913 crs_range_insert(tmp, range_base, range_limit);
914
915 g_ptr_array_set_size(range, 0);
916 for (i = 0; i < tmp->len; i++) {
917 entry = g_ptr_array_index(tmp, i);
918 crs_range_insert(range, entry->base, entry->limit);
919 }
920 g_ptr_array_free(tmp, true);
921 }
922
923 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
924 {
925 Aml *crs = aml_resource_template();
926 CrsRangeSet temp_range_set;
927 CrsRangeEntry *entry;
928 uint8_t max_bus = pci_bus_num(host->bus);
929 uint8_t type;
930 int devfn;
931 int i;
932
933 crs_range_set_init(&temp_range_set);
934 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
935 uint64_t range_base, range_limit;
936 PCIDevice *dev = host->bus->devices[devfn];
937
938 if (!dev) {
939 continue;
940 }
941
942 for (i = 0; i < PCI_NUM_REGIONS; i++) {
943 PCIIORegion *r = &dev->io_regions[i];
944
945 range_base = r->addr;
946 range_limit = r->addr + r->size - 1;
947
948 /*
949 * Work-around for old bioses
950 * that do not support multiple root buses
951 */
952 if (!range_base || range_base > range_limit) {
953 continue;
954 }
955
956 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
957 crs_range_insert(temp_range_set.io_ranges,
958 range_base, range_limit);
959 } else { /* "memory" */
960 crs_range_insert(temp_range_set.mem_ranges,
961 range_base, range_limit);
962 }
963 }
964
965 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
966 if (type == PCI_HEADER_TYPE_BRIDGE) {
967 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
968 if (subordinate > max_bus) {
969 max_bus = subordinate;
970 }
971
972 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
973 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
974
975 /*
976 * Work-around for old bioses
977 * that do not support multiple root buses
978 */
979 if (range_base && range_base <= range_limit) {
980 crs_range_insert(temp_range_set.io_ranges,
981 range_base, range_limit);
982 }
983
984 range_base =
985 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
986 range_limit =
987 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
988
989 /*
990 * Work-around for old bioses
991 * that do not support multiple root buses
992 */
993 if (range_base && range_base <= range_limit) {
994 uint64_t length = range_limit - range_base + 1;
995 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
996 crs_range_insert(temp_range_set.mem_ranges,
997 range_base, range_limit);
998 } else {
999 crs_range_insert(temp_range_set.mem_64bit_ranges,
1000 range_base, range_limit);
1001 }
1002 }
1003
1004 range_base =
1005 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1006 range_limit =
1007 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1008
1009 /*
1010 * Work-around for old bioses
1011 * that do not support multiple root buses
1012 */
1013 if (range_base && range_base <= range_limit) {
1014 uint64_t length = range_limit - range_base + 1;
1015 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
1016 crs_range_insert(temp_range_set.mem_ranges,
1017 range_base, range_limit);
1018 } else {
1019 crs_range_insert(temp_range_set.mem_64bit_ranges,
1020 range_base, range_limit);
1021 }
1022 }
1023 }
1024 }
1025
1026 crs_range_merge(temp_range_set.io_ranges);
1027 for (i = 0; i < temp_range_set.io_ranges->len; i++) {
1028 entry = g_ptr_array_index(temp_range_set.io_ranges, i);
1029 aml_append(crs,
1030 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1031 AML_POS_DECODE, AML_ENTIRE_RANGE,
1032 0, entry->base, entry->limit, 0,
1033 entry->limit - entry->base + 1));
1034 crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
1035 }
1036
1037 crs_range_merge(temp_range_set.mem_ranges);
1038 for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
1039 entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
1040 aml_append(crs,
1041 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1042 AML_MAX_FIXED, AML_NON_CACHEABLE,
1043 AML_READ_WRITE,
1044 0, entry->base, entry->limit, 0,
1045 entry->limit - entry->base + 1));
1046 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
1047 }
1048
1049 crs_range_merge(temp_range_set.mem_64bit_ranges);
1050 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
1051 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
1052 aml_append(crs,
1053 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1054 AML_MAX_FIXED, AML_NON_CACHEABLE,
1055 AML_READ_WRITE,
1056 0, entry->base, entry->limit, 0,
1057 entry->limit - entry->base + 1));
1058 crs_range_insert(range_set->mem_64bit_ranges,
1059 entry->base, entry->limit);
1060 }
1061
1062 crs_range_set_free(&temp_range_set);
1063
1064 aml_append(crs,
1065 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1066 0,
1067 pci_bus_num(host->bus),
1068 max_bus,
1069 0,
1070 max_bus - pci_bus_num(host->bus) + 1));
1071
1072 return crs;
1073 }
1074
1075 static void build_hpet_aml(Aml *table)
1076 {
1077 Aml *crs;
1078 Aml *field;
1079 Aml *method;
1080 Aml *if_ctx;
1081 Aml *scope = aml_scope("_SB");
1082 Aml *dev = aml_device("HPET");
1083 Aml *zero = aml_int(0);
1084 Aml *id = aml_local(0);
1085 Aml *period = aml_local(1);
1086
1087 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1088 aml_append(dev, aml_name_decl("_UID", zero));
1089
1090 aml_append(dev,
1091 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1092 HPET_LEN));
1093 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1094 aml_append(field, aml_named_field("VEND", 32));
1095 aml_append(field, aml_named_field("PRD", 32));
1096 aml_append(dev, field);
1097
1098 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1099 aml_append(method, aml_store(aml_name("VEND"), id));
1100 aml_append(method, aml_store(aml_name("PRD"), period));
1101 aml_append(method, aml_shiftright(id, aml_int(16), id));
1102 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1103 aml_equal(id, aml_int(0xffff))));
1104 {
1105 aml_append(if_ctx, aml_return(zero));
1106 }
1107 aml_append(method, if_ctx);
1108
1109 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1110 aml_lgreater(period, aml_int(100000000))));
1111 {
1112 aml_append(if_ctx, aml_return(zero));
1113 }
1114 aml_append(method, if_ctx);
1115
1116 aml_append(method, aml_return(aml_int(0x0F)));
1117 aml_append(dev, method);
1118
1119 crs = aml_resource_template();
1120 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1121 aml_append(dev, aml_name_decl("_CRS", crs));
1122
1123 aml_append(scope, dev);
1124 aml_append(table, scope);
1125 }
1126
1127 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
1128 {
1129 Aml *dev, *fdi;
1130 uint8_t maxc, maxh, maxs;
1131
1132 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1133
1134 dev = aml_device("FLP%c", 'A' + idx);
1135
1136 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1137
1138 fdi = aml_package(16);
1139 aml_append(fdi, aml_int(idx)); /* Drive Number */
1140 aml_append(fdi,
1141 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1142 /*
1143 * the values below are the limits of the drive, and are thus independent
1144 * of the inserted media
1145 */
1146 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1147 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1148 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1149 /*
1150 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1151 * the drive type, so shall we
1152 */
1153 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1154 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1155 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1156 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1157 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1158 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1159 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1160 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1161 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1162 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1163 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1164
1165 aml_append(dev, aml_name_decl("_FDI", fdi));
1166 return dev;
1167 }
1168
1169 static Aml *build_fdc_device_aml(ISADevice *fdc)
1170 {
1171 int i;
1172 Aml *dev;
1173 Aml *crs;
1174
1175 #define ACPI_FDE_MAX_FD 4
1176 uint32_t fde_buf[5] = {
1177 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1178 cpu_to_le32(2) /* tape presence (2 == never present) */
1179 };
1180
1181 dev = aml_device("FDC0");
1182 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1183
1184 crs = aml_resource_template();
1185 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1186 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1187 aml_append(crs, aml_irq_no_flags(6));
1188 aml_append(crs,
1189 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1190 aml_append(dev, aml_name_decl("_CRS", crs));
1191
1192 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1193 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1194
1195 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1196 fde_buf[i] = cpu_to_le32(1); /* drive present */
1197 aml_append(dev, build_fdinfo_aml(i, type));
1198 }
1199 }
1200 aml_append(dev, aml_name_decl("_FDE",
1201 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1202
1203 return dev;
1204 }
1205
1206 static Aml *build_rtc_device_aml(void)
1207 {
1208 Aml *dev;
1209 Aml *crs;
1210
1211 dev = aml_device("RTC");
1212 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1213 crs = aml_resource_template();
1214 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1215 aml_append(crs, aml_irq_no_flags(8));
1216 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1217 aml_append(dev, aml_name_decl("_CRS", crs));
1218
1219 return dev;
1220 }
1221
1222 static Aml *build_kbd_device_aml(void)
1223 {
1224 Aml *dev;
1225 Aml *crs;
1226 Aml *method;
1227
1228 dev = aml_device("KBD");
1229 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1230
1231 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1232 aml_append(method, aml_return(aml_int(0x0f)));
1233 aml_append(dev, method);
1234
1235 crs = aml_resource_template();
1236 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1237 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1238 aml_append(crs, aml_irq_no_flags(1));
1239 aml_append(dev, aml_name_decl("_CRS", crs));
1240
1241 return dev;
1242 }
1243
1244 static Aml *build_mouse_device_aml(void)
1245 {
1246 Aml *dev;
1247 Aml *crs;
1248 Aml *method;
1249
1250 dev = aml_device("MOU");
1251 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1252
1253 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1254 aml_append(method, aml_return(aml_int(0x0f)));
1255 aml_append(dev, method);
1256
1257 crs = aml_resource_template();
1258 aml_append(crs, aml_irq_no_flags(12));
1259 aml_append(dev, aml_name_decl("_CRS", crs));
1260
1261 return dev;
1262 }
1263
1264 static Aml *build_lpt_device_aml(void)
1265 {
1266 Aml *dev;
1267 Aml *crs;
1268 Aml *method;
1269 Aml *if_ctx;
1270 Aml *else_ctx;
1271 Aml *zero = aml_int(0);
1272 Aml *is_present = aml_local(0);
1273
1274 dev = aml_device("LPT");
1275 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1276
1277 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1278 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1279 if_ctx = aml_if(aml_equal(is_present, zero));
1280 {
1281 aml_append(if_ctx, aml_return(aml_int(0x00)));
1282 }
1283 aml_append(method, if_ctx);
1284 else_ctx = aml_else();
1285 {
1286 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1287 }
1288 aml_append(method, else_ctx);
1289 aml_append(dev, method);
1290
1291 crs = aml_resource_template();
1292 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1293 aml_append(crs, aml_irq_no_flags(7));
1294 aml_append(dev, aml_name_decl("_CRS", crs));
1295
1296 return dev;
1297 }
1298
1299 static Aml *build_com_device_aml(uint8_t uid)
1300 {
1301 Aml *dev;
1302 Aml *crs;
1303 Aml *method;
1304 Aml *if_ctx;
1305 Aml *else_ctx;
1306 Aml *zero = aml_int(0);
1307 Aml *is_present = aml_local(0);
1308 const char *enabled_field = "CAEN";
1309 uint8_t irq = 4;
1310 uint16_t io_port = 0x03F8;
1311
1312 assert(uid == 1 || uid == 2);
1313 if (uid == 2) {
1314 enabled_field = "CBEN";
1315 irq = 3;
1316 io_port = 0x02F8;
1317 }
1318
1319 dev = aml_device("COM%d", uid);
1320 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1321 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1322
1323 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1324 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1325 if_ctx = aml_if(aml_equal(is_present, zero));
1326 {
1327 aml_append(if_ctx, aml_return(aml_int(0x00)));
1328 }
1329 aml_append(method, if_ctx);
1330 else_ctx = aml_else();
1331 {
1332 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1333 }
1334 aml_append(method, else_ctx);
1335 aml_append(dev, method);
1336
1337 crs = aml_resource_template();
1338 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1339 aml_append(crs, aml_irq_no_flags(irq));
1340 aml_append(dev, aml_name_decl("_CRS", crs));
1341
1342 return dev;
1343 }
1344
1345 static void build_isa_devices_aml(Aml *table)
1346 {
1347 ISADevice *fdc = pc_find_fdc0();
1348 bool ambiguous;
1349
1350 Aml *scope = aml_scope("_SB.PCI0.ISA");
1351 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
1352
1353 aml_append(scope, build_rtc_device_aml());
1354 aml_append(scope, build_kbd_device_aml());
1355 aml_append(scope, build_mouse_device_aml());
1356 if (fdc) {
1357 aml_append(scope, build_fdc_device_aml(fdc));
1358 }
1359 aml_append(scope, build_lpt_device_aml());
1360 aml_append(scope, build_com_device_aml(1));
1361 aml_append(scope, build_com_device_aml(2));
1362
1363 if (ambiguous) {
1364 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1365 } else if (!obj) {
1366 error_report("No ISA bus, unable to define IPMI ACPI data");
1367 } else {
1368 build_acpi_ipmi_devices(scope, BUS(obj));
1369 }
1370
1371 aml_append(table, scope);
1372 }
1373
1374 static void build_dbg_aml(Aml *table)
1375 {
1376 Aml *field;
1377 Aml *method;
1378 Aml *while_ctx;
1379 Aml *scope = aml_scope("\\");
1380 Aml *buf = aml_local(0);
1381 Aml *len = aml_local(1);
1382 Aml *idx = aml_local(2);
1383
1384 aml_append(scope,
1385 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1386 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1387 aml_append(field, aml_named_field("DBGB", 8));
1388 aml_append(scope, field);
1389
1390 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1391
1392 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1393 aml_append(method, aml_to_buffer(buf, buf));
1394 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1395 aml_append(method, aml_store(aml_int(0), idx));
1396
1397 while_ctx = aml_while(aml_lless(idx, len));
1398 aml_append(while_ctx,
1399 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1400 aml_append(while_ctx, aml_increment(idx));
1401 aml_append(method, while_ctx);
1402
1403 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1404 aml_append(scope, method);
1405
1406 aml_append(table, scope);
1407 }
1408
1409 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1410 {
1411 Aml *dev;
1412 Aml *crs;
1413 Aml *method;
1414 uint32_t irqs[] = {5, 10, 11};
1415
1416 dev = aml_device("%s", name);
1417 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1418 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1419
1420 crs = aml_resource_template();
1421 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1422 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1423 aml_append(dev, aml_name_decl("_PRS", crs));
1424
1425 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1426 aml_append(method, aml_return(aml_call1("IQST", reg)));
1427 aml_append(dev, method);
1428
1429 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1430 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1431 aml_append(dev, method);
1432
1433 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1434 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1435 aml_append(dev, method);
1436
1437 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1438 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1439 aml_append(method, aml_store(aml_name("PRRI"), reg));
1440 aml_append(dev, method);
1441
1442 return dev;
1443 }
1444
1445 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1446 {
1447 Aml *dev;
1448 Aml *crs;
1449 Aml *method;
1450 uint32_t irqs;
1451
1452 dev = aml_device("%s", name);
1453 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1454 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1455
1456 crs = aml_resource_template();
1457 irqs = gsi;
1458 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1459 AML_SHARED, &irqs, 1));
1460 aml_append(dev, aml_name_decl("_PRS", crs));
1461
1462 aml_append(dev, aml_name_decl("_CRS", crs));
1463
1464 /*
1465 * _DIS can be no-op because the interrupt cannot be disabled.
1466 */
1467 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1468 aml_append(dev, method);
1469
1470 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1471 aml_append(dev, method);
1472
1473 return dev;
1474 }
1475
1476 /* _CRS method - get current settings */
1477 static Aml *build_iqcr_method(bool is_piix4)
1478 {
1479 Aml *if_ctx;
1480 uint32_t irqs;
1481 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1482 Aml *crs = aml_resource_template();
1483
1484 irqs = 0;
1485 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1486 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1487 aml_append(method, aml_name_decl("PRR0", crs));
1488
1489 aml_append(method,
1490 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1491
1492 if (is_piix4) {
1493 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1494 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1495 aml_append(method, if_ctx);
1496 } else {
1497 aml_append(method,
1498 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1499 aml_name("PRRI")));
1500 }
1501
1502 aml_append(method, aml_return(aml_name("PRR0")));
1503 return method;
1504 }
1505
1506 /* _STA method - get status */
1507 static Aml *build_irq_status_method(void)
1508 {
1509 Aml *if_ctx;
1510 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1511
1512 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1513 aml_append(if_ctx, aml_return(aml_int(0x09)));
1514 aml_append(method, if_ctx);
1515 aml_append(method, aml_return(aml_int(0x0B)));
1516 return method;
1517 }
1518
1519 static void build_piix4_pci0_int(Aml *table)
1520 {
1521 Aml *dev;
1522 Aml *crs;
1523 Aml *field;
1524 Aml *method;
1525 uint32_t irqs;
1526 Aml *sb_scope = aml_scope("_SB");
1527 Aml *pci0_scope = aml_scope("PCI0");
1528
1529 aml_append(pci0_scope, build_prt(true));
1530 aml_append(sb_scope, pci0_scope);
1531
1532 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1533 aml_append(field, aml_named_field("PRQ0", 8));
1534 aml_append(field, aml_named_field("PRQ1", 8));
1535 aml_append(field, aml_named_field("PRQ2", 8));
1536 aml_append(field, aml_named_field("PRQ3", 8));
1537 aml_append(sb_scope, field);
1538
1539 aml_append(sb_scope, build_irq_status_method());
1540 aml_append(sb_scope, build_iqcr_method(true));
1541
1542 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1543 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1544 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1545 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1546
1547 dev = aml_device("LNKS");
1548 {
1549 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1550 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1551
1552 crs = aml_resource_template();
1553 irqs = 9;
1554 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1555 AML_ACTIVE_HIGH, AML_SHARED,
1556 &irqs, 1));
1557 aml_append(dev, aml_name_decl("_PRS", crs));
1558
1559 /* The SCI cannot be disabled and is always attached to GSI 9,
1560 * so these are no-ops. We only need this link to override the
1561 * polarity to active high and match the content of the MADT.
1562 */
1563 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1564 aml_append(method, aml_return(aml_int(0x0b)));
1565 aml_append(dev, method);
1566
1567 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1568 aml_append(dev, method);
1569
1570 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1571 aml_append(method, aml_return(aml_name("_PRS")));
1572 aml_append(dev, method);
1573
1574 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1575 aml_append(dev, method);
1576 }
1577 aml_append(sb_scope, dev);
1578
1579 aml_append(table, sb_scope);
1580 }
1581
1582 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1583 {
1584 int i;
1585 int head;
1586 Aml *pkg;
1587 char base = name[3] < 'E' ? 'A' : 'E';
1588 char *s = g_strdup(name);
1589 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1590
1591 assert(strlen(s) == 4);
1592
1593 head = name[3] - base;
1594 for (i = 0; i < 4; i++) {
1595 if (head + i > 3) {
1596 head = i * -1;
1597 }
1598 s[3] = base + head + i;
1599 pkg = aml_package(4);
1600 aml_append(pkg, a_nr);
1601 aml_append(pkg, aml_int(i));
1602 aml_append(pkg, aml_name("%s", s));
1603 aml_append(pkg, aml_int(0));
1604 aml_append(ctx, pkg);
1605 }
1606 g_free(s);
1607 }
1608
1609 static Aml *build_q35_routing_table(const char *str)
1610 {
1611 int i;
1612 Aml *pkg;
1613 char *name = g_strdup_printf("%s ", str);
1614
1615 pkg = aml_package(128);
1616 for (i = 0; i < 0x18; i++) {
1617 name[3] = 'E' + (i & 0x3);
1618 append_q35_prt_entry(pkg, i, name);
1619 }
1620
1621 name[3] = 'E';
1622 append_q35_prt_entry(pkg, 0x18, name);
1623
1624 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1625 for (i = 0x0019; i < 0x1e; i++) {
1626 name[3] = 'A';
1627 append_q35_prt_entry(pkg, i, name);
1628 }
1629
1630 /* PCIe->PCI bridge. use PIRQ[E-H] */
1631 name[3] = 'E';
1632 append_q35_prt_entry(pkg, 0x1e, name);
1633 name[3] = 'A';
1634 append_q35_prt_entry(pkg, 0x1f, name);
1635
1636 g_free(name);
1637 return pkg;
1638 }
1639
1640 static void build_q35_pci0_int(Aml *table)
1641 {
1642 Aml *field;
1643 Aml *method;
1644 Aml *sb_scope = aml_scope("_SB");
1645 Aml *pci0_scope = aml_scope("PCI0");
1646
1647 /* Zero => PIC mode, One => APIC Mode */
1648 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1649 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1650 {
1651 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1652 }
1653 aml_append(table, method);
1654
1655 aml_append(pci0_scope,
1656 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1657 aml_append(pci0_scope,
1658 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1659
1660 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1661 {
1662 Aml *if_ctx;
1663 Aml *else_ctx;
1664
1665 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1666 section 6.2.8.1 */
1667 /* Note: we provide the same info as the PCI routing
1668 table of the Bochs BIOS */
1669 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1670 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1671 aml_append(method, if_ctx);
1672 else_ctx = aml_else();
1673 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1674 aml_append(method, else_ctx);
1675 }
1676 aml_append(pci0_scope, method);
1677 aml_append(sb_scope, pci0_scope);
1678
1679 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1680 aml_append(field, aml_named_field("PRQA", 8));
1681 aml_append(field, aml_named_field("PRQB", 8));
1682 aml_append(field, aml_named_field("PRQC", 8));
1683 aml_append(field, aml_named_field("PRQD", 8));
1684 aml_append(field, aml_reserved_field(0x20));
1685 aml_append(field, aml_named_field("PRQE", 8));
1686 aml_append(field, aml_named_field("PRQF", 8));
1687 aml_append(field, aml_named_field("PRQG", 8));
1688 aml_append(field, aml_named_field("PRQH", 8));
1689 aml_append(sb_scope, field);
1690
1691 aml_append(sb_scope, build_irq_status_method());
1692 aml_append(sb_scope, build_iqcr_method(false));
1693
1694 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1695 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1696 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1697 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1698 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1699 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1700 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1701 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1702
1703 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1704 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1705 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1706 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1707 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1708 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1709 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1710 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1711
1712 aml_append(table, sb_scope);
1713 }
1714
1715 static void build_q35_isa_bridge(Aml *table)
1716 {
1717 Aml *dev;
1718 Aml *scope;
1719 Aml *field;
1720
1721 scope = aml_scope("_SB.PCI0");
1722 dev = aml_device("ISA");
1723 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1724
1725 /* ICH9 PCI to ISA irq remapping */
1726 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1727 aml_int(0x60), 0x0C));
1728
1729 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1730 aml_int(0x80), 0x02));
1731 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1732 aml_append(field, aml_named_field("COMA", 3));
1733 aml_append(field, aml_reserved_field(1));
1734 aml_append(field, aml_named_field("COMB", 3));
1735 aml_append(field, aml_reserved_field(1));
1736 aml_append(field, aml_named_field("LPTD", 2));
1737 aml_append(dev, field);
1738
1739 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1740 aml_int(0x82), 0x02));
1741 /* enable bits */
1742 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1743 aml_append(field, aml_named_field("CAEN", 1));
1744 aml_append(field, aml_named_field("CBEN", 1));
1745 aml_append(field, aml_named_field("LPEN", 1));
1746 aml_append(dev, field);
1747
1748 aml_append(scope, dev);
1749 aml_append(table, scope);
1750 }
1751
1752 static void build_piix4_pm(Aml *table)
1753 {
1754 Aml *dev;
1755 Aml *scope;
1756
1757 scope = aml_scope("_SB.PCI0");
1758 dev = aml_device("PX13");
1759 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1760
1761 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1762 aml_int(0x00), 0xff));
1763 aml_append(scope, dev);
1764 aml_append(table, scope);
1765 }
1766
1767 static void build_piix4_isa_bridge(Aml *table)
1768 {
1769 Aml *dev;
1770 Aml *scope;
1771 Aml *field;
1772
1773 scope = aml_scope("_SB.PCI0");
1774 dev = aml_device("ISA");
1775 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1776
1777 /* PIIX PCI to ISA irq remapping */
1778 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1779 aml_int(0x60), 0x04));
1780 /* enable bits */
1781 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1782 /* Offset(0x5f),, 7, */
1783 aml_append(field, aml_reserved_field(0x2f8));
1784 aml_append(field, aml_reserved_field(7));
1785 aml_append(field, aml_named_field("LPEN", 1));
1786 /* Offset(0x67),, 3, */
1787 aml_append(field, aml_reserved_field(0x38));
1788 aml_append(field, aml_reserved_field(3));
1789 aml_append(field, aml_named_field("CAEN", 1));
1790 aml_append(field, aml_reserved_field(3));
1791 aml_append(field, aml_named_field("CBEN", 1));
1792 aml_append(dev, field);
1793
1794 aml_append(scope, dev);
1795 aml_append(table, scope);
1796 }
1797
1798 static void build_piix4_pci_hotplug(Aml *table)
1799 {
1800 Aml *scope;
1801 Aml *field;
1802 Aml *method;
1803
1804 scope = aml_scope("_SB.PCI0");
1805
1806 aml_append(scope,
1807 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1808 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1809 aml_append(field, aml_named_field("PCIU", 32));
1810 aml_append(field, aml_named_field("PCID", 32));
1811 aml_append(scope, field);
1812
1813 aml_append(scope,
1814 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1815 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1816 aml_append(field, aml_named_field("B0EJ", 32));
1817 aml_append(scope, field);
1818
1819 aml_append(scope,
1820 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1821 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1822 aml_append(field, aml_named_field("BNUM", 32));
1823 aml_append(scope, field);
1824
1825 aml_append(scope, aml_mutex("BLCK", 0));
1826
1827 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1828 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1829 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1830 aml_append(method,
1831 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1832 aml_append(method, aml_release(aml_name("BLCK")));
1833 aml_append(method, aml_return(aml_int(0)));
1834 aml_append(scope, method);
1835
1836 aml_append(table, scope);
1837 }
1838
1839 static Aml *build_q35_osc_method(void)
1840 {
1841 Aml *if_ctx;
1842 Aml *if_ctx2;
1843 Aml *else_ctx;
1844 Aml *method;
1845 Aml *a_cwd1 = aml_name("CDW1");
1846 Aml *a_ctrl = aml_local(0);
1847
1848 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1849 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1850
1851 if_ctx = aml_if(aml_equal(
1852 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1853 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1854 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1855
1856 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1857
1858 /*
1859 * Always allow native PME, AER (no dependencies)
1860 * Allow SHPC (PCI bridges can have SHPC controller)
1861 */
1862 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
1863
1864 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1865 /* Unknown revision */
1866 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1867 aml_append(if_ctx, if_ctx2);
1868
1869 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1870 /* Capabilities bits were masked */
1871 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1872 aml_append(if_ctx, if_ctx2);
1873
1874 /* Update DWORD3 in the buffer */
1875 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1876 aml_append(method, if_ctx);
1877
1878 else_ctx = aml_else();
1879 /* Unrecognized UUID */
1880 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1881 aml_append(method, else_ctx);
1882
1883 aml_append(method, aml_return(aml_arg(3)));
1884 return method;
1885 }
1886
1887 static void
1888 build_dsdt(GArray *table_data, BIOSLinker *linker,
1889 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1890 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1891 {
1892 CrsRangeEntry *entry;
1893 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1894 CrsRangeSet crs_range_set;
1895 PCMachineState *pcms = PC_MACHINE(machine);
1896 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1897 uint32_t nr_mem = machine->ram_slots;
1898 int root_bus_limit = 0xFF;
1899 PCIBus *bus = NULL;
1900 int i;
1901
1902 dsdt = init_aml_allocator();
1903
1904 /* Reserve space for header */
1905 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1906
1907 build_dbg_aml(dsdt);
1908 if (misc->is_piix4) {
1909 sb_scope = aml_scope("_SB");
1910 dev = aml_device("PCI0");
1911 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1912 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1913 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1914 aml_append(sb_scope, dev);
1915 aml_append(dsdt, sb_scope);
1916
1917 build_hpet_aml(dsdt);
1918 build_piix4_pm(dsdt);
1919 build_piix4_isa_bridge(dsdt);
1920 build_isa_devices_aml(dsdt);
1921 build_piix4_pci_hotplug(dsdt);
1922 build_piix4_pci0_int(dsdt);
1923 } else {
1924 sb_scope = aml_scope("_SB");
1925 dev = aml_device("PCI0");
1926 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1927 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1928 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1929 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1930 aml_append(dev, build_q35_osc_method());
1931 aml_append(sb_scope, dev);
1932 aml_append(dsdt, sb_scope);
1933
1934 build_hpet_aml(dsdt);
1935 build_q35_isa_bridge(dsdt);
1936 build_isa_devices_aml(dsdt);
1937 build_q35_pci0_int(dsdt);
1938 }
1939
1940 if (pcmc->legacy_cpu_hotplug) {
1941 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1942 } else {
1943 CPUHotplugFeatures opts = {
1944 .apci_1_compatible = true, .has_legacy_cphp = true
1945 };
1946 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1947 "\\_SB.PCI0", "\\_GPE._E02");
1948 }
1949 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", "\\_GPE._E03");
1950
1951 scope = aml_scope("_GPE");
1952 {
1953 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1954
1955 if (misc->is_piix4) {
1956 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1957 aml_append(method,
1958 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1959 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1960 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1961 aml_append(scope, method);
1962 }
1963
1964 if (pcms->acpi_nvdimm_state.is_enabled) {
1965 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1966 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1967 aml_int(0x80)));
1968 aml_append(scope, method);
1969 }
1970 }
1971 aml_append(dsdt, scope);
1972
1973 crs_range_set_init(&crs_range_set);
1974 bus = PC_MACHINE(machine)->bus;
1975 if (bus) {
1976 QLIST_FOREACH(bus, &bus->child, sibling) {
1977 uint8_t bus_num = pci_bus_num(bus);
1978 uint8_t numa_node = pci_bus_numa_node(bus);
1979
1980 /* look only for expander root buses */
1981 if (!pci_bus_is_root(bus)) {
1982 continue;
1983 }
1984
1985 if (bus_num < root_bus_limit) {
1986 root_bus_limit = bus_num - 1;
1987 }
1988
1989 scope = aml_scope("\\_SB");
1990 dev = aml_device("PC%.02X", bus_num);
1991 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1992 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1993 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1994 if (pci_bus_is_express(bus)) {
1995 aml_append(dev, build_q35_osc_method());
1996 }
1997
1998 if (numa_node != NUMA_NODE_UNASSIGNED) {
1999 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
2000 }
2001
2002 aml_append(dev, build_prt(false));
2003 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
2004 aml_append(dev, aml_name_decl("_CRS", crs));
2005 aml_append(scope, dev);
2006 aml_append(dsdt, scope);
2007 }
2008 }
2009
2010 scope = aml_scope("\\_SB.PCI0");
2011 /* build PCI0._CRS */
2012 crs = aml_resource_template();
2013 aml_append(crs,
2014 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
2015 0x0000, 0x0, root_bus_limit,
2016 0x0000, root_bus_limit + 1));
2017 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
2018
2019 aml_append(crs,
2020 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2021 AML_POS_DECODE, AML_ENTIRE_RANGE,
2022 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
2023
2024 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
2025 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
2026 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
2027 aml_append(crs,
2028 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2029 AML_POS_DECODE, AML_ENTIRE_RANGE,
2030 0x0000, entry->base, entry->limit,
2031 0x0000, entry->limit - entry->base + 1));
2032 }
2033
2034 aml_append(crs,
2035 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2036 AML_CACHEABLE, AML_READ_WRITE,
2037 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2038
2039 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
2040 range_lob(pci_hole),
2041 range_upb(pci_hole));
2042 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
2043 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
2044 aml_append(crs,
2045 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2046 AML_NON_CACHEABLE, AML_READ_WRITE,
2047 0, entry->base, entry->limit,
2048 0, entry->limit - entry->base + 1));
2049 }
2050
2051 if (!range_is_empty(pci_hole64)) {
2052 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
2053 range_lob(pci_hole64),
2054 range_upb(pci_hole64));
2055 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
2056 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
2057 aml_append(crs,
2058 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
2059 AML_MAX_FIXED,
2060 AML_CACHEABLE, AML_READ_WRITE,
2061 0, entry->base, entry->limit,
2062 0, entry->limit - entry->base + 1));
2063 }
2064 }
2065
2066 if (TPM_IS_TIS(tpm_find())) {
2067 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2068 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2069 }
2070 aml_append(scope, aml_name_decl("_CRS", crs));
2071
2072 /* reserve GPE0 block resources */
2073 dev = aml_device("GPE0");
2074 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2075 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2076 /* device present, functioning, decoding, not shown in UI */
2077 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2078 crs = aml_resource_template();
2079 aml_append(crs,
2080 aml_io(
2081 AML_DECODE16,
2082 pm->fadt.gpe0_blk.address,
2083 pm->fadt.gpe0_blk.address,
2084 1,
2085 pm->fadt.gpe0_blk.bit_width / 8)
2086 );
2087 aml_append(dev, aml_name_decl("_CRS", crs));
2088 aml_append(scope, dev);
2089
2090 crs_range_set_free(&crs_range_set);
2091
2092 /* reserve PCIHP resources */
2093 if (pm->pcihp_io_len) {
2094 dev = aml_device("PHPR");
2095 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2096 aml_append(dev,
2097 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2098 /* device present, functioning, decoding, not shown in UI */
2099 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2100 crs = aml_resource_template();
2101 aml_append(crs,
2102 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2103 pm->pcihp_io_len)
2104 );
2105 aml_append(dev, aml_name_decl("_CRS", crs));
2106 aml_append(scope, dev);
2107 }
2108 aml_append(dsdt, scope);
2109
2110 /* create S3_ / S4_ / S5_ packages if necessary */
2111 scope = aml_scope("\\");
2112 if (!pm->s3_disabled) {
2113 pkg = aml_package(4);
2114 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2115 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2116 aml_append(pkg, aml_int(0)); /* reserved */
2117 aml_append(pkg, aml_int(0)); /* reserved */
2118 aml_append(scope, aml_name_decl("_S3", pkg));
2119 }
2120
2121 if (!pm->s4_disabled) {
2122 pkg = aml_package(4);
2123 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2124 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2125 aml_append(pkg, aml_int(pm->s4_val));
2126 aml_append(pkg, aml_int(0)); /* reserved */
2127 aml_append(pkg, aml_int(0)); /* reserved */
2128 aml_append(scope, aml_name_decl("_S4", pkg));
2129 }
2130
2131 pkg = aml_package(4);
2132 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2133 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2134 aml_append(pkg, aml_int(0)); /* reserved */
2135 aml_append(pkg, aml_int(0)); /* reserved */
2136 aml_append(scope, aml_name_decl("_S5", pkg));
2137 aml_append(dsdt, scope);
2138
2139 /* create fw_cfg node, unconditionally */
2140 {
2141 /* when using port i/o, the 8-bit data register *always* overlaps
2142 * with half of the 16-bit control register. Hence, the total size
2143 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2144 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2145 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2146 "dma_enabled", NULL) ?
2147 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2148 FW_CFG_CTL_SIZE;
2149
2150 scope = aml_scope("\\_SB.PCI0");
2151 dev = aml_device("FWCF");
2152
2153 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2154
2155 /* device present, functioning, decoding, not shown in UI */
2156 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2157
2158 crs = aml_resource_template();
2159 aml_append(crs,
2160 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2161 );
2162 aml_append(dev, aml_name_decl("_CRS", crs));
2163
2164 aml_append(scope, dev);
2165 aml_append(dsdt, scope);
2166 }
2167
2168 if (misc->applesmc_io_base) {
2169 scope = aml_scope("\\_SB.PCI0.ISA");
2170 dev = aml_device("SMC");
2171
2172 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2173 /* device present, functioning, decoding, not shown in UI */
2174 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2175
2176 crs = aml_resource_template();
2177 aml_append(crs,
2178 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2179 0x01, APPLESMC_MAX_DATA_LENGTH)
2180 );
2181 aml_append(crs, aml_irq_no_flags(6));
2182 aml_append(dev, aml_name_decl("_CRS", crs));
2183
2184 aml_append(scope, dev);
2185 aml_append(dsdt, scope);
2186 }
2187
2188 if (misc->pvpanic_port) {
2189 scope = aml_scope("\\_SB.PCI0.ISA");
2190
2191 dev = aml_device("PEVT");
2192 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2193
2194 crs = aml_resource_template();
2195 aml_append(crs,
2196 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2197 );
2198 aml_append(dev, aml_name_decl("_CRS", crs));
2199
2200 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2201 aml_int(misc->pvpanic_port), 1));
2202 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2203 aml_append(field, aml_named_field("PEPT", 8));
2204 aml_append(dev, field);
2205
2206 /* device present, functioning, decoding, shown in UI */
2207 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2208
2209 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2210 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2211 aml_append(method, aml_return(aml_local(0)));
2212 aml_append(dev, method);
2213
2214 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2215 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2216 aml_append(dev, method);
2217
2218 aml_append(scope, dev);
2219 aml_append(dsdt, scope);
2220 }
2221
2222 sb_scope = aml_scope("\\_SB");
2223 {
2224 Object *pci_host;
2225 PCIBus *bus = NULL;
2226
2227 pci_host = acpi_get_i386_pci_host();
2228 if (pci_host) {
2229 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2230 }
2231
2232 if (bus) {
2233 Aml *scope = aml_scope("PCI0");
2234 /* Scan all PCI buses. Generate tables to support hotplug. */
2235 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2236
2237 if (TPM_IS_TIS(tpm_find())) {
2238 dev = aml_device("ISA.TPM");
2239 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2240 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2241 crs = aml_resource_template();
2242 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2243 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2244 /*
2245 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2246 Rewrite to take IRQ from TPM device model and
2247 fix default IRQ value there to use some unused IRQ
2248 */
2249 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2250 aml_append(dev, aml_name_decl("_CRS", crs));
2251 aml_append(scope, dev);
2252 }
2253
2254 aml_append(sb_scope, scope);
2255 }
2256 }
2257
2258 if (TPM_IS_CRB(tpm_find())) {
2259 dev = aml_device("TPM");
2260 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
2261 crs = aml_resource_template();
2262 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
2263 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
2264 aml_append(dev, aml_name_decl("_CRS", crs));
2265
2266 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
2267 aml_append(method, aml_return(aml_int(0x0f)));
2268 aml_append(dev, method);
2269
2270 aml_append(sb_scope, dev);
2271 }
2272
2273 aml_append(dsdt, sb_scope);
2274
2275 /* copy AML table into ACPI tables blob and patch header there */
2276 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
2277 build_header(linker, table_data,
2278 (void *)(table_data->data + table_data->len - dsdt->buf->len),
2279 "DSDT", dsdt->buf->len, 1, NULL, NULL);
2280 free_aml_allocator();
2281 }
2282
2283 static void
2284 build_hpet(GArray *table_data, BIOSLinker *linker)
2285 {
2286 Acpi20Hpet *hpet;
2287
2288 hpet = acpi_data_push(table_data, sizeof(*hpet));
2289 /* Note timer_block_id value must be kept in sync with value advertised by
2290 * emulated hpet
2291 */
2292 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2293 hpet->addr.address = cpu_to_le64(HPET_BASE);
2294 build_header(linker, table_data,
2295 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
2296 }
2297
2298 static void
2299 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2300 {
2301 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2302 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
2303 unsigned log_addr_offset =
2304 (char *)&tcpa->log_area_start_address - table_data->data;
2305
2306 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2307 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2308 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
2309
2310 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
2311 false /* high memory */);
2312
2313 /* log area start address to be filled by Guest linker */
2314 bios_linker_loader_add_pointer(linker,
2315 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
2316 ACPI_BUILD_TPMLOG_FILE, 0);
2317
2318 build_header(linker, table_data,
2319 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
2320 }
2321
2322 static void
2323 build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2324 {
2325 Acpi20TPM2 *tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2326 unsigned log_addr_size = sizeof(tpm2_ptr->log_area_start_address);
2327 unsigned log_addr_offset =
2328 (char *)&tpm2_ptr->log_area_start_address - table_data->data;
2329
2330 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2331 if (TPM_IS_TIS(tpm_find())) {
2332 tpm2_ptr->control_area_address = cpu_to_le64(0);
2333 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2334 } else if (TPM_IS_CRB(tpm_find())) {
2335 tpm2_ptr->control_area_address = cpu_to_le64(TPM_CRB_ADDR_CTRL);
2336 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_CRB);
2337 } else {
2338 g_warn_if_reached();
2339 }
2340
2341 tpm2_ptr->log_area_minimum_length =
2342 cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2343
2344 /* log area start address to be filled by Guest linker */
2345 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
2346 log_addr_offset, log_addr_size,
2347 ACPI_BUILD_TPMLOG_FILE, 0);
2348 build_header(linker, table_data,
2349 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
2350 }
2351
2352 #define HOLE_640K_START (640 * 1024)
2353 #define HOLE_640K_END (1024 * 1024)
2354
2355 static void
2356 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
2357 {
2358 AcpiSystemResourceAffinityTable *srat;
2359 AcpiSratMemoryAffinity *numamem;
2360
2361 int i;
2362 int srat_start, numa_start, slots;
2363 uint64_t mem_len, mem_base, next_base;
2364 MachineClass *mc = MACHINE_GET_CLASS(machine);
2365 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
2366 PCMachineState *pcms = PC_MACHINE(machine);
2367 ram_addr_t hotplugabble_address_space_size =
2368 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
2369 NULL);
2370
2371 srat_start = table_data->len;
2372
2373 srat = acpi_data_push(table_data, sizeof *srat);
2374 srat->reserved1 = cpu_to_le32(1);
2375
2376 for (i = 0; i < apic_ids->len; i++) {
2377 int node_id = apic_ids->cpus[i].props.node_id;
2378 uint32_t apic_id = apic_ids->cpus[i].arch_id;
2379
2380 if (apic_id < 255) {
2381 AcpiSratProcessorAffinity *core;
2382
2383 core = acpi_data_push(table_data, sizeof *core);
2384 core->type = ACPI_SRAT_PROCESSOR_APIC;
2385 core->length = sizeof(*core);
2386 core->local_apic_id = apic_id;
2387 core->proximity_lo = node_id;
2388 memset(core->proximity_hi, 0, 3);
2389 core->local_sapic_eid = 0;
2390 core->flags = cpu_to_le32(1);
2391 } else {
2392 AcpiSratProcessorX2ApicAffinity *core;
2393
2394 core = acpi_data_push(table_data, sizeof *core);
2395 core->type = ACPI_SRAT_PROCESSOR_x2APIC;
2396 core->length = sizeof(*core);
2397 core->x2apic_id = cpu_to_le32(apic_id);
2398 core->proximity_domain = cpu_to_le32(node_id);
2399 core->flags = cpu_to_le32(1);
2400 }
2401 }
2402
2403
2404 /* the memory map is a bit tricky, it contains at least one hole
2405 * from 640k-1M and possibly another one from 3.5G-4G.
2406 */
2407 next_base = 0;
2408 numa_start = table_data->len;
2409
2410 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2411 mem_base = next_base;
2412 mem_len = pcms->node_mem[i - 1];
2413 next_base = mem_base + mem_len;
2414
2415 /* Cut out the 640K hole */
2416 if (mem_base <= HOLE_640K_START &&
2417 next_base > HOLE_640K_START) {
2418 mem_len -= next_base - HOLE_640K_START;
2419 if (mem_len > 0) {
2420 numamem = acpi_data_push(table_data, sizeof *numamem);
2421 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2422 MEM_AFFINITY_ENABLED);
2423 }
2424
2425 /* Check for the rare case: 640K < RAM < 1M */
2426 if (next_base <= HOLE_640K_END) {
2427 next_base = HOLE_640K_END;
2428 continue;
2429 }
2430 mem_base = HOLE_640K_END;
2431 mem_len = next_base - HOLE_640K_END;
2432 }
2433
2434 /* Cut out the ACPI_PCI hole */
2435 if (mem_base <= pcms->below_4g_mem_size &&
2436 next_base > pcms->below_4g_mem_size) {
2437 mem_len -= next_base - pcms->below_4g_mem_size;
2438 if (mem_len > 0) {
2439 numamem = acpi_data_push(table_data, sizeof *numamem);
2440 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2441 MEM_AFFINITY_ENABLED);
2442 }
2443 mem_base = 1ULL << 32;
2444 mem_len = next_base - pcms->below_4g_mem_size;
2445 next_base = mem_base + mem_len;
2446 }
2447 numamem = acpi_data_push(table_data, sizeof *numamem);
2448 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2449 MEM_AFFINITY_ENABLED);
2450 }
2451 slots = (table_data->len - numa_start) / sizeof *numamem;
2452 for (; slots < pcms->numa_nodes + 2; slots++) {
2453 numamem = acpi_data_push(table_data, sizeof *numamem);
2454 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2455 }
2456
2457 /*
2458 * Entry is required for Windows to enable memory hotplug in OS
2459 * and for Linux to enable SWIOTLB when booted with less than
2460 * 4G of RAM. Windows works better if the entry sets proximity
2461 * to the highest NUMA node in the machine.
2462 * Memory devices may override proximity set by this entry,
2463 * providing _PXM method if necessary.
2464 */
2465 if (hotplugabble_address_space_size) {
2466 numamem = acpi_data_push(table_data, sizeof *numamem);
2467 build_srat_memory(numamem, pcms->hotplug_memory.base,
2468 hotplugabble_address_space_size, pcms->numa_nodes - 1,
2469 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2470 }
2471
2472 build_header(linker, table_data,
2473 (void *)(table_data->data + srat_start),
2474 "SRAT",
2475 table_data->len - srat_start, 1, NULL, NULL);
2476 }
2477
2478 static void
2479 build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info)
2480 {
2481 AcpiTableMcfg *mcfg;
2482 const char *sig;
2483 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2484
2485 mcfg = acpi_data_push(table_data, len);
2486 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2487 /* Only a single allocation so no need to play with segments */
2488 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2489 mcfg->allocation[0].start_bus_number = 0;
2490 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2491
2492 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2493 * To avoid table size changes (which create migration issues),
2494 * always create the table even if there are no allocations,
2495 * but set the signature to a reserved value in this case.
2496 * ACPI spec requires OSPMs to ignore such tables.
2497 */
2498 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
2499 /* Reserved signature: ignored by OSPM */
2500 sig = "QEMU";
2501 } else {
2502 sig = "MCFG";
2503 }
2504 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
2505 }
2506
2507 /*
2508 * VT-d spec 8.1 DMA Remapping Reporting Structure
2509 * (version Oct. 2014 or later)
2510 */
2511 static void
2512 build_dmar_q35(GArray *table_data, BIOSLinker *linker)
2513 {
2514 int dmar_start = table_data->len;
2515
2516 AcpiTableDmar *dmar;
2517 AcpiDmarHardwareUnit *drhd;
2518 AcpiDmarRootPortATS *atsr;
2519 uint8_t dmar_flags = 0;
2520 X86IOMMUState *iommu = x86_iommu_get_default();
2521 AcpiDmarDeviceScope *scope = NULL;
2522 /* Root complex IOAPIC use one path[0] only */
2523 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
2524 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2525
2526 assert(iommu);
2527 if (iommu->intr_supported) {
2528 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2529 }
2530
2531 dmar = acpi_data_push(table_data, sizeof(*dmar));
2532 dmar->host_address_width = intel_iommu->aw_bits - 1;
2533 dmar->flags = dmar_flags;
2534
2535 /* DMAR Remapping Hardware Unit Definition structure */
2536 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
2537 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2538 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
2539 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2540 drhd->pci_segment = cpu_to_le16(0);
2541 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2542
2543 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2544 * 8.3.1 (version Oct. 2014 or later). */
2545 scope = &drhd->scope[0];
2546 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
2547 scope->length = ioapic_scope_size;
2548 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2549 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
2550 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
2551 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
2552
2553 if (iommu->dt_supported) {
2554 atsr = acpi_data_push(table_data, sizeof(*atsr));
2555 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
2556 atsr->length = cpu_to_le16(sizeof(*atsr));
2557 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
2558 atsr->pci_segment = cpu_to_le16(0);
2559 }
2560
2561 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2562 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2563 }
2564 /*
2565 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2566 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2567 */
2568 static void
2569 build_amd_iommu(GArray *table_data, BIOSLinker *linker)
2570 {
2571 int iommu_start = table_data->len;
2572 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2573
2574 /* IVRS header */
2575 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2576 /* IVinfo - IO virtualization information common to all
2577 * IOMMU units in a system
2578 */
2579 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2580 /* reserved */
2581 build_append_int_noprefix(table_data, 0, 8);
2582
2583 /* IVHD definition - type 10h */
2584 build_append_int_noprefix(table_data, 0x10, 1);
2585 /* virtualization flags */
2586 build_append_int_noprefix(table_data,
2587 (1UL << 0) | /* HtTunEn */
2588 (1UL << 4) | /* iotblSup */
2589 (1UL << 6) | /* PrefSup */
2590 (1UL << 7), /* PPRSup */
2591 1);
2592 /* IVHD length */
2593 build_append_int_noprefix(table_data, 0x24, 2);
2594 /* DeviceID */
2595 build_append_int_noprefix(table_data, s->devid, 2);
2596 /* Capability offset */
2597 build_append_int_noprefix(table_data, s->capab_offset, 2);
2598 /* IOMMU base address */
2599 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2600 /* PCI Segment Group */
2601 build_append_int_noprefix(table_data, 0, 2);
2602 /* IOMMU info */
2603 build_append_int_noprefix(table_data, 0, 2);
2604 /* IOMMU Feature Reporting */
2605 build_append_int_noprefix(table_data,
2606 (48UL << 30) | /* HATS */
2607 (48UL << 28) | /* GATS */
2608 (1UL << 2), /* GTSup */
2609 4);
2610 /*
2611 * Type 1 device entry reporting all devices
2612 * These are 4-byte device entries currently reporting the range of
2613 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2614 */
2615 build_append_int_noprefix(table_data, 0x0000001, 4);
2616
2617 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2618 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2619 }
2620
2621 static GArray *
2622 build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset)
2623 {
2624 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2625 unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address);
2626 unsigned rsdt_pa_offset =
2627 (char *)&rsdp->rsdt_physical_address - rsdp_table->data;
2628
2629 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16,
2630 true /* fseg memory */);
2631
2632 memcpy(&rsdp->signature, "RSD PTR ", 8);
2633 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
2634 /* Address to be filled by Guest linker */
2635 bios_linker_loader_add_pointer(linker,
2636 ACPI_BUILD_RSDP_FILE, rsdt_pa_offset, rsdt_pa_size,
2637 ACPI_BUILD_TABLE_FILE, rsdt_tbl_offset);
2638
2639 /* Checksum to be filled by Guest linker */
2640 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
2641 (char *)rsdp - rsdp_table->data, sizeof *rsdp,
2642 (char *)&rsdp->checksum - rsdp_table->data);
2643
2644 return rsdp_table;
2645 }
2646
2647 typedef
2648 struct AcpiBuildState {
2649 /* Copy of table in RAM (for patching). */
2650 MemoryRegion *table_mr;
2651 /* Is table patched? */
2652 uint8_t patched;
2653 void *rsdp;
2654 MemoryRegion *rsdp_mr;
2655 MemoryRegion *linker_mr;
2656 } AcpiBuildState;
2657
2658 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2659 {
2660 Object *pci_host;
2661 QObject *o;
2662
2663 pci_host = acpi_get_i386_pci_host();
2664 g_assert(pci_host);
2665
2666 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2667 if (!o) {
2668 return false;
2669 }
2670 mcfg->mcfg_base = qnum_get_uint(qobject_to_qnum(o));
2671 qobject_decref(o);
2672
2673 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2674 assert(o);
2675 mcfg->mcfg_size = qnum_get_uint(qobject_to_qnum(o));
2676 qobject_decref(o);
2677 return true;
2678 }
2679
2680 static
2681 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2682 {
2683 PCMachineState *pcms = PC_MACHINE(machine);
2684 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2685 GArray *table_offsets;
2686 unsigned facs, dsdt, rsdt, fadt;
2687 AcpiPmInfo pm;
2688 AcpiMiscInfo misc;
2689 AcpiMcfgInfo mcfg;
2690 Range pci_hole, pci_hole64;
2691 uint8_t *u;
2692 size_t aml_len = 0;
2693 GArray *tables_blob = tables->table_data;
2694 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2695 Object *vmgenid_dev;
2696
2697 acpi_get_pm_info(&pm);
2698 acpi_get_misc_info(&misc);
2699 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2700 acpi_get_slic_oem(&slic_oem);
2701
2702 table_offsets = g_array_new(false, true /* clear */,
2703 sizeof(uint32_t));
2704 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2705
2706 bios_linker_loader_alloc(tables->linker,
2707 ACPI_BUILD_TABLE_FILE, tables_blob,
2708 64 /* Ensure FACS is aligned */,
2709 false /* high memory */);
2710
2711 /*
2712 * FACS is pointed to by FADT.
2713 * We place it first since it's the only table that has alignment
2714 * requirements.
2715 */
2716 facs = tables_blob->len;
2717 build_facs(tables_blob, tables->linker);
2718
2719 /* DSDT is pointed to by FADT */
2720 dsdt = tables_blob->len;
2721 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2722 &pci_hole, &pci_hole64, machine);
2723
2724 /* Count the size of the DSDT and SSDT, we will need it for legacy
2725 * sizing of ACPI tables.
2726 */
2727 aml_len += tables_blob->len - dsdt;
2728
2729 /* ACPI tables pointed to by RSDT */
2730 fadt = tables_blob->len;
2731 acpi_add_table(table_offsets, tables_blob);
2732 pm.fadt.facs_tbl_offset = &facs;
2733 pm.fadt.dsdt_tbl_offset = &dsdt;
2734 pm.fadt.xdsdt_tbl_offset = &dsdt;
2735 build_fadt(tables_blob, tables->linker, &pm.fadt,
2736 slic_oem.id, slic_oem.table_id);
2737 aml_len += tables_blob->len - fadt;
2738
2739 acpi_add_table(table_offsets, tables_blob);
2740 build_madt(tables_blob, tables->linker, pcms);
2741
2742 vmgenid_dev = find_vmgenid_dev();
2743 if (vmgenid_dev) {
2744 acpi_add_table(table_offsets, tables_blob);
2745 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2746 tables->vmgenid, tables->linker);
2747 }
2748
2749 if (misc.has_hpet) {
2750 acpi_add_table(table_offsets, tables_blob);
2751 build_hpet(tables_blob, tables->linker);
2752 }
2753 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2754 acpi_add_table(table_offsets, tables_blob);
2755 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2756
2757 if (misc.tpm_version == TPM_VERSION_2_0) {
2758 acpi_add_table(table_offsets, tables_blob);
2759 build_tpm2(tables_blob, tables->linker, tables->tcpalog);
2760 }
2761 }
2762 if (pcms->numa_nodes) {
2763 acpi_add_table(table_offsets, tables_blob);
2764 build_srat(tables_blob, tables->linker, machine);
2765 if (have_numa_distance) {
2766 acpi_add_table(table_offsets, tables_blob);
2767 build_slit(tables_blob, tables->linker);
2768 }
2769 }
2770 if (acpi_get_mcfg(&mcfg)) {
2771 acpi_add_table(table_offsets, tables_blob);
2772 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2773 }
2774 if (x86_iommu_get_default()) {
2775 IommuType IOMMUType = x86_iommu_get_type();
2776 if (IOMMUType == TYPE_AMD) {
2777 acpi_add_table(table_offsets, tables_blob);
2778 build_amd_iommu(tables_blob, tables->linker);
2779 } else if (IOMMUType == TYPE_INTEL) {
2780 acpi_add_table(table_offsets, tables_blob);
2781 build_dmar_q35(tables_blob, tables->linker);
2782 }
2783 }
2784 if (pcms->acpi_nvdimm_state.is_enabled) {
2785 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2786 &pcms->acpi_nvdimm_state, machine->ram_slots);
2787 }
2788
2789 /* Add tables supplied by user (if any) */
2790 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2791 unsigned len = acpi_table_len(u);
2792
2793 acpi_add_table(table_offsets, tables_blob);
2794 g_array_append_vals(tables_blob, u, len);
2795 }
2796
2797 /* RSDT is pointed to by RSDP */
2798 rsdt = tables_blob->len;
2799 build_rsdt(tables_blob, tables->linker, table_offsets,
2800 slic_oem.id, slic_oem.table_id);
2801
2802 /* RSDP is in FSEG memory, so allocate it separately */
2803 build_rsdp(tables->rsdp, tables->linker, rsdt);
2804
2805 /* We'll expose it all to Guest so we want to reduce
2806 * chance of size changes.
2807 *
2808 * We used to align the tables to 4k, but of course this would
2809 * too simple to be enough. 4k turned out to be too small an
2810 * alignment very soon, and in fact it is almost impossible to
2811 * keep the table size stable for all (max_cpus, max_memory_slots)
2812 * combinations. So the table size is always 64k for pc-i440fx-2.1
2813 * and we give an error if the table grows beyond that limit.
2814 *
2815 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2816 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2817 * than 2.0 and we can always pad the smaller tables with zeros. We can
2818 * then use the exact size of the 2.0 tables.
2819 *
2820 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2821 */
2822 if (pcmc->legacy_acpi_table_size) {
2823 /* Subtracting aml_len gives the size of fixed tables. Then add the
2824 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2825 */
2826 int legacy_aml_len =
2827 pcmc->legacy_acpi_table_size +
2828 ACPI_BUILD_LEGACY_CPU_AML_SIZE * pcms->apic_id_limit;
2829 int legacy_table_size =
2830 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2831 ACPI_BUILD_ALIGN_SIZE);
2832 if (tables_blob->len > legacy_table_size) {
2833 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2834 warn_report("ACPI table size %u exceeds %d bytes,"
2835 " migration may not work",
2836 tables_blob->len, legacy_table_size);
2837 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2838 " or PCI bridges.");
2839 }
2840 g_array_set_size(tables_blob, legacy_table_size);
2841 } else {
2842 /* Make sure we have a buffer in case we need to resize the tables. */
2843 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2844 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2845 warn_report("ACPI table size %u exceeds %d bytes,"
2846 " migration may not work",
2847 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2848 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2849 " or PCI bridges.");
2850 }
2851 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2852 }
2853
2854 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2855
2856 /* Cleanup memory that's no longer used. */
2857 g_array_free(table_offsets, true);
2858 }
2859
2860 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2861 {
2862 uint32_t size = acpi_data_len(data);
2863
2864 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2865 memory_region_ram_resize(mr, size, &error_abort);
2866
2867 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2868 memory_region_set_dirty(mr, 0, size);
2869 }
2870
2871 static void acpi_build_update(void *build_opaque)
2872 {
2873 AcpiBuildState *build_state = build_opaque;
2874 AcpiBuildTables tables;
2875
2876 /* No state to update or already patched? Nothing to do. */
2877 if (!build_state || build_state->patched) {
2878 return;
2879 }
2880 build_state->patched = 1;
2881
2882 acpi_build_tables_init(&tables);
2883
2884 acpi_build(&tables, MACHINE(qdev_get_machine()));
2885
2886 acpi_ram_update(build_state->table_mr, tables.table_data);
2887
2888 if (build_state->rsdp) {
2889 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2890 } else {
2891 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2892 }
2893
2894 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2895 acpi_build_tables_cleanup(&tables, true);
2896 }
2897
2898 static void acpi_build_reset(void *build_opaque)
2899 {
2900 AcpiBuildState *build_state = build_opaque;
2901 build_state->patched = 0;
2902 }
2903
2904 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2905 GArray *blob, const char *name,
2906 uint64_t max_size)
2907 {
2908 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2909 name, acpi_build_update, build_state, NULL, true);
2910 }
2911
2912 static const VMStateDescription vmstate_acpi_build = {
2913 .name = "acpi_build",
2914 .version_id = 1,
2915 .minimum_version_id = 1,
2916 .fields = (VMStateField[]) {
2917 VMSTATE_UINT8(patched, AcpiBuildState),
2918 VMSTATE_END_OF_LIST()
2919 },
2920 };
2921
2922 void acpi_setup(void)
2923 {
2924 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2925 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2926 AcpiBuildTables tables;
2927 AcpiBuildState *build_state;
2928 Object *vmgenid_dev;
2929
2930 if (!pcms->fw_cfg) {
2931 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2932 return;
2933 }
2934
2935 if (!pcms->acpi_build_enabled) {
2936 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2937 return;
2938 }
2939
2940 if (!acpi_enabled) {
2941 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2942 return;
2943 }
2944
2945 build_state = g_malloc0(sizeof *build_state);
2946
2947 acpi_build_tables_init(&tables);
2948 acpi_build(&tables, MACHINE(pcms));
2949
2950 /* Now expose it all to Guest */
2951 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
2952 ACPI_BUILD_TABLE_FILE,
2953 ACPI_BUILD_TABLE_MAX_SIZE);
2954 assert(build_state->table_mr != NULL);
2955
2956 build_state->linker_mr =
2957 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
2958 "etc/table-loader", 0);
2959
2960 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2961 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2962
2963 vmgenid_dev = find_vmgenid_dev();
2964 if (vmgenid_dev) {
2965 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), pcms->fw_cfg,
2966 tables.vmgenid);
2967 }
2968
2969 if (!pcmc->rsdp_in_ram) {
2970 /*
2971 * Keep for compatibility with old machine types.
2972 * Though RSDP is small, its contents isn't immutable, so
2973 * we'll update it along with the rest of tables on guest access.
2974 */
2975 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2976
2977 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2978 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2979 acpi_build_update, NULL, build_state,
2980 build_state->rsdp, rsdp_size, true);
2981 build_state->rsdp_mr = NULL;
2982 } else {
2983 build_state->rsdp = NULL;
2984 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
2985 ACPI_BUILD_RSDP_FILE, 0);
2986 }
2987
2988 qemu_register_reset(acpi_build_reset, build_state);
2989 acpi_build_reset(build_state);
2990 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2991
2992 /* Cleanup tables but don't free the memory: we track it
2993 * in build_state.
2994 */
2995 acpi_build_tables_cleanup(&tables, false);
2996 }
QEMU mirror