1 /* Support for generating ACPI tables and passing them to Guests
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
7 * Author: Michael S. Tsirkin <mst@redhat.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "acpi-build.h"
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
31 #include "hw/i386/pc.h"
32 #include "target/i386/cpu.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/acpi/cpu.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "sysemu/tpm_backend.h"
47 #include "hw/timer/mc146818rtc_regs.h"
48 #include "sysemu/numa.h"
50 /* Supported chipsets: */
51 #include "hw/acpi/piix4.h"
52 #include "hw/acpi/pcihp.h"
53 #include "hw/i386/ich9.h"
54 #include "hw/pci/pci_bus.h"
55 #include "hw/pci-host/q35.h"
56 #include "hw/i386/x86-iommu.h"
58 #include "hw/acpi/aml-build.h"
60 #include "qapi/qmp/qint.h"
61 #include "qom/qom-qobject.h"
62 #include "hw/i386/amd_iommu.h"
63 #include "hw/i386/intel_iommu.h"
65 #include "hw/acpi/ipmi.h"
67 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
68 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
69 * a little bit, there should be plenty of free space since the DSDT
70 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
72 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
73 #define ACPI_BUILD_ALIGN_SIZE 0x1000
75 #define ACPI_BUILD_TABLE_SIZE 0x20000
77 /* #define DEBUG_ACPI_BUILD */
78 #ifdef DEBUG_ACPI_BUILD
79 #define ACPI_BUILD_DPRINTF(fmt, ...) \
80 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
82 #define ACPI_BUILD_DPRINTF(fmt, ...)
85 /* Default IOAPIC ID */
86 #define ACPI_BUILD_IOAPIC_ID 0x0
88 typedef struct AcpiMcfgInfo
{
93 typedef struct AcpiPmInfo
{
99 uint8_t acpi_enable_cmd
;
100 uint8_t acpi_disable_cmd
;
102 uint32_t gpe0_blk_len
;
104 uint16_t cpu_hp_io_base
;
105 uint16_t pcihp_io_base
;
106 uint16_t pcihp_io_len
;
109 typedef struct AcpiMiscInfo
{
112 TPMVersion tpm_version
;
113 const unsigned char *dsdt_code
;
115 uint16_t pvpanic_port
;
116 uint16_t applesmc_io_base
;
119 typedef struct AcpiBuildPciBusHotplugState
{
120 GArray
*device_table
;
121 GArray
*notify_table
;
122 struct AcpiBuildPciBusHotplugState
*parent
;
123 bool pcihp_bridge_en
;
124 } AcpiBuildPciBusHotplugState
;
126 static void acpi_get_pm_info(AcpiPmInfo
*pm
)
128 Object
*piix
= piix4_pm_find();
129 Object
*lpc
= ich9_lpc_find();
133 pm
->cpu_hp_io_base
= 0;
134 pm
->pcihp_io_base
= 0;
135 pm
->pcihp_io_len
= 0;
138 pm
->cpu_hp_io_base
= PIIX4_CPU_HOTPLUG_IO_BASE
;
140 object_property_get_int(obj
, ACPI_PCIHP_IO_BASE_PROP
, NULL
);
142 object_property_get_int(obj
, ACPI_PCIHP_IO_LEN_PROP
, NULL
);
146 pm
->cpu_hp_io_base
= ICH9_CPU_HOTPLUG_IO_BASE
;
150 /* Fill in optional s3/s4 related properties */
151 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S3_DISABLED
, NULL
);
153 pm
->s3_disabled
= qint_get_int(qobject_to_qint(o
));
155 pm
->s3_disabled
= false;
158 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_DISABLED
, NULL
);
160 pm
->s4_disabled
= qint_get_int(qobject_to_qint(o
));
162 pm
->s4_disabled
= false;
165 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_VAL
, NULL
);
167 pm
->s4_val
= qint_get_int(qobject_to_qint(o
));
173 /* Fill in mandatory properties */
174 pm
->sci_int
= object_property_get_int(obj
, ACPI_PM_PROP_SCI_INT
, NULL
);
176 pm
->acpi_enable_cmd
= object_property_get_int(obj
,
177 ACPI_PM_PROP_ACPI_ENABLE_CMD
,
179 pm
->acpi_disable_cmd
= object_property_get_int(obj
,
180 ACPI_PM_PROP_ACPI_DISABLE_CMD
,
182 pm
->io_base
= object_property_get_int(obj
, ACPI_PM_PROP_PM_IO_BASE
,
184 pm
->gpe0_blk
= object_property_get_int(obj
, ACPI_PM_PROP_GPE0_BLK
,
186 pm
->gpe0_blk_len
= object_property_get_int(obj
, ACPI_PM_PROP_GPE0_BLK_LEN
,
188 pm
->pcihp_bridge_en
=
189 object_property_get_bool(obj
, "acpi-pci-hotplug-with-bridge-support",
193 static void acpi_get_misc_info(AcpiMiscInfo
*info
)
195 Object
*piix
= piix4_pm_find();
196 Object
*lpc
= ich9_lpc_find();
197 assert(!!piix
!= !!lpc
);
200 info
->is_piix4
= true;
203 info
->is_piix4
= false;
206 info
->has_hpet
= hpet_find();
207 info
->tpm_version
= tpm_get_version();
208 info
->pvpanic_port
= pvpanic_port();
209 info
->applesmc_io_base
= applesmc_port();
213 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
214 * On i386 arch we only have two pci hosts, so we can look only for them.
216 static Object
*acpi_get_i386_pci_host(void)
220 host
= OBJECT_CHECK(PCIHostState
,
221 object_resolve_path("/machine/i440fx", NULL
),
222 TYPE_PCI_HOST_BRIDGE
);
224 host
= OBJECT_CHECK(PCIHostState
,
225 object_resolve_path("/machine/q35", NULL
),
226 TYPE_PCI_HOST_BRIDGE
);
232 static void acpi_get_pci_holes(Range
*hole
, Range
*hole64
)
236 pci_host
= acpi_get_i386_pci_host();
239 range_set_bounds1(hole
,
240 object_property_get_int(pci_host
,
241 PCI_HOST_PROP_PCI_HOLE_START
,
243 object_property_get_int(pci_host
,
244 PCI_HOST_PROP_PCI_HOLE_END
,
246 range_set_bounds1(hole64
,
247 object_property_get_int(pci_host
,
248 PCI_HOST_PROP_PCI_HOLE64_START
,
250 object_property_get_int(pci_host
,
251 PCI_HOST_PROP_PCI_HOLE64_END
,
255 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
257 static void acpi_align_size(GArray
*blob
, unsigned align
)
259 /* Align size to multiple of given size. This reduces the chance
260 * we need to change size in the future (breaking cross version migration).
262 g_array_set_size(blob
, ROUND_UP(acpi_data_len(blob
), align
));
267 build_facs(GArray
*table_data
, BIOSLinker
*linker
)
269 AcpiFacsDescriptorRev1
*facs
= acpi_data_push(table_data
, sizeof *facs
);
270 memcpy(&facs
->signature
, "FACS", 4);
271 facs
->length
= cpu_to_le32(sizeof(*facs
));
274 /* Load chipset information in FADT */
275 static void fadt_setup(AcpiFadtDescriptorRev3
*fadt
, AcpiPmInfo
*pm
)
279 fadt
->sci_int
= cpu_to_le16(pm
->sci_int
);
280 fadt
->smi_cmd
= cpu_to_le32(ACPI_PORT_SMI_CMD
);
281 fadt
->acpi_enable
= pm
->acpi_enable_cmd
;
282 fadt
->acpi_disable
= pm
->acpi_disable_cmd
;
283 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
284 fadt
->pm1a_evt_blk
= cpu_to_le32(pm
->io_base
);
285 fadt
->pm1a_cnt_blk
= cpu_to_le32(pm
->io_base
+ 0x04);
286 fadt
->pm_tmr_blk
= cpu_to_le32(pm
->io_base
+ 0x08);
287 fadt
->gpe0_blk
= cpu_to_le32(pm
->gpe0_blk
);
288 /* EVT, CNT, TMR length matches hw/acpi/core.c */
289 fadt
->pm1_evt_len
= 4;
290 fadt
->pm1_cnt_len
= 2;
291 fadt
->pm_tmr_len
= 4;
292 fadt
->gpe0_blk_len
= pm
->gpe0_blk_len
;
293 fadt
->plvl2_lat
= cpu_to_le16(0xfff); /* C2 state not supported */
294 fadt
->plvl3_lat
= cpu_to_le16(0xfff); /* C3 state not supported */
295 fadt
->flags
= cpu_to_le32((1 << ACPI_FADT_F_WBINVD
) |
296 (1 << ACPI_FADT_F_PROC_C1
) |
297 (1 << ACPI_FADT_F_SLP_BUTTON
) |
298 (1 << ACPI_FADT_F_RTC_S4
));
299 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK
);
300 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
301 * For more than 8 CPUs, "Clustered Logical" mode has to be used
304 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL
);
306 fadt
->century
= RTC_CENTURY
;
308 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_RESET_REG_SUP
);
309 fadt
->reset_value
= 0xf;
310 fadt
->reset_register
.space_id
= AML_SYSTEM_IO
;
311 fadt
->reset_register
.bit_width
= 8;
312 fadt
->reset_register
.address
= cpu_to_le64(ICH9_RST_CNT_IOPORT
);
313 /* The above need not be conditional on machine type because the reset port
314 * happens to be the same on PIIX (pc) and ICH9 (q35). */
315 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT
!= RCR_IOPORT
);
317 fadt
->xpm1a_event_block
.space_id
= AML_SYSTEM_IO
;
318 fadt
->xpm1a_event_block
.bit_width
= fadt
->pm1_evt_len
* 8;
319 fadt
->xpm1a_event_block
.address
= cpu_to_le64(pm
->io_base
);
321 fadt
->xpm1a_control_block
.space_id
= AML_SYSTEM_IO
;
322 fadt
->xpm1a_control_block
.bit_width
= fadt
->pm1_cnt_len
* 8;
323 fadt
->xpm1a_control_block
.address
= cpu_to_le64(pm
->io_base
+ 0x4);
325 fadt
->xpm_timer_block
.space_id
= AML_SYSTEM_IO
;
326 fadt
->xpm_timer_block
.bit_width
= fadt
->pm_tmr_len
* 8;
327 fadt
->xpm_timer_block
.address
= cpu_to_le64(pm
->io_base
+ 0x8);
329 fadt
->xgpe0_block
.space_id
= AML_SYSTEM_IO
;
330 fadt
->xgpe0_block
.bit_width
= pm
->gpe0_blk_len
* 8;
331 fadt
->xgpe0_block
.address
= cpu_to_le64(pm
->gpe0_blk
);
337 build_fadt(GArray
*table_data
, BIOSLinker
*linker
, AcpiPmInfo
*pm
,
338 unsigned facs_tbl_offset
, unsigned dsdt_tbl_offset
,
339 const char *oem_id
, const char *oem_table_id
)
341 AcpiFadtDescriptorRev3
*fadt
= acpi_data_push(table_data
, sizeof(*fadt
));
342 unsigned fw_ctrl_offset
= (char *)&fadt
->firmware_ctrl
- table_data
->data
;
343 unsigned dsdt_entry_offset
= (char *)&fadt
->dsdt
- table_data
->data
;
344 unsigned xdsdt_entry_offset
= (char *)&fadt
->x_dsdt
- table_data
->data
;
346 /* FACS address to be filled by Guest linker */
347 bios_linker_loader_add_pointer(linker
,
348 ACPI_BUILD_TABLE_FILE
, fw_ctrl_offset
, sizeof(fadt
->firmware_ctrl
),
349 ACPI_BUILD_TABLE_FILE
, facs_tbl_offset
);
351 /* DSDT address to be filled by Guest linker */
352 fadt_setup(fadt
, pm
);
353 bios_linker_loader_add_pointer(linker
,
354 ACPI_BUILD_TABLE_FILE
, dsdt_entry_offset
, sizeof(fadt
->dsdt
),
355 ACPI_BUILD_TABLE_FILE
, dsdt_tbl_offset
);
356 bios_linker_loader_add_pointer(linker
,
357 ACPI_BUILD_TABLE_FILE
, xdsdt_entry_offset
, sizeof(fadt
->x_dsdt
),
358 ACPI_BUILD_TABLE_FILE
, dsdt_tbl_offset
);
360 build_header(linker
, table_data
,
361 (void *)fadt
, "FACP", sizeof(*fadt
), 3, oem_id
, oem_table_id
);
364 void pc_madt_cpu_entry(AcpiDeviceIf
*adev
, int uid
,
365 const CPUArchIdList
*apic_ids
, GArray
*entry
)
367 uint32_t apic_id
= apic_ids
->cpus
[uid
].arch_id
;
369 /* ACPI spec says that LAPIC entry for non present
370 * CPU may be omitted from MADT or it must be marked
371 * as disabled. However omitting non present CPU from
372 * MADT breaks hotplug on linux. So possible CPUs
373 * should be put in MADT but kept disabled.
376 AcpiMadtProcessorApic
*apic
= acpi_data_push(entry
, sizeof *apic
);
378 apic
->type
= ACPI_APIC_PROCESSOR
;
379 apic
->length
= sizeof(*apic
);
380 apic
->processor_id
= uid
;
381 apic
->local_apic_id
= apic_id
;
382 if (apic_ids
->cpus
[uid
].cpu
!= NULL
) {
383 apic
->flags
= cpu_to_le32(1);
385 apic
->flags
= cpu_to_le32(0);
388 AcpiMadtProcessorX2Apic
*apic
= acpi_data_push(entry
, sizeof *apic
);
390 apic
->type
= ACPI_APIC_LOCAL_X2APIC
;
391 apic
->length
= sizeof(*apic
);
392 apic
->uid
= cpu_to_le32(uid
);
393 apic
->x2apic_id
= cpu_to_le32(apic_id
);
394 if (apic_ids
->cpus
[uid
].cpu
!= NULL
) {
395 apic
->flags
= cpu_to_le32(1);
397 apic
->flags
= cpu_to_le32(0);
403 build_madt(GArray
*table_data
, BIOSLinker
*linker
, PCMachineState
*pcms
)
405 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
406 const CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(MACHINE(pcms
));
407 int madt_start
= table_data
->len
;
408 AcpiDeviceIfClass
*adevc
= ACPI_DEVICE_IF_GET_CLASS(pcms
->acpi_dev
);
409 AcpiDeviceIf
*adev
= ACPI_DEVICE_IF(pcms
->acpi_dev
);
410 bool x2apic_mode
= false;
412 AcpiMultipleApicTable
*madt
;
413 AcpiMadtIoApic
*io_apic
;
414 AcpiMadtIntsrcovr
*intsrcovr
;
417 madt
= acpi_data_push(table_data
, sizeof *madt
);
418 madt
->local_apic_address
= cpu_to_le32(APIC_DEFAULT_ADDRESS
);
419 madt
->flags
= cpu_to_le32(1);
421 for (i
= 0; i
< apic_ids
->len
; i
++) {
422 adevc
->madt_cpu(adev
, i
, apic_ids
, table_data
);
423 if (apic_ids
->cpus
[i
].arch_id
> 254) {
428 io_apic
= acpi_data_push(table_data
, sizeof *io_apic
);
429 io_apic
->type
= ACPI_APIC_IO
;
430 io_apic
->length
= sizeof(*io_apic
);
431 io_apic
->io_apic_id
= ACPI_BUILD_IOAPIC_ID
;
432 io_apic
->address
= cpu_to_le32(IO_APIC_DEFAULT_ADDRESS
);
433 io_apic
->interrupt
= cpu_to_le32(0);
435 if (pcms
->apic_xrupt_override
) {
436 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
437 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
438 intsrcovr
->length
= sizeof(*intsrcovr
);
439 intsrcovr
->source
= 0;
440 intsrcovr
->gsi
= cpu_to_le32(2);
441 intsrcovr
->flags
= cpu_to_le16(0); /* conforms to bus specifications */
443 for (i
= 1; i
< 16; i
++) {
444 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
445 if (!(ACPI_BUILD_PCI_IRQS
& (1 << i
))) {
446 /* No need for a INT source override structure. */
449 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
450 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
451 intsrcovr
->length
= sizeof(*intsrcovr
);
452 intsrcovr
->source
= i
;
453 intsrcovr
->gsi
= cpu_to_le32(i
);
454 intsrcovr
->flags
= cpu_to_le16(0xd); /* active high, level triggered */
458 AcpiMadtLocalX2ApicNmi
*local_nmi
;
460 local_nmi
= acpi_data_push(table_data
, sizeof *local_nmi
);
461 local_nmi
->type
= ACPI_APIC_LOCAL_X2APIC_NMI
;
462 local_nmi
->length
= sizeof(*local_nmi
);
463 local_nmi
->uid
= 0xFFFFFFFF; /* all processors */
464 local_nmi
->flags
= cpu_to_le16(0);
465 local_nmi
->lint
= 1; /* ACPI_LINT1 */
467 AcpiMadtLocalNmi
*local_nmi
;
469 local_nmi
= acpi_data_push(table_data
, sizeof *local_nmi
);
470 local_nmi
->type
= ACPI_APIC_LOCAL_NMI
;
471 local_nmi
->length
= sizeof(*local_nmi
);
472 local_nmi
->processor_id
= 0xff; /* all processors */
473 local_nmi
->flags
= cpu_to_le16(0);
474 local_nmi
->lint
= 1; /* ACPI_LINT1 */
477 build_header(linker
, table_data
,
478 (void *)(table_data
->data
+ madt_start
), "APIC",
479 table_data
->len
- madt_start
, 1, NULL
, NULL
);
482 /* Assign BSEL property to all buses. In the future, this can be changed
483 * to only assign to buses that support hotplug.
485 static void *acpi_set_bsel(PCIBus
*bus
, void *opaque
)
487 unsigned *bsel_alloc
= opaque
;
490 if (qbus_is_hotpluggable(BUS(bus
))) {
491 bus_bsel
= g_malloc(sizeof *bus_bsel
);
493 *bus_bsel
= (*bsel_alloc
)++;
494 object_property_add_uint32_ptr(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
,
495 bus_bsel
, &error_abort
);
501 static void acpi_set_pci_info(void)
503 PCIBus
*bus
= find_i440fx(); /* TODO: Q35 support */
504 unsigned bsel_alloc
= ACPI_PCIHP_BSEL_DEFAULT
;
507 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
508 pci_for_each_bus_depth_first(bus
, acpi_set_bsel
, NULL
, &bsel_alloc
);
512 static void build_append_pcihp_notify_entry(Aml
*method
, int slot
)
515 int32_t devfn
= PCI_DEVFN(slot
, 0);
517 if_ctx
= aml_if(aml_and(aml_arg(0), aml_int(0x1U
<< slot
), NULL
));
518 aml_append(if_ctx
, aml_notify(aml_name("S%.02X", devfn
), aml_arg(1)));
519 aml_append(method
, if_ctx
);
522 static void build_append_pci_bus_devices(Aml
*parent_scope
, PCIBus
*bus
,
523 bool pcihp_bridge_en
)
525 Aml
*dev
, *notify_method
, *method
;
530 bsel
= object_property_get_qobject(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
, NULL
);
532 int64_t bsel_val
= qint_get_int(qobject_to_qint(bsel
));
534 aml_append(parent_scope
, aml_name_decl("BSEL", aml_int(bsel_val
)));
535 notify_method
= aml_method("DVNT", 2, AML_NOTSERIALIZED
);
538 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); i
+= PCI_FUNC_MAX
) {
541 PCIDevice
*pdev
= bus
->devices
[i
];
542 int slot
= PCI_SLOT(i
);
543 bool hotplug_enabled_dev
;
547 if (bsel
) { /* add hotplug slots for non present devices */
548 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
549 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
550 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
551 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
553 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
555 aml_append(dev
, method
);
556 aml_append(parent_scope
, dev
);
558 build_append_pcihp_notify_entry(notify_method
, slot
);
563 pc
= PCI_DEVICE_GET_CLASS(pdev
);
564 dc
= DEVICE_GET_CLASS(pdev
);
566 /* When hotplug for bridges is enabled, bridges are
567 * described in ACPI separately (see build_pci_bus_end).
568 * In this case they aren't themselves hot-pluggable.
569 * Hotplugged bridges *are* hot-pluggable.
571 bridge_in_acpi
= pc
->is_bridge
&& pcihp_bridge_en
&&
572 !DEVICE(pdev
)->hotplugged
;
574 hotplug_enabled_dev
= bsel
&& dc
->hotpluggable
&& !bridge_in_acpi
;
576 if (pc
->class_id
== PCI_CLASS_BRIDGE_ISA
) {
580 /* start to compose PCI slot descriptor */
581 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
582 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
584 if (pc
->class_id
== PCI_CLASS_DISPLAY_VGA
) {
585 /* add VGA specific AML methods */
588 if (object_dynamic_cast(OBJECT(pdev
), "qxl-vga")) {
594 method
= aml_method("_S1D", 0, AML_NOTSERIALIZED
);
595 aml_append(method
, aml_return(aml_int(0)));
596 aml_append(dev
, method
);
598 method
= aml_method("_S2D", 0, AML_NOTSERIALIZED
);
599 aml_append(method
, aml_return(aml_int(0)));
600 aml_append(dev
, method
);
602 method
= aml_method("_S3D", 0, AML_NOTSERIALIZED
);
603 aml_append(method
, aml_return(aml_int(s3d
)));
604 aml_append(dev
, method
);
605 } else if (hotplug_enabled_dev
) {
606 /* add _SUN/_EJ0 to make slot hotpluggable */
607 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
609 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
611 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
613 aml_append(dev
, method
);
616 build_append_pcihp_notify_entry(notify_method
, slot
);
618 } else if (bridge_in_acpi
) {
620 * device is coldplugged bridge,
621 * add child device descriptions into its scope
623 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
625 build_append_pci_bus_devices(dev
, sec_bus
, pcihp_bridge_en
);
627 /* slot descriptor has been composed, add it into parent context */
628 aml_append(parent_scope
, dev
);
632 aml_append(parent_scope
, notify_method
);
635 /* Append PCNT method to notify about events on local and child buses.
636 * Add unconditionally for root since DSDT expects it.
638 method
= aml_method("PCNT", 0, AML_NOTSERIALIZED
);
640 /* If bus supports hotplug select it and notify about local events */
642 int64_t bsel_val
= qint_get_int(qobject_to_qint(bsel
));
643 aml_append(method
, aml_store(aml_int(bsel_val
), aml_name("BNUM")));
645 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
648 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
652 /* Notify about child bus events in any case */
653 if (pcihp_bridge_en
) {
654 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
655 int32_t devfn
= sec
->parent_dev
->devfn
;
657 if (pci_bus_is_root(sec
) || pci_bus_is_express(sec
)) {
661 aml_append(method
, aml_name("^S%.02X.PCNT", devfn
));
664 aml_append(parent_scope
, method
);
665 qobject_decref(bsel
);
670 * @link_name: link name for PCI route entry
672 * build AML package containing a PCI route entry for @link_name
674 static Aml
*build_prt_entry(const char *link_name
)
676 Aml
*a_zero
= aml_int(0);
677 Aml
*pkg
= aml_package(4);
678 aml_append(pkg
, a_zero
);
679 aml_append(pkg
, a_zero
);
680 aml_append(pkg
, aml_name("%s", link_name
));
681 aml_append(pkg
, a_zero
);
686 * initialize_route - Initialize the interrupt routing rule
687 * through a specific LINK:
688 * if (lnk_idx == idx)
689 * route using link 'link_name'
691 static Aml
*initialize_route(Aml
*route
, const char *link_name
,
692 Aml
*lnk_idx
, int idx
)
694 Aml
*if_ctx
= aml_if(aml_equal(lnk_idx
, aml_int(idx
)));
695 Aml
*pkg
= build_prt_entry(link_name
);
697 aml_append(if_ctx
, aml_store(pkg
, route
));
703 * build_prt - Define interrupt rounting rules
705 * Returns an array of 128 routes, one for each device,
706 * based on device location.
707 * The main goal is to equaly distribute the interrupts
708 * over the 4 existing ACPI links (works only for i440fx).
709 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
712 static Aml
*build_prt(bool is_pci0_prt
)
714 Aml
*method
, *while_ctx
, *pin
, *res
;
716 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
719 aml_append(method
, aml_store(aml_package(128), res
));
720 aml_append(method
, aml_store(aml_int(0), pin
));
722 /* while (pin < 128) */
723 while_ctx
= aml_while(aml_lless(pin
, aml_int(128)));
725 Aml
*slot
= aml_local(2);
726 Aml
*lnk_idx
= aml_local(3);
727 Aml
*route
= aml_local(4);
729 /* slot = pin >> 2 */
730 aml_append(while_ctx
,
731 aml_store(aml_shiftright(pin
, aml_int(2), NULL
), slot
));
732 /* lnk_idx = (slot + pin) & 3 */
733 aml_append(while_ctx
,
734 aml_store(aml_and(aml_add(pin
, slot
, NULL
), aml_int(3), NULL
),
737 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
738 aml_append(while_ctx
, initialize_route(route
, "LNKD", lnk_idx
, 0));
740 Aml
*if_device_1
, *if_pin_4
, *else_pin_4
;
742 /* device 1 is the power-management device, needs SCI */
743 if_device_1
= aml_if(aml_equal(lnk_idx
, aml_int(1)));
745 if_pin_4
= aml_if(aml_equal(pin
, aml_int(4)));
748 aml_store(build_prt_entry("LNKS"), route
));
750 aml_append(if_device_1
, if_pin_4
);
751 else_pin_4
= aml_else();
753 aml_append(else_pin_4
,
754 aml_store(build_prt_entry("LNKA"), route
));
756 aml_append(if_device_1
, else_pin_4
);
758 aml_append(while_ctx
, if_device_1
);
760 aml_append(while_ctx
, initialize_route(route
, "LNKA", lnk_idx
, 1));
762 aml_append(while_ctx
, initialize_route(route
, "LNKB", lnk_idx
, 2));
763 aml_append(while_ctx
, initialize_route(route
, "LNKC", lnk_idx
, 3));
765 /* route[0] = 0x[slot]FFFF */
766 aml_append(while_ctx
,
767 aml_store(aml_or(aml_shiftleft(slot
, aml_int(16)), aml_int(0xFFFF),
769 aml_index(route
, aml_int(0))));
770 /* route[1] = pin & 3 */
771 aml_append(while_ctx
,
772 aml_store(aml_and(pin
, aml_int(3), NULL
),
773 aml_index(route
, aml_int(1))));
774 /* res[pin] = route */
775 aml_append(while_ctx
, aml_store(route
, aml_index(res
, pin
)));
777 aml_append(while_ctx
, aml_increment(pin
));
779 aml_append(method
, while_ctx
);
781 aml_append(method
, aml_return(res
));
786 typedef struct CrsRangeEntry
{
791 static void crs_range_insert(GPtrArray
*ranges
, uint64_t base
, uint64_t limit
)
793 CrsRangeEntry
*entry
;
795 entry
= g_malloc(sizeof(*entry
));
797 entry
->limit
= limit
;
799 g_ptr_array_add(ranges
, entry
);
802 static void crs_range_free(gpointer data
)
804 CrsRangeEntry
*entry
= (CrsRangeEntry
*)data
;
808 typedef struct CrsRangeSet
{
809 GPtrArray
*io_ranges
;
810 GPtrArray
*mem_ranges
;
811 GPtrArray
*mem_64bit_ranges
;
814 static void crs_range_set_init(CrsRangeSet
*range_set
)
816 range_set
->io_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
817 range_set
->mem_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
818 range_set
->mem_64bit_ranges
=
819 g_ptr_array_new_with_free_func(crs_range_free
);
822 static void crs_range_set_free(CrsRangeSet
*range_set
)
824 g_ptr_array_free(range_set
->io_ranges
, true);
825 g_ptr_array_free(range_set
->mem_ranges
, true);
826 g_ptr_array_free(range_set
->mem_64bit_ranges
, true);
829 static gint
crs_range_compare(gconstpointer a
, gconstpointer b
)
831 CrsRangeEntry
*entry_a
= *(CrsRangeEntry
**)a
;
832 CrsRangeEntry
*entry_b
= *(CrsRangeEntry
**)b
;
834 return (int64_t)entry_a
->base
- (int64_t)entry_b
->base
;
838 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
839 * interval, computes the 'free' ranges from the same interval.
840 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
841 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
843 static void crs_replace_with_free_ranges(GPtrArray
*ranges
,
844 uint64_t start
, uint64_t end
)
846 GPtrArray
*free_ranges
= g_ptr_array_new();
847 uint64_t free_base
= start
;
850 g_ptr_array_sort(ranges
, crs_range_compare
);
851 for (i
= 0; i
< ranges
->len
; i
++) {
852 CrsRangeEntry
*used
= g_ptr_array_index(ranges
, i
);
854 if (free_base
< used
->base
) {
855 crs_range_insert(free_ranges
, free_base
, used
->base
- 1);
858 free_base
= used
->limit
+ 1;
861 if (free_base
< end
) {
862 crs_range_insert(free_ranges
, free_base
, end
);
865 g_ptr_array_set_size(ranges
, 0);
866 for (i
= 0; i
< free_ranges
->len
; i
++) {
867 g_ptr_array_add(ranges
, g_ptr_array_index(free_ranges
, i
));
870 g_ptr_array_free(free_ranges
, true);
874 * crs_range_merge - merges adjacent ranges in the given array.
875 * Array elements are deleted and replaced with the merged ranges.
877 static void crs_range_merge(GPtrArray
*range
)
879 GPtrArray
*tmp
= g_ptr_array_new_with_free_func(crs_range_free
);
880 CrsRangeEntry
*entry
;
881 uint64_t range_base
, range_limit
;
888 g_ptr_array_sort(range
, crs_range_compare
);
890 entry
= g_ptr_array_index(range
, 0);
891 range_base
= entry
->base
;
892 range_limit
= entry
->limit
;
893 for (i
= 1; i
< range
->len
; i
++) {
894 entry
= g_ptr_array_index(range
, i
);
895 if (entry
->base
- 1 == range_limit
) {
896 range_limit
= entry
->limit
;
898 crs_range_insert(tmp
, range_base
, range_limit
);
899 range_base
= entry
->base
;
900 range_limit
= entry
->limit
;
903 crs_range_insert(tmp
, range_base
, range_limit
);
905 g_ptr_array_set_size(range
, 0);
906 for (i
= 0; i
< tmp
->len
; i
++) {
907 entry
= g_ptr_array_index(tmp
, i
);
908 crs_range_insert(range
, entry
->base
, entry
->limit
);
910 g_ptr_array_free(tmp
, true);
913 static Aml
*build_crs(PCIHostState
*host
, CrsRangeSet
*range_set
)
915 Aml
*crs
= aml_resource_template();
916 CrsRangeSet temp_range_set
;
917 CrsRangeEntry
*entry
;
918 uint8_t max_bus
= pci_bus_num(host
->bus
);
923 crs_range_set_init(&temp_range_set
);
924 for (devfn
= 0; devfn
< ARRAY_SIZE(host
->bus
->devices
); devfn
++) {
925 uint64_t range_base
, range_limit
;
926 PCIDevice
*dev
= host
->bus
->devices
[devfn
];
932 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
933 PCIIORegion
*r
= &dev
->io_regions
[i
];
935 range_base
= r
->addr
;
936 range_limit
= r
->addr
+ r
->size
- 1;
939 * Work-around for old bioses
940 * that do not support multiple root buses
942 if (!range_base
|| range_base
> range_limit
) {
946 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
947 crs_range_insert(temp_range_set
.io_ranges
,
948 range_base
, range_limit
);
949 } else { /* "memory" */
950 crs_range_insert(temp_range_set
.mem_ranges
,
951 range_base
, range_limit
);
955 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
956 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
957 uint8_t subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
958 if (subordinate
> max_bus
) {
959 max_bus
= subordinate
;
962 range_base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
963 range_limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
966 * Work-around for old bioses
967 * that do not support multiple root buses
969 if (range_base
&& range_base
<= range_limit
) {
970 crs_range_insert(temp_range_set
.io_ranges
,
971 range_base
, range_limit
);
975 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
977 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
980 * Work-around for old bioses
981 * that do not support multiple root buses
983 if (range_base
&& range_base
<= range_limit
) {
984 uint64_t length
= range_limit
- range_base
+ 1;
985 if (range_limit
<= UINT32_MAX
&& length
<= UINT32_MAX
) {
986 crs_range_insert(temp_range_set
.mem_ranges
,
987 range_base
, range_limit
);
989 crs_range_insert(temp_range_set
.mem_64bit_ranges
,
990 range_base
, range_limit
);
995 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
997 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1000 * Work-around for old bioses
1001 * that do not support multiple root buses
1003 if (range_base
&& range_base
<= range_limit
) {
1004 uint64_t length
= range_limit
- range_base
+ 1;
1005 if (range_limit
<= UINT32_MAX
&& length
<= UINT32_MAX
) {
1006 crs_range_insert(temp_range_set
.mem_ranges
,
1007 range_base
, range_limit
);
1009 crs_range_insert(temp_range_set
.mem_64bit_ranges
,
1010 range_base
, range_limit
);
1016 crs_range_merge(temp_range_set
.io_ranges
);
1017 for (i
= 0; i
< temp_range_set
.io_ranges
->len
; i
++) {
1018 entry
= g_ptr_array_index(temp_range_set
.io_ranges
, i
);
1020 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
1021 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
1022 0, entry
->base
, entry
->limit
, 0,
1023 entry
->limit
- entry
->base
+ 1));
1024 crs_range_insert(range_set
->io_ranges
, entry
->base
, entry
->limit
);
1027 crs_range_merge(temp_range_set
.mem_ranges
);
1028 for (i
= 0; i
< temp_range_set
.mem_ranges
->len
; i
++) {
1029 entry
= g_ptr_array_index(temp_range_set
.mem_ranges
, i
);
1031 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
1032 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
1034 0, entry
->base
, entry
->limit
, 0,
1035 entry
->limit
- entry
->base
+ 1));
1036 crs_range_insert(range_set
->mem_ranges
, entry
->base
, entry
->limit
);
1039 crs_range_merge(temp_range_set
.mem_64bit_ranges
);
1040 for (i
= 0; i
< temp_range_set
.mem_64bit_ranges
->len
; i
++) {
1041 entry
= g_ptr_array_index(temp_range_set
.mem_64bit_ranges
, i
);
1043 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
1044 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
1046 0, entry
->base
, entry
->limit
, 0,
1047 entry
->limit
- entry
->base
+ 1));
1048 crs_range_insert(range_set
->mem_64bit_ranges
,
1049 entry
->base
, entry
->limit
);
1052 crs_range_set_free(&temp_range_set
);
1055 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
1057 pci_bus_num(host
->bus
),
1060 max_bus
- pci_bus_num(host
->bus
) + 1));
1065 static void build_hpet_aml(Aml
*table
)
1071 Aml
*scope
= aml_scope("_SB");
1072 Aml
*dev
= aml_device("HPET");
1073 Aml
*zero
= aml_int(0);
1074 Aml
*id
= aml_local(0);
1075 Aml
*period
= aml_local(1);
1077 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1078 aml_append(dev
, aml_name_decl("_UID", zero
));
1081 aml_operation_region("HPTM", AML_SYSTEM_MEMORY
, aml_int(HPET_BASE
),
1083 field
= aml_field("HPTM", AML_DWORD_ACC
, AML_LOCK
, AML_PRESERVE
);
1084 aml_append(field
, aml_named_field("VEND", 32));
1085 aml_append(field
, aml_named_field("PRD", 32));
1086 aml_append(dev
, field
);
1088 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1089 aml_append(method
, aml_store(aml_name("VEND"), id
));
1090 aml_append(method
, aml_store(aml_name("PRD"), period
));
1091 aml_append(method
, aml_shiftright(id
, aml_int(16), id
));
1092 if_ctx
= aml_if(aml_lor(aml_equal(id
, zero
),
1093 aml_equal(id
, aml_int(0xffff))));
1095 aml_append(if_ctx
, aml_return(zero
));
1097 aml_append(method
, if_ctx
);
1099 if_ctx
= aml_if(aml_lor(aml_equal(period
, zero
),
1100 aml_lgreater(period
, aml_int(100000000))));
1102 aml_append(if_ctx
, aml_return(zero
));
1104 aml_append(method
, if_ctx
);
1106 aml_append(method
, aml_return(aml_int(0x0F)));
1107 aml_append(dev
, method
);
1109 crs
= aml_resource_template();
1110 aml_append(crs
, aml_memory32_fixed(HPET_BASE
, HPET_LEN
, AML_READ_ONLY
));
1111 aml_append(dev
, aml_name_decl("_CRS", crs
));
1113 aml_append(scope
, dev
);
1114 aml_append(table
, scope
);
1117 static Aml
*build_fdinfo_aml(int idx
, FloppyDriveType type
)
1120 uint8_t maxc
, maxh
, maxs
;
1122 isa_fdc_get_drive_max_chs(type
, &maxc
, &maxh
, &maxs
);
1124 dev
= aml_device("FLP%c", 'A' + idx
);
1126 aml_append(dev
, aml_name_decl("_ADR", aml_int(idx
)));
1128 fdi
= aml_package(16);
1129 aml_append(fdi
, aml_int(idx
)); /* Drive Number */
1131 aml_int(cmos_get_fd_drive_type(type
))); /* Device Type */
1133 * the values below are the limits of the drive, and are thus independent
1134 * of the inserted media
1136 aml_append(fdi
, aml_int(maxc
)); /* Maximum Cylinder Number */
1137 aml_append(fdi
, aml_int(maxs
)); /* Maximum Sector Number */
1138 aml_append(fdi
, aml_int(maxh
)); /* Maximum Head Number */
1140 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1141 * the drive type, so shall we
1143 aml_append(fdi
, aml_int(0xAF)); /* disk_specify_1 */
1144 aml_append(fdi
, aml_int(0x02)); /* disk_specify_2 */
1145 aml_append(fdi
, aml_int(0x25)); /* disk_motor_wait */
1146 aml_append(fdi
, aml_int(0x02)); /* disk_sector_siz */
1147 aml_append(fdi
, aml_int(0x12)); /* disk_eot */
1148 aml_append(fdi
, aml_int(0x1B)); /* disk_rw_gap */
1149 aml_append(fdi
, aml_int(0xFF)); /* disk_dtl */
1150 aml_append(fdi
, aml_int(0x6C)); /* disk_formt_gap */
1151 aml_append(fdi
, aml_int(0xF6)); /* disk_fill */
1152 aml_append(fdi
, aml_int(0x0F)); /* disk_head_sttl */
1153 aml_append(fdi
, aml_int(0x08)); /* disk_motor_strt */
1155 aml_append(dev
, aml_name_decl("_FDI", fdi
));
1159 static Aml
*build_fdc_device_aml(ISADevice
*fdc
)
1165 #define ACPI_FDE_MAX_FD 4
1166 uint32_t fde_buf
[5] = {
1167 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1168 cpu_to_le32(2) /* tape presence (2 == never present) */
1171 dev
= aml_device("FDC0");
1172 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1174 crs
= aml_resource_template();
1175 aml_append(crs
, aml_io(AML_DECODE16
, 0x03F2, 0x03F2, 0x00, 0x04));
1176 aml_append(crs
, aml_io(AML_DECODE16
, 0x03F7, 0x03F7, 0x00, 0x01));
1177 aml_append(crs
, aml_irq_no_flags(6));
1179 aml_dma(AML_COMPATIBILITY
, AML_NOTBUSMASTER
, AML_TRANSFER8
, 2));
1180 aml_append(dev
, aml_name_decl("_CRS", crs
));
1182 for (i
= 0; i
< MIN(MAX_FD
, ACPI_FDE_MAX_FD
); i
++) {
1183 FloppyDriveType type
= isa_fdc_get_drive_type(fdc
, i
);
1185 if (type
< FLOPPY_DRIVE_TYPE_NONE
) {
1186 fde_buf
[i
] = cpu_to_le32(1); /* drive present */
1187 aml_append(dev
, build_fdinfo_aml(i
, type
));
1190 aml_append(dev
, aml_name_decl("_FDE",
1191 aml_buffer(sizeof(fde_buf
), (uint8_t *)fde_buf
)));
1196 static Aml
*build_rtc_device_aml(void)
1201 dev
= aml_device("RTC");
1202 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1203 crs
= aml_resource_template();
1204 aml_append(crs
, aml_io(AML_DECODE16
, 0x0070, 0x0070, 0x10, 0x02));
1205 aml_append(crs
, aml_irq_no_flags(8));
1206 aml_append(crs
, aml_io(AML_DECODE16
, 0x0072, 0x0072, 0x02, 0x06));
1207 aml_append(dev
, aml_name_decl("_CRS", crs
));
1212 static Aml
*build_kbd_device_aml(void)
1218 dev
= aml_device("KBD");
1219 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1221 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1222 aml_append(method
, aml_return(aml_int(0x0f)));
1223 aml_append(dev
, method
);
1225 crs
= aml_resource_template();
1226 aml_append(crs
, aml_io(AML_DECODE16
, 0x0060, 0x0060, 0x01, 0x01));
1227 aml_append(crs
, aml_io(AML_DECODE16
, 0x0064, 0x0064, 0x01, 0x01));
1228 aml_append(crs
, aml_irq_no_flags(1));
1229 aml_append(dev
, aml_name_decl("_CRS", crs
));
1234 static Aml
*build_mouse_device_aml(void)
1240 dev
= aml_device("MOU");
1241 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1243 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1244 aml_append(method
, aml_return(aml_int(0x0f)));
1245 aml_append(dev
, method
);
1247 crs
= aml_resource_template();
1248 aml_append(crs
, aml_irq_no_flags(12));
1249 aml_append(dev
, aml_name_decl("_CRS", crs
));
1254 static Aml
*build_lpt_device_aml(void)
1261 Aml
*zero
= aml_int(0);
1262 Aml
*is_present
= aml_local(0);
1264 dev
= aml_device("LPT");
1265 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1267 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1268 aml_append(method
, aml_store(aml_name("LPEN"), is_present
));
1269 if_ctx
= aml_if(aml_equal(is_present
, zero
));
1271 aml_append(if_ctx
, aml_return(aml_int(0x00)));
1273 aml_append(method
, if_ctx
);
1274 else_ctx
= aml_else();
1276 aml_append(else_ctx
, aml_return(aml_int(0x0f)));
1278 aml_append(method
, else_ctx
);
1279 aml_append(dev
, method
);
1281 crs
= aml_resource_template();
1282 aml_append(crs
, aml_io(AML_DECODE16
, 0x0378, 0x0378, 0x08, 0x08));
1283 aml_append(crs
, aml_irq_no_flags(7));
1284 aml_append(dev
, aml_name_decl("_CRS", crs
));
1289 static Aml
*build_com_device_aml(uint8_t uid
)
1296 Aml
*zero
= aml_int(0);
1297 Aml
*is_present
= aml_local(0);
1298 const char *enabled_field
= "CAEN";
1300 uint16_t io_port
= 0x03F8;
1302 assert(uid
== 1 || uid
== 2);
1304 enabled_field
= "CBEN";
1309 dev
= aml_device("COM%d", uid
);
1310 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1311 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1313 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1314 aml_append(method
, aml_store(aml_name("%s", enabled_field
), is_present
));
1315 if_ctx
= aml_if(aml_equal(is_present
, zero
));
1317 aml_append(if_ctx
, aml_return(aml_int(0x00)));
1319 aml_append(method
, if_ctx
);
1320 else_ctx
= aml_else();
1322 aml_append(else_ctx
, aml_return(aml_int(0x0f)));
1324 aml_append(method
, else_ctx
);
1325 aml_append(dev
, method
);
1327 crs
= aml_resource_template();
1328 aml_append(crs
, aml_io(AML_DECODE16
, io_port
, io_port
, 0x00, 0x08));
1329 aml_append(crs
, aml_irq_no_flags(irq
));
1330 aml_append(dev
, aml_name_decl("_CRS", crs
));
1335 static void build_isa_devices_aml(Aml
*table
)
1337 ISADevice
*fdc
= pc_find_fdc0();
1340 Aml
*scope
= aml_scope("_SB.PCI0.ISA");
1341 Object
*obj
= object_resolve_path_type("", TYPE_ISA_BUS
, &ambiguous
);
1343 aml_append(scope
, build_rtc_device_aml());
1344 aml_append(scope
, build_kbd_device_aml());
1345 aml_append(scope
, build_mouse_device_aml());
1347 aml_append(scope
, build_fdc_device_aml(fdc
));
1349 aml_append(scope
, build_lpt_device_aml());
1350 aml_append(scope
, build_com_device_aml(1));
1351 aml_append(scope
, build_com_device_aml(2));
1354 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1356 error_report("No ISA bus, unable to define IPMI ACPI data");
1358 build_acpi_ipmi_devices(scope
, BUS(obj
));
1361 aml_append(table
, scope
);
1364 static void build_dbg_aml(Aml
*table
)
1369 Aml
*scope
= aml_scope("\\");
1370 Aml
*buf
= aml_local(0);
1371 Aml
*len
= aml_local(1);
1372 Aml
*idx
= aml_local(2);
1375 aml_operation_region("DBG", AML_SYSTEM_IO
, aml_int(0x0402), 0x01));
1376 field
= aml_field("DBG", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1377 aml_append(field
, aml_named_field("DBGB", 8));
1378 aml_append(scope
, field
);
1380 method
= aml_method("DBUG", 1, AML_NOTSERIALIZED
);
1382 aml_append(method
, aml_to_hexstring(aml_arg(0), buf
));
1383 aml_append(method
, aml_to_buffer(buf
, buf
));
1384 aml_append(method
, aml_subtract(aml_sizeof(buf
), aml_int(1), len
));
1385 aml_append(method
, aml_store(aml_int(0), idx
));
1387 while_ctx
= aml_while(aml_lless(idx
, len
));
1388 aml_append(while_ctx
,
1389 aml_store(aml_derefof(aml_index(buf
, idx
)), aml_name("DBGB")));
1390 aml_append(while_ctx
, aml_increment(idx
));
1391 aml_append(method
, while_ctx
);
1393 aml_append(method
, aml_store(aml_int(0x0A), aml_name("DBGB")));
1394 aml_append(scope
, method
);
1396 aml_append(table
, scope
);
1399 static Aml
*build_link_dev(const char *name
, uint8_t uid
, Aml
*reg
)
1404 uint32_t irqs
[] = {5, 10, 11};
1406 dev
= aml_device("%s", name
);
1407 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1408 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1410 crs
= aml_resource_template();
1411 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1412 AML_SHARED
, irqs
, ARRAY_SIZE(irqs
)));
1413 aml_append(dev
, aml_name_decl("_PRS", crs
));
1415 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1416 aml_append(method
, aml_return(aml_call1("IQST", reg
)));
1417 aml_append(dev
, method
);
1419 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1420 aml_append(method
, aml_or(reg
, aml_int(0x80), reg
));
1421 aml_append(dev
, method
);
1423 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1424 aml_append(method
, aml_return(aml_call1("IQCR", reg
)));
1425 aml_append(dev
, method
);
1427 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1428 aml_append(method
, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1429 aml_append(method
, aml_store(aml_name("PRRI"), reg
));
1430 aml_append(dev
, method
);
1435 static Aml
*build_gsi_link_dev(const char *name
, uint8_t uid
, uint8_t gsi
)
1442 dev
= aml_device("%s", name
);
1443 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1444 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1446 crs
= aml_resource_template();
1448 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1449 AML_SHARED
, &irqs
, 1));
1450 aml_append(dev
, aml_name_decl("_PRS", crs
));
1452 aml_append(dev
, aml_name_decl("_CRS", crs
));
1455 * _DIS can be no-op because the interrupt cannot be disabled.
1457 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1458 aml_append(dev
, method
);
1460 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1461 aml_append(dev
, method
);
1466 /* _CRS method - get current settings */
1467 static Aml
*build_iqcr_method(bool is_piix4
)
1471 Aml
*method
= aml_method("IQCR", 1, AML_SERIALIZED
);
1472 Aml
*crs
= aml_resource_template();
1475 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1476 AML_ACTIVE_HIGH
, AML_SHARED
, &irqs
, 1));
1477 aml_append(method
, aml_name_decl("PRR0", crs
));
1480 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1483 if_ctx
= aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1484 aml_append(if_ctx
, aml_store(aml_arg(0), aml_name("PRRI")));
1485 aml_append(method
, if_ctx
);
1488 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL
),
1492 aml_append(method
, aml_return(aml_name("PRR0")));
1496 /* _STA method - get status */
1497 static Aml
*build_irq_status_method(void)
1500 Aml
*method
= aml_method("IQST", 1, AML_NOTSERIALIZED
);
1502 if_ctx
= aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL
));
1503 aml_append(if_ctx
, aml_return(aml_int(0x09)));
1504 aml_append(method
, if_ctx
);
1505 aml_append(method
, aml_return(aml_int(0x0B)));
1509 static void build_piix4_pci0_int(Aml
*table
)
1516 Aml
*sb_scope
= aml_scope("_SB");
1517 Aml
*pci0_scope
= aml_scope("PCI0");
1519 aml_append(pci0_scope
, build_prt(true));
1520 aml_append(sb_scope
, pci0_scope
);
1522 field
= aml_field("PCI0.ISA.P40C", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1523 aml_append(field
, aml_named_field("PRQ0", 8));
1524 aml_append(field
, aml_named_field("PRQ1", 8));
1525 aml_append(field
, aml_named_field("PRQ2", 8));
1526 aml_append(field
, aml_named_field("PRQ3", 8));
1527 aml_append(sb_scope
, field
);
1529 aml_append(sb_scope
, build_irq_status_method());
1530 aml_append(sb_scope
, build_iqcr_method(true));
1532 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1533 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1534 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1535 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1537 dev
= aml_device("LNKS");
1539 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1540 aml_append(dev
, aml_name_decl("_UID", aml_int(4)));
1542 crs
= aml_resource_template();
1544 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1545 AML_ACTIVE_HIGH
, AML_SHARED
,
1547 aml_append(dev
, aml_name_decl("_PRS", crs
));
1549 /* The SCI cannot be disabled and is always attached to GSI 9,
1550 * so these are no-ops. We only need this link to override the
1551 * polarity to active high and match the content of the MADT.
1553 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1554 aml_append(method
, aml_return(aml_int(0x0b)));
1555 aml_append(dev
, method
);
1557 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1558 aml_append(dev
, method
);
1560 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1561 aml_append(method
, aml_return(aml_name("_PRS")));
1562 aml_append(dev
, method
);
1564 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1565 aml_append(dev
, method
);
1567 aml_append(sb_scope
, dev
);
1569 aml_append(table
, sb_scope
);
1572 static void append_q35_prt_entry(Aml
*ctx
, uint32_t nr
, const char *name
)
1577 char base
= name
[3] < 'E' ? 'A' : 'E';
1578 char *s
= g_strdup(name
);
1579 Aml
*a_nr
= aml_int((nr
<< 16) | 0xffff);
1581 assert(strlen(s
) == 4);
1583 head
= name
[3] - base
;
1584 for (i
= 0; i
< 4; i
++) {
1588 s
[3] = base
+ head
+ i
;
1589 pkg
= aml_package(4);
1590 aml_append(pkg
, a_nr
);
1591 aml_append(pkg
, aml_int(i
));
1592 aml_append(pkg
, aml_name("%s", s
));
1593 aml_append(pkg
, aml_int(0));
1594 aml_append(ctx
, pkg
);
1599 static Aml
*build_q35_routing_table(const char *str
)
1603 char *name
= g_strdup_printf("%s ", str
);
1605 pkg
= aml_package(128);
1606 for (i
= 0; i
< 0x18; i
++) {
1607 name
[3] = 'E' + (i
& 0x3);
1608 append_q35_prt_entry(pkg
, i
, name
);
1612 append_q35_prt_entry(pkg
, 0x18, name
);
1614 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1615 for (i
= 0x0019; i
< 0x1e; i
++) {
1617 append_q35_prt_entry(pkg
, i
, name
);
1620 /* PCIe->PCI bridge. use PIRQ[E-H] */
1622 append_q35_prt_entry(pkg
, 0x1e, name
);
1624 append_q35_prt_entry(pkg
, 0x1f, name
);
1630 static void build_q35_pci0_int(Aml
*table
)
1634 Aml
*sb_scope
= aml_scope("_SB");
1635 Aml
*pci0_scope
= aml_scope("PCI0");
1637 /* Zero => PIC mode, One => APIC Mode */
1638 aml_append(table
, aml_name_decl("PICF", aml_int(0)));
1639 method
= aml_method("_PIC", 1, AML_NOTSERIALIZED
);
1641 aml_append(method
, aml_store(aml_arg(0), aml_name("PICF")));
1643 aml_append(table
, method
);
1645 aml_append(pci0_scope
,
1646 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1647 aml_append(pci0_scope
,
1648 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1650 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
1655 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1657 /* Note: we provide the same info as the PCI routing
1658 table of the Bochs BIOS */
1659 if_ctx
= aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1660 aml_append(if_ctx
, aml_return(aml_name("PRTP")));
1661 aml_append(method
, if_ctx
);
1662 else_ctx
= aml_else();
1663 aml_append(else_ctx
, aml_return(aml_name("PRTA")));
1664 aml_append(method
, else_ctx
);
1666 aml_append(pci0_scope
, method
);
1667 aml_append(sb_scope
, pci0_scope
);
1669 field
= aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1670 aml_append(field
, aml_named_field("PRQA", 8));
1671 aml_append(field
, aml_named_field("PRQB", 8));
1672 aml_append(field
, aml_named_field("PRQC", 8));
1673 aml_append(field
, aml_named_field("PRQD", 8));
1674 aml_append(field
, aml_reserved_field(0x20));
1675 aml_append(field
, aml_named_field("PRQE", 8));
1676 aml_append(field
, aml_named_field("PRQF", 8));
1677 aml_append(field
, aml_named_field("PRQG", 8));
1678 aml_append(field
, aml_named_field("PRQH", 8));
1679 aml_append(sb_scope
, field
);
1681 aml_append(sb_scope
, build_irq_status_method());
1682 aml_append(sb_scope
, build_iqcr_method(false));
1684 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQA")));
1685 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQB")));
1686 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQC")));
1687 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQD")));
1688 aml_append(sb_scope
, build_link_dev("LNKE", 4, aml_name("PRQE")));
1689 aml_append(sb_scope
, build_link_dev("LNKF", 5, aml_name("PRQF")));
1690 aml_append(sb_scope
, build_link_dev("LNKG", 6, aml_name("PRQG")));
1691 aml_append(sb_scope
, build_link_dev("LNKH", 7, aml_name("PRQH")));
1693 aml_append(sb_scope
, build_gsi_link_dev("GSIA", 0x10, 0x10));
1694 aml_append(sb_scope
, build_gsi_link_dev("GSIB", 0x11, 0x11));
1695 aml_append(sb_scope
, build_gsi_link_dev("GSIC", 0x12, 0x12));
1696 aml_append(sb_scope
, build_gsi_link_dev("GSID", 0x13, 0x13));
1697 aml_append(sb_scope
, build_gsi_link_dev("GSIE", 0x14, 0x14));
1698 aml_append(sb_scope
, build_gsi_link_dev("GSIF", 0x15, 0x15));
1699 aml_append(sb_scope
, build_gsi_link_dev("GSIG", 0x16, 0x16));
1700 aml_append(sb_scope
, build_gsi_link_dev("GSIH", 0x17, 0x17));
1702 aml_append(table
, sb_scope
);
1705 static void build_q35_isa_bridge(Aml
*table
)
1711 scope
= aml_scope("_SB.PCI0");
1712 dev
= aml_device("ISA");
1713 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x001F0000)));
1715 /* ICH9 PCI to ISA irq remapping */
1716 aml_append(dev
, aml_operation_region("PIRQ", AML_PCI_CONFIG
,
1717 aml_int(0x60), 0x0C));
1719 aml_append(dev
, aml_operation_region("LPCD", AML_PCI_CONFIG
,
1720 aml_int(0x80), 0x02));
1721 field
= aml_field("LPCD", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1722 aml_append(field
, aml_named_field("COMA", 3));
1723 aml_append(field
, aml_reserved_field(1));
1724 aml_append(field
, aml_named_field("COMB", 3));
1725 aml_append(field
, aml_reserved_field(1));
1726 aml_append(field
, aml_named_field("LPTD", 2));
1727 aml_append(dev
, field
);
1729 aml_append(dev
, aml_operation_region("LPCE", AML_PCI_CONFIG
,
1730 aml_int(0x82), 0x02));
1732 field
= aml_field("LPCE", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1733 aml_append(field
, aml_named_field("CAEN", 1));
1734 aml_append(field
, aml_named_field("CBEN", 1));
1735 aml_append(field
, aml_named_field("LPEN", 1));
1736 aml_append(dev
, field
);
1738 aml_append(scope
, dev
);
1739 aml_append(table
, scope
);
1742 static void build_piix4_pm(Aml
*table
)
1747 scope
= aml_scope("_SB.PCI0");
1748 dev
= aml_device("PX13");
1749 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010003)));
1751 aml_append(dev
, aml_operation_region("P13C", AML_PCI_CONFIG
,
1752 aml_int(0x00), 0xff));
1753 aml_append(scope
, dev
);
1754 aml_append(table
, scope
);
1757 static void build_piix4_isa_bridge(Aml
*table
)
1763 scope
= aml_scope("_SB.PCI0");
1764 dev
= aml_device("ISA");
1765 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010000)));
1767 /* PIIX PCI to ISA irq remapping */
1768 aml_append(dev
, aml_operation_region("P40C", AML_PCI_CONFIG
,
1769 aml_int(0x60), 0x04));
1771 field
= aml_field("^PX13.P13C", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1772 /* Offset(0x5f),, 7, */
1773 aml_append(field
, aml_reserved_field(0x2f8));
1774 aml_append(field
, aml_reserved_field(7));
1775 aml_append(field
, aml_named_field("LPEN", 1));
1776 /* Offset(0x67),, 3, */
1777 aml_append(field
, aml_reserved_field(0x38));
1778 aml_append(field
, aml_reserved_field(3));
1779 aml_append(field
, aml_named_field("CAEN", 1));
1780 aml_append(field
, aml_reserved_field(3));
1781 aml_append(field
, aml_named_field("CBEN", 1));
1782 aml_append(dev
, field
);
1784 aml_append(scope
, dev
);
1785 aml_append(table
, scope
);
1788 static void build_piix4_pci_hotplug(Aml
*table
)
1794 scope
= aml_scope("_SB.PCI0");
1797 aml_operation_region("PCST", AML_SYSTEM_IO
, aml_int(0xae00), 0x08));
1798 field
= aml_field("PCST", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1799 aml_append(field
, aml_named_field("PCIU", 32));
1800 aml_append(field
, aml_named_field("PCID", 32));
1801 aml_append(scope
, field
);
1804 aml_operation_region("SEJ", AML_SYSTEM_IO
, aml_int(0xae08), 0x04));
1805 field
= aml_field("SEJ", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1806 aml_append(field
, aml_named_field("B0EJ", 32));
1807 aml_append(scope
, field
);
1810 aml_operation_region("BNMR", AML_SYSTEM_IO
, aml_int(0xae10), 0x04));
1811 field
= aml_field("BNMR", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1812 aml_append(field
, aml_named_field("BNUM", 32));
1813 aml_append(scope
, field
);
1815 aml_append(scope
, aml_mutex("BLCK", 0));
1817 method
= aml_method("PCEJ", 2, AML_NOTSERIALIZED
);
1818 aml_append(method
, aml_acquire(aml_name("BLCK"), 0xFFFF));
1819 aml_append(method
, aml_store(aml_arg(0), aml_name("BNUM")));
1821 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1822 aml_append(method
, aml_release(aml_name("BLCK")));
1823 aml_append(method
, aml_return(aml_int(0)));
1824 aml_append(scope
, method
);
1826 aml_append(table
, scope
);
1829 static Aml
*build_q35_osc_method(void)
1835 Aml
*a_cwd1
= aml_name("CDW1");
1836 Aml
*a_ctrl
= aml_local(0);
1838 method
= aml_method("_OSC", 4, AML_NOTSERIALIZED
);
1839 aml_append(method
, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1841 if_ctx
= aml_if(aml_equal(
1842 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1843 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1844 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1846 aml_append(if_ctx
, aml_store(aml_name("CDW3"), a_ctrl
));
1849 * Always allow native PME, AER (no dependencies)
1850 * Never allow SHPC (no SHPC controller in this system)
1852 aml_append(if_ctx
, aml_and(a_ctrl
, aml_int(0x1D), a_ctrl
));
1854 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1855 /* Unknown revision */
1856 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x08), a_cwd1
));
1857 aml_append(if_ctx
, if_ctx2
);
1859 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl
)));
1860 /* Capabilities bits were masked */
1861 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x10), a_cwd1
));
1862 aml_append(if_ctx
, if_ctx2
);
1864 /* Update DWORD3 in the buffer */
1865 aml_append(if_ctx
, aml_store(a_ctrl
, aml_name("CDW3")));
1866 aml_append(method
, if_ctx
);
1868 else_ctx
= aml_else();
1869 /* Unrecognized UUID */
1870 aml_append(else_ctx
, aml_or(a_cwd1
, aml_int(4), a_cwd1
));
1871 aml_append(method
, else_ctx
);
1873 aml_append(method
, aml_return(aml_arg(3)));
1878 build_dsdt(GArray
*table_data
, BIOSLinker
*linker
,
1879 AcpiPmInfo
*pm
, AcpiMiscInfo
*misc
,
1880 Range
*pci_hole
, Range
*pci_hole64
, MachineState
*machine
)
1882 CrsRangeEntry
*entry
;
1883 Aml
*dsdt
, *sb_scope
, *scope
, *dev
, *method
, *field
, *pkg
, *crs
;
1884 CrsRangeSet crs_range_set
;
1885 PCMachineState
*pcms
= PC_MACHINE(machine
);
1886 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(machine
);
1887 uint32_t nr_mem
= machine
->ram_slots
;
1888 int root_bus_limit
= 0xFF;
1892 dsdt
= init_aml_allocator();
1894 /* Reserve space for header */
1895 acpi_data_push(dsdt
->buf
, sizeof(AcpiTableHeader
));
1897 build_dbg_aml(dsdt
);
1898 if (misc
->is_piix4
) {
1899 sb_scope
= aml_scope("_SB");
1900 dev
= aml_device("PCI0");
1901 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1902 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
1903 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
1904 aml_append(sb_scope
, dev
);
1905 aml_append(dsdt
, sb_scope
);
1907 build_hpet_aml(dsdt
);
1908 build_piix4_pm(dsdt
);
1909 build_piix4_isa_bridge(dsdt
);
1910 build_isa_devices_aml(dsdt
);
1911 build_piix4_pci_hotplug(dsdt
);
1912 build_piix4_pci0_int(dsdt
);
1914 sb_scope
= aml_scope("_SB");
1915 aml_append(sb_scope
,
1916 aml_operation_region("PCST", AML_SYSTEM_IO
, aml_int(0xae00), 0x0c));
1917 aml_append(sb_scope
,
1918 aml_operation_region("PCSB", AML_SYSTEM_IO
, aml_int(0xae0c), 0x01));
1919 field
= aml_field("PCSB", AML_ANY_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1920 aml_append(field
, aml_named_field("PCIB", 8));
1921 aml_append(sb_scope
, field
);
1922 aml_append(dsdt
, sb_scope
);
1924 sb_scope
= aml_scope("_SB");
1925 dev
= aml_device("PCI0");
1926 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1927 aml_append(dev
, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1928 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
1929 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
1930 aml_append(dev
, build_q35_osc_method());
1931 aml_append(sb_scope
, dev
);
1932 aml_append(dsdt
, sb_scope
);
1934 build_hpet_aml(dsdt
);
1935 build_q35_isa_bridge(dsdt
);
1936 build_isa_devices_aml(dsdt
);
1937 build_q35_pci0_int(dsdt
);
1940 if (pcmc
->legacy_cpu_hotplug
) {
1941 build_legacy_cpu_hotplug_aml(dsdt
, machine
, pm
->cpu_hp_io_base
);
1943 CPUHotplugFeatures opts
= {
1944 .apci_1_compatible
= true, .has_legacy_cphp
= true
1946 build_cpus_aml(dsdt
, machine
, opts
, pm
->cpu_hp_io_base
,
1947 "\\_SB.PCI0", "\\_GPE._E02");
1949 build_memory_hotplug_aml(dsdt
, nr_mem
, "\\_SB.PCI0", "\\_GPE._E03");
1951 scope
= aml_scope("_GPE");
1953 aml_append(scope
, aml_name_decl("_HID", aml_string("ACPI0006")));
1955 if (misc
->is_piix4
) {
1956 method
= aml_method("_E01", 0, AML_NOTSERIALIZED
);
1958 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1959 aml_append(method
, aml_call0("\\_SB.PCI0.PCNT"));
1960 aml_append(method
, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1961 aml_append(scope
, method
);
1964 if (pcms
->acpi_nvdimm_state
.is_enabled
) {
1965 method
= aml_method("_E04", 0, AML_NOTSERIALIZED
);
1966 aml_append(method
, aml_notify(aml_name("\\_SB.NVDR"),
1968 aml_append(scope
, method
);
1971 aml_append(dsdt
, scope
);
1973 crs_range_set_init(&crs_range_set
);
1974 bus
= PC_MACHINE(machine
)->bus
;
1976 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
1977 uint8_t bus_num
= pci_bus_num(bus
);
1978 uint8_t numa_node
= pci_bus_numa_node(bus
);
1980 /* look only for expander root buses */
1981 if (!pci_bus_is_root(bus
)) {
1985 if (bus_num
< root_bus_limit
) {
1986 root_bus_limit
= bus_num
- 1;
1989 scope
= aml_scope("\\_SB");
1990 dev
= aml_device("PC%.02X", bus_num
);
1991 aml_append(dev
, aml_name_decl("_UID", aml_int(bus_num
)));
1992 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1993 aml_append(dev
, aml_name_decl("_BBN", aml_int(bus_num
)));
1994 if (pci_bus_is_express(bus
)) {
1995 aml_append(dev
, build_q35_osc_method());
1998 if (numa_node
!= NUMA_NODE_UNASSIGNED
) {
1999 aml_append(dev
, aml_name_decl("_PXM", aml_int(numa_node
)));
2002 aml_append(dev
, build_prt(false));
2003 crs
= build_crs(PCI_HOST_BRIDGE(BUS(bus
)->parent
), &crs_range_set
);
2004 aml_append(dev
, aml_name_decl("_CRS", crs
));
2005 aml_append(scope
, dev
);
2006 aml_append(dsdt
, scope
);
2010 scope
= aml_scope("\\_SB.PCI0");
2011 /* build PCI0._CRS */
2012 crs
= aml_resource_template();
2014 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
2015 0x0000, 0x0, root_bus_limit
,
2016 0x0000, root_bus_limit
+ 1));
2017 aml_append(crs
, aml_io(AML_DECODE16
, 0x0CF8, 0x0CF8, 0x01, 0x08));
2020 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
2021 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
2022 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
2024 crs_replace_with_free_ranges(crs_range_set
.io_ranges
, 0x0D00, 0xFFFF);
2025 for (i
= 0; i
< crs_range_set
.io_ranges
->len
; i
++) {
2026 entry
= g_ptr_array_index(crs_range_set
.io_ranges
, i
);
2028 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
2029 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
2030 0x0000, entry
->base
, entry
->limit
,
2031 0x0000, entry
->limit
- entry
->base
+ 1));
2035 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
2036 AML_CACHEABLE
, AML_READ_WRITE
,
2037 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2039 crs_replace_with_free_ranges(crs_range_set
.mem_ranges
,
2040 range_lob(pci_hole
),
2041 range_upb(pci_hole
));
2042 for (i
= 0; i
< crs_range_set
.mem_ranges
->len
; i
++) {
2043 entry
= g_ptr_array_index(crs_range_set
.mem_ranges
, i
);
2045 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
2046 AML_NON_CACHEABLE
, AML_READ_WRITE
,
2047 0, entry
->base
, entry
->limit
,
2048 0, entry
->limit
- entry
->base
+ 1));
2051 if (!range_is_empty(pci_hole64
)) {
2052 crs_replace_with_free_ranges(crs_range_set
.mem_64bit_ranges
,
2053 range_lob(pci_hole64
),
2054 range_upb(pci_hole64
));
2055 for (i
= 0; i
< crs_range_set
.mem_64bit_ranges
->len
; i
++) {
2056 entry
= g_ptr_array_index(crs_range_set
.mem_64bit_ranges
, i
);
2058 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
2060 AML_CACHEABLE
, AML_READ_WRITE
,
2061 0, entry
->base
, entry
->limit
,
2062 0, entry
->limit
- entry
->base
+ 1));
2066 if (misc
->tpm_version
!= TPM_VERSION_UNSPEC
) {
2067 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
2068 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
2070 aml_append(scope
, aml_name_decl("_CRS", crs
));
2072 /* reserve GPE0 block resources */
2073 dev
= aml_device("GPE0");
2074 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
2075 aml_append(dev
, aml_name_decl("_UID", aml_string("GPE0 resources")));
2076 /* device present, functioning, decoding, not shown in UI */
2077 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2078 crs
= aml_resource_template();
2080 aml_io(AML_DECODE16
, pm
->gpe0_blk
, pm
->gpe0_blk
, 1, pm
->gpe0_blk_len
)
2082 aml_append(dev
, aml_name_decl("_CRS", crs
));
2083 aml_append(scope
, dev
);
2085 crs_range_set_free(&crs_range_set
);
2087 /* reserve PCIHP resources */
2088 if (pm
->pcihp_io_len
) {
2089 dev
= aml_device("PHPR");
2090 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
2092 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2093 /* device present, functioning, decoding, not shown in UI */
2094 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2095 crs
= aml_resource_template();
2097 aml_io(AML_DECODE16
, pm
->pcihp_io_base
, pm
->pcihp_io_base
, 1,
2100 aml_append(dev
, aml_name_decl("_CRS", crs
));
2101 aml_append(scope
, dev
);
2103 aml_append(dsdt
, scope
);
2105 /* create S3_ / S4_ / S5_ packages if necessary */
2106 scope
= aml_scope("\\");
2107 if (!pm
->s3_disabled
) {
2108 pkg
= aml_package(4);
2109 aml_append(pkg
, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2110 aml_append(pkg
, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2111 aml_append(pkg
, aml_int(0)); /* reserved */
2112 aml_append(pkg
, aml_int(0)); /* reserved */
2113 aml_append(scope
, aml_name_decl("_S3", pkg
));
2116 if (!pm
->s4_disabled
) {
2117 pkg
= aml_package(4);
2118 aml_append(pkg
, aml_int(pm
->s4_val
)); /* PM1a_CNT.SLP_TYP */
2119 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2120 aml_append(pkg
, aml_int(pm
->s4_val
));
2121 aml_append(pkg
, aml_int(0)); /* reserved */
2122 aml_append(pkg
, aml_int(0)); /* reserved */
2123 aml_append(scope
, aml_name_decl("_S4", pkg
));
2126 pkg
= aml_package(4);
2127 aml_append(pkg
, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2128 aml_append(pkg
, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2129 aml_append(pkg
, aml_int(0)); /* reserved */
2130 aml_append(pkg
, aml_int(0)); /* reserved */
2131 aml_append(scope
, aml_name_decl("_S5", pkg
));
2132 aml_append(dsdt
, scope
);
2134 /* create fw_cfg node, unconditionally */
2136 /* when using port i/o, the 8-bit data register *always* overlaps
2137 * with half of the 16-bit control register. Hence, the total size
2138 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2139 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2140 uint8_t io_size
= object_property_get_bool(OBJECT(pcms
->fw_cfg
),
2141 "dma_enabled", NULL
) ?
2142 ROUND_UP(FW_CFG_CTL_SIZE
, 4) + sizeof(dma_addr_t
) :
2145 scope
= aml_scope("\\_SB.PCI0");
2146 dev
= aml_device("FWCF");
2148 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0002")));
2150 /* device present, functioning, decoding, not shown in UI */
2151 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2153 crs
= aml_resource_template();
2155 aml_io(AML_DECODE16
, FW_CFG_IO_BASE
, FW_CFG_IO_BASE
, 0x01, io_size
)
2157 aml_append(dev
, aml_name_decl("_CRS", crs
));
2159 aml_append(scope
, dev
);
2160 aml_append(dsdt
, scope
);
2163 if (misc
->applesmc_io_base
) {
2164 scope
= aml_scope("\\_SB.PCI0.ISA");
2165 dev
= aml_device("SMC");
2167 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("APP0001")));
2168 /* device present, functioning, decoding, not shown in UI */
2169 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2171 crs
= aml_resource_template();
2173 aml_io(AML_DECODE16
, misc
->applesmc_io_base
, misc
->applesmc_io_base
,
2174 0x01, APPLESMC_MAX_DATA_LENGTH
)
2176 aml_append(crs
, aml_irq_no_flags(6));
2177 aml_append(dev
, aml_name_decl("_CRS", crs
));
2179 aml_append(scope
, dev
);
2180 aml_append(dsdt
, scope
);
2183 if (misc
->pvpanic_port
) {
2184 scope
= aml_scope("\\_SB.PCI0.ISA");
2186 dev
= aml_device("PEVT");
2187 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0001")));
2189 crs
= aml_resource_template();
2191 aml_io(AML_DECODE16
, misc
->pvpanic_port
, misc
->pvpanic_port
, 1, 1)
2193 aml_append(dev
, aml_name_decl("_CRS", crs
));
2195 aml_append(dev
, aml_operation_region("PEOR", AML_SYSTEM_IO
,
2196 aml_int(misc
->pvpanic_port
), 1));
2197 field
= aml_field("PEOR", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
2198 aml_append(field
, aml_named_field("PEPT", 8));
2199 aml_append(dev
, field
);
2201 /* device present, functioning, decoding, shown in UI */
2202 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
2204 method
= aml_method("RDPT", 0, AML_NOTSERIALIZED
);
2205 aml_append(method
, aml_store(aml_name("PEPT"), aml_local(0)));
2206 aml_append(method
, aml_return(aml_local(0)));
2207 aml_append(dev
, method
);
2209 method
= aml_method("WRPT", 1, AML_NOTSERIALIZED
);
2210 aml_append(method
, aml_store(aml_arg(0), aml_name("PEPT")));
2211 aml_append(dev
, method
);
2213 aml_append(scope
, dev
);
2214 aml_append(dsdt
, scope
);
2217 sb_scope
= aml_scope("\\_SB");
2222 pci_host
= acpi_get_i386_pci_host();
2224 bus
= PCI_HOST_BRIDGE(pci_host
)->bus
;
2228 Aml
*scope
= aml_scope("PCI0");
2229 /* Scan all PCI buses. Generate tables to support hotplug. */
2230 build_append_pci_bus_devices(scope
, bus
, pm
->pcihp_bridge_en
);
2232 if (misc
->tpm_version
!= TPM_VERSION_UNSPEC
) {
2233 dev
= aml_device("ISA.TPM");
2234 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2235 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
2236 crs
= aml_resource_template();
2237 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
2238 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
2240 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2241 Rewrite to take IRQ from TPM device model and
2242 fix default IRQ value there to use some unused IRQ
2244 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2245 aml_append(dev
, aml_name_decl("_CRS", crs
));
2246 aml_append(scope
, dev
);
2249 aml_append(sb_scope
, scope
);
2252 aml_append(dsdt
, sb_scope
);
2254 /* copy AML table into ACPI tables blob and patch header there */
2255 g_array_append_vals(table_data
, dsdt
->buf
->data
, dsdt
->buf
->len
);
2256 build_header(linker
, table_data
,
2257 (void *)(table_data
->data
+ table_data
->len
- dsdt
->buf
->len
),
2258 "DSDT", dsdt
->buf
->len
, 1, NULL
, NULL
);
2259 free_aml_allocator();
2263 build_hpet(GArray
*table_data
, BIOSLinker
*linker
)
2267 hpet
= acpi_data_push(table_data
, sizeof(*hpet
));
2268 /* Note timer_block_id value must be kept in sync with value advertised by
2271 hpet
->timer_block_id
= cpu_to_le32(0x8086a201);
2272 hpet
->addr
.address
= cpu_to_le64(HPET_BASE
);
2273 build_header(linker
, table_data
,
2274 (void *)hpet
, "HPET", sizeof(*hpet
), 1, NULL
, NULL
);
2278 build_tpm_tcpa(GArray
*table_data
, BIOSLinker
*linker
, GArray
*tcpalog
)
2280 Acpi20Tcpa
*tcpa
= acpi_data_push(table_data
, sizeof *tcpa
);
2281 unsigned log_addr_size
= sizeof(tcpa
->log_area_start_address
);
2282 unsigned log_addr_offset
=
2283 (char *)&tcpa
->log_area_start_address
- table_data
->data
;
2285 tcpa
->platform_class
= cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT
);
2286 tcpa
->log_area_minimum_length
= cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE
);
2287 acpi_data_push(tcpalog
, le32_to_cpu(tcpa
->log_area_minimum_length
));
2289 bios_linker_loader_alloc(linker
, ACPI_BUILD_TPMLOG_FILE
, tcpalog
, 1,
2290 false /* high memory */);
2292 /* log area start address to be filled by Guest linker */
2293 bios_linker_loader_add_pointer(linker
,
2294 ACPI_BUILD_TABLE_FILE
, log_addr_offset
, log_addr_size
,
2295 ACPI_BUILD_TPMLOG_FILE
, 0);
2297 build_header(linker
, table_data
,
2298 (void *)tcpa
, "TCPA", sizeof(*tcpa
), 2, NULL
, NULL
);
2302 build_tpm2(GArray
*table_data
, BIOSLinker
*linker
)
2304 Acpi20TPM2
*tpm2_ptr
;
2306 tpm2_ptr
= acpi_data_push(table_data
, sizeof *tpm2_ptr
);
2308 tpm2_ptr
->platform_class
= cpu_to_le16(TPM2_ACPI_CLASS_CLIENT
);
2309 tpm2_ptr
->control_area_address
= cpu_to_le64(0);
2310 tpm2_ptr
->start_method
= cpu_to_le32(TPM2_START_METHOD_MMIO
);
2312 build_header(linker
, table_data
,
2313 (void *)tpm2_ptr
, "TPM2", sizeof(*tpm2_ptr
), 4, NULL
, NULL
);
2317 build_srat(GArray
*table_data
, BIOSLinker
*linker
, MachineState
*machine
)
2319 AcpiSystemResourceAffinityTable
*srat
;
2320 AcpiSratMemoryAffinity
*numamem
;
2323 int srat_start
, numa_start
, slots
;
2324 uint64_t mem_len
, mem_base
, next_base
;
2325 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2326 const CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(machine
);
2327 PCMachineState
*pcms
= PC_MACHINE(machine
);
2328 ram_addr_t hotplugabble_address_space_size
=
2329 object_property_get_int(OBJECT(pcms
), PC_MACHINE_MEMHP_REGION_SIZE
,
2332 srat_start
= table_data
->len
;
2334 srat
= acpi_data_push(table_data
, sizeof *srat
);
2335 srat
->reserved1
= cpu_to_le32(1);
2337 for (i
= 0; i
< apic_ids
->len
; i
++) {
2338 int node_id
= apic_ids
->cpus
[i
].props
.node_id
;
2339 uint32_t apic_id
= apic_ids
->cpus
[i
].arch_id
;
2341 if (apic_id
< 255) {
2342 AcpiSratProcessorAffinity
*core
;
2344 core
= acpi_data_push(table_data
, sizeof *core
);
2345 core
->type
= ACPI_SRAT_PROCESSOR_APIC
;
2346 core
->length
= sizeof(*core
);
2347 core
->local_apic_id
= apic_id
;
2348 core
->proximity_lo
= node_id
;
2349 memset(core
->proximity_hi
, 0, 3);
2350 core
->local_sapic_eid
= 0;
2351 core
->flags
= cpu_to_le32(1);
2353 AcpiSratProcessorX2ApicAffinity
*core
;
2355 core
= acpi_data_push(table_data
, sizeof *core
);
2356 core
->type
= ACPI_SRAT_PROCESSOR_x2APIC
;
2357 core
->length
= sizeof(*core
);
2358 core
->x2apic_id
= cpu_to_le32(apic_id
);
2359 core
->proximity_domain
= cpu_to_le32(node_id
);
2360 core
->flags
= cpu_to_le32(1);
2365 /* the memory map is a bit tricky, it contains at least one hole
2366 * from 640k-1M and possibly another one from 3.5G-4G.
2369 numa_start
= table_data
->len
;
2371 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2372 build_srat_memory(numamem
, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED
);
2373 next_base
= 1024 * 1024;
2374 for (i
= 1; i
< pcms
->numa_nodes
+ 1; ++i
) {
2375 mem_base
= next_base
;
2376 mem_len
= pcms
->node_mem
[i
- 1];
2378 mem_len
-= 1024 * 1024;
2380 next_base
= mem_base
+ mem_len
;
2382 /* Cut out the ACPI_PCI hole */
2383 if (mem_base
<= pcms
->below_4g_mem_size
&&
2384 next_base
> pcms
->below_4g_mem_size
) {
2385 mem_len
-= next_base
- pcms
->below_4g_mem_size
;
2387 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2388 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2389 MEM_AFFINITY_ENABLED
);
2391 mem_base
= 1ULL << 32;
2392 mem_len
= next_base
- pcms
->below_4g_mem_size
;
2393 next_base
+= (1ULL << 32) - pcms
->below_4g_mem_size
;
2395 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2396 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2397 MEM_AFFINITY_ENABLED
);
2399 slots
= (table_data
->len
- numa_start
) / sizeof *numamem
;
2400 for (; slots
< pcms
->numa_nodes
+ 2; slots
++) {
2401 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2402 build_srat_memory(numamem
, 0, 0, 0, MEM_AFFINITY_NOFLAGS
);
2406 * Entry is required for Windows to enable memory hotplug in OS
2407 * and for Linux to enable SWIOTLB when booted with less than
2408 * 4G of RAM. Windows works better if the entry sets proximity
2409 * to the highest NUMA node in the machine.
2410 * Memory devices may override proximity set by this entry,
2411 * providing _PXM method if necessary.
2413 if (hotplugabble_address_space_size
) {
2414 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2415 build_srat_memory(numamem
, pcms
->hotplug_memory
.base
,
2416 hotplugabble_address_space_size
, pcms
->numa_nodes
- 1,
2417 MEM_AFFINITY_HOTPLUGGABLE
| MEM_AFFINITY_ENABLED
);
2420 build_header(linker
, table_data
,
2421 (void *)(table_data
->data
+ srat_start
),
2423 table_data
->len
- srat_start
, 1, NULL
, NULL
);
2427 build_mcfg_q35(GArray
*table_data
, BIOSLinker
*linker
, AcpiMcfgInfo
*info
)
2429 AcpiTableMcfg
*mcfg
;
2431 int len
= sizeof(*mcfg
) + 1 * sizeof(mcfg
->allocation
[0]);
2433 mcfg
= acpi_data_push(table_data
, len
);
2434 mcfg
->allocation
[0].address
= cpu_to_le64(info
->mcfg_base
);
2435 /* Only a single allocation so no need to play with segments */
2436 mcfg
->allocation
[0].pci_segment
= cpu_to_le16(0);
2437 mcfg
->allocation
[0].start_bus_number
= 0;
2438 mcfg
->allocation
[0].end_bus_number
= PCIE_MMCFG_BUS(info
->mcfg_size
- 1);
2440 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2441 * To avoid table size changes (which create migration issues),
2442 * always create the table even if there are no allocations,
2443 * but set the signature to a reserved value in this case.
2444 * ACPI spec requires OSPMs to ignore such tables.
2446 if (info
->mcfg_base
== PCIE_BASE_ADDR_UNMAPPED
) {
2447 /* Reserved signature: ignored by OSPM */
2452 build_header(linker
, table_data
, (void *)mcfg
, sig
, len
, 1, NULL
, NULL
);
2456 * VT-d spec 8.1 DMA Remapping Reporting Structure
2457 * (version Oct. 2014 or later)
2460 build_dmar_q35(GArray
*table_data
, BIOSLinker
*linker
)
2462 int dmar_start
= table_data
->len
;
2464 AcpiTableDmar
*dmar
;
2465 AcpiDmarHardwareUnit
*drhd
;
2466 AcpiDmarRootPortATS
*atsr
;
2467 uint8_t dmar_flags
= 0;
2468 X86IOMMUState
*iommu
= x86_iommu_get_default();
2469 AcpiDmarDeviceScope
*scope
= NULL
;
2470 /* Root complex IOAPIC use one path[0] only */
2471 size_t ioapic_scope_size
= sizeof(*scope
) + sizeof(scope
->path
[0]);
2474 if (iommu
->intr_supported
) {
2475 dmar_flags
|= 0x1; /* Flags: 0x1: INT_REMAP */
2478 dmar
= acpi_data_push(table_data
, sizeof(*dmar
));
2479 dmar
->host_address_width
= VTD_HOST_ADDRESS_WIDTH
- 1;
2480 dmar
->flags
= dmar_flags
;
2482 /* DMAR Remapping Hardware Unit Definition structure */
2483 drhd
= acpi_data_push(table_data
, sizeof(*drhd
) + ioapic_scope_size
);
2484 drhd
->type
= cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT
);
2485 drhd
->length
= cpu_to_le16(sizeof(*drhd
) + ioapic_scope_size
);
2486 drhd
->flags
= ACPI_DMAR_INCLUDE_PCI_ALL
;
2487 drhd
->pci_segment
= cpu_to_le16(0);
2488 drhd
->address
= cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR
);
2490 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2491 * 8.3.1 (version Oct. 2014 or later). */
2492 scope
= &drhd
->scope
[0];
2493 scope
->entry_type
= 0x03; /* Type: 0x03 for IOAPIC */
2494 scope
->length
= ioapic_scope_size
;
2495 scope
->enumeration_id
= ACPI_BUILD_IOAPIC_ID
;
2496 scope
->bus
= Q35_PSEUDO_BUS_PLATFORM
;
2497 scope
->path
[0].device
= PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC
);
2498 scope
->path
[0].function
= PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC
);
2500 if (iommu
->dt_supported
) {
2501 atsr
= acpi_data_push(table_data
, sizeof(*atsr
));
2502 atsr
->type
= cpu_to_le16(ACPI_DMAR_TYPE_ATSR
);
2503 atsr
->length
= cpu_to_le16(sizeof(*atsr
));
2504 atsr
->flags
= ACPI_DMAR_ATSR_ALL_PORTS
;
2505 atsr
->pci_segment
= cpu_to_le16(0);
2508 build_header(linker
, table_data
, (void *)(table_data
->data
+ dmar_start
),
2509 "DMAR", table_data
->len
- dmar_start
, 1, NULL
, NULL
);
2512 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2513 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2516 build_amd_iommu(GArray
*table_data
, BIOSLinker
*linker
)
2518 int iommu_start
= table_data
->len
;
2519 AMDVIState
*s
= AMD_IOMMU_DEVICE(x86_iommu_get_default());
2522 acpi_data_push(table_data
, sizeof(AcpiTableHeader
));
2523 /* IVinfo - IO virtualization information common to all
2524 * IOMMU units in a system
2526 build_append_int_noprefix(table_data
, 40UL << 8/* PASize */, 4);
2528 build_append_int_noprefix(table_data
, 0, 8);
2530 /* IVHD definition - type 10h */
2531 build_append_int_noprefix(table_data
, 0x10, 1);
2532 /* virtualization flags */
2533 build_append_int_noprefix(table_data
,
2534 (1UL << 0) | /* HtTunEn */
2535 (1UL << 4) | /* iotblSup */
2536 (1UL << 6) | /* PrefSup */
2537 (1UL << 7), /* PPRSup */
2540 build_append_int_noprefix(table_data
, 0x24, 2);
2542 build_append_int_noprefix(table_data
, s
->devid
, 2);
2543 /* Capability offset */
2544 build_append_int_noprefix(table_data
, s
->capab_offset
, 2);
2545 /* IOMMU base address */
2546 build_append_int_noprefix(table_data
, s
->mmio
.addr
, 8);
2547 /* PCI Segment Group */
2548 build_append_int_noprefix(table_data
, 0, 2);
2550 build_append_int_noprefix(table_data
, 0, 2);
2551 /* IOMMU Feature Reporting */
2552 build_append_int_noprefix(table_data
,
2553 (48UL << 30) | /* HATS */
2554 (48UL << 28) | /* GATS */
2555 (1UL << 2), /* GTSup */
2558 * Type 1 device entry reporting all devices
2559 * These are 4-byte device entries currently reporting the range of
2560 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2562 build_append_int_noprefix(table_data
, 0x0000001, 4);
2564 build_header(linker
, table_data
, (void *)(table_data
->data
+ iommu_start
),
2565 "IVRS", table_data
->len
- iommu_start
, 1, NULL
, NULL
);
2569 build_rsdp(GArray
*rsdp_table
, BIOSLinker
*linker
, unsigned rsdt_tbl_offset
)
2571 AcpiRsdpDescriptor
*rsdp
= acpi_data_push(rsdp_table
, sizeof *rsdp
);
2572 unsigned rsdt_pa_size
= sizeof(rsdp
->rsdt_physical_address
);
2573 unsigned rsdt_pa_offset
=
2574 (char *)&rsdp
->rsdt_physical_address
- rsdp_table
->data
;
2576 bios_linker_loader_alloc(linker
, ACPI_BUILD_RSDP_FILE
, rsdp_table
, 16,
2577 true /* fseg memory */);
2579 memcpy(&rsdp
->signature
, "RSD PTR ", 8);
2580 memcpy(rsdp
->oem_id
, ACPI_BUILD_APPNAME6
, 6);
2581 /* Address to be filled by Guest linker */
2582 bios_linker_loader_add_pointer(linker
,
2583 ACPI_BUILD_RSDP_FILE
, rsdt_pa_offset
, rsdt_pa_size
,
2584 ACPI_BUILD_TABLE_FILE
, rsdt_tbl_offset
);
2586 /* Checksum to be filled by Guest linker */
2587 bios_linker_loader_add_checksum(linker
, ACPI_BUILD_RSDP_FILE
,
2588 (char *)rsdp
- rsdp_table
->data
, sizeof *rsdp
,
2589 (char *)&rsdp
->checksum
- rsdp_table
->data
);
2595 struct AcpiBuildState
{
2596 /* Copy of table in RAM (for patching). */
2597 MemoryRegion
*table_mr
;
2598 /* Is table patched? */
2601 MemoryRegion
*rsdp_mr
;
2602 MemoryRegion
*linker_mr
;
2605 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
)
2610 pci_host
= acpi_get_i386_pci_host();
2613 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_BASE
, NULL
);
2617 mcfg
->mcfg_base
= qint_get_int(qobject_to_qint(o
));
2620 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_SIZE
, NULL
);
2622 mcfg
->mcfg_size
= qint_get_int(qobject_to_qint(o
));
2628 void acpi_build(AcpiBuildTables
*tables
, MachineState
*machine
)
2630 PCMachineState
*pcms
= PC_MACHINE(machine
);
2631 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2632 GArray
*table_offsets
;
2633 unsigned facs
, dsdt
, rsdt
, fadt
;
2637 Range pci_hole
, pci_hole64
;
2640 GArray
*tables_blob
= tables
->table_data
;
2641 AcpiSlicOem slic_oem
= { .id
= NULL
, .table_id
= NULL
};
2642 Object
*vmgenid_dev
;
2644 acpi_get_pm_info(&pm
);
2645 acpi_get_misc_info(&misc
);
2646 acpi_get_pci_holes(&pci_hole
, &pci_hole64
);
2647 acpi_get_slic_oem(&slic_oem
);
2649 table_offsets
= g_array_new(false, true /* clear */,
2651 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2653 bios_linker_loader_alloc(tables
->linker
,
2654 ACPI_BUILD_TABLE_FILE
, tables_blob
,
2655 64 /* Ensure FACS is aligned */,
2656 false /* high memory */);
2659 * FACS is pointed to by FADT.
2660 * We place it first since it's the only table that has alignment
2663 facs
= tables_blob
->len
;
2664 build_facs(tables_blob
, tables
->linker
);
2666 /* DSDT is pointed to by FADT */
2667 dsdt
= tables_blob
->len
;
2668 build_dsdt(tables_blob
, tables
->linker
, &pm
, &misc
,
2669 &pci_hole
, &pci_hole64
, machine
);
2671 /* Count the size of the DSDT and SSDT, we will need it for legacy
2672 * sizing of ACPI tables.
2674 aml_len
+= tables_blob
->len
- dsdt
;
2676 /* ACPI tables pointed to by RSDT */
2677 fadt
= tables_blob
->len
;
2678 acpi_add_table(table_offsets
, tables_blob
);
2679 build_fadt(tables_blob
, tables
->linker
, &pm
, facs
, dsdt
,
2680 slic_oem
.id
, slic_oem
.table_id
);
2681 aml_len
+= tables_blob
->len
- fadt
;
2683 acpi_add_table(table_offsets
, tables_blob
);
2684 build_madt(tables_blob
, tables
->linker
, pcms
);
2686 vmgenid_dev
= find_vmgenid_dev();
2688 acpi_add_table(table_offsets
, tables_blob
);
2689 vmgenid_build_acpi(VMGENID(vmgenid_dev
), tables_blob
,
2690 tables
->vmgenid
, tables
->linker
);
2693 if (misc
.has_hpet
) {
2694 acpi_add_table(table_offsets
, tables_blob
);
2695 build_hpet(tables_blob
, tables
->linker
);
2697 if (misc
.tpm_version
!= TPM_VERSION_UNSPEC
) {
2698 acpi_add_table(table_offsets
, tables_blob
);
2699 build_tpm_tcpa(tables_blob
, tables
->linker
, tables
->tcpalog
);
2701 if (misc
.tpm_version
== TPM_VERSION_2_0
) {
2702 acpi_add_table(table_offsets
, tables_blob
);
2703 build_tpm2(tables_blob
, tables
->linker
);
2706 if (pcms
->numa_nodes
) {
2707 acpi_add_table(table_offsets
, tables_blob
);
2708 build_srat(tables_blob
, tables
->linker
, machine
);
2709 if (have_numa_distance
) {
2710 acpi_add_table(table_offsets
, tables_blob
);
2711 build_slit(tables_blob
, tables
->linker
);
2714 if (acpi_get_mcfg(&mcfg
)) {
2715 acpi_add_table(table_offsets
, tables_blob
);
2716 build_mcfg_q35(tables_blob
, tables
->linker
, &mcfg
);
2718 if (x86_iommu_get_default()) {
2719 IommuType IOMMUType
= x86_iommu_get_type();
2720 if (IOMMUType
== TYPE_AMD
) {
2721 acpi_add_table(table_offsets
, tables_blob
);
2722 build_amd_iommu(tables_blob
, tables
->linker
);
2723 } else if (IOMMUType
== TYPE_INTEL
) {
2724 acpi_add_table(table_offsets
, tables_blob
);
2725 build_dmar_q35(tables_blob
, tables
->linker
);
2728 if (pcms
->acpi_nvdimm_state
.is_enabled
) {
2729 nvdimm_build_acpi(table_offsets
, tables_blob
, tables
->linker
,
2730 &pcms
->acpi_nvdimm_state
, machine
->ram_slots
);
2733 /* Add tables supplied by user (if any) */
2734 for (u
= acpi_table_first(); u
; u
= acpi_table_next(u
)) {
2735 unsigned len
= acpi_table_len(u
);
2737 acpi_add_table(table_offsets
, tables_blob
);
2738 g_array_append_vals(tables_blob
, u
, len
);
2741 /* RSDT is pointed to by RSDP */
2742 rsdt
= tables_blob
->len
;
2743 build_rsdt(tables_blob
, tables
->linker
, table_offsets
,
2744 slic_oem
.id
, slic_oem
.table_id
);
2746 /* RSDP is in FSEG memory, so allocate it separately */
2747 build_rsdp(tables
->rsdp
, tables
->linker
, rsdt
);
2749 /* We'll expose it all to Guest so we want to reduce
2750 * chance of size changes.
2752 * We used to align the tables to 4k, but of course this would
2753 * too simple to be enough. 4k turned out to be too small an
2754 * alignment very soon, and in fact it is almost impossible to
2755 * keep the table size stable for all (max_cpus, max_memory_slots)
2756 * combinations. So the table size is always 64k for pc-i440fx-2.1
2757 * and we give an error if the table grows beyond that limit.
2759 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2760 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2761 * than 2.0 and we can always pad the smaller tables with zeros. We can
2762 * then use the exact size of the 2.0 tables.
2764 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2766 if (pcmc
->legacy_acpi_table_size
) {
2767 /* Subtracting aml_len gives the size of fixed tables. Then add the
2768 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2770 int legacy_aml_len
=
2771 pcmc
->legacy_acpi_table_size
+
2772 ACPI_BUILD_LEGACY_CPU_AML_SIZE
* pcms
->apic_id_limit
;
2773 int legacy_table_size
=
2774 ROUND_UP(tables_blob
->len
- aml_len
+ legacy_aml_len
,
2775 ACPI_BUILD_ALIGN_SIZE
);
2776 if (tables_blob
->len
> legacy_table_size
) {
2777 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2778 error_report("Warning: migration may not work.");
2780 g_array_set_size(tables_blob
, legacy_table_size
);
2782 /* Make sure we have a buffer in case we need to resize the tables. */
2783 if (tables_blob
->len
> ACPI_BUILD_TABLE_SIZE
/ 2) {
2784 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2785 error_report("Warning: ACPI tables are larger than 64k.");
2786 error_report("Warning: migration may not work.");
2787 error_report("Warning: please remove CPUs, NUMA nodes, "
2788 "memory slots or PCI bridges.");
2790 acpi_align_size(tables_blob
, ACPI_BUILD_TABLE_SIZE
);
2793 acpi_align_size(tables
->linker
->cmd_blob
, ACPI_BUILD_ALIGN_SIZE
);
2795 /* Cleanup memory that's no longer used. */
2796 g_array_free(table_offsets
, true);
2799 static void acpi_ram_update(MemoryRegion
*mr
, GArray
*data
)
2801 uint32_t size
= acpi_data_len(data
);
2803 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2804 memory_region_ram_resize(mr
, size
, &error_abort
);
2806 memcpy(memory_region_get_ram_ptr(mr
), data
->data
, size
);
2807 memory_region_set_dirty(mr
, 0, size
);
2810 static void acpi_build_update(void *build_opaque
)
2812 AcpiBuildState
*build_state
= build_opaque
;
2813 AcpiBuildTables tables
;
2815 /* No state to update or already patched? Nothing to do. */
2816 if (!build_state
|| build_state
->patched
) {
2819 build_state
->patched
= 1;
2821 acpi_build_tables_init(&tables
);
2823 acpi_build(&tables
, MACHINE(qdev_get_machine()));
2825 acpi_ram_update(build_state
->table_mr
, tables
.table_data
);
2827 if (build_state
->rsdp
) {
2828 memcpy(build_state
->rsdp
, tables
.rsdp
->data
, acpi_data_len(tables
.rsdp
));
2830 acpi_ram_update(build_state
->rsdp_mr
, tables
.rsdp
);
2833 acpi_ram_update(build_state
->linker_mr
, tables
.linker
->cmd_blob
);
2834 acpi_build_tables_cleanup(&tables
, true);
2837 static void acpi_build_reset(void *build_opaque
)
2839 AcpiBuildState
*build_state
= build_opaque
;
2840 build_state
->patched
= 0;
2843 static MemoryRegion
*acpi_add_rom_blob(AcpiBuildState
*build_state
,
2844 GArray
*blob
, const char *name
,
2847 return rom_add_blob(name
, blob
->data
, acpi_data_len(blob
), max_size
, -1,
2848 name
, acpi_build_update
, build_state
, NULL
, true);
2851 static const VMStateDescription vmstate_acpi_build
= {
2852 .name
= "acpi_build",
2854 .minimum_version_id
= 1,
2855 .fields
= (VMStateField
[]) {
2856 VMSTATE_UINT8(patched
, AcpiBuildState
),
2857 VMSTATE_END_OF_LIST()
2861 void acpi_setup(void)
2863 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
2864 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2865 AcpiBuildTables tables
;
2866 AcpiBuildState
*build_state
;
2867 Object
*vmgenid_dev
;
2869 if (!pcms
->fw_cfg
) {
2870 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2874 if (!pcms
->acpi_build_enabled
) {
2875 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2879 if (!acpi_enabled
) {
2880 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2884 build_state
= g_malloc0(sizeof *build_state
);
2886 acpi_set_pci_info();
2888 acpi_build_tables_init(&tables
);
2889 acpi_build(&tables
, MACHINE(pcms
));
2891 /* Now expose it all to Guest */
2892 build_state
->table_mr
= acpi_add_rom_blob(build_state
, tables
.table_data
,
2893 ACPI_BUILD_TABLE_FILE
,
2894 ACPI_BUILD_TABLE_MAX_SIZE
);
2895 assert(build_state
->table_mr
!= NULL
);
2897 build_state
->linker_mr
=
2898 acpi_add_rom_blob(build_state
, tables
.linker
->cmd_blob
,
2899 "etc/table-loader", 0);
2901 fw_cfg_add_file(pcms
->fw_cfg
, ACPI_BUILD_TPMLOG_FILE
,
2902 tables
.tcpalog
->data
, acpi_data_len(tables
.tcpalog
));
2904 vmgenid_dev
= find_vmgenid_dev();
2906 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev
), pcms
->fw_cfg
,
2910 if (!pcmc
->rsdp_in_ram
) {
2912 * Keep for compatibility with old machine types.
2913 * Though RSDP is small, its contents isn't immutable, so
2914 * we'll update it along with the rest of tables on guest access.
2916 uint32_t rsdp_size
= acpi_data_len(tables
.rsdp
);
2918 build_state
->rsdp
= g_memdup(tables
.rsdp
->data
, rsdp_size
);
2919 fw_cfg_add_file_callback(pcms
->fw_cfg
, ACPI_BUILD_RSDP_FILE
,
2920 acpi_build_update
, build_state
,
2921 build_state
->rsdp
, rsdp_size
, true);
2922 build_state
->rsdp_mr
= NULL
;
2924 build_state
->rsdp
= NULL
;
2925 build_state
->rsdp_mr
= acpi_add_rom_blob(build_state
, tables
.rsdp
,
2926 ACPI_BUILD_RSDP_FILE
, 0);
2929 qemu_register_reset(acpi_build_reset
, build_state
);
2930 acpi_build_reset(build_state
);
2931 vmstate_register(NULL
, 0, &vmstate_acpi_build
, build_state
);
2933 /* Cleanup tables but don't free the memory: we track it
2936 acpi_build_tables_cleanup(&tables
, false);