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memhp: move build_memory_devices() into memory_hotplug.c
[mirror_qemu.git] / hw / i386 / acpi-build.c
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "acpi-build.h"
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
30 #include "qom/cpu.h"
31 #include "hw/i386/pc.h"
32 #include "target/i386/cpu.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/acpi/cpu.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "sysemu/tpm_backend.h"
46 #include "hw/timer/mc146818rtc_regs.h"
47 #include "sysemu/numa.h"
48
49 /* Supported chipsets: */
50 #include "hw/acpi/piix4.h"
51 #include "hw/acpi/pcihp.h"
52 #include "hw/i386/ich9.h"
53 #include "hw/pci/pci_bus.h"
54 #include "hw/pci-host/q35.h"
55 #include "hw/i386/x86-iommu.h"
56
57 #include "hw/acpi/aml-build.h"
58
59 #include "qapi/qmp/qint.h"
60 #include "qom/qom-qobject.h"
61 #include "hw/i386/amd_iommu.h"
62 #include "hw/i386/intel_iommu.h"
63
64 #include "hw/acpi/ipmi.h"
65
66 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
67 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
68 * a little bit, there should be plenty of free space since the DSDT
69 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
70 */
71 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
72 #define ACPI_BUILD_ALIGN_SIZE 0x1000
73
74 #define ACPI_BUILD_TABLE_SIZE 0x20000
75
76 /* #define DEBUG_ACPI_BUILD */
77 #ifdef DEBUG_ACPI_BUILD
78 #define ACPI_BUILD_DPRINTF(fmt, ...) \
79 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
80 #else
81 #define ACPI_BUILD_DPRINTF(fmt, ...)
82 #endif
83
84 /* Default IOAPIC ID */
85 #define ACPI_BUILD_IOAPIC_ID 0x0
86
87 typedef struct AcpiMcfgInfo {
88 uint64_t mcfg_base;
89 uint32_t mcfg_size;
90 } AcpiMcfgInfo;
91
92 typedef struct AcpiPmInfo {
93 bool s3_disabled;
94 bool s4_disabled;
95 bool pcihp_bridge_en;
96 uint8_t s4_val;
97 uint16_t sci_int;
98 uint8_t acpi_enable_cmd;
99 uint8_t acpi_disable_cmd;
100 uint32_t gpe0_blk;
101 uint32_t gpe0_blk_len;
102 uint32_t io_base;
103 uint16_t cpu_hp_io_base;
104 uint16_t mem_hp_io_base;
105 uint16_t mem_hp_io_len;
106 uint16_t pcihp_io_base;
107 uint16_t pcihp_io_len;
108 } AcpiPmInfo;
109
110 typedef struct AcpiMiscInfo {
111 bool is_piix4;
112 bool has_hpet;
113 TPMVersion tpm_version;
114 const unsigned char *dsdt_code;
115 unsigned dsdt_size;
116 uint16_t pvpanic_port;
117 uint16_t applesmc_io_base;
118 } AcpiMiscInfo;
119
120 typedef struct AcpiBuildPciBusHotplugState {
121 GArray *device_table;
122 GArray *notify_table;
123 struct AcpiBuildPciBusHotplugState *parent;
124 bool pcihp_bridge_en;
125 } AcpiBuildPciBusHotplugState;
126
127 static void acpi_get_pm_info(AcpiPmInfo *pm)
128 {
129 Object *piix = piix4_pm_find();
130 Object *lpc = ich9_lpc_find();
131 Object *obj = NULL;
132 QObject *o;
133
134 pm->cpu_hp_io_base = 0;
135 pm->pcihp_io_base = 0;
136 pm->pcihp_io_len = 0;
137 if (piix) {
138 obj = piix;
139 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
140 pm->pcihp_io_base =
141 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
142 pm->pcihp_io_len =
143 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
144 }
145 if (lpc) {
146 obj = lpc;
147 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
148 }
149 assert(obj);
150
151 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
152 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
153
154 /* Fill in optional s3/s4 related properties */
155 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
156 if (o) {
157 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
158 } else {
159 pm->s3_disabled = false;
160 }
161 qobject_decref(o);
162 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
163 if (o) {
164 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
165 } else {
166 pm->s4_disabled = false;
167 }
168 qobject_decref(o);
169 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
170 if (o) {
171 pm->s4_val = qint_get_int(qobject_to_qint(o));
172 } else {
173 pm->s4_val = false;
174 }
175 qobject_decref(o);
176
177 /* Fill in mandatory properties */
178 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
179
180 pm->acpi_enable_cmd = object_property_get_int(obj,
181 ACPI_PM_PROP_ACPI_ENABLE_CMD,
182 NULL);
183 pm->acpi_disable_cmd = object_property_get_int(obj,
184 ACPI_PM_PROP_ACPI_DISABLE_CMD,
185 NULL);
186 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
187 NULL);
188 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
189 NULL);
190 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
191 NULL);
192 pm->pcihp_bridge_en =
193 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
194 NULL);
195 }
196
197 static void acpi_get_misc_info(AcpiMiscInfo *info)
198 {
199 Object *piix = piix4_pm_find();
200 Object *lpc = ich9_lpc_find();
201 assert(!!piix != !!lpc);
202
203 if (piix) {
204 info->is_piix4 = true;
205 }
206 if (lpc) {
207 info->is_piix4 = false;
208 }
209
210 info->has_hpet = hpet_find();
211 info->tpm_version = tpm_get_version();
212 info->pvpanic_port = pvpanic_port();
213 info->applesmc_io_base = applesmc_port();
214 }
215
216 /*
217 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
218 * On i386 arch we only have two pci hosts, so we can look only for them.
219 */
220 static Object *acpi_get_i386_pci_host(void)
221 {
222 PCIHostState *host;
223
224 host = OBJECT_CHECK(PCIHostState,
225 object_resolve_path("/machine/i440fx", NULL),
226 TYPE_PCI_HOST_BRIDGE);
227 if (!host) {
228 host = OBJECT_CHECK(PCIHostState,
229 object_resolve_path("/machine/q35", NULL),
230 TYPE_PCI_HOST_BRIDGE);
231 }
232
233 return OBJECT(host);
234 }
235
236 static void acpi_get_pci_holes(Range *hole, Range *hole64)
237 {
238 Object *pci_host;
239
240 pci_host = acpi_get_i386_pci_host();
241 g_assert(pci_host);
242
243 range_set_bounds1(hole,
244 object_property_get_int(pci_host,
245 PCI_HOST_PROP_PCI_HOLE_START,
246 NULL),
247 object_property_get_int(pci_host,
248 PCI_HOST_PROP_PCI_HOLE_END,
249 NULL));
250 range_set_bounds1(hole64,
251 object_property_get_int(pci_host,
252 PCI_HOST_PROP_PCI_HOLE64_START,
253 NULL),
254 object_property_get_int(pci_host,
255 PCI_HOST_PROP_PCI_HOLE64_END,
256 NULL));
257 }
258
259 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
260
261 static void acpi_align_size(GArray *blob, unsigned align)
262 {
263 /* Align size to multiple of given size. This reduces the chance
264 * we need to change size in the future (breaking cross version migration).
265 */
266 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
267 }
268
269 /* FACS */
270 static void
271 build_facs(GArray *table_data, BIOSLinker *linker)
272 {
273 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
274 memcpy(&facs->signature, "FACS", 4);
275 facs->length = cpu_to_le32(sizeof(*facs));
276 }
277
278 /* Load chipset information in FADT */
279 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
280 {
281 fadt->model = 1;
282 fadt->reserved1 = 0;
283 fadt->sci_int = cpu_to_le16(pm->sci_int);
284 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
285 fadt->acpi_enable = pm->acpi_enable_cmd;
286 fadt->acpi_disable = pm->acpi_disable_cmd;
287 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
288 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
289 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
290 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
291 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
292 /* EVT, CNT, TMR length matches hw/acpi/core.c */
293 fadt->pm1_evt_len = 4;
294 fadt->pm1_cnt_len = 2;
295 fadt->pm_tmr_len = 4;
296 fadt->gpe0_blk_len = pm->gpe0_blk_len;
297 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
298 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
299 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
300 (1 << ACPI_FADT_F_PROC_C1) |
301 (1 << ACPI_FADT_F_SLP_BUTTON) |
302 (1 << ACPI_FADT_F_RTC_S4));
303 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
304 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
305 * For more than 8 CPUs, "Clustered Logical" mode has to be used
306 */
307 if (max_cpus > 8) {
308 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
309 }
310 fadt->century = RTC_CENTURY;
311 }
312
313
314 /* FADT */
315 static void
316 build_fadt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm,
317 unsigned facs_tbl_offset, unsigned dsdt_tbl_offset,
318 const char *oem_id, const char *oem_table_id)
319 {
320 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
321 unsigned fw_ctrl_offset = (char *)&fadt->firmware_ctrl - table_data->data;
322 unsigned dsdt_entry_offset = (char *)&fadt->dsdt - table_data->data;
323
324 /* FACS address to be filled by Guest linker */
325 bios_linker_loader_add_pointer(linker,
326 ACPI_BUILD_TABLE_FILE, fw_ctrl_offset, sizeof(fadt->firmware_ctrl),
327 ACPI_BUILD_TABLE_FILE, facs_tbl_offset);
328
329 /* DSDT address to be filled by Guest linker */
330 fadt_setup(fadt, pm);
331 bios_linker_loader_add_pointer(linker,
332 ACPI_BUILD_TABLE_FILE, dsdt_entry_offset, sizeof(fadt->dsdt),
333 ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset);
334
335 build_header(linker, table_data,
336 (void *)fadt, "FACP", sizeof(*fadt), 1, oem_id, oem_table_id);
337 }
338
339 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
340 CPUArchIdList *apic_ids, GArray *entry)
341 {
342 uint32_t apic_id = apic_ids->cpus[uid].arch_id;
343
344 /* ACPI spec says that LAPIC entry for non present
345 * CPU may be omitted from MADT or it must be marked
346 * as disabled. However omitting non present CPU from
347 * MADT breaks hotplug on linux. So possible CPUs
348 * should be put in MADT but kept disabled.
349 */
350 if (apic_id < 255) {
351 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
352
353 apic->type = ACPI_APIC_PROCESSOR;
354 apic->length = sizeof(*apic);
355 apic->processor_id = uid;
356 apic->local_apic_id = apic_id;
357 if (apic_ids->cpus[uid].cpu != NULL) {
358 apic->flags = cpu_to_le32(1);
359 } else {
360 apic->flags = cpu_to_le32(0);
361 }
362 } else {
363 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic);
364
365 apic->type = ACPI_APIC_LOCAL_X2APIC;
366 apic->length = sizeof(*apic);
367 apic->uid = cpu_to_le32(uid);
368 apic->x2apic_id = cpu_to_le32(apic_id);
369 if (apic_ids->cpus[uid].cpu != NULL) {
370 apic->flags = cpu_to_le32(1);
371 } else {
372 apic->flags = cpu_to_le32(0);
373 }
374 }
375 }
376
377 static void
378 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
379 {
380 MachineClass *mc = MACHINE_GET_CLASS(pcms);
381 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
382 int madt_start = table_data->len;
383 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
384 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
385 bool x2apic_mode = false;
386
387 AcpiMultipleApicTable *madt;
388 AcpiMadtIoApic *io_apic;
389 AcpiMadtIntsrcovr *intsrcovr;
390 int i;
391
392 madt = acpi_data_push(table_data, sizeof *madt);
393 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
394 madt->flags = cpu_to_le32(1);
395
396 for (i = 0; i < apic_ids->len; i++) {
397 adevc->madt_cpu(adev, i, apic_ids, table_data);
398 if (apic_ids->cpus[i].arch_id > 254) {
399 x2apic_mode = true;
400 }
401 }
402 g_free(apic_ids);
403
404 io_apic = acpi_data_push(table_data, sizeof *io_apic);
405 io_apic->type = ACPI_APIC_IO;
406 io_apic->length = sizeof(*io_apic);
407 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
408 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
409 io_apic->interrupt = cpu_to_le32(0);
410
411 if (pcms->apic_xrupt_override) {
412 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
413 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
414 intsrcovr->length = sizeof(*intsrcovr);
415 intsrcovr->source = 0;
416 intsrcovr->gsi = cpu_to_le32(2);
417 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
418 }
419 for (i = 1; i < 16; i++) {
420 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
421 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
422 /* No need for a INT source override structure. */
423 continue;
424 }
425 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
426 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
427 intsrcovr->length = sizeof(*intsrcovr);
428 intsrcovr->source = i;
429 intsrcovr->gsi = cpu_to_le32(i);
430 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
431 }
432
433 if (x2apic_mode) {
434 AcpiMadtLocalX2ApicNmi *local_nmi;
435
436 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
437 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI;
438 local_nmi->length = sizeof(*local_nmi);
439 local_nmi->uid = 0xFFFFFFFF; /* all processors */
440 local_nmi->flags = cpu_to_le16(0);
441 local_nmi->lint = 1; /* ACPI_LINT1 */
442 } else {
443 AcpiMadtLocalNmi *local_nmi;
444
445 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
446 local_nmi->type = ACPI_APIC_LOCAL_NMI;
447 local_nmi->length = sizeof(*local_nmi);
448 local_nmi->processor_id = 0xff; /* all processors */
449 local_nmi->flags = cpu_to_le16(0);
450 local_nmi->lint = 1; /* ACPI_LINT1 */
451 }
452
453 build_header(linker, table_data,
454 (void *)(table_data->data + madt_start), "APIC",
455 table_data->len - madt_start, 1, NULL, NULL);
456 }
457
458 /* Assign BSEL property to all buses. In the future, this can be changed
459 * to only assign to buses that support hotplug.
460 */
461 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
462 {
463 unsigned *bsel_alloc = opaque;
464 unsigned *bus_bsel;
465
466 if (qbus_is_hotpluggable(BUS(bus))) {
467 bus_bsel = g_malloc(sizeof *bus_bsel);
468
469 *bus_bsel = (*bsel_alloc)++;
470 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
471 bus_bsel, NULL);
472 }
473
474 return bsel_alloc;
475 }
476
477 static void acpi_set_pci_info(void)
478 {
479 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
480 unsigned bsel_alloc = 0;
481
482 if (bus) {
483 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
484 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
485 }
486 }
487
488 static void build_append_pcihp_notify_entry(Aml *method, int slot)
489 {
490 Aml *if_ctx;
491 int32_t devfn = PCI_DEVFN(slot, 0);
492
493 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
494 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
495 aml_append(method, if_ctx);
496 }
497
498 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
499 bool pcihp_bridge_en)
500 {
501 Aml *dev, *notify_method, *method;
502 QObject *bsel;
503 PCIBus *sec;
504 int i;
505
506 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
507 if (bsel) {
508 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
509
510 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
511 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
512 }
513
514 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
515 DeviceClass *dc;
516 PCIDeviceClass *pc;
517 PCIDevice *pdev = bus->devices[i];
518 int slot = PCI_SLOT(i);
519 bool hotplug_enabled_dev;
520 bool bridge_in_acpi;
521
522 if (!pdev) {
523 if (bsel) { /* add hotplug slots for non present devices */
524 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
525 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
526 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
527 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
528 aml_append(method,
529 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
530 );
531 aml_append(dev, method);
532 aml_append(parent_scope, dev);
533
534 build_append_pcihp_notify_entry(notify_method, slot);
535 }
536 continue;
537 }
538
539 pc = PCI_DEVICE_GET_CLASS(pdev);
540 dc = DEVICE_GET_CLASS(pdev);
541
542 /* When hotplug for bridges is enabled, bridges are
543 * described in ACPI separately (see build_pci_bus_end).
544 * In this case they aren't themselves hot-pluggable.
545 * Hotplugged bridges *are* hot-pluggable.
546 */
547 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
548 !DEVICE(pdev)->hotplugged;
549
550 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
551
552 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
553 continue;
554 }
555
556 /* start to compose PCI slot descriptor */
557 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
558 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
559
560 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
561 /* add VGA specific AML methods */
562 int s3d;
563
564 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
565 s3d = 3;
566 } else {
567 s3d = 0;
568 }
569
570 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
571 aml_append(method, aml_return(aml_int(0)));
572 aml_append(dev, method);
573
574 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
575 aml_append(method, aml_return(aml_int(0)));
576 aml_append(dev, method);
577
578 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
579 aml_append(method, aml_return(aml_int(s3d)));
580 aml_append(dev, method);
581 } else if (hotplug_enabled_dev) {
582 /* add _SUN/_EJ0 to make slot hotpluggable */
583 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
584
585 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
586 aml_append(method,
587 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
588 );
589 aml_append(dev, method);
590
591 if (bsel) {
592 build_append_pcihp_notify_entry(notify_method, slot);
593 }
594 } else if (bridge_in_acpi) {
595 /*
596 * device is coldplugged bridge,
597 * add child device descriptions into its scope
598 */
599 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
600
601 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
602 }
603 /* slot descriptor has been composed, add it into parent context */
604 aml_append(parent_scope, dev);
605 }
606
607 if (bsel) {
608 aml_append(parent_scope, notify_method);
609 }
610
611 /* Append PCNT method to notify about events on local and child buses.
612 * Add unconditionally for root since DSDT expects it.
613 */
614 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
615
616 /* If bus supports hotplug select it and notify about local events */
617 if (bsel) {
618 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
619 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
620 aml_append(method,
621 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
622 );
623 aml_append(method,
624 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
625 );
626 }
627
628 /* Notify about child bus events in any case */
629 if (pcihp_bridge_en) {
630 QLIST_FOREACH(sec, &bus->child, sibling) {
631 int32_t devfn = sec->parent_dev->devfn;
632
633 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
634 continue;
635 }
636
637 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
638 }
639 }
640 aml_append(parent_scope, method);
641 qobject_decref(bsel);
642 }
643
644 /**
645 * build_prt_entry:
646 * @link_name: link name for PCI route entry
647 *
648 * build AML package containing a PCI route entry for @link_name
649 */
650 static Aml *build_prt_entry(const char *link_name)
651 {
652 Aml *a_zero = aml_int(0);
653 Aml *pkg = aml_package(4);
654 aml_append(pkg, a_zero);
655 aml_append(pkg, a_zero);
656 aml_append(pkg, aml_name("%s", link_name));
657 aml_append(pkg, a_zero);
658 return pkg;
659 }
660
661 /*
662 * initialize_route - Initialize the interrupt routing rule
663 * through a specific LINK:
664 * if (lnk_idx == idx)
665 * route using link 'link_name'
666 */
667 static Aml *initialize_route(Aml *route, const char *link_name,
668 Aml *lnk_idx, int idx)
669 {
670 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
671 Aml *pkg = build_prt_entry(link_name);
672
673 aml_append(if_ctx, aml_store(pkg, route));
674
675 return if_ctx;
676 }
677
678 /*
679 * build_prt - Define interrupt rounting rules
680 *
681 * Returns an array of 128 routes, one for each device,
682 * based on device location.
683 * The main goal is to equaly distribute the interrupts
684 * over the 4 existing ACPI links (works only for i440fx).
685 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
686 *
687 */
688 static Aml *build_prt(bool is_pci0_prt)
689 {
690 Aml *method, *while_ctx, *pin, *res;
691
692 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
693 res = aml_local(0);
694 pin = aml_local(1);
695 aml_append(method, aml_store(aml_package(128), res));
696 aml_append(method, aml_store(aml_int(0), pin));
697
698 /* while (pin < 128) */
699 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
700 {
701 Aml *slot = aml_local(2);
702 Aml *lnk_idx = aml_local(3);
703 Aml *route = aml_local(4);
704
705 /* slot = pin >> 2 */
706 aml_append(while_ctx,
707 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
708 /* lnk_idx = (slot + pin) & 3 */
709 aml_append(while_ctx,
710 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
711 lnk_idx));
712
713 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
714 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
715 if (is_pci0_prt) {
716 Aml *if_device_1, *if_pin_4, *else_pin_4;
717
718 /* device 1 is the power-management device, needs SCI */
719 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
720 {
721 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
722 {
723 aml_append(if_pin_4,
724 aml_store(build_prt_entry("LNKS"), route));
725 }
726 aml_append(if_device_1, if_pin_4);
727 else_pin_4 = aml_else();
728 {
729 aml_append(else_pin_4,
730 aml_store(build_prt_entry("LNKA"), route));
731 }
732 aml_append(if_device_1, else_pin_4);
733 }
734 aml_append(while_ctx, if_device_1);
735 } else {
736 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
737 }
738 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
739 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
740
741 /* route[0] = 0x[slot]FFFF */
742 aml_append(while_ctx,
743 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
744 NULL),
745 aml_index(route, aml_int(0))));
746 /* route[1] = pin & 3 */
747 aml_append(while_ctx,
748 aml_store(aml_and(pin, aml_int(3), NULL),
749 aml_index(route, aml_int(1))));
750 /* res[pin] = route */
751 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
752 /* pin++ */
753 aml_append(while_ctx, aml_increment(pin));
754 }
755 aml_append(method, while_ctx);
756 /* return res*/
757 aml_append(method, aml_return(res));
758
759 return method;
760 }
761
762 typedef struct CrsRangeEntry {
763 uint64_t base;
764 uint64_t limit;
765 } CrsRangeEntry;
766
767 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
768 {
769 CrsRangeEntry *entry;
770
771 entry = g_malloc(sizeof(*entry));
772 entry->base = base;
773 entry->limit = limit;
774
775 g_ptr_array_add(ranges, entry);
776 }
777
778 static void crs_range_free(gpointer data)
779 {
780 CrsRangeEntry *entry = (CrsRangeEntry *)data;
781 g_free(entry);
782 }
783
784 typedef struct CrsRangeSet {
785 GPtrArray *io_ranges;
786 GPtrArray *mem_ranges;
787 GPtrArray *mem_64bit_ranges;
788 } CrsRangeSet;
789
790 static void crs_range_set_init(CrsRangeSet *range_set)
791 {
792 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
793 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
794 range_set->mem_64bit_ranges =
795 g_ptr_array_new_with_free_func(crs_range_free);
796 }
797
798 static void crs_range_set_free(CrsRangeSet *range_set)
799 {
800 g_ptr_array_free(range_set->io_ranges, true);
801 g_ptr_array_free(range_set->mem_ranges, true);
802 g_ptr_array_free(range_set->mem_64bit_ranges, true);
803 }
804
805 static gint crs_range_compare(gconstpointer a, gconstpointer b)
806 {
807 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
808 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
809
810 return (int64_t)entry_a->base - (int64_t)entry_b->base;
811 }
812
813 /*
814 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
815 * interval, computes the 'free' ranges from the same interval.
816 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
817 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
818 */
819 static void crs_replace_with_free_ranges(GPtrArray *ranges,
820 uint64_t start, uint64_t end)
821 {
822 GPtrArray *free_ranges = g_ptr_array_new();
823 uint64_t free_base = start;
824 int i;
825
826 g_ptr_array_sort(ranges, crs_range_compare);
827 for (i = 0; i < ranges->len; i++) {
828 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
829
830 if (free_base < used->base) {
831 crs_range_insert(free_ranges, free_base, used->base - 1);
832 }
833
834 free_base = used->limit + 1;
835 }
836
837 if (free_base < end) {
838 crs_range_insert(free_ranges, free_base, end);
839 }
840
841 g_ptr_array_set_size(ranges, 0);
842 for (i = 0; i < free_ranges->len; i++) {
843 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
844 }
845
846 g_ptr_array_free(free_ranges, true);
847 }
848
849 /*
850 * crs_range_merge - merges adjacent ranges in the given array.
851 * Array elements are deleted and replaced with the merged ranges.
852 */
853 static void crs_range_merge(GPtrArray *range)
854 {
855 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
856 CrsRangeEntry *entry;
857 uint64_t range_base, range_limit;
858 int i;
859
860 if (!range->len) {
861 return;
862 }
863
864 g_ptr_array_sort(range, crs_range_compare);
865
866 entry = g_ptr_array_index(range, 0);
867 range_base = entry->base;
868 range_limit = entry->limit;
869 for (i = 1; i < range->len; i++) {
870 entry = g_ptr_array_index(range, i);
871 if (entry->base - 1 == range_limit) {
872 range_limit = entry->limit;
873 } else {
874 crs_range_insert(tmp, range_base, range_limit);
875 range_base = entry->base;
876 range_limit = entry->limit;
877 }
878 }
879 crs_range_insert(tmp, range_base, range_limit);
880
881 g_ptr_array_set_size(range, 0);
882 for (i = 0; i < tmp->len; i++) {
883 entry = g_ptr_array_index(tmp, i);
884 crs_range_insert(range, entry->base, entry->limit);
885 }
886 g_ptr_array_free(tmp, true);
887 }
888
889 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
890 {
891 Aml *crs = aml_resource_template();
892 CrsRangeSet temp_range_set;
893 CrsRangeEntry *entry;
894 uint8_t max_bus = pci_bus_num(host->bus);
895 uint8_t type;
896 int devfn;
897 int i;
898
899 crs_range_set_init(&temp_range_set);
900 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
901 uint64_t range_base, range_limit;
902 PCIDevice *dev = host->bus->devices[devfn];
903
904 if (!dev) {
905 continue;
906 }
907
908 for (i = 0; i < PCI_NUM_REGIONS; i++) {
909 PCIIORegion *r = &dev->io_regions[i];
910
911 range_base = r->addr;
912 range_limit = r->addr + r->size - 1;
913
914 /*
915 * Work-around for old bioses
916 * that do not support multiple root buses
917 */
918 if (!range_base || range_base > range_limit) {
919 continue;
920 }
921
922 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
923 crs_range_insert(temp_range_set.io_ranges,
924 range_base, range_limit);
925 } else { /* "memory" */
926 crs_range_insert(temp_range_set.mem_ranges,
927 range_base, range_limit);
928 }
929 }
930
931 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
932 if (type == PCI_HEADER_TYPE_BRIDGE) {
933 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
934 if (subordinate > max_bus) {
935 max_bus = subordinate;
936 }
937
938 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
939 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
940
941 /*
942 * Work-around for old bioses
943 * that do not support multiple root buses
944 */
945 if (range_base && range_base <= range_limit) {
946 crs_range_insert(temp_range_set.io_ranges,
947 range_base, range_limit);
948 }
949
950 range_base =
951 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
952 range_limit =
953 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
954
955 /*
956 * Work-around for old bioses
957 * that do not support multiple root buses
958 */
959 if (range_base && range_base <= range_limit) {
960 uint64_t length = range_limit - range_base + 1;
961 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
962 crs_range_insert(temp_range_set.mem_ranges,
963 range_base, range_limit);
964 } else {
965 crs_range_insert(temp_range_set.mem_64bit_ranges,
966 range_base, range_limit);
967 }
968 }
969
970 range_base =
971 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
972 range_limit =
973 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
974
975 /*
976 * Work-around for old bioses
977 * that do not support multiple root buses
978 */
979 if (range_base && range_base <= range_limit) {
980 uint64_t length = range_limit - range_base + 1;
981 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
982 crs_range_insert(temp_range_set.mem_ranges,
983 range_base, range_limit);
984 } else {
985 crs_range_insert(temp_range_set.mem_64bit_ranges,
986 range_base, range_limit);
987 }
988 }
989 }
990 }
991
992 crs_range_merge(temp_range_set.io_ranges);
993 for (i = 0; i < temp_range_set.io_ranges->len; i++) {
994 entry = g_ptr_array_index(temp_range_set.io_ranges, i);
995 aml_append(crs,
996 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
997 AML_POS_DECODE, AML_ENTIRE_RANGE,
998 0, entry->base, entry->limit, 0,
999 entry->limit - entry->base + 1));
1000 crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
1001 }
1002
1003 crs_range_merge(temp_range_set.mem_ranges);
1004 for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
1005 entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
1006 aml_append(crs,
1007 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1008 AML_MAX_FIXED, AML_NON_CACHEABLE,
1009 AML_READ_WRITE,
1010 0, entry->base, entry->limit, 0,
1011 entry->limit - entry->base + 1));
1012 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
1013 }
1014
1015 crs_range_merge(temp_range_set.mem_64bit_ranges);
1016 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
1017 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
1018 aml_append(crs,
1019 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1020 AML_MAX_FIXED, AML_NON_CACHEABLE,
1021 AML_READ_WRITE,
1022 0, entry->base, entry->limit, 0,
1023 entry->limit - entry->base + 1));
1024 crs_range_insert(range_set->mem_64bit_ranges,
1025 entry->base, entry->limit);
1026 }
1027
1028 crs_range_set_free(&temp_range_set);
1029
1030 aml_append(crs,
1031 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1032 0,
1033 pci_bus_num(host->bus),
1034 max_bus,
1035 0,
1036 max_bus - pci_bus_num(host->bus) + 1));
1037
1038 return crs;
1039 }
1040
1041 static void build_hpet_aml(Aml *table)
1042 {
1043 Aml *crs;
1044 Aml *field;
1045 Aml *method;
1046 Aml *if_ctx;
1047 Aml *scope = aml_scope("_SB");
1048 Aml *dev = aml_device("HPET");
1049 Aml *zero = aml_int(0);
1050 Aml *id = aml_local(0);
1051 Aml *period = aml_local(1);
1052
1053 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1054 aml_append(dev, aml_name_decl("_UID", zero));
1055
1056 aml_append(dev,
1057 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1058 HPET_LEN));
1059 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1060 aml_append(field, aml_named_field("VEND", 32));
1061 aml_append(field, aml_named_field("PRD", 32));
1062 aml_append(dev, field);
1063
1064 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1065 aml_append(method, aml_store(aml_name("VEND"), id));
1066 aml_append(method, aml_store(aml_name("PRD"), period));
1067 aml_append(method, aml_shiftright(id, aml_int(16), id));
1068 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1069 aml_equal(id, aml_int(0xffff))));
1070 {
1071 aml_append(if_ctx, aml_return(zero));
1072 }
1073 aml_append(method, if_ctx);
1074
1075 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1076 aml_lgreater(period, aml_int(100000000))));
1077 {
1078 aml_append(if_ctx, aml_return(zero));
1079 }
1080 aml_append(method, if_ctx);
1081
1082 aml_append(method, aml_return(aml_int(0x0F)));
1083 aml_append(dev, method);
1084
1085 crs = aml_resource_template();
1086 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1087 aml_append(dev, aml_name_decl("_CRS", crs));
1088
1089 aml_append(scope, dev);
1090 aml_append(table, scope);
1091 }
1092
1093 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
1094 {
1095 Aml *dev, *fdi;
1096 uint8_t maxc, maxh, maxs;
1097
1098 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1099
1100 dev = aml_device("FLP%c", 'A' + idx);
1101
1102 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1103
1104 fdi = aml_package(16);
1105 aml_append(fdi, aml_int(idx)); /* Drive Number */
1106 aml_append(fdi,
1107 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1108 /*
1109 * the values below are the limits of the drive, and are thus independent
1110 * of the inserted media
1111 */
1112 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1113 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1114 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1115 /*
1116 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1117 * the drive type, so shall we
1118 */
1119 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1120 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1121 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1122 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1123 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1124 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1125 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1126 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1127 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1128 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1129 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1130
1131 aml_append(dev, aml_name_decl("_FDI", fdi));
1132 return dev;
1133 }
1134
1135 static Aml *build_fdc_device_aml(ISADevice *fdc)
1136 {
1137 int i;
1138 Aml *dev;
1139 Aml *crs;
1140
1141 #define ACPI_FDE_MAX_FD 4
1142 uint32_t fde_buf[5] = {
1143 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1144 cpu_to_le32(2) /* tape presence (2 == never present) */
1145 };
1146
1147 dev = aml_device("FDC0");
1148 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1149
1150 crs = aml_resource_template();
1151 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1152 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1153 aml_append(crs, aml_irq_no_flags(6));
1154 aml_append(crs,
1155 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1156 aml_append(dev, aml_name_decl("_CRS", crs));
1157
1158 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1159 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1160
1161 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1162 fde_buf[i] = cpu_to_le32(1); /* drive present */
1163 aml_append(dev, build_fdinfo_aml(i, type));
1164 }
1165 }
1166 aml_append(dev, aml_name_decl("_FDE",
1167 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1168
1169 return dev;
1170 }
1171
1172 static Aml *build_rtc_device_aml(void)
1173 {
1174 Aml *dev;
1175 Aml *crs;
1176
1177 dev = aml_device("RTC");
1178 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1179 crs = aml_resource_template();
1180 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1181 aml_append(crs, aml_irq_no_flags(8));
1182 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1183 aml_append(dev, aml_name_decl("_CRS", crs));
1184
1185 return dev;
1186 }
1187
1188 static Aml *build_kbd_device_aml(void)
1189 {
1190 Aml *dev;
1191 Aml *crs;
1192 Aml *method;
1193
1194 dev = aml_device("KBD");
1195 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1196
1197 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1198 aml_append(method, aml_return(aml_int(0x0f)));
1199 aml_append(dev, method);
1200
1201 crs = aml_resource_template();
1202 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1203 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1204 aml_append(crs, aml_irq_no_flags(1));
1205 aml_append(dev, aml_name_decl("_CRS", crs));
1206
1207 return dev;
1208 }
1209
1210 static Aml *build_mouse_device_aml(void)
1211 {
1212 Aml *dev;
1213 Aml *crs;
1214 Aml *method;
1215
1216 dev = aml_device("MOU");
1217 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1218
1219 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1220 aml_append(method, aml_return(aml_int(0x0f)));
1221 aml_append(dev, method);
1222
1223 crs = aml_resource_template();
1224 aml_append(crs, aml_irq_no_flags(12));
1225 aml_append(dev, aml_name_decl("_CRS", crs));
1226
1227 return dev;
1228 }
1229
1230 static Aml *build_lpt_device_aml(void)
1231 {
1232 Aml *dev;
1233 Aml *crs;
1234 Aml *method;
1235 Aml *if_ctx;
1236 Aml *else_ctx;
1237 Aml *zero = aml_int(0);
1238 Aml *is_present = aml_local(0);
1239
1240 dev = aml_device("LPT");
1241 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1242
1243 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1244 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1245 if_ctx = aml_if(aml_equal(is_present, zero));
1246 {
1247 aml_append(if_ctx, aml_return(aml_int(0x00)));
1248 }
1249 aml_append(method, if_ctx);
1250 else_ctx = aml_else();
1251 {
1252 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1253 }
1254 aml_append(method, else_ctx);
1255 aml_append(dev, method);
1256
1257 crs = aml_resource_template();
1258 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1259 aml_append(crs, aml_irq_no_flags(7));
1260 aml_append(dev, aml_name_decl("_CRS", crs));
1261
1262 return dev;
1263 }
1264
1265 static Aml *build_com_device_aml(uint8_t uid)
1266 {
1267 Aml *dev;
1268 Aml *crs;
1269 Aml *method;
1270 Aml *if_ctx;
1271 Aml *else_ctx;
1272 Aml *zero = aml_int(0);
1273 Aml *is_present = aml_local(0);
1274 const char *enabled_field = "CAEN";
1275 uint8_t irq = 4;
1276 uint16_t io_port = 0x03F8;
1277
1278 assert(uid == 1 || uid == 2);
1279 if (uid == 2) {
1280 enabled_field = "CBEN";
1281 irq = 3;
1282 io_port = 0x02F8;
1283 }
1284
1285 dev = aml_device("COM%d", uid);
1286 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1287 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1288
1289 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1290 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1291 if_ctx = aml_if(aml_equal(is_present, zero));
1292 {
1293 aml_append(if_ctx, aml_return(aml_int(0x00)));
1294 }
1295 aml_append(method, if_ctx);
1296 else_ctx = aml_else();
1297 {
1298 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1299 }
1300 aml_append(method, else_ctx);
1301 aml_append(dev, method);
1302
1303 crs = aml_resource_template();
1304 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1305 aml_append(crs, aml_irq_no_flags(irq));
1306 aml_append(dev, aml_name_decl("_CRS", crs));
1307
1308 return dev;
1309 }
1310
1311 static void build_isa_devices_aml(Aml *table)
1312 {
1313 ISADevice *fdc = pc_find_fdc0();
1314 bool ambiguous;
1315
1316 Aml *scope = aml_scope("_SB.PCI0.ISA");
1317 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
1318
1319 aml_append(scope, build_rtc_device_aml());
1320 aml_append(scope, build_kbd_device_aml());
1321 aml_append(scope, build_mouse_device_aml());
1322 if (fdc) {
1323 aml_append(scope, build_fdc_device_aml(fdc));
1324 }
1325 aml_append(scope, build_lpt_device_aml());
1326 aml_append(scope, build_com_device_aml(1));
1327 aml_append(scope, build_com_device_aml(2));
1328
1329 if (ambiguous) {
1330 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1331 } else if (!obj) {
1332 error_report("No ISA bus, unable to define IPMI ACPI data");
1333 } else {
1334 build_acpi_ipmi_devices(scope, BUS(obj));
1335 }
1336
1337 aml_append(table, scope);
1338 }
1339
1340 static void build_dbg_aml(Aml *table)
1341 {
1342 Aml *field;
1343 Aml *method;
1344 Aml *while_ctx;
1345 Aml *scope = aml_scope("\\");
1346 Aml *buf = aml_local(0);
1347 Aml *len = aml_local(1);
1348 Aml *idx = aml_local(2);
1349
1350 aml_append(scope,
1351 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1352 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1353 aml_append(field, aml_named_field("DBGB", 8));
1354 aml_append(scope, field);
1355
1356 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1357
1358 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1359 aml_append(method, aml_to_buffer(buf, buf));
1360 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1361 aml_append(method, aml_store(aml_int(0), idx));
1362
1363 while_ctx = aml_while(aml_lless(idx, len));
1364 aml_append(while_ctx,
1365 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1366 aml_append(while_ctx, aml_increment(idx));
1367 aml_append(method, while_ctx);
1368
1369 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1370 aml_append(scope, method);
1371
1372 aml_append(table, scope);
1373 }
1374
1375 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1376 {
1377 Aml *dev;
1378 Aml *crs;
1379 Aml *method;
1380 uint32_t irqs[] = {5, 10, 11};
1381
1382 dev = aml_device("%s", name);
1383 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1384 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1385
1386 crs = aml_resource_template();
1387 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1388 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1389 aml_append(dev, aml_name_decl("_PRS", crs));
1390
1391 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1392 aml_append(method, aml_return(aml_call1("IQST", reg)));
1393 aml_append(dev, method);
1394
1395 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1396 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1397 aml_append(dev, method);
1398
1399 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1400 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1401 aml_append(dev, method);
1402
1403 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1404 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1405 aml_append(method, aml_store(aml_name("PRRI"), reg));
1406 aml_append(dev, method);
1407
1408 return dev;
1409 }
1410
1411 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1412 {
1413 Aml *dev;
1414 Aml *crs;
1415 Aml *method;
1416 uint32_t irqs;
1417
1418 dev = aml_device("%s", name);
1419 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1420 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1421
1422 crs = aml_resource_template();
1423 irqs = gsi;
1424 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1425 AML_SHARED, &irqs, 1));
1426 aml_append(dev, aml_name_decl("_PRS", crs));
1427
1428 aml_append(dev, aml_name_decl("_CRS", crs));
1429
1430 /*
1431 * _DIS can be no-op because the interrupt cannot be disabled.
1432 */
1433 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1434 aml_append(dev, method);
1435
1436 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1437 aml_append(dev, method);
1438
1439 return dev;
1440 }
1441
1442 /* _CRS method - get current settings */
1443 static Aml *build_iqcr_method(bool is_piix4)
1444 {
1445 Aml *if_ctx;
1446 uint32_t irqs;
1447 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1448 Aml *crs = aml_resource_template();
1449
1450 irqs = 0;
1451 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1452 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1453 aml_append(method, aml_name_decl("PRR0", crs));
1454
1455 aml_append(method,
1456 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1457
1458 if (is_piix4) {
1459 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1460 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1461 aml_append(method, if_ctx);
1462 } else {
1463 aml_append(method,
1464 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1465 aml_name("PRRI")));
1466 }
1467
1468 aml_append(method, aml_return(aml_name("PRR0")));
1469 return method;
1470 }
1471
1472 /* _STA method - get status */
1473 static Aml *build_irq_status_method(void)
1474 {
1475 Aml *if_ctx;
1476 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1477
1478 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1479 aml_append(if_ctx, aml_return(aml_int(0x09)));
1480 aml_append(method, if_ctx);
1481 aml_append(method, aml_return(aml_int(0x0B)));
1482 return method;
1483 }
1484
1485 static void build_piix4_pci0_int(Aml *table)
1486 {
1487 Aml *dev;
1488 Aml *crs;
1489 Aml *field;
1490 Aml *method;
1491 uint32_t irqs;
1492 Aml *sb_scope = aml_scope("_SB");
1493 Aml *pci0_scope = aml_scope("PCI0");
1494
1495 aml_append(pci0_scope, build_prt(true));
1496 aml_append(sb_scope, pci0_scope);
1497
1498 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1499 aml_append(field, aml_named_field("PRQ0", 8));
1500 aml_append(field, aml_named_field("PRQ1", 8));
1501 aml_append(field, aml_named_field("PRQ2", 8));
1502 aml_append(field, aml_named_field("PRQ3", 8));
1503 aml_append(sb_scope, field);
1504
1505 aml_append(sb_scope, build_irq_status_method());
1506 aml_append(sb_scope, build_iqcr_method(true));
1507
1508 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1509 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1510 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1511 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1512
1513 dev = aml_device("LNKS");
1514 {
1515 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1516 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1517
1518 crs = aml_resource_template();
1519 irqs = 9;
1520 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1521 AML_ACTIVE_HIGH, AML_SHARED,
1522 &irqs, 1));
1523 aml_append(dev, aml_name_decl("_PRS", crs));
1524
1525 /* The SCI cannot be disabled and is always attached to GSI 9,
1526 * so these are no-ops. We only need this link to override the
1527 * polarity to active high and match the content of the MADT.
1528 */
1529 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1530 aml_append(method, aml_return(aml_int(0x0b)));
1531 aml_append(dev, method);
1532
1533 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1534 aml_append(dev, method);
1535
1536 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1537 aml_append(method, aml_return(aml_name("_PRS")));
1538 aml_append(dev, method);
1539
1540 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1541 aml_append(dev, method);
1542 }
1543 aml_append(sb_scope, dev);
1544
1545 aml_append(table, sb_scope);
1546 }
1547
1548 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1549 {
1550 int i;
1551 int head;
1552 Aml *pkg;
1553 char base = name[3] < 'E' ? 'A' : 'E';
1554 char *s = g_strdup(name);
1555 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1556
1557 assert(strlen(s) == 4);
1558
1559 head = name[3] - base;
1560 for (i = 0; i < 4; i++) {
1561 if (head + i > 3) {
1562 head = i * -1;
1563 }
1564 s[3] = base + head + i;
1565 pkg = aml_package(4);
1566 aml_append(pkg, a_nr);
1567 aml_append(pkg, aml_int(i));
1568 aml_append(pkg, aml_name("%s", s));
1569 aml_append(pkg, aml_int(0));
1570 aml_append(ctx, pkg);
1571 }
1572 g_free(s);
1573 }
1574
1575 static Aml *build_q35_routing_table(const char *str)
1576 {
1577 int i;
1578 Aml *pkg;
1579 char *name = g_strdup_printf("%s ", str);
1580
1581 pkg = aml_package(128);
1582 for (i = 0; i < 0x18; i++) {
1583 name[3] = 'E' + (i & 0x3);
1584 append_q35_prt_entry(pkg, i, name);
1585 }
1586
1587 name[3] = 'E';
1588 append_q35_prt_entry(pkg, 0x18, name);
1589
1590 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1591 for (i = 0x0019; i < 0x1e; i++) {
1592 name[3] = 'A';
1593 append_q35_prt_entry(pkg, i, name);
1594 }
1595
1596 /* PCIe->PCI bridge. use PIRQ[E-H] */
1597 name[3] = 'E';
1598 append_q35_prt_entry(pkg, 0x1e, name);
1599 name[3] = 'A';
1600 append_q35_prt_entry(pkg, 0x1f, name);
1601
1602 g_free(name);
1603 return pkg;
1604 }
1605
1606 static void build_q35_pci0_int(Aml *table)
1607 {
1608 Aml *field;
1609 Aml *method;
1610 Aml *sb_scope = aml_scope("_SB");
1611 Aml *pci0_scope = aml_scope("PCI0");
1612
1613 /* Zero => PIC mode, One => APIC Mode */
1614 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1615 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1616 {
1617 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1618 }
1619 aml_append(table, method);
1620
1621 aml_append(pci0_scope,
1622 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1623 aml_append(pci0_scope,
1624 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1625
1626 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1627 {
1628 Aml *if_ctx;
1629 Aml *else_ctx;
1630
1631 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1632 section 6.2.8.1 */
1633 /* Note: we provide the same info as the PCI routing
1634 table of the Bochs BIOS */
1635 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1636 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1637 aml_append(method, if_ctx);
1638 else_ctx = aml_else();
1639 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1640 aml_append(method, else_ctx);
1641 }
1642 aml_append(pci0_scope, method);
1643 aml_append(sb_scope, pci0_scope);
1644
1645 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1646 aml_append(field, aml_named_field("PRQA", 8));
1647 aml_append(field, aml_named_field("PRQB", 8));
1648 aml_append(field, aml_named_field("PRQC", 8));
1649 aml_append(field, aml_named_field("PRQD", 8));
1650 aml_append(field, aml_reserved_field(0x20));
1651 aml_append(field, aml_named_field("PRQE", 8));
1652 aml_append(field, aml_named_field("PRQF", 8));
1653 aml_append(field, aml_named_field("PRQG", 8));
1654 aml_append(field, aml_named_field("PRQH", 8));
1655 aml_append(sb_scope, field);
1656
1657 aml_append(sb_scope, build_irq_status_method());
1658 aml_append(sb_scope, build_iqcr_method(false));
1659
1660 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1661 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1662 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1663 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1664 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1665 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1666 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1667 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1668
1669 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1670 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1671 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1672 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1673 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1674 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1675 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1676 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1677
1678 aml_append(table, sb_scope);
1679 }
1680
1681 static void build_q35_isa_bridge(Aml *table)
1682 {
1683 Aml *dev;
1684 Aml *scope;
1685 Aml *field;
1686
1687 scope = aml_scope("_SB.PCI0");
1688 dev = aml_device("ISA");
1689 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1690
1691 /* ICH9 PCI to ISA irq remapping */
1692 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1693 aml_int(0x60), 0x0C));
1694
1695 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1696 aml_int(0x80), 0x02));
1697 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1698 aml_append(field, aml_named_field("COMA", 3));
1699 aml_append(field, aml_reserved_field(1));
1700 aml_append(field, aml_named_field("COMB", 3));
1701 aml_append(field, aml_reserved_field(1));
1702 aml_append(field, aml_named_field("LPTD", 2));
1703 aml_append(dev, field);
1704
1705 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1706 aml_int(0x82), 0x02));
1707 /* enable bits */
1708 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1709 aml_append(field, aml_named_field("CAEN", 1));
1710 aml_append(field, aml_named_field("CBEN", 1));
1711 aml_append(field, aml_named_field("LPEN", 1));
1712 aml_append(dev, field);
1713
1714 aml_append(scope, dev);
1715 aml_append(table, scope);
1716 }
1717
1718 static void build_piix4_pm(Aml *table)
1719 {
1720 Aml *dev;
1721 Aml *scope;
1722
1723 scope = aml_scope("_SB.PCI0");
1724 dev = aml_device("PX13");
1725 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1726
1727 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1728 aml_int(0x00), 0xff));
1729 aml_append(scope, dev);
1730 aml_append(table, scope);
1731 }
1732
1733 static void build_piix4_isa_bridge(Aml *table)
1734 {
1735 Aml *dev;
1736 Aml *scope;
1737 Aml *field;
1738
1739 scope = aml_scope("_SB.PCI0");
1740 dev = aml_device("ISA");
1741 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1742
1743 /* PIIX PCI to ISA irq remapping */
1744 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1745 aml_int(0x60), 0x04));
1746 /* enable bits */
1747 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1748 /* Offset(0x5f),, 7, */
1749 aml_append(field, aml_reserved_field(0x2f8));
1750 aml_append(field, aml_reserved_field(7));
1751 aml_append(field, aml_named_field("LPEN", 1));
1752 /* Offset(0x67),, 3, */
1753 aml_append(field, aml_reserved_field(0x38));
1754 aml_append(field, aml_reserved_field(3));
1755 aml_append(field, aml_named_field("CAEN", 1));
1756 aml_append(field, aml_reserved_field(3));
1757 aml_append(field, aml_named_field("CBEN", 1));
1758 aml_append(dev, field);
1759
1760 aml_append(scope, dev);
1761 aml_append(table, scope);
1762 }
1763
1764 static void build_piix4_pci_hotplug(Aml *table)
1765 {
1766 Aml *scope;
1767 Aml *field;
1768 Aml *method;
1769
1770 scope = aml_scope("_SB.PCI0");
1771
1772 aml_append(scope,
1773 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1774 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1775 aml_append(field, aml_named_field("PCIU", 32));
1776 aml_append(field, aml_named_field("PCID", 32));
1777 aml_append(scope, field);
1778
1779 aml_append(scope,
1780 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1781 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1782 aml_append(field, aml_named_field("B0EJ", 32));
1783 aml_append(scope, field);
1784
1785 aml_append(scope,
1786 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1787 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1788 aml_append(field, aml_named_field("BNUM", 32));
1789 aml_append(scope, field);
1790
1791 aml_append(scope, aml_mutex("BLCK", 0));
1792
1793 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1794 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1795 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1796 aml_append(method,
1797 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1798 aml_append(method, aml_release(aml_name("BLCK")));
1799 aml_append(method, aml_return(aml_int(0)));
1800 aml_append(scope, method);
1801
1802 aml_append(table, scope);
1803 }
1804
1805 static Aml *build_q35_osc_method(void)
1806 {
1807 Aml *if_ctx;
1808 Aml *if_ctx2;
1809 Aml *else_ctx;
1810 Aml *method;
1811 Aml *a_cwd1 = aml_name("CDW1");
1812 Aml *a_ctrl = aml_name("CTRL");
1813
1814 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1815 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1816
1817 if_ctx = aml_if(aml_equal(
1818 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1819 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1820 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1821
1822 aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1823 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1824
1825 /*
1826 * Always allow native PME, AER (no dependencies)
1827 * Never allow SHPC (no SHPC controller in this system)
1828 */
1829 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
1830
1831 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1832 /* Unknown revision */
1833 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1834 aml_append(if_ctx, if_ctx2);
1835
1836 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1837 /* Capabilities bits were masked */
1838 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1839 aml_append(if_ctx, if_ctx2);
1840
1841 /* Update DWORD3 in the buffer */
1842 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1843 aml_append(method, if_ctx);
1844
1845 else_ctx = aml_else();
1846 /* Unrecognized UUID */
1847 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1848 aml_append(method, else_ctx);
1849
1850 aml_append(method, aml_return(aml_arg(3)));
1851 return method;
1852 }
1853
1854 static void
1855 build_dsdt(GArray *table_data, BIOSLinker *linker,
1856 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1857 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1858 {
1859 CrsRangeEntry *entry;
1860 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1861 CrsRangeSet crs_range_set;
1862 PCMachineState *pcms = PC_MACHINE(machine);
1863 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1864 uint32_t nr_mem = machine->ram_slots;
1865 int root_bus_limit = 0xFF;
1866 PCIBus *bus = NULL;
1867 int i;
1868
1869 dsdt = init_aml_allocator();
1870
1871 /* Reserve space for header */
1872 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1873
1874 build_dbg_aml(dsdt);
1875 if (misc->is_piix4) {
1876 sb_scope = aml_scope("_SB");
1877 dev = aml_device("PCI0");
1878 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1879 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1880 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1881 aml_append(sb_scope, dev);
1882 aml_append(dsdt, sb_scope);
1883
1884 build_hpet_aml(dsdt);
1885 build_piix4_pm(dsdt);
1886 build_piix4_isa_bridge(dsdt);
1887 build_isa_devices_aml(dsdt);
1888 build_piix4_pci_hotplug(dsdt);
1889 build_piix4_pci0_int(dsdt);
1890 } else {
1891 sb_scope = aml_scope("_SB");
1892 aml_append(sb_scope,
1893 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c));
1894 aml_append(sb_scope,
1895 aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01));
1896 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1897 aml_append(field, aml_named_field("PCIB", 8));
1898 aml_append(sb_scope, field);
1899 aml_append(dsdt, sb_scope);
1900
1901 sb_scope = aml_scope("_SB");
1902 dev = aml_device("PCI0");
1903 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1904 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1905 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1906 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1907 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
1908 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
1909 aml_append(dev, build_q35_osc_method());
1910 aml_append(sb_scope, dev);
1911 aml_append(dsdt, sb_scope);
1912
1913 build_hpet_aml(dsdt);
1914 build_q35_isa_bridge(dsdt);
1915 build_isa_devices_aml(dsdt);
1916 build_q35_pci0_int(dsdt);
1917 }
1918
1919 if (pcmc->legacy_cpu_hotplug) {
1920 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1921 } else {
1922 CPUHotplugFeatures opts = {
1923 .apci_1_compatible = true, .has_legacy_cphp = true
1924 };
1925 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1926 "\\_SB.PCI0", "\\_GPE._E02");
1927 }
1928 build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base,
1929 pm->mem_hp_io_len);
1930
1931 scope = aml_scope("_GPE");
1932 {
1933 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1934
1935 if (misc->is_piix4) {
1936 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1937 aml_append(method,
1938 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1939 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1940 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1941 aml_append(scope, method);
1942 }
1943
1944 method = aml_method("_E03", 0, AML_NOTSERIALIZED);
1945 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
1946 aml_append(scope, method);
1947
1948 if (pcms->acpi_nvdimm_state.is_enabled) {
1949 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1950 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1951 aml_int(0x80)));
1952 aml_append(scope, method);
1953 }
1954 }
1955 aml_append(dsdt, scope);
1956
1957 crs_range_set_init(&crs_range_set);
1958 bus = PC_MACHINE(machine)->bus;
1959 if (bus) {
1960 QLIST_FOREACH(bus, &bus->child, sibling) {
1961 uint8_t bus_num = pci_bus_num(bus);
1962 uint8_t numa_node = pci_bus_numa_node(bus);
1963
1964 /* look only for expander root buses */
1965 if (!pci_bus_is_root(bus)) {
1966 continue;
1967 }
1968
1969 if (bus_num < root_bus_limit) {
1970 root_bus_limit = bus_num - 1;
1971 }
1972
1973 scope = aml_scope("\\_SB");
1974 dev = aml_device("PC%.02X", bus_num);
1975 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1976 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1977 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1978
1979 if (numa_node != NUMA_NODE_UNASSIGNED) {
1980 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1981 }
1982
1983 aml_append(dev, build_prt(false));
1984 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
1985 aml_append(dev, aml_name_decl("_CRS", crs));
1986 aml_append(scope, dev);
1987 aml_append(dsdt, scope);
1988 }
1989 }
1990
1991 scope = aml_scope("\\_SB.PCI0");
1992 /* build PCI0._CRS */
1993 crs = aml_resource_template();
1994 aml_append(crs,
1995 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1996 0x0000, 0x0, root_bus_limit,
1997 0x0000, root_bus_limit + 1));
1998 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1999
2000 aml_append(crs,
2001 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2002 AML_POS_DECODE, AML_ENTIRE_RANGE,
2003 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
2004
2005 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
2006 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
2007 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
2008 aml_append(crs,
2009 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2010 AML_POS_DECODE, AML_ENTIRE_RANGE,
2011 0x0000, entry->base, entry->limit,
2012 0x0000, entry->limit - entry->base + 1));
2013 }
2014
2015 aml_append(crs,
2016 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2017 AML_CACHEABLE, AML_READ_WRITE,
2018 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2019
2020 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
2021 range_lob(pci_hole),
2022 range_upb(pci_hole));
2023 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
2024 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
2025 aml_append(crs,
2026 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2027 AML_NON_CACHEABLE, AML_READ_WRITE,
2028 0, entry->base, entry->limit,
2029 0, entry->limit - entry->base + 1));
2030 }
2031
2032 if (!range_is_empty(pci_hole64)) {
2033 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
2034 range_lob(pci_hole64),
2035 range_upb(pci_hole64));
2036 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
2037 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
2038 aml_append(crs,
2039 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
2040 AML_MAX_FIXED,
2041 AML_CACHEABLE, AML_READ_WRITE,
2042 0, entry->base, entry->limit,
2043 0, entry->limit - entry->base + 1));
2044 }
2045 }
2046
2047 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2048 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2049 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2050 }
2051 aml_append(scope, aml_name_decl("_CRS", crs));
2052
2053 /* reserve GPE0 block resources */
2054 dev = aml_device("GPE0");
2055 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2056 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2057 /* device present, functioning, decoding, not shown in UI */
2058 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2059 crs = aml_resource_template();
2060 aml_append(crs,
2061 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
2062 );
2063 aml_append(dev, aml_name_decl("_CRS", crs));
2064 aml_append(scope, dev);
2065
2066 crs_range_set_free(&crs_range_set);
2067
2068 /* reserve PCIHP resources */
2069 if (pm->pcihp_io_len) {
2070 dev = aml_device("PHPR");
2071 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2072 aml_append(dev,
2073 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2074 /* device present, functioning, decoding, not shown in UI */
2075 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2076 crs = aml_resource_template();
2077 aml_append(crs,
2078 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2079 pm->pcihp_io_len)
2080 );
2081 aml_append(dev, aml_name_decl("_CRS", crs));
2082 aml_append(scope, dev);
2083 }
2084 aml_append(dsdt, scope);
2085
2086 /* create S3_ / S4_ / S5_ packages if necessary */
2087 scope = aml_scope("\\");
2088 if (!pm->s3_disabled) {
2089 pkg = aml_package(4);
2090 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2091 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2092 aml_append(pkg, aml_int(0)); /* reserved */
2093 aml_append(pkg, aml_int(0)); /* reserved */
2094 aml_append(scope, aml_name_decl("_S3", pkg));
2095 }
2096
2097 if (!pm->s4_disabled) {
2098 pkg = aml_package(4);
2099 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2100 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2101 aml_append(pkg, aml_int(pm->s4_val));
2102 aml_append(pkg, aml_int(0)); /* reserved */
2103 aml_append(pkg, aml_int(0)); /* reserved */
2104 aml_append(scope, aml_name_decl("_S4", pkg));
2105 }
2106
2107 pkg = aml_package(4);
2108 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2109 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2110 aml_append(pkg, aml_int(0)); /* reserved */
2111 aml_append(pkg, aml_int(0)); /* reserved */
2112 aml_append(scope, aml_name_decl("_S5", pkg));
2113 aml_append(dsdt, scope);
2114
2115 /* create fw_cfg node, unconditionally */
2116 {
2117 /* when using port i/o, the 8-bit data register *always* overlaps
2118 * with half of the 16-bit control register. Hence, the total size
2119 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2120 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2121 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2122 "dma_enabled", NULL) ?
2123 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2124 FW_CFG_CTL_SIZE;
2125
2126 scope = aml_scope("\\_SB.PCI0");
2127 dev = aml_device("FWCF");
2128
2129 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2130
2131 /* device present, functioning, decoding, not shown in UI */
2132 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2133
2134 crs = aml_resource_template();
2135 aml_append(crs,
2136 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2137 );
2138 aml_append(dev, aml_name_decl("_CRS", crs));
2139
2140 aml_append(scope, dev);
2141 aml_append(dsdt, scope);
2142 }
2143
2144 if (misc->applesmc_io_base) {
2145 scope = aml_scope("\\_SB.PCI0.ISA");
2146 dev = aml_device("SMC");
2147
2148 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2149 /* device present, functioning, decoding, not shown in UI */
2150 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2151
2152 crs = aml_resource_template();
2153 aml_append(crs,
2154 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2155 0x01, APPLESMC_MAX_DATA_LENGTH)
2156 );
2157 aml_append(crs, aml_irq_no_flags(6));
2158 aml_append(dev, aml_name_decl("_CRS", crs));
2159
2160 aml_append(scope, dev);
2161 aml_append(dsdt, scope);
2162 }
2163
2164 if (misc->pvpanic_port) {
2165 scope = aml_scope("\\_SB.PCI0.ISA");
2166
2167 dev = aml_device("PEVT");
2168 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2169
2170 crs = aml_resource_template();
2171 aml_append(crs,
2172 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2173 );
2174 aml_append(dev, aml_name_decl("_CRS", crs));
2175
2176 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2177 aml_int(misc->pvpanic_port), 1));
2178 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2179 aml_append(field, aml_named_field("PEPT", 8));
2180 aml_append(dev, field);
2181
2182 /* device present, functioning, decoding, shown in UI */
2183 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2184
2185 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2186 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2187 aml_append(method, aml_return(aml_local(0)));
2188 aml_append(dev, method);
2189
2190 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2191 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2192 aml_append(dev, method);
2193
2194 aml_append(scope, dev);
2195 aml_append(dsdt, scope);
2196 }
2197
2198 sb_scope = aml_scope("\\_SB");
2199 {
2200 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base,
2201 pm->mem_hp_io_len);
2202
2203 {
2204 Object *pci_host;
2205 PCIBus *bus = NULL;
2206
2207 pci_host = acpi_get_i386_pci_host();
2208 if (pci_host) {
2209 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2210 }
2211
2212 if (bus) {
2213 Aml *scope = aml_scope("PCI0");
2214 /* Scan all PCI buses. Generate tables to support hotplug. */
2215 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2216
2217 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2218 dev = aml_device("ISA.TPM");
2219 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2220 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2221 crs = aml_resource_template();
2222 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2223 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2224 /*
2225 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2226 Rewrite to take IRQ from TPM device model and
2227 fix default IRQ value there to use some unused IRQ
2228 */
2229 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2230 aml_append(dev, aml_name_decl("_CRS", crs));
2231 aml_append(scope, dev);
2232 }
2233
2234 aml_append(sb_scope, scope);
2235 }
2236 }
2237 aml_append(dsdt, sb_scope);
2238 }
2239
2240 /* copy AML table into ACPI tables blob and patch header there */
2241 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
2242 build_header(linker, table_data,
2243 (void *)(table_data->data + table_data->len - dsdt->buf->len),
2244 "DSDT", dsdt->buf->len, 1, NULL, NULL);
2245 free_aml_allocator();
2246 }
2247
2248 static void
2249 build_hpet(GArray *table_data, BIOSLinker *linker)
2250 {
2251 Acpi20Hpet *hpet;
2252
2253 hpet = acpi_data_push(table_data, sizeof(*hpet));
2254 /* Note timer_block_id value must be kept in sync with value advertised by
2255 * emulated hpet
2256 */
2257 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2258 hpet->addr.address = cpu_to_le64(HPET_BASE);
2259 build_header(linker, table_data,
2260 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
2261 }
2262
2263 static void
2264 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2265 {
2266 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2267 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
2268 unsigned log_addr_offset =
2269 (char *)&tcpa->log_area_start_address - table_data->data;
2270
2271 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2272 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2273 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
2274
2275 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
2276 false /* high memory */);
2277
2278 /* log area start address to be filled by Guest linker */
2279 bios_linker_loader_add_pointer(linker,
2280 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
2281 ACPI_BUILD_TPMLOG_FILE, 0);
2282
2283 build_header(linker, table_data,
2284 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
2285 }
2286
2287 static void
2288 build_tpm2(GArray *table_data, BIOSLinker *linker)
2289 {
2290 Acpi20TPM2 *tpm2_ptr;
2291
2292 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2293
2294 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2295 tpm2_ptr->control_area_address = cpu_to_le64(0);
2296 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2297
2298 build_header(linker, table_data,
2299 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
2300 }
2301
2302 static void
2303 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
2304 {
2305 AcpiSystemResourceAffinityTable *srat;
2306 AcpiSratMemoryAffinity *numamem;
2307
2308 int i;
2309 int srat_start, numa_start, slots;
2310 uint64_t mem_len, mem_base, next_base;
2311 MachineClass *mc = MACHINE_GET_CLASS(machine);
2312 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
2313 PCMachineState *pcms = PC_MACHINE(machine);
2314 ram_addr_t hotplugabble_address_space_size =
2315 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
2316 NULL);
2317
2318 srat_start = table_data->len;
2319
2320 srat = acpi_data_push(table_data, sizeof *srat);
2321 srat->reserved1 = cpu_to_le32(1);
2322
2323 for (i = 0; i < apic_ids->len; i++) {
2324 int j = numa_get_node_for_cpu(i);
2325 uint32_t apic_id = apic_ids->cpus[i].arch_id;
2326
2327 if (apic_id < 255) {
2328 AcpiSratProcessorAffinity *core;
2329
2330 core = acpi_data_push(table_data, sizeof *core);
2331 core->type = ACPI_SRAT_PROCESSOR_APIC;
2332 core->length = sizeof(*core);
2333 core->local_apic_id = apic_id;
2334 if (j < nb_numa_nodes) {
2335 core->proximity_lo = j;
2336 }
2337 memset(core->proximity_hi, 0, 3);
2338 core->local_sapic_eid = 0;
2339 core->flags = cpu_to_le32(1);
2340 } else {
2341 AcpiSratProcessorX2ApicAffinity *core;
2342
2343 core = acpi_data_push(table_data, sizeof *core);
2344 core->type = ACPI_SRAT_PROCESSOR_x2APIC;
2345 core->length = sizeof(*core);
2346 core->x2apic_id = cpu_to_le32(apic_id);
2347 if (j < nb_numa_nodes) {
2348 core->proximity_domain = cpu_to_le32(j);
2349 }
2350 core->flags = cpu_to_le32(1);
2351 }
2352 }
2353
2354
2355 /* the memory map is a bit tricky, it contains at least one hole
2356 * from 640k-1M and possibly another one from 3.5G-4G.
2357 */
2358 next_base = 0;
2359 numa_start = table_data->len;
2360
2361 numamem = acpi_data_push(table_data, sizeof *numamem);
2362 build_srat_memory(numamem, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED);
2363 next_base = 1024 * 1024;
2364 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2365 mem_base = next_base;
2366 mem_len = pcms->node_mem[i - 1];
2367 if (i == 1) {
2368 mem_len -= 1024 * 1024;
2369 }
2370 next_base = mem_base + mem_len;
2371
2372 /* Cut out the ACPI_PCI hole */
2373 if (mem_base <= pcms->below_4g_mem_size &&
2374 next_base > pcms->below_4g_mem_size) {
2375 mem_len -= next_base - pcms->below_4g_mem_size;
2376 if (mem_len > 0) {
2377 numamem = acpi_data_push(table_data, sizeof *numamem);
2378 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2379 MEM_AFFINITY_ENABLED);
2380 }
2381 mem_base = 1ULL << 32;
2382 mem_len = next_base - pcms->below_4g_mem_size;
2383 next_base += (1ULL << 32) - pcms->below_4g_mem_size;
2384 }
2385 numamem = acpi_data_push(table_data, sizeof *numamem);
2386 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2387 MEM_AFFINITY_ENABLED);
2388 }
2389 slots = (table_data->len - numa_start) / sizeof *numamem;
2390 for (; slots < pcms->numa_nodes + 2; slots++) {
2391 numamem = acpi_data_push(table_data, sizeof *numamem);
2392 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2393 }
2394
2395 /*
2396 * Entry is required for Windows to enable memory hotplug in OS.
2397 * Memory devices may override proximity set by this entry,
2398 * providing _PXM method if necessary.
2399 */
2400 if (hotplugabble_address_space_size) {
2401 numamem = acpi_data_push(table_data, sizeof *numamem);
2402 build_srat_memory(numamem, pcms->hotplug_memory.base,
2403 hotplugabble_address_space_size, 0,
2404 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2405 }
2406
2407 build_header(linker, table_data,
2408 (void *)(table_data->data + srat_start),
2409 "SRAT",
2410 table_data->len - srat_start, 1, NULL, NULL);
2411 g_free(apic_ids);
2412 }
2413
2414 static void
2415 build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info)
2416 {
2417 AcpiTableMcfg *mcfg;
2418 const char *sig;
2419 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2420
2421 mcfg = acpi_data_push(table_data, len);
2422 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2423 /* Only a single allocation so no need to play with segments */
2424 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2425 mcfg->allocation[0].start_bus_number = 0;
2426 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2427
2428 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2429 * To avoid table size changes (which create migration issues),
2430 * always create the table even if there are no allocations,
2431 * but set the signature to a reserved value in this case.
2432 * ACPI spec requires OSPMs to ignore such tables.
2433 */
2434 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
2435 /* Reserved signature: ignored by OSPM */
2436 sig = "QEMU";
2437 } else {
2438 sig = "MCFG";
2439 }
2440 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
2441 }
2442
2443 /*
2444 * VT-d spec 8.1 DMA Remapping Reporting Structure
2445 * (version Oct. 2014 or later)
2446 */
2447 static void
2448 build_dmar_q35(GArray *table_data, BIOSLinker *linker)
2449 {
2450 int dmar_start = table_data->len;
2451
2452 AcpiTableDmar *dmar;
2453 AcpiDmarHardwareUnit *drhd;
2454 AcpiDmarRootPortATS *atsr;
2455 uint8_t dmar_flags = 0;
2456 X86IOMMUState *iommu = x86_iommu_get_default();
2457 AcpiDmarDeviceScope *scope = NULL;
2458 /* Root complex IOAPIC use one path[0] only */
2459 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
2460
2461 assert(iommu);
2462 if (iommu->intr_supported) {
2463 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2464 }
2465
2466 dmar = acpi_data_push(table_data, sizeof(*dmar));
2467 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
2468 dmar->flags = dmar_flags;
2469
2470 /* DMAR Remapping Hardware Unit Definition structure */
2471 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
2472 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2473 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
2474 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2475 drhd->pci_segment = cpu_to_le16(0);
2476 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2477
2478 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2479 * 8.3.1 (version Oct. 2014 or later). */
2480 scope = &drhd->scope[0];
2481 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
2482 scope->length = ioapic_scope_size;
2483 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2484 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
2485 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
2486 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
2487
2488 if (iommu->dt_supported) {
2489 atsr = acpi_data_push(table_data, sizeof(*atsr));
2490 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
2491 atsr->length = cpu_to_le16(sizeof(*atsr));
2492 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
2493 atsr->pci_segment = cpu_to_le16(0);
2494 }
2495
2496 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2497 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2498 }
2499 /*
2500 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2501 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2502 */
2503 static void
2504 build_amd_iommu(GArray *table_data, BIOSLinker *linker)
2505 {
2506 int iommu_start = table_data->len;
2507 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2508
2509 /* IVRS header */
2510 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2511 /* IVinfo - IO virtualization information common to all
2512 * IOMMU units in a system
2513 */
2514 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2515 /* reserved */
2516 build_append_int_noprefix(table_data, 0, 8);
2517
2518 /* IVHD definition - type 10h */
2519 build_append_int_noprefix(table_data, 0x10, 1);
2520 /* virtualization flags */
2521 build_append_int_noprefix(table_data,
2522 (1UL << 0) | /* HtTunEn */
2523 (1UL << 4) | /* iotblSup */
2524 (1UL << 6) | /* PrefSup */
2525 (1UL << 7), /* PPRSup */
2526 1);
2527 /* IVHD length */
2528 build_append_int_noprefix(table_data, 0x24, 2);
2529 /* DeviceID */
2530 build_append_int_noprefix(table_data, s->devid, 2);
2531 /* Capability offset */
2532 build_append_int_noprefix(table_data, s->capab_offset, 2);
2533 /* IOMMU base address */
2534 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2535 /* PCI Segment Group */
2536 build_append_int_noprefix(table_data, 0, 2);
2537 /* IOMMU info */
2538 build_append_int_noprefix(table_data, 0, 2);
2539 /* IOMMU Feature Reporting */
2540 build_append_int_noprefix(table_data,
2541 (48UL << 30) | /* HATS */
2542 (48UL << 28) | /* GATS */
2543 (1UL << 2), /* GTSup */
2544 4);
2545 /*
2546 * Type 1 device entry reporting all devices
2547 * These are 4-byte device entries currently reporting the range of
2548 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2549 */
2550 build_append_int_noprefix(table_data, 0x0000001, 4);
2551
2552 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2553 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2554 }
2555
2556 static GArray *
2557 build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset)
2558 {
2559 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2560 unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address);
2561 unsigned rsdt_pa_offset =
2562 (char *)&rsdp->rsdt_physical_address - rsdp_table->data;
2563
2564 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16,
2565 true /* fseg memory */);
2566
2567 memcpy(&rsdp->signature, "RSD PTR ", 8);
2568 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
2569 /* Address to be filled by Guest linker */
2570 bios_linker_loader_add_pointer(linker,
2571 ACPI_BUILD_RSDP_FILE, rsdt_pa_offset, rsdt_pa_size,
2572 ACPI_BUILD_TABLE_FILE, rsdt_tbl_offset);
2573
2574 /* Checksum to be filled by Guest linker */
2575 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
2576 (char *)rsdp - rsdp_table->data, sizeof *rsdp,
2577 (char *)&rsdp->checksum - rsdp_table->data);
2578
2579 return rsdp_table;
2580 }
2581
2582 typedef
2583 struct AcpiBuildState {
2584 /* Copy of table in RAM (for patching). */
2585 MemoryRegion *table_mr;
2586 /* Is table patched? */
2587 uint8_t patched;
2588 void *rsdp;
2589 MemoryRegion *rsdp_mr;
2590 MemoryRegion *linker_mr;
2591 } AcpiBuildState;
2592
2593 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2594 {
2595 Object *pci_host;
2596 QObject *o;
2597
2598 pci_host = acpi_get_i386_pci_host();
2599 g_assert(pci_host);
2600
2601 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2602 if (!o) {
2603 return false;
2604 }
2605 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
2606 qobject_decref(o);
2607
2608 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2609 assert(o);
2610 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
2611 qobject_decref(o);
2612 return true;
2613 }
2614
2615 static
2616 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2617 {
2618 PCMachineState *pcms = PC_MACHINE(machine);
2619 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2620 GArray *table_offsets;
2621 unsigned facs, dsdt, rsdt, fadt;
2622 AcpiPmInfo pm;
2623 AcpiMiscInfo misc;
2624 AcpiMcfgInfo mcfg;
2625 Range pci_hole, pci_hole64;
2626 uint8_t *u;
2627 size_t aml_len = 0;
2628 GArray *tables_blob = tables->table_data;
2629 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2630
2631 acpi_get_pm_info(&pm);
2632 acpi_get_misc_info(&misc);
2633 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2634 acpi_get_slic_oem(&slic_oem);
2635
2636 table_offsets = g_array_new(false, true /* clear */,
2637 sizeof(uint32_t));
2638 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2639
2640 bios_linker_loader_alloc(tables->linker,
2641 ACPI_BUILD_TABLE_FILE, tables_blob,
2642 64 /* Ensure FACS is aligned */,
2643 false /* high memory */);
2644
2645 /*
2646 * FACS is pointed to by FADT.
2647 * We place it first since it's the only table that has alignment
2648 * requirements.
2649 */
2650 facs = tables_blob->len;
2651 build_facs(tables_blob, tables->linker);
2652
2653 /* DSDT is pointed to by FADT */
2654 dsdt = tables_blob->len;
2655 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2656 &pci_hole, &pci_hole64, machine);
2657
2658 /* Count the size of the DSDT and SSDT, we will need it for legacy
2659 * sizing of ACPI tables.
2660 */
2661 aml_len += tables_blob->len - dsdt;
2662
2663 /* ACPI tables pointed to by RSDT */
2664 fadt = tables_blob->len;
2665 acpi_add_table(table_offsets, tables_blob);
2666 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt,
2667 slic_oem.id, slic_oem.table_id);
2668 aml_len += tables_blob->len - fadt;
2669
2670 acpi_add_table(table_offsets, tables_blob);
2671 build_madt(tables_blob, tables->linker, pcms);
2672
2673 if (misc.has_hpet) {
2674 acpi_add_table(table_offsets, tables_blob);
2675 build_hpet(tables_blob, tables->linker);
2676 }
2677 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2678 acpi_add_table(table_offsets, tables_blob);
2679 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2680
2681 if (misc.tpm_version == TPM_VERSION_2_0) {
2682 acpi_add_table(table_offsets, tables_blob);
2683 build_tpm2(tables_blob, tables->linker);
2684 }
2685 }
2686 if (pcms->numa_nodes) {
2687 acpi_add_table(table_offsets, tables_blob);
2688 build_srat(tables_blob, tables->linker, machine);
2689 }
2690 if (acpi_get_mcfg(&mcfg)) {
2691 acpi_add_table(table_offsets, tables_blob);
2692 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2693 }
2694 if (x86_iommu_get_default()) {
2695 IommuType IOMMUType = x86_iommu_get_type();
2696 if (IOMMUType == TYPE_AMD) {
2697 acpi_add_table(table_offsets, tables_blob);
2698 build_amd_iommu(tables_blob, tables->linker);
2699 } else if (IOMMUType == TYPE_INTEL) {
2700 acpi_add_table(table_offsets, tables_blob);
2701 build_dmar_q35(tables_blob, tables->linker);
2702 }
2703 }
2704 if (pcms->acpi_nvdimm_state.is_enabled) {
2705 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2706 &pcms->acpi_nvdimm_state, machine->ram_slots);
2707 }
2708
2709 /* Add tables supplied by user (if any) */
2710 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2711 unsigned len = acpi_table_len(u);
2712
2713 acpi_add_table(table_offsets, tables_blob);
2714 g_array_append_vals(tables_blob, u, len);
2715 }
2716
2717 /* RSDT is pointed to by RSDP */
2718 rsdt = tables_blob->len;
2719 build_rsdt(tables_blob, tables->linker, table_offsets,
2720 slic_oem.id, slic_oem.table_id);
2721
2722 /* RSDP is in FSEG memory, so allocate it separately */
2723 build_rsdp(tables->rsdp, tables->linker, rsdt);
2724
2725 /* We'll expose it all to Guest so we want to reduce
2726 * chance of size changes.
2727 *
2728 * We used to align the tables to 4k, but of course this would
2729 * too simple to be enough. 4k turned out to be too small an
2730 * alignment very soon, and in fact it is almost impossible to
2731 * keep the table size stable for all (max_cpus, max_memory_slots)
2732 * combinations. So the table size is always 64k for pc-i440fx-2.1
2733 * and we give an error if the table grows beyond that limit.
2734 *
2735 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2736 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2737 * than 2.0 and we can always pad the smaller tables with zeros. We can
2738 * then use the exact size of the 2.0 tables.
2739 *
2740 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2741 */
2742 if (pcmc->legacy_acpi_table_size) {
2743 /* Subtracting aml_len gives the size of fixed tables. Then add the
2744 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2745 */
2746 int legacy_aml_len =
2747 pcmc->legacy_acpi_table_size +
2748 ACPI_BUILD_LEGACY_CPU_AML_SIZE * pcms->apic_id_limit;
2749 int legacy_table_size =
2750 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2751 ACPI_BUILD_ALIGN_SIZE);
2752 if (tables_blob->len > legacy_table_size) {
2753 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2754 error_report("Warning: migration may not work.");
2755 }
2756 g_array_set_size(tables_blob, legacy_table_size);
2757 } else {
2758 /* Make sure we have a buffer in case we need to resize the tables. */
2759 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2760 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2761 error_report("Warning: ACPI tables are larger than 64k.");
2762 error_report("Warning: migration may not work.");
2763 error_report("Warning: please remove CPUs, NUMA nodes, "
2764 "memory slots or PCI bridges.");
2765 }
2766 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2767 }
2768
2769 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2770
2771 /* Cleanup memory that's no longer used. */
2772 g_array_free(table_offsets, true);
2773 }
2774
2775 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2776 {
2777 uint32_t size = acpi_data_len(data);
2778
2779 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2780 memory_region_ram_resize(mr, size, &error_abort);
2781
2782 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2783 memory_region_set_dirty(mr, 0, size);
2784 }
2785
2786 static void acpi_build_update(void *build_opaque)
2787 {
2788 AcpiBuildState *build_state = build_opaque;
2789 AcpiBuildTables tables;
2790
2791 /* No state to update or already patched? Nothing to do. */
2792 if (!build_state || build_state->patched) {
2793 return;
2794 }
2795 build_state->patched = 1;
2796
2797 acpi_build_tables_init(&tables);
2798
2799 acpi_build(&tables, MACHINE(qdev_get_machine()));
2800
2801 acpi_ram_update(build_state->table_mr, tables.table_data);
2802
2803 if (build_state->rsdp) {
2804 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2805 } else {
2806 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2807 }
2808
2809 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2810 acpi_build_tables_cleanup(&tables, true);
2811 }
2812
2813 static void acpi_build_reset(void *build_opaque)
2814 {
2815 AcpiBuildState *build_state = build_opaque;
2816 build_state->patched = 0;
2817 }
2818
2819 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2820 GArray *blob, const char *name,
2821 uint64_t max_size)
2822 {
2823 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2824 name, acpi_build_update, build_state, NULL);
2825 }
2826
2827 static const VMStateDescription vmstate_acpi_build = {
2828 .name = "acpi_build",
2829 .version_id = 1,
2830 .minimum_version_id = 1,
2831 .fields = (VMStateField[]) {
2832 VMSTATE_UINT8(patched, AcpiBuildState),
2833 VMSTATE_END_OF_LIST()
2834 },
2835 };
2836
2837 void acpi_setup(void)
2838 {
2839 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2840 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2841 AcpiBuildTables tables;
2842 AcpiBuildState *build_state;
2843
2844 if (!pcms->fw_cfg) {
2845 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2846 return;
2847 }
2848
2849 if (!pcms->acpi_build_enabled) {
2850 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2851 return;
2852 }
2853
2854 if (!acpi_enabled) {
2855 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2856 return;
2857 }
2858
2859 build_state = g_malloc0(sizeof *build_state);
2860
2861 acpi_set_pci_info();
2862
2863 acpi_build_tables_init(&tables);
2864 acpi_build(&tables, MACHINE(pcms));
2865
2866 /* Now expose it all to Guest */
2867 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
2868 ACPI_BUILD_TABLE_FILE,
2869 ACPI_BUILD_TABLE_MAX_SIZE);
2870 assert(build_state->table_mr != NULL);
2871
2872 build_state->linker_mr =
2873 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
2874 "etc/table-loader", 0);
2875
2876 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2877 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2878
2879 if (!pcmc->rsdp_in_ram) {
2880 /*
2881 * Keep for compatibility with old machine types.
2882 * Though RSDP is small, its contents isn't immutable, so
2883 * we'll update it along with the rest of tables on guest access.
2884 */
2885 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2886
2887 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2888 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2889 acpi_build_update, build_state,
2890 build_state->rsdp, rsdp_size);
2891 build_state->rsdp_mr = NULL;
2892 } else {
2893 build_state->rsdp = NULL;
2894 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
2895 ACPI_BUILD_RSDP_FILE, 0);
2896 }
2897
2898 qemu_register_reset(acpi_build_reset, build_state);
2899 acpi_build_reset(build_state);
2900 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2901
2902 /* Cleanup tables but don't free the memory: we track it
2903 * in build_state.
2904 */
2905 acpi_build_tables_cleanup(&tables, false);
2906 }
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