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[mirror_qemu.git] / hw / i386 / acpi-build.c
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "acpi-build.h"
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
30 #include "qom/cpu.h"
31 #include "hw/i386/pc.h"
32 #include "target/i386/cpu.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/acpi/cpu.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "sysemu/tpm_backend.h"
46 #include "hw/timer/mc146818rtc_regs.h"
47 #include "sysemu/numa.h"
48
49 /* Supported chipsets: */
50 #include "hw/acpi/piix4.h"
51 #include "hw/acpi/pcihp.h"
52 #include "hw/i386/ich9.h"
53 #include "hw/pci/pci_bus.h"
54 #include "hw/pci-host/q35.h"
55 #include "hw/i386/x86-iommu.h"
56
57 #include "hw/acpi/aml-build.h"
58
59 #include "qapi/qmp/qint.h"
60 #include "qom/qom-qobject.h"
61 #include "hw/i386/amd_iommu.h"
62 #include "hw/i386/intel_iommu.h"
63
64 #include "hw/acpi/ipmi.h"
65
66 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
67 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
68 * a little bit, there should be plenty of free space since the DSDT
69 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
70 */
71 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
72 #define ACPI_BUILD_ALIGN_SIZE 0x1000
73
74 #define ACPI_BUILD_TABLE_SIZE 0x20000
75
76 /* #define DEBUG_ACPI_BUILD */
77 #ifdef DEBUG_ACPI_BUILD
78 #define ACPI_BUILD_DPRINTF(fmt, ...) \
79 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
80 #else
81 #define ACPI_BUILD_DPRINTF(fmt, ...)
82 #endif
83
84 /* Default IOAPIC ID */
85 #define ACPI_BUILD_IOAPIC_ID 0x0
86
87 typedef struct AcpiMcfgInfo {
88 uint64_t mcfg_base;
89 uint32_t mcfg_size;
90 } AcpiMcfgInfo;
91
92 typedef struct AcpiPmInfo {
93 bool s3_disabled;
94 bool s4_disabled;
95 bool pcihp_bridge_en;
96 uint8_t s4_val;
97 uint16_t sci_int;
98 uint8_t acpi_enable_cmd;
99 uint8_t acpi_disable_cmd;
100 uint32_t gpe0_blk;
101 uint32_t gpe0_blk_len;
102 uint32_t io_base;
103 uint16_t cpu_hp_io_base;
104 uint16_t pcihp_io_base;
105 uint16_t pcihp_io_len;
106 } AcpiPmInfo;
107
108 typedef struct AcpiMiscInfo {
109 bool is_piix4;
110 bool has_hpet;
111 TPMVersion tpm_version;
112 const unsigned char *dsdt_code;
113 unsigned dsdt_size;
114 uint16_t pvpanic_port;
115 uint16_t applesmc_io_base;
116 } AcpiMiscInfo;
117
118 typedef struct AcpiBuildPciBusHotplugState {
119 GArray *device_table;
120 GArray *notify_table;
121 struct AcpiBuildPciBusHotplugState *parent;
122 bool pcihp_bridge_en;
123 } AcpiBuildPciBusHotplugState;
124
125 static void acpi_get_pm_info(AcpiPmInfo *pm)
126 {
127 Object *piix = piix4_pm_find();
128 Object *lpc = ich9_lpc_find();
129 Object *obj = NULL;
130 QObject *o;
131
132 pm->cpu_hp_io_base = 0;
133 pm->pcihp_io_base = 0;
134 pm->pcihp_io_len = 0;
135 if (piix) {
136 obj = piix;
137 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
138 pm->pcihp_io_base =
139 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
140 pm->pcihp_io_len =
141 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
142 }
143 if (lpc) {
144 obj = lpc;
145 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
146 }
147 assert(obj);
148
149 /* Fill in optional s3/s4 related properties */
150 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
151 if (o) {
152 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
153 } else {
154 pm->s3_disabled = false;
155 }
156 qobject_decref(o);
157 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
158 if (o) {
159 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
160 } else {
161 pm->s4_disabled = false;
162 }
163 qobject_decref(o);
164 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
165 if (o) {
166 pm->s4_val = qint_get_int(qobject_to_qint(o));
167 } else {
168 pm->s4_val = false;
169 }
170 qobject_decref(o);
171
172 /* Fill in mandatory properties */
173 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
174
175 pm->acpi_enable_cmd = object_property_get_int(obj,
176 ACPI_PM_PROP_ACPI_ENABLE_CMD,
177 NULL);
178 pm->acpi_disable_cmd = object_property_get_int(obj,
179 ACPI_PM_PROP_ACPI_DISABLE_CMD,
180 NULL);
181 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
182 NULL);
183 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
184 NULL);
185 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
186 NULL);
187 pm->pcihp_bridge_en =
188 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
189 NULL);
190 }
191
192 static void acpi_get_misc_info(AcpiMiscInfo *info)
193 {
194 Object *piix = piix4_pm_find();
195 Object *lpc = ich9_lpc_find();
196 assert(!!piix != !!lpc);
197
198 if (piix) {
199 info->is_piix4 = true;
200 }
201 if (lpc) {
202 info->is_piix4 = false;
203 }
204
205 info->has_hpet = hpet_find();
206 info->tpm_version = tpm_get_version();
207 info->pvpanic_port = pvpanic_port();
208 info->applesmc_io_base = applesmc_port();
209 }
210
211 /*
212 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
213 * On i386 arch we only have two pci hosts, so we can look only for them.
214 */
215 static Object *acpi_get_i386_pci_host(void)
216 {
217 PCIHostState *host;
218
219 host = OBJECT_CHECK(PCIHostState,
220 object_resolve_path("/machine/i440fx", NULL),
221 TYPE_PCI_HOST_BRIDGE);
222 if (!host) {
223 host = OBJECT_CHECK(PCIHostState,
224 object_resolve_path("/machine/q35", NULL),
225 TYPE_PCI_HOST_BRIDGE);
226 }
227
228 return OBJECT(host);
229 }
230
231 static void acpi_get_pci_holes(Range *hole, Range *hole64)
232 {
233 Object *pci_host;
234
235 pci_host = acpi_get_i386_pci_host();
236 g_assert(pci_host);
237
238 range_set_bounds1(hole,
239 object_property_get_int(pci_host,
240 PCI_HOST_PROP_PCI_HOLE_START,
241 NULL),
242 object_property_get_int(pci_host,
243 PCI_HOST_PROP_PCI_HOLE_END,
244 NULL));
245 range_set_bounds1(hole64,
246 object_property_get_int(pci_host,
247 PCI_HOST_PROP_PCI_HOLE64_START,
248 NULL),
249 object_property_get_int(pci_host,
250 PCI_HOST_PROP_PCI_HOLE64_END,
251 NULL));
252 }
253
254 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
255
256 static void acpi_align_size(GArray *blob, unsigned align)
257 {
258 /* Align size to multiple of given size. This reduces the chance
259 * we need to change size in the future (breaking cross version migration).
260 */
261 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
262 }
263
264 /* FACS */
265 static void
266 build_facs(GArray *table_data, BIOSLinker *linker)
267 {
268 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
269 memcpy(&facs->signature, "FACS", 4);
270 facs->length = cpu_to_le32(sizeof(*facs));
271 }
272
273 /* Load chipset information in FADT */
274 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
275 {
276 fadt->model = 1;
277 fadt->reserved1 = 0;
278 fadt->sci_int = cpu_to_le16(pm->sci_int);
279 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
280 fadt->acpi_enable = pm->acpi_enable_cmd;
281 fadt->acpi_disable = pm->acpi_disable_cmd;
282 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
283 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
284 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
285 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
286 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
287 /* EVT, CNT, TMR length matches hw/acpi/core.c */
288 fadt->pm1_evt_len = 4;
289 fadt->pm1_cnt_len = 2;
290 fadt->pm_tmr_len = 4;
291 fadt->gpe0_blk_len = pm->gpe0_blk_len;
292 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
293 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
294 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
295 (1 << ACPI_FADT_F_PROC_C1) |
296 (1 << ACPI_FADT_F_SLP_BUTTON) |
297 (1 << ACPI_FADT_F_RTC_S4));
298 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
299 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
300 * For more than 8 CPUs, "Clustered Logical" mode has to be used
301 */
302 if (max_cpus > 8) {
303 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
304 }
305 fadt->century = RTC_CENTURY;
306 }
307
308
309 /* FADT */
310 static void
311 build_fadt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm,
312 unsigned facs_tbl_offset, unsigned dsdt_tbl_offset,
313 const char *oem_id, const char *oem_table_id)
314 {
315 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
316 unsigned fw_ctrl_offset = (char *)&fadt->firmware_ctrl - table_data->data;
317 unsigned dsdt_entry_offset = (char *)&fadt->dsdt - table_data->data;
318
319 /* FACS address to be filled by Guest linker */
320 bios_linker_loader_add_pointer(linker,
321 ACPI_BUILD_TABLE_FILE, fw_ctrl_offset, sizeof(fadt->firmware_ctrl),
322 ACPI_BUILD_TABLE_FILE, facs_tbl_offset);
323
324 /* DSDT address to be filled by Guest linker */
325 fadt_setup(fadt, pm);
326 bios_linker_loader_add_pointer(linker,
327 ACPI_BUILD_TABLE_FILE, dsdt_entry_offset, sizeof(fadt->dsdt),
328 ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset);
329
330 build_header(linker, table_data,
331 (void *)fadt, "FACP", sizeof(*fadt), 1, oem_id, oem_table_id);
332 }
333
334 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
335 const CPUArchIdList *apic_ids, GArray *entry)
336 {
337 uint32_t apic_id = apic_ids->cpus[uid].arch_id;
338
339 /* ACPI spec says that LAPIC entry for non present
340 * CPU may be omitted from MADT or it must be marked
341 * as disabled. However omitting non present CPU from
342 * MADT breaks hotplug on linux. So possible CPUs
343 * should be put in MADT but kept disabled.
344 */
345 if (apic_id < 255) {
346 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
347
348 apic->type = ACPI_APIC_PROCESSOR;
349 apic->length = sizeof(*apic);
350 apic->processor_id = uid;
351 apic->local_apic_id = apic_id;
352 if (apic_ids->cpus[uid].cpu != NULL) {
353 apic->flags = cpu_to_le32(1);
354 } else {
355 apic->flags = cpu_to_le32(0);
356 }
357 } else {
358 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic);
359
360 apic->type = ACPI_APIC_LOCAL_X2APIC;
361 apic->length = sizeof(*apic);
362 apic->uid = cpu_to_le32(uid);
363 apic->x2apic_id = cpu_to_le32(apic_id);
364 if (apic_ids->cpus[uid].cpu != NULL) {
365 apic->flags = cpu_to_le32(1);
366 } else {
367 apic->flags = cpu_to_le32(0);
368 }
369 }
370 }
371
372 static void
373 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
374 {
375 MachineClass *mc = MACHINE_GET_CLASS(pcms);
376 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
377 int madt_start = table_data->len;
378 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
379 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
380 bool x2apic_mode = false;
381
382 AcpiMultipleApicTable *madt;
383 AcpiMadtIoApic *io_apic;
384 AcpiMadtIntsrcovr *intsrcovr;
385 int i;
386
387 madt = acpi_data_push(table_data, sizeof *madt);
388 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
389 madt->flags = cpu_to_le32(1);
390
391 for (i = 0; i < apic_ids->len; i++) {
392 adevc->madt_cpu(adev, i, apic_ids, table_data);
393 if (apic_ids->cpus[i].arch_id > 254) {
394 x2apic_mode = true;
395 }
396 }
397
398 io_apic = acpi_data_push(table_data, sizeof *io_apic);
399 io_apic->type = ACPI_APIC_IO;
400 io_apic->length = sizeof(*io_apic);
401 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
402 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
403 io_apic->interrupt = cpu_to_le32(0);
404
405 if (pcms->apic_xrupt_override) {
406 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
407 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
408 intsrcovr->length = sizeof(*intsrcovr);
409 intsrcovr->source = 0;
410 intsrcovr->gsi = cpu_to_le32(2);
411 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
412 }
413 for (i = 1; i < 16; i++) {
414 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
415 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
416 /* No need for a INT source override structure. */
417 continue;
418 }
419 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
420 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
421 intsrcovr->length = sizeof(*intsrcovr);
422 intsrcovr->source = i;
423 intsrcovr->gsi = cpu_to_le32(i);
424 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
425 }
426
427 if (x2apic_mode) {
428 AcpiMadtLocalX2ApicNmi *local_nmi;
429
430 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
431 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI;
432 local_nmi->length = sizeof(*local_nmi);
433 local_nmi->uid = 0xFFFFFFFF; /* all processors */
434 local_nmi->flags = cpu_to_le16(0);
435 local_nmi->lint = 1; /* ACPI_LINT1 */
436 } else {
437 AcpiMadtLocalNmi *local_nmi;
438
439 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
440 local_nmi->type = ACPI_APIC_LOCAL_NMI;
441 local_nmi->length = sizeof(*local_nmi);
442 local_nmi->processor_id = 0xff; /* all processors */
443 local_nmi->flags = cpu_to_le16(0);
444 local_nmi->lint = 1; /* ACPI_LINT1 */
445 }
446
447 build_header(linker, table_data,
448 (void *)(table_data->data + madt_start), "APIC",
449 table_data->len - madt_start, 1, NULL, NULL);
450 }
451
452 /* Assign BSEL property to all buses. In the future, this can be changed
453 * to only assign to buses that support hotplug.
454 */
455 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
456 {
457 unsigned *bsel_alloc = opaque;
458 unsigned *bus_bsel;
459
460 if (qbus_is_hotpluggable(BUS(bus))) {
461 bus_bsel = g_malloc(sizeof *bus_bsel);
462
463 *bus_bsel = (*bsel_alloc)++;
464 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
465 bus_bsel, NULL);
466 }
467
468 return bsel_alloc;
469 }
470
471 static void acpi_set_pci_info(void)
472 {
473 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
474 unsigned bsel_alloc = 0;
475
476 if (bus) {
477 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
478 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
479 }
480 }
481
482 static void build_append_pcihp_notify_entry(Aml *method, int slot)
483 {
484 Aml *if_ctx;
485 int32_t devfn = PCI_DEVFN(slot, 0);
486
487 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
488 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
489 aml_append(method, if_ctx);
490 }
491
492 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
493 bool pcihp_bridge_en)
494 {
495 Aml *dev, *notify_method, *method;
496 QObject *bsel;
497 PCIBus *sec;
498 int i;
499
500 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
501 if (bsel) {
502 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
503
504 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
505 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
506 }
507
508 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
509 DeviceClass *dc;
510 PCIDeviceClass *pc;
511 PCIDevice *pdev = bus->devices[i];
512 int slot = PCI_SLOT(i);
513 bool hotplug_enabled_dev;
514 bool bridge_in_acpi;
515
516 if (!pdev) {
517 if (bsel) { /* add hotplug slots for non present devices */
518 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
519 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
520 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
521 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
522 aml_append(method,
523 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
524 );
525 aml_append(dev, method);
526 aml_append(parent_scope, dev);
527
528 build_append_pcihp_notify_entry(notify_method, slot);
529 }
530 continue;
531 }
532
533 pc = PCI_DEVICE_GET_CLASS(pdev);
534 dc = DEVICE_GET_CLASS(pdev);
535
536 /* When hotplug for bridges is enabled, bridges are
537 * described in ACPI separately (see build_pci_bus_end).
538 * In this case they aren't themselves hot-pluggable.
539 * Hotplugged bridges *are* hot-pluggable.
540 */
541 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
542 !DEVICE(pdev)->hotplugged;
543
544 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
545
546 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
547 continue;
548 }
549
550 /* start to compose PCI slot descriptor */
551 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
552 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
553
554 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
555 /* add VGA specific AML methods */
556 int s3d;
557
558 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
559 s3d = 3;
560 } else {
561 s3d = 0;
562 }
563
564 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
565 aml_append(method, aml_return(aml_int(0)));
566 aml_append(dev, method);
567
568 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
569 aml_append(method, aml_return(aml_int(0)));
570 aml_append(dev, method);
571
572 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
573 aml_append(method, aml_return(aml_int(s3d)));
574 aml_append(dev, method);
575 } else if (hotplug_enabled_dev) {
576 /* add _SUN/_EJ0 to make slot hotpluggable */
577 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
578
579 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
580 aml_append(method,
581 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
582 );
583 aml_append(dev, method);
584
585 if (bsel) {
586 build_append_pcihp_notify_entry(notify_method, slot);
587 }
588 } else if (bridge_in_acpi) {
589 /*
590 * device is coldplugged bridge,
591 * add child device descriptions into its scope
592 */
593 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
594
595 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
596 }
597 /* slot descriptor has been composed, add it into parent context */
598 aml_append(parent_scope, dev);
599 }
600
601 if (bsel) {
602 aml_append(parent_scope, notify_method);
603 }
604
605 /* Append PCNT method to notify about events on local and child buses.
606 * Add unconditionally for root since DSDT expects it.
607 */
608 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
609
610 /* If bus supports hotplug select it and notify about local events */
611 if (bsel) {
612 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
613 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
614 aml_append(method,
615 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
616 );
617 aml_append(method,
618 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
619 );
620 }
621
622 /* Notify about child bus events in any case */
623 if (pcihp_bridge_en) {
624 QLIST_FOREACH(sec, &bus->child, sibling) {
625 int32_t devfn = sec->parent_dev->devfn;
626
627 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
628 continue;
629 }
630
631 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
632 }
633 }
634 aml_append(parent_scope, method);
635 qobject_decref(bsel);
636 }
637
638 /**
639 * build_prt_entry:
640 * @link_name: link name for PCI route entry
641 *
642 * build AML package containing a PCI route entry for @link_name
643 */
644 static Aml *build_prt_entry(const char *link_name)
645 {
646 Aml *a_zero = aml_int(0);
647 Aml *pkg = aml_package(4);
648 aml_append(pkg, a_zero);
649 aml_append(pkg, a_zero);
650 aml_append(pkg, aml_name("%s", link_name));
651 aml_append(pkg, a_zero);
652 return pkg;
653 }
654
655 /*
656 * initialize_route - Initialize the interrupt routing rule
657 * through a specific LINK:
658 * if (lnk_idx == idx)
659 * route using link 'link_name'
660 */
661 static Aml *initialize_route(Aml *route, const char *link_name,
662 Aml *lnk_idx, int idx)
663 {
664 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
665 Aml *pkg = build_prt_entry(link_name);
666
667 aml_append(if_ctx, aml_store(pkg, route));
668
669 return if_ctx;
670 }
671
672 /*
673 * build_prt - Define interrupt rounting rules
674 *
675 * Returns an array of 128 routes, one for each device,
676 * based on device location.
677 * The main goal is to equaly distribute the interrupts
678 * over the 4 existing ACPI links (works only for i440fx).
679 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
680 *
681 */
682 static Aml *build_prt(bool is_pci0_prt)
683 {
684 Aml *method, *while_ctx, *pin, *res;
685
686 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
687 res = aml_local(0);
688 pin = aml_local(1);
689 aml_append(method, aml_store(aml_package(128), res));
690 aml_append(method, aml_store(aml_int(0), pin));
691
692 /* while (pin < 128) */
693 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
694 {
695 Aml *slot = aml_local(2);
696 Aml *lnk_idx = aml_local(3);
697 Aml *route = aml_local(4);
698
699 /* slot = pin >> 2 */
700 aml_append(while_ctx,
701 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
702 /* lnk_idx = (slot + pin) & 3 */
703 aml_append(while_ctx,
704 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
705 lnk_idx));
706
707 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
708 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
709 if (is_pci0_prt) {
710 Aml *if_device_1, *if_pin_4, *else_pin_4;
711
712 /* device 1 is the power-management device, needs SCI */
713 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
714 {
715 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
716 {
717 aml_append(if_pin_4,
718 aml_store(build_prt_entry("LNKS"), route));
719 }
720 aml_append(if_device_1, if_pin_4);
721 else_pin_4 = aml_else();
722 {
723 aml_append(else_pin_4,
724 aml_store(build_prt_entry("LNKA"), route));
725 }
726 aml_append(if_device_1, else_pin_4);
727 }
728 aml_append(while_ctx, if_device_1);
729 } else {
730 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
731 }
732 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
733 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
734
735 /* route[0] = 0x[slot]FFFF */
736 aml_append(while_ctx,
737 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
738 NULL),
739 aml_index(route, aml_int(0))));
740 /* route[1] = pin & 3 */
741 aml_append(while_ctx,
742 aml_store(aml_and(pin, aml_int(3), NULL),
743 aml_index(route, aml_int(1))));
744 /* res[pin] = route */
745 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
746 /* pin++ */
747 aml_append(while_ctx, aml_increment(pin));
748 }
749 aml_append(method, while_ctx);
750 /* return res*/
751 aml_append(method, aml_return(res));
752
753 return method;
754 }
755
756 typedef struct CrsRangeEntry {
757 uint64_t base;
758 uint64_t limit;
759 } CrsRangeEntry;
760
761 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
762 {
763 CrsRangeEntry *entry;
764
765 entry = g_malloc(sizeof(*entry));
766 entry->base = base;
767 entry->limit = limit;
768
769 g_ptr_array_add(ranges, entry);
770 }
771
772 static void crs_range_free(gpointer data)
773 {
774 CrsRangeEntry *entry = (CrsRangeEntry *)data;
775 g_free(entry);
776 }
777
778 typedef struct CrsRangeSet {
779 GPtrArray *io_ranges;
780 GPtrArray *mem_ranges;
781 GPtrArray *mem_64bit_ranges;
782 } CrsRangeSet;
783
784 static void crs_range_set_init(CrsRangeSet *range_set)
785 {
786 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
787 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
788 range_set->mem_64bit_ranges =
789 g_ptr_array_new_with_free_func(crs_range_free);
790 }
791
792 static void crs_range_set_free(CrsRangeSet *range_set)
793 {
794 g_ptr_array_free(range_set->io_ranges, true);
795 g_ptr_array_free(range_set->mem_ranges, true);
796 g_ptr_array_free(range_set->mem_64bit_ranges, true);
797 }
798
799 static gint crs_range_compare(gconstpointer a, gconstpointer b)
800 {
801 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
802 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
803
804 return (int64_t)entry_a->base - (int64_t)entry_b->base;
805 }
806
807 /*
808 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
809 * interval, computes the 'free' ranges from the same interval.
810 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
811 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
812 */
813 static void crs_replace_with_free_ranges(GPtrArray *ranges,
814 uint64_t start, uint64_t end)
815 {
816 GPtrArray *free_ranges = g_ptr_array_new();
817 uint64_t free_base = start;
818 int i;
819
820 g_ptr_array_sort(ranges, crs_range_compare);
821 for (i = 0; i < ranges->len; i++) {
822 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
823
824 if (free_base < used->base) {
825 crs_range_insert(free_ranges, free_base, used->base - 1);
826 }
827
828 free_base = used->limit + 1;
829 }
830
831 if (free_base < end) {
832 crs_range_insert(free_ranges, free_base, end);
833 }
834
835 g_ptr_array_set_size(ranges, 0);
836 for (i = 0; i < free_ranges->len; i++) {
837 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
838 }
839
840 g_ptr_array_free(free_ranges, true);
841 }
842
843 /*
844 * crs_range_merge - merges adjacent ranges in the given array.
845 * Array elements are deleted and replaced with the merged ranges.
846 */
847 static void crs_range_merge(GPtrArray *range)
848 {
849 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
850 CrsRangeEntry *entry;
851 uint64_t range_base, range_limit;
852 int i;
853
854 if (!range->len) {
855 return;
856 }
857
858 g_ptr_array_sort(range, crs_range_compare);
859
860 entry = g_ptr_array_index(range, 0);
861 range_base = entry->base;
862 range_limit = entry->limit;
863 for (i = 1; i < range->len; i++) {
864 entry = g_ptr_array_index(range, i);
865 if (entry->base - 1 == range_limit) {
866 range_limit = entry->limit;
867 } else {
868 crs_range_insert(tmp, range_base, range_limit);
869 range_base = entry->base;
870 range_limit = entry->limit;
871 }
872 }
873 crs_range_insert(tmp, range_base, range_limit);
874
875 g_ptr_array_set_size(range, 0);
876 for (i = 0; i < tmp->len; i++) {
877 entry = g_ptr_array_index(tmp, i);
878 crs_range_insert(range, entry->base, entry->limit);
879 }
880 g_ptr_array_free(tmp, true);
881 }
882
883 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
884 {
885 Aml *crs = aml_resource_template();
886 CrsRangeSet temp_range_set;
887 CrsRangeEntry *entry;
888 uint8_t max_bus = pci_bus_num(host->bus);
889 uint8_t type;
890 int devfn;
891 int i;
892
893 crs_range_set_init(&temp_range_set);
894 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
895 uint64_t range_base, range_limit;
896 PCIDevice *dev = host->bus->devices[devfn];
897
898 if (!dev) {
899 continue;
900 }
901
902 for (i = 0; i < PCI_NUM_REGIONS; i++) {
903 PCIIORegion *r = &dev->io_regions[i];
904
905 range_base = r->addr;
906 range_limit = r->addr + r->size - 1;
907
908 /*
909 * Work-around for old bioses
910 * that do not support multiple root buses
911 */
912 if (!range_base || range_base > range_limit) {
913 continue;
914 }
915
916 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
917 crs_range_insert(temp_range_set.io_ranges,
918 range_base, range_limit);
919 } else { /* "memory" */
920 crs_range_insert(temp_range_set.mem_ranges,
921 range_base, range_limit);
922 }
923 }
924
925 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
926 if (type == PCI_HEADER_TYPE_BRIDGE) {
927 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
928 if (subordinate > max_bus) {
929 max_bus = subordinate;
930 }
931
932 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
933 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
934
935 /*
936 * Work-around for old bioses
937 * that do not support multiple root buses
938 */
939 if (range_base && range_base <= range_limit) {
940 crs_range_insert(temp_range_set.io_ranges,
941 range_base, range_limit);
942 }
943
944 range_base =
945 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
946 range_limit =
947 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
948
949 /*
950 * Work-around for old bioses
951 * that do not support multiple root buses
952 */
953 if (range_base && range_base <= range_limit) {
954 uint64_t length = range_limit - range_base + 1;
955 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
956 crs_range_insert(temp_range_set.mem_ranges,
957 range_base, range_limit);
958 } else {
959 crs_range_insert(temp_range_set.mem_64bit_ranges,
960 range_base, range_limit);
961 }
962 }
963
964 range_base =
965 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
966 range_limit =
967 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
968
969 /*
970 * Work-around for old bioses
971 * that do not support multiple root buses
972 */
973 if (range_base && range_base <= range_limit) {
974 uint64_t length = range_limit - range_base + 1;
975 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
976 crs_range_insert(temp_range_set.mem_ranges,
977 range_base, range_limit);
978 } else {
979 crs_range_insert(temp_range_set.mem_64bit_ranges,
980 range_base, range_limit);
981 }
982 }
983 }
984 }
985
986 crs_range_merge(temp_range_set.io_ranges);
987 for (i = 0; i < temp_range_set.io_ranges->len; i++) {
988 entry = g_ptr_array_index(temp_range_set.io_ranges, i);
989 aml_append(crs,
990 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
991 AML_POS_DECODE, AML_ENTIRE_RANGE,
992 0, entry->base, entry->limit, 0,
993 entry->limit - entry->base + 1));
994 crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
995 }
996
997 crs_range_merge(temp_range_set.mem_ranges);
998 for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
999 entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
1000 aml_append(crs,
1001 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1002 AML_MAX_FIXED, AML_NON_CACHEABLE,
1003 AML_READ_WRITE,
1004 0, entry->base, entry->limit, 0,
1005 entry->limit - entry->base + 1));
1006 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
1007 }
1008
1009 crs_range_merge(temp_range_set.mem_64bit_ranges);
1010 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
1011 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
1012 aml_append(crs,
1013 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1014 AML_MAX_FIXED, AML_NON_CACHEABLE,
1015 AML_READ_WRITE,
1016 0, entry->base, entry->limit, 0,
1017 entry->limit - entry->base + 1));
1018 crs_range_insert(range_set->mem_64bit_ranges,
1019 entry->base, entry->limit);
1020 }
1021
1022 crs_range_set_free(&temp_range_set);
1023
1024 aml_append(crs,
1025 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1026 0,
1027 pci_bus_num(host->bus),
1028 max_bus,
1029 0,
1030 max_bus - pci_bus_num(host->bus) + 1));
1031
1032 return crs;
1033 }
1034
1035 static void build_hpet_aml(Aml *table)
1036 {
1037 Aml *crs;
1038 Aml *field;
1039 Aml *method;
1040 Aml *if_ctx;
1041 Aml *scope = aml_scope("_SB");
1042 Aml *dev = aml_device("HPET");
1043 Aml *zero = aml_int(0);
1044 Aml *id = aml_local(0);
1045 Aml *period = aml_local(1);
1046
1047 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1048 aml_append(dev, aml_name_decl("_UID", zero));
1049
1050 aml_append(dev,
1051 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1052 HPET_LEN));
1053 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1054 aml_append(field, aml_named_field("VEND", 32));
1055 aml_append(field, aml_named_field("PRD", 32));
1056 aml_append(dev, field);
1057
1058 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1059 aml_append(method, aml_store(aml_name("VEND"), id));
1060 aml_append(method, aml_store(aml_name("PRD"), period));
1061 aml_append(method, aml_shiftright(id, aml_int(16), id));
1062 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1063 aml_equal(id, aml_int(0xffff))));
1064 {
1065 aml_append(if_ctx, aml_return(zero));
1066 }
1067 aml_append(method, if_ctx);
1068
1069 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1070 aml_lgreater(period, aml_int(100000000))));
1071 {
1072 aml_append(if_ctx, aml_return(zero));
1073 }
1074 aml_append(method, if_ctx);
1075
1076 aml_append(method, aml_return(aml_int(0x0F)));
1077 aml_append(dev, method);
1078
1079 crs = aml_resource_template();
1080 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1081 aml_append(dev, aml_name_decl("_CRS", crs));
1082
1083 aml_append(scope, dev);
1084 aml_append(table, scope);
1085 }
1086
1087 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
1088 {
1089 Aml *dev, *fdi;
1090 uint8_t maxc, maxh, maxs;
1091
1092 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1093
1094 dev = aml_device("FLP%c", 'A' + idx);
1095
1096 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1097
1098 fdi = aml_package(16);
1099 aml_append(fdi, aml_int(idx)); /* Drive Number */
1100 aml_append(fdi,
1101 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1102 /*
1103 * the values below are the limits of the drive, and are thus independent
1104 * of the inserted media
1105 */
1106 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1107 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1108 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1109 /*
1110 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1111 * the drive type, so shall we
1112 */
1113 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1114 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1115 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1116 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1117 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1118 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1119 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1120 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1121 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1122 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1123 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1124
1125 aml_append(dev, aml_name_decl("_FDI", fdi));
1126 return dev;
1127 }
1128
1129 static Aml *build_fdc_device_aml(ISADevice *fdc)
1130 {
1131 int i;
1132 Aml *dev;
1133 Aml *crs;
1134
1135 #define ACPI_FDE_MAX_FD 4
1136 uint32_t fde_buf[5] = {
1137 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1138 cpu_to_le32(2) /* tape presence (2 == never present) */
1139 };
1140
1141 dev = aml_device("FDC0");
1142 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1143
1144 crs = aml_resource_template();
1145 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1146 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1147 aml_append(crs, aml_irq_no_flags(6));
1148 aml_append(crs,
1149 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1150 aml_append(dev, aml_name_decl("_CRS", crs));
1151
1152 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1153 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1154
1155 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1156 fde_buf[i] = cpu_to_le32(1); /* drive present */
1157 aml_append(dev, build_fdinfo_aml(i, type));
1158 }
1159 }
1160 aml_append(dev, aml_name_decl("_FDE",
1161 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1162
1163 return dev;
1164 }
1165
1166 static Aml *build_rtc_device_aml(void)
1167 {
1168 Aml *dev;
1169 Aml *crs;
1170
1171 dev = aml_device("RTC");
1172 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1173 crs = aml_resource_template();
1174 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1175 aml_append(crs, aml_irq_no_flags(8));
1176 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1177 aml_append(dev, aml_name_decl("_CRS", crs));
1178
1179 return dev;
1180 }
1181
1182 static Aml *build_kbd_device_aml(void)
1183 {
1184 Aml *dev;
1185 Aml *crs;
1186 Aml *method;
1187
1188 dev = aml_device("KBD");
1189 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1190
1191 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1192 aml_append(method, aml_return(aml_int(0x0f)));
1193 aml_append(dev, method);
1194
1195 crs = aml_resource_template();
1196 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1197 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1198 aml_append(crs, aml_irq_no_flags(1));
1199 aml_append(dev, aml_name_decl("_CRS", crs));
1200
1201 return dev;
1202 }
1203
1204 static Aml *build_mouse_device_aml(void)
1205 {
1206 Aml *dev;
1207 Aml *crs;
1208 Aml *method;
1209
1210 dev = aml_device("MOU");
1211 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1212
1213 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1214 aml_append(method, aml_return(aml_int(0x0f)));
1215 aml_append(dev, method);
1216
1217 crs = aml_resource_template();
1218 aml_append(crs, aml_irq_no_flags(12));
1219 aml_append(dev, aml_name_decl("_CRS", crs));
1220
1221 return dev;
1222 }
1223
1224 static Aml *build_lpt_device_aml(void)
1225 {
1226 Aml *dev;
1227 Aml *crs;
1228 Aml *method;
1229 Aml *if_ctx;
1230 Aml *else_ctx;
1231 Aml *zero = aml_int(0);
1232 Aml *is_present = aml_local(0);
1233
1234 dev = aml_device("LPT");
1235 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1236
1237 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1238 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1239 if_ctx = aml_if(aml_equal(is_present, zero));
1240 {
1241 aml_append(if_ctx, aml_return(aml_int(0x00)));
1242 }
1243 aml_append(method, if_ctx);
1244 else_ctx = aml_else();
1245 {
1246 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1247 }
1248 aml_append(method, else_ctx);
1249 aml_append(dev, method);
1250
1251 crs = aml_resource_template();
1252 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1253 aml_append(crs, aml_irq_no_flags(7));
1254 aml_append(dev, aml_name_decl("_CRS", crs));
1255
1256 return dev;
1257 }
1258
1259 static Aml *build_com_device_aml(uint8_t uid)
1260 {
1261 Aml *dev;
1262 Aml *crs;
1263 Aml *method;
1264 Aml *if_ctx;
1265 Aml *else_ctx;
1266 Aml *zero = aml_int(0);
1267 Aml *is_present = aml_local(0);
1268 const char *enabled_field = "CAEN";
1269 uint8_t irq = 4;
1270 uint16_t io_port = 0x03F8;
1271
1272 assert(uid == 1 || uid == 2);
1273 if (uid == 2) {
1274 enabled_field = "CBEN";
1275 irq = 3;
1276 io_port = 0x02F8;
1277 }
1278
1279 dev = aml_device("COM%d", uid);
1280 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1281 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1282
1283 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1284 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1285 if_ctx = aml_if(aml_equal(is_present, zero));
1286 {
1287 aml_append(if_ctx, aml_return(aml_int(0x00)));
1288 }
1289 aml_append(method, if_ctx);
1290 else_ctx = aml_else();
1291 {
1292 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1293 }
1294 aml_append(method, else_ctx);
1295 aml_append(dev, method);
1296
1297 crs = aml_resource_template();
1298 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1299 aml_append(crs, aml_irq_no_flags(irq));
1300 aml_append(dev, aml_name_decl("_CRS", crs));
1301
1302 return dev;
1303 }
1304
1305 static void build_isa_devices_aml(Aml *table)
1306 {
1307 ISADevice *fdc = pc_find_fdc0();
1308 bool ambiguous;
1309
1310 Aml *scope = aml_scope("_SB.PCI0.ISA");
1311 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
1312
1313 aml_append(scope, build_rtc_device_aml());
1314 aml_append(scope, build_kbd_device_aml());
1315 aml_append(scope, build_mouse_device_aml());
1316 if (fdc) {
1317 aml_append(scope, build_fdc_device_aml(fdc));
1318 }
1319 aml_append(scope, build_lpt_device_aml());
1320 aml_append(scope, build_com_device_aml(1));
1321 aml_append(scope, build_com_device_aml(2));
1322
1323 if (ambiguous) {
1324 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1325 } else if (!obj) {
1326 error_report("No ISA bus, unable to define IPMI ACPI data");
1327 } else {
1328 build_acpi_ipmi_devices(scope, BUS(obj));
1329 }
1330
1331 aml_append(table, scope);
1332 }
1333
1334 static void build_dbg_aml(Aml *table)
1335 {
1336 Aml *field;
1337 Aml *method;
1338 Aml *while_ctx;
1339 Aml *scope = aml_scope("\\");
1340 Aml *buf = aml_local(0);
1341 Aml *len = aml_local(1);
1342 Aml *idx = aml_local(2);
1343
1344 aml_append(scope,
1345 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1346 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1347 aml_append(field, aml_named_field("DBGB", 8));
1348 aml_append(scope, field);
1349
1350 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1351
1352 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1353 aml_append(method, aml_to_buffer(buf, buf));
1354 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1355 aml_append(method, aml_store(aml_int(0), idx));
1356
1357 while_ctx = aml_while(aml_lless(idx, len));
1358 aml_append(while_ctx,
1359 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1360 aml_append(while_ctx, aml_increment(idx));
1361 aml_append(method, while_ctx);
1362
1363 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1364 aml_append(scope, method);
1365
1366 aml_append(table, scope);
1367 }
1368
1369 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1370 {
1371 Aml *dev;
1372 Aml *crs;
1373 Aml *method;
1374 uint32_t irqs[] = {5, 10, 11};
1375
1376 dev = aml_device("%s", name);
1377 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1378 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1379
1380 crs = aml_resource_template();
1381 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1382 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1383 aml_append(dev, aml_name_decl("_PRS", crs));
1384
1385 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1386 aml_append(method, aml_return(aml_call1("IQST", reg)));
1387 aml_append(dev, method);
1388
1389 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1390 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1391 aml_append(dev, method);
1392
1393 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1394 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1395 aml_append(dev, method);
1396
1397 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1398 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1399 aml_append(method, aml_store(aml_name("PRRI"), reg));
1400 aml_append(dev, method);
1401
1402 return dev;
1403 }
1404
1405 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1406 {
1407 Aml *dev;
1408 Aml *crs;
1409 Aml *method;
1410 uint32_t irqs;
1411
1412 dev = aml_device("%s", name);
1413 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1414 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1415
1416 crs = aml_resource_template();
1417 irqs = gsi;
1418 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1419 AML_SHARED, &irqs, 1));
1420 aml_append(dev, aml_name_decl("_PRS", crs));
1421
1422 aml_append(dev, aml_name_decl("_CRS", crs));
1423
1424 /*
1425 * _DIS can be no-op because the interrupt cannot be disabled.
1426 */
1427 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1428 aml_append(dev, method);
1429
1430 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1431 aml_append(dev, method);
1432
1433 return dev;
1434 }
1435
1436 /* _CRS method - get current settings */
1437 static Aml *build_iqcr_method(bool is_piix4)
1438 {
1439 Aml *if_ctx;
1440 uint32_t irqs;
1441 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1442 Aml *crs = aml_resource_template();
1443
1444 irqs = 0;
1445 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1446 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1447 aml_append(method, aml_name_decl("PRR0", crs));
1448
1449 aml_append(method,
1450 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1451
1452 if (is_piix4) {
1453 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1454 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1455 aml_append(method, if_ctx);
1456 } else {
1457 aml_append(method,
1458 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1459 aml_name("PRRI")));
1460 }
1461
1462 aml_append(method, aml_return(aml_name("PRR0")));
1463 return method;
1464 }
1465
1466 /* _STA method - get status */
1467 static Aml *build_irq_status_method(void)
1468 {
1469 Aml *if_ctx;
1470 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1471
1472 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1473 aml_append(if_ctx, aml_return(aml_int(0x09)));
1474 aml_append(method, if_ctx);
1475 aml_append(method, aml_return(aml_int(0x0B)));
1476 return method;
1477 }
1478
1479 static void build_piix4_pci0_int(Aml *table)
1480 {
1481 Aml *dev;
1482 Aml *crs;
1483 Aml *field;
1484 Aml *method;
1485 uint32_t irqs;
1486 Aml *sb_scope = aml_scope("_SB");
1487 Aml *pci0_scope = aml_scope("PCI0");
1488
1489 aml_append(pci0_scope, build_prt(true));
1490 aml_append(sb_scope, pci0_scope);
1491
1492 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1493 aml_append(field, aml_named_field("PRQ0", 8));
1494 aml_append(field, aml_named_field("PRQ1", 8));
1495 aml_append(field, aml_named_field("PRQ2", 8));
1496 aml_append(field, aml_named_field("PRQ3", 8));
1497 aml_append(sb_scope, field);
1498
1499 aml_append(sb_scope, build_irq_status_method());
1500 aml_append(sb_scope, build_iqcr_method(true));
1501
1502 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1503 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1504 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1505 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1506
1507 dev = aml_device("LNKS");
1508 {
1509 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1510 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1511
1512 crs = aml_resource_template();
1513 irqs = 9;
1514 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1515 AML_ACTIVE_HIGH, AML_SHARED,
1516 &irqs, 1));
1517 aml_append(dev, aml_name_decl("_PRS", crs));
1518
1519 /* The SCI cannot be disabled and is always attached to GSI 9,
1520 * so these are no-ops. We only need this link to override the
1521 * polarity to active high and match the content of the MADT.
1522 */
1523 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1524 aml_append(method, aml_return(aml_int(0x0b)));
1525 aml_append(dev, method);
1526
1527 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1528 aml_append(dev, method);
1529
1530 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1531 aml_append(method, aml_return(aml_name("_PRS")));
1532 aml_append(dev, method);
1533
1534 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1535 aml_append(dev, method);
1536 }
1537 aml_append(sb_scope, dev);
1538
1539 aml_append(table, sb_scope);
1540 }
1541
1542 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1543 {
1544 int i;
1545 int head;
1546 Aml *pkg;
1547 char base = name[3] < 'E' ? 'A' : 'E';
1548 char *s = g_strdup(name);
1549 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1550
1551 assert(strlen(s) == 4);
1552
1553 head = name[3] - base;
1554 for (i = 0; i < 4; i++) {
1555 if (head + i > 3) {
1556 head = i * -1;
1557 }
1558 s[3] = base + head + i;
1559 pkg = aml_package(4);
1560 aml_append(pkg, a_nr);
1561 aml_append(pkg, aml_int(i));
1562 aml_append(pkg, aml_name("%s", s));
1563 aml_append(pkg, aml_int(0));
1564 aml_append(ctx, pkg);
1565 }
1566 g_free(s);
1567 }
1568
1569 static Aml *build_q35_routing_table(const char *str)
1570 {
1571 int i;
1572 Aml *pkg;
1573 char *name = g_strdup_printf("%s ", str);
1574
1575 pkg = aml_package(128);
1576 for (i = 0; i < 0x18; i++) {
1577 name[3] = 'E' + (i & 0x3);
1578 append_q35_prt_entry(pkg, i, name);
1579 }
1580
1581 name[3] = 'E';
1582 append_q35_prt_entry(pkg, 0x18, name);
1583
1584 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1585 for (i = 0x0019; i < 0x1e; i++) {
1586 name[3] = 'A';
1587 append_q35_prt_entry(pkg, i, name);
1588 }
1589
1590 /* PCIe->PCI bridge. use PIRQ[E-H] */
1591 name[3] = 'E';
1592 append_q35_prt_entry(pkg, 0x1e, name);
1593 name[3] = 'A';
1594 append_q35_prt_entry(pkg, 0x1f, name);
1595
1596 g_free(name);
1597 return pkg;
1598 }
1599
1600 static void build_q35_pci0_int(Aml *table)
1601 {
1602 Aml *field;
1603 Aml *method;
1604 Aml *sb_scope = aml_scope("_SB");
1605 Aml *pci0_scope = aml_scope("PCI0");
1606
1607 /* Zero => PIC mode, One => APIC Mode */
1608 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1609 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1610 {
1611 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1612 }
1613 aml_append(table, method);
1614
1615 aml_append(pci0_scope,
1616 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1617 aml_append(pci0_scope,
1618 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1619
1620 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1621 {
1622 Aml *if_ctx;
1623 Aml *else_ctx;
1624
1625 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1626 section 6.2.8.1 */
1627 /* Note: we provide the same info as the PCI routing
1628 table of the Bochs BIOS */
1629 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1630 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1631 aml_append(method, if_ctx);
1632 else_ctx = aml_else();
1633 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1634 aml_append(method, else_ctx);
1635 }
1636 aml_append(pci0_scope, method);
1637 aml_append(sb_scope, pci0_scope);
1638
1639 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1640 aml_append(field, aml_named_field("PRQA", 8));
1641 aml_append(field, aml_named_field("PRQB", 8));
1642 aml_append(field, aml_named_field("PRQC", 8));
1643 aml_append(field, aml_named_field("PRQD", 8));
1644 aml_append(field, aml_reserved_field(0x20));
1645 aml_append(field, aml_named_field("PRQE", 8));
1646 aml_append(field, aml_named_field("PRQF", 8));
1647 aml_append(field, aml_named_field("PRQG", 8));
1648 aml_append(field, aml_named_field("PRQH", 8));
1649 aml_append(sb_scope, field);
1650
1651 aml_append(sb_scope, build_irq_status_method());
1652 aml_append(sb_scope, build_iqcr_method(false));
1653
1654 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1655 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1656 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1657 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1658 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1659 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1660 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1661 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1662
1663 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1664 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1665 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1666 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1667 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1668 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1669 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1670 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1671
1672 aml_append(table, sb_scope);
1673 }
1674
1675 static void build_q35_isa_bridge(Aml *table)
1676 {
1677 Aml *dev;
1678 Aml *scope;
1679 Aml *field;
1680
1681 scope = aml_scope("_SB.PCI0");
1682 dev = aml_device("ISA");
1683 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1684
1685 /* ICH9 PCI to ISA irq remapping */
1686 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1687 aml_int(0x60), 0x0C));
1688
1689 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1690 aml_int(0x80), 0x02));
1691 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1692 aml_append(field, aml_named_field("COMA", 3));
1693 aml_append(field, aml_reserved_field(1));
1694 aml_append(field, aml_named_field("COMB", 3));
1695 aml_append(field, aml_reserved_field(1));
1696 aml_append(field, aml_named_field("LPTD", 2));
1697 aml_append(dev, field);
1698
1699 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1700 aml_int(0x82), 0x02));
1701 /* enable bits */
1702 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1703 aml_append(field, aml_named_field("CAEN", 1));
1704 aml_append(field, aml_named_field("CBEN", 1));
1705 aml_append(field, aml_named_field("LPEN", 1));
1706 aml_append(dev, field);
1707
1708 aml_append(scope, dev);
1709 aml_append(table, scope);
1710 }
1711
1712 static void build_piix4_pm(Aml *table)
1713 {
1714 Aml *dev;
1715 Aml *scope;
1716
1717 scope = aml_scope("_SB.PCI0");
1718 dev = aml_device("PX13");
1719 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1720
1721 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1722 aml_int(0x00), 0xff));
1723 aml_append(scope, dev);
1724 aml_append(table, scope);
1725 }
1726
1727 static void build_piix4_isa_bridge(Aml *table)
1728 {
1729 Aml *dev;
1730 Aml *scope;
1731 Aml *field;
1732
1733 scope = aml_scope("_SB.PCI0");
1734 dev = aml_device("ISA");
1735 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1736
1737 /* PIIX PCI to ISA irq remapping */
1738 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1739 aml_int(0x60), 0x04));
1740 /* enable bits */
1741 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1742 /* Offset(0x5f),, 7, */
1743 aml_append(field, aml_reserved_field(0x2f8));
1744 aml_append(field, aml_reserved_field(7));
1745 aml_append(field, aml_named_field("LPEN", 1));
1746 /* Offset(0x67),, 3, */
1747 aml_append(field, aml_reserved_field(0x38));
1748 aml_append(field, aml_reserved_field(3));
1749 aml_append(field, aml_named_field("CAEN", 1));
1750 aml_append(field, aml_reserved_field(3));
1751 aml_append(field, aml_named_field("CBEN", 1));
1752 aml_append(dev, field);
1753
1754 aml_append(scope, dev);
1755 aml_append(table, scope);
1756 }
1757
1758 static void build_piix4_pci_hotplug(Aml *table)
1759 {
1760 Aml *scope;
1761 Aml *field;
1762 Aml *method;
1763
1764 scope = aml_scope("_SB.PCI0");
1765
1766 aml_append(scope,
1767 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1768 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1769 aml_append(field, aml_named_field("PCIU", 32));
1770 aml_append(field, aml_named_field("PCID", 32));
1771 aml_append(scope, field);
1772
1773 aml_append(scope,
1774 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1775 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1776 aml_append(field, aml_named_field("B0EJ", 32));
1777 aml_append(scope, field);
1778
1779 aml_append(scope,
1780 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1781 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1782 aml_append(field, aml_named_field("BNUM", 32));
1783 aml_append(scope, field);
1784
1785 aml_append(scope, aml_mutex("BLCK", 0));
1786
1787 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1788 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1789 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1790 aml_append(method,
1791 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1792 aml_append(method, aml_release(aml_name("BLCK")));
1793 aml_append(method, aml_return(aml_int(0)));
1794 aml_append(scope, method);
1795
1796 aml_append(table, scope);
1797 }
1798
1799 static Aml *build_q35_osc_method(void)
1800 {
1801 Aml *if_ctx;
1802 Aml *if_ctx2;
1803 Aml *else_ctx;
1804 Aml *method;
1805 Aml *a_cwd1 = aml_name("CDW1");
1806 Aml *a_ctrl = aml_name("CTRL");
1807
1808 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1809 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1810
1811 if_ctx = aml_if(aml_equal(
1812 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1813 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1814 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1815
1816 aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1817 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1818
1819 /*
1820 * Always allow native PME, AER (no dependencies)
1821 * Never allow SHPC (no SHPC controller in this system)
1822 */
1823 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
1824
1825 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1826 /* Unknown revision */
1827 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1828 aml_append(if_ctx, if_ctx2);
1829
1830 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1831 /* Capabilities bits were masked */
1832 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1833 aml_append(if_ctx, if_ctx2);
1834
1835 /* Update DWORD3 in the buffer */
1836 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1837 aml_append(method, if_ctx);
1838
1839 else_ctx = aml_else();
1840 /* Unrecognized UUID */
1841 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1842 aml_append(method, else_ctx);
1843
1844 aml_append(method, aml_return(aml_arg(3)));
1845 return method;
1846 }
1847
1848 static void
1849 build_dsdt(GArray *table_data, BIOSLinker *linker,
1850 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1851 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1852 {
1853 CrsRangeEntry *entry;
1854 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1855 CrsRangeSet crs_range_set;
1856 PCMachineState *pcms = PC_MACHINE(machine);
1857 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1858 uint32_t nr_mem = machine->ram_slots;
1859 int root_bus_limit = 0xFF;
1860 PCIBus *bus = NULL;
1861 int i;
1862
1863 dsdt = init_aml_allocator();
1864
1865 /* Reserve space for header */
1866 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1867
1868 build_dbg_aml(dsdt);
1869 if (misc->is_piix4) {
1870 sb_scope = aml_scope("_SB");
1871 dev = aml_device("PCI0");
1872 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1873 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1874 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1875 aml_append(sb_scope, dev);
1876 aml_append(dsdt, sb_scope);
1877
1878 build_hpet_aml(dsdt);
1879 build_piix4_pm(dsdt);
1880 build_piix4_isa_bridge(dsdt);
1881 build_isa_devices_aml(dsdt);
1882 build_piix4_pci_hotplug(dsdt);
1883 build_piix4_pci0_int(dsdt);
1884 } else {
1885 sb_scope = aml_scope("_SB");
1886 aml_append(sb_scope,
1887 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c));
1888 aml_append(sb_scope,
1889 aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01));
1890 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1891 aml_append(field, aml_named_field("PCIB", 8));
1892 aml_append(sb_scope, field);
1893 aml_append(dsdt, sb_scope);
1894
1895 sb_scope = aml_scope("_SB");
1896 dev = aml_device("PCI0");
1897 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1898 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1899 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1900 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1901 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
1902 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
1903 aml_append(dev, build_q35_osc_method());
1904 aml_append(sb_scope, dev);
1905 aml_append(dsdt, sb_scope);
1906
1907 build_hpet_aml(dsdt);
1908 build_q35_isa_bridge(dsdt);
1909 build_isa_devices_aml(dsdt);
1910 build_q35_pci0_int(dsdt);
1911 }
1912
1913 if (pcmc->legacy_cpu_hotplug) {
1914 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1915 } else {
1916 CPUHotplugFeatures opts = {
1917 .apci_1_compatible = true, .has_legacy_cphp = true
1918 };
1919 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1920 "\\_SB.PCI0", "\\_GPE._E02");
1921 }
1922 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", "\\_GPE._E03");
1923
1924 scope = aml_scope("_GPE");
1925 {
1926 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1927
1928 if (misc->is_piix4) {
1929 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1930 aml_append(method,
1931 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1932 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1933 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1934 aml_append(scope, method);
1935 }
1936
1937 if (pcms->acpi_nvdimm_state.is_enabled) {
1938 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1939 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1940 aml_int(0x80)));
1941 aml_append(scope, method);
1942 }
1943 }
1944 aml_append(dsdt, scope);
1945
1946 crs_range_set_init(&crs_range_set);
1947 bus = PC_MACHINE(machine)->bus;
1948 if (bus) {
1949 QLIST_FOREACH(bus, &bus->child, sibling) {
1950 uint8_t bus_num = pci_bus_num(bus);
1951 uint8_t numa_node = pci_bus_numa_node(bus);
1952
1953 /* look only for expander root buses */
1954 if (!pci_bus_is_root(bus)) {
1955 continue;
1956 }
1957
1958 if (bus_num < root_bus_limit) {
1959 root_bus_limit = bus_num - 1;
1960 }
1961
1962 scope = aml_scope("\\_SB");
1963 dev = aml_device("PC%.02X", bus_num);
1964 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1965 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1966 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1967
1968 if (numa_node != NUMA_NODE_UNASSIGNED) {
1969 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1970 }
1971
1972 aml_append(dev, build_prt(false));
1973 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
1974 aml_append(dev, aml_name_decl("_CRS", crs));
1975 aml_append(scope, dev);
1976 aml_append(dsdt, scope);
1977 }
1978 }
1979
1980 scope = aml_scope("\\_SB.PCI0");
1981 /* build PCI0._CRS */
1982 crs = aml_resource_template();
1983 aml_append(crs,
1984 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1985 0x0000, 0x0, root_bus_limit,
1986 0x0000, root_bus_limit + 1));
1987 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1988
1989 aml_append(crs,
1990 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1991 AML_POS_DECODE, AML_ENTIRE_RANGE,
1992 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1993
1994 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1995 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1996 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1997 aml_append(crs,
1998 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1999 AML_POS_DECODE, AML_ENTIRE_RANGE,
2000 0x0000, entry->base, entry->limit,
2001 0x0000, entry->limit - entry->base + 1));
2002 }
2003
2004 aml_append(crs,
2005 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2006 AML_CACHEABLE, AML_READ_WRITE,
2007 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2008
2009 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
2010 range_lob(pci_hole),
2011 range_upb(pci_hole));
2012 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
2013 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
2014 aml_append(crs,
2015 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2016 AML_NON_CACHEABLE, AML_READ_WRITE,
2017 0, entry->base, entry->limit,
2018 0, entry->limit - entry->base + 1));
2019 }
2020
2021 if (!range_is_empty(pci_hole64)) {
2022 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
2023 range_lob(pci_hole64),
2024 range_upb(pci_hole64));
2025 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
2026 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
2027 aml_append(crs,
2028 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
2029 AML_MAX_FIXED,
2030 AML_CACHEABLE, AML_READ_WRITE,
2031 0, entry->base, entry->limit,
2032 0, entry->limit - entry->base + 1));
2033 }
2034 }
2035
2036 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2037 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2038 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2039 }
2040 aml_append(scope, aml_name_decl("_CRS", crs));
2041
2042 /* reserve GPE0 block resources */
2043 dev = aml_device("GPE0");
2044 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2045 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2046 /* device present, functioning, decoding, not shown in UI */
2047 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2048 crs = aml_resource_template();
2049 aml_append(crs,
2050 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
2051 );
2052 aml_append(dev, aml_name_decl("_CRS", crs));
2053 aml_append(scope, dev);
2054
2055 crs_range_set_free(&crs_range_set);
2056
2057 /* reserve PCIHP resources */
2058 if (pm->pcihp_io_len) {
2059 dev = aml_device("PHPR");
2060 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2061 aml_append(dev,
2062 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2063 /* device present, functioning, decoding, not shown in UI */
2064 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2065 crs = aml_resource_template();
2066 aml_append(crs,
2067 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2068 pm->pcihp_io_len)
2069 );
2070 aml_append(dev, aml_name_decl("_CRS", crs));
2071 aml_append(scope, dev);
2072 }
2073 aml_append(dsdt, scope);
2074
2075 /* create S3_ / S4_ / S5_ packages if necessary */
2076 scope = aml_scope("\\");
2077 if (!pm->s3_disabled) {
2078 pkg = aml_package(4);
2079 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2080 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2081 aml_append(pkg, aml_int(0)); /* reserved */
2082 aml_append(pkg, aml_int(0)); /* reserved */
2083 aml_append(scope, aml_name_decl("_S3", pkg));
2084 }
2085
2086 if (!pm->s4_disabled) {
2087 pkg = aml_package(4);
2088 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2089 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2090 aml_append(pkg, aml_int(pm->s4_val));
2091 aml_append(pkg, aml_int(0)); /* reserved */
2092 aml_append(pkg, aml_int(0)); /* reserved */
2093 aml_append(scope, aml_name_decl("_S4", pkg));
2094 }
2095
2096 pkg = aml_package(4);
2097 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2098 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2099 aml_append(pkg, aml_int(0)); /* reserved */
2100 aml_append(pkg, aml_int(0)); /* reserved */
2101 aml_append(scope, aml_name_decl("_S5", pkg));
2102 aml_append(dsdt, scope);
2103
2104 /* create fw_cfg node, unconditionally */
2105 {
2106 /* when using port i/o, the 8-bit data register *always* overlaps
2107 * with half of the 16-bit control register. Hence, the total size
2108 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2109 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2110 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2111 "dma_enabled", NULL) ?
2112 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2113 FW_CFG_CTL_SIZE;
2114
2115 scope = aml_scope("\\_SB.PCI0");
2116 dev = aml_device("FWCF");
2117
2118 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2119
2120 /* device present, functioning, decoding, not shown in UI */
2121 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2122
2123 crs = aml_resource_template();
2124 aml_append(crs,
2125 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2126 );
2127 aml_append(dev, aml_name_decl("_CRS", crs));
2128
2129 aml_append(scope, dev);
2130 aml_append(dsdt, scope);
2131 }
2132
2133 if (misc->applesmc_io_base) {
2134 scope = aml_scope("\\_SB.PCI0.ISA");
2135 dev = aml_device("SMC");
2136
2137 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2138 /* device present, functioning, decoding, not shown in UI */
2139 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2140
2141 crs = aml_resource_template();
2142 aml_append(crs,
2143 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2144 0x01, APPLESMC_MAX_DATA_LENGTH)
2145 );
2146 aml_append(crs, aml_irq_no_flags(6));
2147 aml_append(dev, aml_name_decl("_CRS", crs));
2148
2149 aml_append(scope, dev);
2150 aml_append(dsdt, scope);
2151 }
2152
2153 if (misc->pvpanic_port) {
2154 scope = aml_scope("\\_SB.PCI0.ISA");
2155
2156 dev = aml_device("PEVT");
2157 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2158
2159 crs = aml_resource_template();
2160 aml_append(crs,
2161 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2162 );
2163 aml_append(dev, aml_name_decl("_CRS", crs));
2164
2165 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2166 aml_int(misc->pvpanic_port), 1));
2167 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2168 aml_append(field, aml_named_field("PEPT", 8));
2169 aml_append(dev, field);
2170
2171 /* device present, functioning, decoding, shown in UI */
2172 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2173
2174 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2175 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2176 aml_append(method, aml_return(aml_local(0)));
2177 aml_append(dev, method);
2178
2179 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2180 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2181 aml_append(dev, method);
2182
2183 aml_append(scope, dev);
2184 aml_append(dsdt, scope);
2185 }
2186
2187 sb_scope = aml_scope("\\_SB");
2188 {
2189 Object *pci_host;
2190 PCIBus *bus = NULL;
2191
2192 pci_host = acpi_get_i386_pci_host();
2193 if (pci_host) {
2194 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2195 }
2196
2197 if (bus) {
2198 Aml *scope = aml_scope("PCI0");
2199 /* Scan all PCI buses. Generate tables to support hotplug. */
2200 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2201
2202 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2203 dev = aml_device("ISA.TPM");
2204 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2205 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2206 crs = aml_resource_template();
2207 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2208 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2209 /*
2210 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2211 Rewrite to take IRQ from TPM device model and
2212 fix default IRQ value there to use some unused IRQ
2213 */
2214 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2215 aml_append(dev, aml_name_decl("_CRS", crs));
2216 aml_append(scope, dev);
2217 }
2218
2219 aml_append(sb_scope, scope);
2220 }
2221 }
2222 aml_append(dsdt, sb_scope);
2223
2224 /* copy AML table into ACPI tables blob and patch header there */
2225 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
2226 build_header(linker, table_data,
2227 (void *)(table_data->data + table_data->len - dsdt->buf->len),
2228 "DSDT", dsdt->buf->len, 1, NULL, NULL);
2229 free_aml_allocator();
2230 }
2231
2232 static void
2233 build_hpet(GArray *table_data, BIOSLinker *linker)
2234 {
2235 Acpi20Hpet *hpet;
2236
2237 hpet = acpi_data_push(table_data, sizeof(*hpet));
2238 /* Note timer_block_id value must be kept in sync with value advertised by
2239 * emulated hpet
2240 */
2241 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2242 hpet->addr.address = cpu_to_le64(HPET_BASE);
2243 build_header(linker, table_data,
2244 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
2245 }
2246
2247 static void
2248 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2249 {
2250 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2251 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
2252 unsigned log_addr_offset =
2253 (char *)&tcpa->log_area_start_address - table_data->data;
2254
2255 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2256 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2257 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
2258
2259 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
2260 false /* high memory */);
2261
2262 /* log area start address to be filled by Guest linker */
2263 bios_linker_loader_add_pointer(linker,
2264 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
2265 ACPI_BUILD_TPMLOG_FILE, 0);
2266
2267 build_header(linker, table_data,
2268 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
2269 }
2270
2271 static void
2272 build_tpm2(GArray *table_data, BIOSLinker *linker)
2273 {
2274 Acpi20TPM2 *tpm2_ptr;
2275
2276 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2277
2278 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2279 tpm2_ptr->control_area_address = cpu_to_le64(0);
2280 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2281
2282 build_header(linker, table_data,
2283 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
2284 }
2285
2286 static void
2287 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
2288 {
2289 AcpiSystemResourceAffinityTable *srat;
2290 AcpiSratMemoryAffinity *numamem;
2291
2292 int i;
2293 int srat_start, numa_start, slots;
2294 uint64_t mem_len, mem_base, next_base;
2295 MachineClass *mc = MACHINE_GET_CLASS(machine);
2296 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
2297 PCMachineState *pcms = PC_MACHINE(machine);
2298 ram_addr_t hotplugabble_address_space_size =
2299 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
2300 NULL);
2301
2302 srat_start = table_data->len;
2303
2304 srat = acpi_data_push(table_data, sizeof *srat);
2305 srat->reserved1 = cpu_to_le32(1);
2306
2307 for (i = 0; i < apic_ids->len; i++) {
2308 int j = numa_get_node_for_cpu(i);
2309 uint32_t apic_id = apic_ids->cpus[i].arch_id;
2310
2311 if (apic_id < 255) {
2312 AcpiSratProcessorAffinity *core;
2313
2314 core = acpi_data_push(table_data, sizeof *core);
2315 core->type = ACPI_SRAT_PROCESSOR_APIC;
2316 core->length = sizeof(*core);
2317 core->local_apic_id = apic_id;
2318 if (j < nb_numa_nodes) {
2319 core->proximity_lo = j;
2320 }
2321 memset(core->proximity_hi, 0, 3);
2322 core->local_sapic_eid = 0;
2323 core->flags = cpu_to_le32(1);
2324 } else {
2325 AcpiSratProcessorX2ApicAffinity *core;
2326
2327 core = acpi_data_push(table_data, sizeof *core);
2328 core->type = ACPI_SRAT_PROCESSOR_x2APIC;
2329 core->length = sizeof(*core);
2330 core->x2apic_id = cpu_to_le32(apic_id);
2331 if (j < nb_numa_nodes) {
2332 core->proximity_domain = cpu_to_le32(j);
2333 }
2334 core->flags = cpu_to_le32(1);
2335 }
2336 }
2337
2338
2339 /* the memory map is a bit tricky, it contains at least one hole
2340 * from 640k-1M and possibly another one from 3.5G-4G.
2341 */
2342 next_base = 0;
2343 numa_start = table_data->len;
2344
2345 numamem = acpi_data_push(table_data, sizeof *numamem);
2346 build_srat_memory(numamem, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED);
2347 next_base = 1024 * 1024;
2348 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2349 mem_base = next_base;
2350 mem_len = pcms->node_mem[i - 1];
2351 if (i == 1) {
2352 mem_len -= 1024 * 1024;
2353 }
2354 next_base = mem_base + mem_len;
2355
2356 /* Cut out the ACPI_PCI hole */
2357 if (mem_base <= pcms->below_4g_mem_size &&
2358 next_base > pcms->below_4g_mem_size) {
2359 mem_len -= next_base - pcms->below_4g_mem_size;
2360 if (mem_len > 0) {
2361 numamem = acpi_data_push(table_data, sizeof *numamem);
2362 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2363 MEM_AFFINITY_ENABLED);
2364 }
2365 mem_base = 1ULL << 32;
2366 mem_len = next_base - pcms->below_4g_mem_size;
2367 next_base += (1ULL << 32) - pcms->below_4g_mem_size;
2368 }
2369 numamem = acpi_data_push(table_data, sizeof *numamem);
2370 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2371 MEM_AFFINITY_ENABLED);
2372 }
2373 slots = (table_data->len - numa_start) / sizeof *numamem;
2374 for (; slots < pcms->numa_nodes + 2; slots++) {
2375 numamem = acpi_data_push(table_data, sizeof *numamem);
2376 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2377 }
2378
2379 /*
2380 * Entry is required for Windows to enable memory hotplug in OS.
2381 * Memory devices may override proximity set by this entry,
2382 * providing _PXM method if necessary.
2383 */
2384 if (hotplugabble_address_space_size) {
2385 numamem = acpi_data_push(table_data, sizeof *numamem);
2386 build_srat_memory(numamem, pcms->hotplug_memory.base,
2387 hotplugabble_address_space_size, 0,
2388 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2389 }
2390
2391 build_header(linker, table_data,
2392 (void *)(table_data->data + srat_start),
2393 "SRAT",
2394 table_data->len - srat_start, 1, NULL, NULL);
2395 }
2396
2397 static void
2398 build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info)
2399 {
2400 AcpiTableMcfg *mcfg;
2401 const char *sig;
2402 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2403
2404 mcfg = acpi_data_push(table_data, len);
2405 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2406 /* Only a single allocation so no need to play with segments */
2407 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2408 mcfg->allocation[0].start_bus_number = 0;
2409 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2410
2411 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2412 * To avoid table size changes (which create migration issues),
2413 * always create the table even if there are no allocations,
2414 * but set the signature to a reserved value in this case.
2415 * ACPI spec requires OSPMs to ignore such tables.
2416 */
2417 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
2418 /* Reserved signature: ignored by OSPM */
2419 sig = "QEMU";
2420 } else {
2421 sig = "MCFG";
2422 }
2423 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
2424 }
2425
2426 /*
2427 * VT-d spec 8.1 DMA Remapping Reporting Structure
2428 * (version Oct. 2014 or later)
2429 */
2430 static void
2431 build_dmar_q35(GArray *table_data, BIOSLinker *linker)
2432 {
2433 int dmar_start = table_data->len;
2434
2435 AcpiTableDmar *dmar;
2436 AcpiDmarHardwareUnit *drhd;
2437 AcpiDmarRootPortATS *atsr;
2438 uint8_t dmar_flags = 0;
2439 X86IOMMUState *iommu = x86_iommu_get_default();
2440 AcpiDmarDeviceScope *scope = NULL;
2441 /* Root complex IOAPIC use one path[0] only */
2442 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
2443
2444 assert(iommu);
2445 if (iommu->intr_supported) {
2446 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2447 }
2448
2449 dmar = acpi_data_push(table_data, sizeof(*dmar));
2450 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
2451 dmar->flags = dmar_flags;
2452
2453 /* DMAR Remapping Hardware Unit Definition structure */
2454 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
2455 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2456 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
2457 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2458 drhd->pci_segment = cpu_to_le16(0);
2459 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2460
2461 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2462 * 8.3.1 (version Oct. 2014 or later). */
2463 scope = &drhd->scope[0];
2464 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
2465 scope->length = ioapic_scope_size;
2466 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2467 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
2468 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
2469 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
2470
2471 if (iommu->dt_supported) {
2472 atsr = acpi_data_push(table_data, sizeof(*atsr));
2473 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
2474 atsr->length = cpu_to_le16(sizeof(*atsr));
2475 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
2476 atsr->pci_segment = cpu_to_le16(0);
2477 }
2478
2479 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2480 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2481 }
2482 /*
2483 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2484 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2485 */
2486 static void
2487 build_amd_iommu(GArray *table_data, BIOSLinker *linker)
2488 {
2489 int iommu_start = table_data->len;
2490 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2491
2492 /* IVRS header */
2493 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2494 /* IVinfo - IO virtualization information common to all
2495 * IOMMU units in a system
2496 */
2497 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2498 /* reserved */
2499 build_append_int_noprefix(table_data, 0, 8);
2500
2501 /* IVHD definition - type 10h */
2502 build_append_int_noprefix(table_data, 0x10, 1);
2503 /* virtualization flags */
2504 build_append_int_noprefix(table_data,
2505 (1UL << 0) | /* HtTunEn */
2506 (1UL << 4) | /* iotblSup */
2507 (1UL << 6) | /* PrefSup */
2508 (1UL << 7), /* PPRSup */
2509 1);
2510 /* IVHD length */
2511 build_append_int_noprefix(table_data, 0x24, 2);
2512 /* DeviceID */
2513 build_append_int_noprefix(table_data, s->devid, 2);
2514 /* Capability offset */
2515 build_append_int_noprefix(table_data, s->capab_offset, 2);
2516 /* IOMMU base address */
2517 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2518 /* PCI Segment Group */
2519 build_append_int_noprefix(table_data, 0, 2);
2520 /* IOMMU info */
2521 build_append_int_noprefix(table_data, 0, 2);
2522 /* IOMMU Feature Reporting */
2523 build_append_int_noprefix(table_data,
2524 (48UL << 30) | /* HATS */
2525 (48UL << 28) | /* GATS */
2526 (1UL << 2), /* GTSup */
2527 4);
2528 /*
2529 * Type 1 device entry reporting all devices
2530 * These are 4-byte device entries currently reporting the range of
2531 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2532 */
2533 build_append_int_noprefix(table_data, 0x0000001, 4);
2534
2535 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2536 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2537 }
2538
2539 static GArray *
2540 build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset)
2541 {
2542 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2543 unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address);
2544 unsigned rsdt_pa_offset =
2545 (char *)&rsdp->rsdt_physical_address - rsdp_table->data;
2546
2547 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16,
2548 true /* fseg memory */);
2549
2550 memcpy(&rsdp->signature, "RSD PTR ", 8);
2551 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
2552 /* Address to be filled by Guest linker */
2553 bios_linker_loader_add_pointer(linker,
2554 ACPI_BUILD_RSDP_FILE, rsdt_pa_offset, rsdt_pa_size,
2555 ACPI_BUILD_TABLE_FILE, rsdt_tbl_offset);
2556
2557 /* Checksum to be filled by Guest linker */
2558 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
2559 (char *)rsdp - rsdp_table->data, sizeof *rsdp,
2560 (char *)&rsdp->checksum - rsdp_table->data);
2561
2562 return rsdp_table;
2563 }
2564
2565 typedef
2566 struct AcpiBuildState {
2567 /* Copy of table in RAM (for patching). */
2568 MemoryRegion *table_mr;
2569 /* Is table patched? */
2570 uint8_t patched;
2571 void *rsdp;
2572 MemoryRegion *rsdp_mr;
2573 MemoryRegion *linker_mr;
2574 } AcpiBuildState;
2575
2576 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2577 {
2578 Object *pci_host;
2579 QObject *o;
2580
2581 pci_host = acpi_get_i386_pci_host();
2582 g_assert(pci_host);
2583
2584 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2585 if (!o) {
2586 return false;
2587 }
2588 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
2589 qobject_decref(o);
2590
2591 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2592 assert(o);
2593 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
2594 qobject_decref(o);
2595 return true;
2596 }
2597
2598 static
2599 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2600 {
2601 PCMachineState *pcms = PC_MACHINE(machine);
2602 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2603 GArray *table_offsets;
2604 unsigned facs, dsdt, rsdt, fadt;
2605 AcpiPmInfo pm;
2606 AcpiMiscInfo misc;
2607 AcpiMcfgInfo mcfg;
2608 Range pci_hole, pci_hole64;
2609 uint8_t *u;
2610 size_t aml_len = 0;
2611 GArray *tables_blob = tables->table_data;
2612 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2613
2614 acpi_get_pm_info(&pm);
2615 acpi_get_misc_info(&misc);
2616 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2617 acpi_get_slic_oem(&slic_oem);
2618
2619 table_offsets = g_array_new(false, true /* clear */,
2620 sizeof(uint32_t));
2621 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2622
2623 bios_linker_loader_alloc(tables->linker,
2624 ACPI_BUILD_TABLE_FILE, tables_blob,
2625 64 /* Ensure FACS is aligned */,
2626 false /* high memory */);
2627
2628 /*
2629 * FACS is pointed to by FADT.
2630 * We place it first since it's the only table that has alignment
2631 * requirements.
2632 */
2633 facs = tables_blob->len;
2634 build_facs(tables_blob, tables->linker);
2635
2636 /* DSDT is pointed to by FADT */
2637 dsdt = tables_blob->len;
2638 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2639 &pci_hole, &pci_hole64, machine);
2640
2641 /* Count the size of the DSDT and SSDT, we will need it for legacy
2642 * sizing of ACPI tables.
2643 */
2644 aml_len += tables_blob->len - dsdt;
2645
2646 /* ACPI tables pointed to by RSDT */
2647 fadt = tables_blob->len;
2648 acpi_add_table(table_offsets, tables_blob);
2649 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt,
2650 slic_oem.id, slic_oem.table_id);
2651 aml_len += tables_blob->len - fadt;
2652
2653 acpi_add_table(table_offsets, tables_blob);
2654 build_madt(tables_blob, tables->linker, pcms);
2655
2656 if (misc.has_hpet) {
2657 acpi_add_table(table_offsets, tables_blob);
2658 build_hpet(tables_blob, tables->linker);
2659 }
2660 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2661 acpi_add_table(table_offsets, tables_blob);
2662 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2663
2664 if (misc.tpm_version == TPM_VERSION_2_0) {
2665 acpi_add_table(table_offsets, tables_blob);
2666 build_tpm2(tables_blob, tables->linker);
2667 }
2668 }
2669 if (pcms->numa_nodes) {
2670 acpi_add_table(table_offsets, tables_blob);
2671 build_srat(tables_blob, tables->linker, machine);
2672 }
2673 if (acpi_get_mcfg(&mcfg)) {
2674 acpi_add_table(table_offsets, tables_blob);
2675 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2676 }
2677 if (x86_iommu_get_default()) {
2678 IommuType IOMMUType = x86_iommu_get_type();
2679 if (IOMMUType == TYPE_AMD) {
2680 acpi_add_table(table_offsets, tables_blob);
2681 build_amd_iommu(tables_blob, tables->linker);
2682 } else if (IOMMUType == TYPE_INTEL) {
2683 acpi_add_table(table_offsets, tables_blob);
2684 build_dmar_q35(tables_blob, tables->linker);
2685 }
2686 }
2687 if (pcms->acpi_nvdimm_state.is_enabled) {
2688 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2689 &pcms->acpi_nvdimm_state, machine->ram_slots);
2690 }
2691
2692 /* Add tables supplied by user (if any) */
2693 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2694 unsigned len = acpi_table_len(u);
2695
2696 acpi_add_table(table_offsets, tables_blob);
2697 g_array_append_vals(tables_blob, u, len);
2698 }
2699
2700 /* RSDT is pointed to by RSDP */
2701 rsdt = tables_blob->len;
2702 build_rsdt(tables_blob, tables->linker, table_offsets,
2703 slic_oem.id, slic_oem.table_id);
2704
2705 /* RSDP is in FSEG memory, so allocate it separately */
2706 build_rsdp(tables->rsdp, tables->linker, rsdt);
2707
2708 /* We'll expose it all to Guest so we want to reduce
2709 * chance of size changes.
2710 *
2711 * We used to align the tables to 4k, but of course this would
2712 * too simple to be enough. 4k turned out to be too small an
2713 * alignment very soon, and in fact it is almost impossible to
2714 * keep the table size stable for all (max_cpus, max_memory_slots)
2715 * combinations. So the table size is always 64k for pc-i440fx-2.1
2716 * and we give an error if the table grows beyond that limit.
2717 *
2718 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2719 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2720 * than 2.0 and we can always pad the smaller tables with zeros. We can
2721 * then use the exact size of the 2.0 tables.
2722 *
2723 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2724 */
2725 if (pcmc->legacy_acpi_table_size) {
2726 /* Subtracting aml_len gives the size of fixed tables. Then add the
2727 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2728 */
2729 int legacy_aml_len =
2730 pcmc->legacy_acpi_table_size +
2731 ACPI_BUILD_LEGACY_CPU_AML_SIZE * pcms->apic_id_limit;
2732 int legacy_table_size =
2733 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2734 ACPI_BUILD_ALIGN_SIZE);
2735 if (tables_blob->len > legacy_table_size) {
2736 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2737 error_report("Warning: migration may not work.");
2738 }
2739 g_array_set_size(tables_blob, legacy_table_size);
2740 } else {
2741 /* Make sure we have a buffer in case we need to resize the tables. */
2742 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2743 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2744 error_report("Warning: ACPI tables are larger than 64k.");
2745 error_report("Warning: migration may not work.");
2746 error_report("Warning: please remove CPUs, NUMA nodes, "
2747 "memory slots or PCI bridges.");
2748 }
2749 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2750 }
2751
2752 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2753
2754 /* Cleanup memory that's no longer used. */
2755 g_array_free(table_offsets, true);
2756 }
2757
2758 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2759 {
2760 uint32_t size = acpi_data_len(data);
2761
2762 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2763 memory_region_ram_resize(mr, size, &error_abort);
2764
2765 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2766 memory_region_set_dirty(mr, 0, size);
2767 }
2768
2769 static void acpi_build_update(void *build_opaque)
2770 {
2771 AcpiBuildState *build_state = build_opaque;
2772 AcpiBuildTables tables;
2773
2774 /* No state to update or already patched? Nothing to do. */
2775 if (!build_state || build_state->patched) {
2776 return;
2777 }
2778 build_state->patched = 1;
2779
2780 acpi_build_tables_init(&tables);
2781
2782 acpi_build(&tables, MACHINE(qdev_get_machine()));
2783
2784 acpi_ram_update(build_state->table_mr, tables.table_data);
2785
2786 if (build_state->rsdp) {
2787 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2788 } else {
2789 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2790 }
2791
2792 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2793 acpi_build_tables_cleanup(&tables, true);
2794 }
2795
2796 static void acpi_build_reset(void *build_opaque)
2797 {
2798 AcpiBuildState *build_state = build_opaque;
2799 build_state->patched = 0;
2800 }
2801
2802 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2803 GArray *blob, const char *name,
2804 uint64_t max_size)
2805 {
2806 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2807 name, acpi_build_update, build_state, NULL, true);
2808 }
2809
2810 static const VMStateDescription vmstate_acpi_build = {
2811 .name = "acpi_build",
2812 .version_id = 1,
2813 .minimum_version_id = 1,
2814 .fields = (VMStateField[]) {
2815 VMSTATE_UINT8(patched, AcpiBuildState),
2816 VMSTATE_END_OF_LIST()
2817 },
2818 };
2819
2820 void acpi_setup(void)
2821 {
2822 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2823 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2824 AcpiBuildTables tables;
2825 AcpiBuildState *build_state;
2826
2827 if (!pcms->fw_cfg) {
2828 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2829 return;
2830 }
2831
2832 if (!pcms->acpi_build_enabled) {
2833 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2834 return;
2835 }
2836
2837 if (!acpi_enabled) {
2838 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2839 return;
2840 }
2841
2842 build_state = g_malloc0(sizeof *build_state);
2843
2844 acpi_set_pci_info();
2845
2846 acpi_build_tables_init(&tables);
2847 acpi_build(&tables, MACHINE(pcms));
2848
2849 /* Now expose it all to Guest */
2850 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
2851 ACPI_BUILD_TABLE_FILE,
2852 ACPI_BUILD_TABLE_MAX_SIZE);
2853 assert(build_state->table_mr != NULL);
2854
2855 build_state->linker_mr =
2856 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
2857 "etc/table-loader", 0);
2858
2859 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2860 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2861
2862 if (!pcmc->rsdp_in_ram) {
2863 /*
2864 * Keep for compatibility with old machine types.
2865 * Though RSDP is small, its contents isn't immutable, so
2866 * we'll update it along with the rest of tables on guest access.
2867 */
2868 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2869
2870 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2871 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2872 acpi_build_update, build_state,
2873 build_state->rsdp, rsdp_size, true);
2874 build_state->rsdp_mr = NULL;
2875 } else {
2876 build_state->rsdp = NULL;
2877 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
2878 ACPI_BUILD_RSDP_FILE, 0);
2879 }
2880
2881 qemu_register_reset(acpi_build_reset, build_state);
2882 acpi_build_reset(build_state);
2883 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2884
2885 /* Cleanup tables but don't free the memory: we track it
2886 * in build_state.
2887 */
2888 acpi_build_tables_cleanup(&tables, false);
2889 }
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