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i386:acpi: Remove _HID from the SMBus ACPI entry
[mirror_qemu.git] / hw / i386 / acpi-build.c
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
30 #include "hw/core/cpu.h"
31 #include "target/i386/cpu.h"
32 #include "hw/misc/pvpanic.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/acpi/cpu.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/isa/isa.h"
40 #include "hw/block/fdc.h"
41 #include "hw/acpi/memory_hotplug.h"
42 #include "sysemu/tpm.h"
43 #include "hw/acpi/tpm.h"
44 #include "hw/acpi/vmgenid.h"
45 #include "hw/boards.h"
46 #include "sysemu/tpm_backend.h"
47 #include "hw/rtc/mc146818rtc_regs.h"
48 #include "migration/vmstate.h"
49 #include "hw/mem/memory-device.h"
50 #include "sysemu/numa.h"
51 #include "sysemu/reset.h"
52
53 /* Supported chipsets: */
54 #include "hw/southbridge/piix.h"
55 #include "hw/acpi/pcihp.h"
56 #include "hw/i386/fw_cfg.h"
57 #include "hw/i386/ich9.h"
58 #include "hw/pci/pci_bus.h"
59 #include "hw/pci-host/q35.h"
60 #include "hw/i386/x86-iommu.h"
61
62 #include "hw/acpi/aml-build.h"
63 #include "hw/acpi/utils.h"
64 #include "hw/acpi/pci.h"
65
66 #include "qom/qom-qobject.h"
67 #include "hw/i386/amd_iommu.h"
68 #include "hw/i386/intel_iommu.h"
69
70 #include "hw/acpi/ipmi.h"
71 #include "hw/acpi/hmat.h"
72
73 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
74 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
75 * a little bit, there should be plenty of free space since the DSDT
76 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
77 */
78 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
79 #define ACPI_BUILD_ALIGN_SIZE 0x1000
80
81 #define ACPI_BUILD_TABLE_SIZE 0x20000
82
83 /* #define DEBUG_ACPI_BUILD */
84 #ifdef DEBUG_ACPI_BUILD
85 #define ACPI_BUILD_DPRINTF(fmt, ...) \
86 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
87 #else
88 #define ACPI_BUILD_DPRINTF(fmt, ...)
89 #endif
90
91 /* Default IOAPIC ID */
92 #define ACPI_BUILD_IOAPIC_ID 0x0
93
94 typedef struct AcpiPmInfo {
95 bool s3_disabled;
96 bool s4_disabled;
97 bool pcihp_bridge_en;
98 uint8_t s4_val;
99 AcpiFadtData fadt;
100 uint16_t cpu_hp_io_base;
101 uint16_t pcihp_io_base;
102 uint16_t pcihp_io_len;
103 } AcpiPmInfo;
104
105 typedef struct AcpiMiscInfo {
106 bool is_piix4;
107 bool has_hpet;
108 TPMVersion tpm_version;
109 const unsigned char *dsdt_code;
110 unsigned dsdt_size;
111 uint16_t pvpanic_port;
112 uint16_t applesmc_io_base;
113 } AcpiMiscInfo;
114
115 typedef struct AcpiBuildPciBusHotplugState {
116 GArray *device_table;
117 GArray *notify_table;
118 struct AcpiBuildPciBusHotplugState *parent;
119 bool pcihp_bridge_en;
120 } AcpiBuildPciBusHotplugState;
121
122 typedef struct FwCfgTPMConfig {
123 uint32_t tpmppi_address;
124 uint8_t tpm_version;
125 uint8_t tpmppi_version;
126 } QEMU_PACKED FwCfgTPMConfig;
127
128 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
129
130 static void init_common_fadt_data(MachineState *ms, Object *o,
131 AcpiFadtData *data)
132 {
133 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
134 AmlAddressSpace as = AML_AS_SYSTEM_IO;
135 AcpiFadtData fadt = {
136 .rev = 3,
137 .flags =
138 (1 << ACPI_FADT_F_WBINVD) |
139 (1 << ACPI_FADT_F_PROC_C1) |
140 (1 << ACPI_FADT_F_SLP_BUTTON) |
141 (1 << ACPI_FADT_F_RTC_S4) |
142 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
143 /* APIC destination mode ("Flat Logical") has an upper limit of 8
144 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
145 * used
146 */
147 ((ms->smp.max_cpus > 8) ?
148 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
149 .int_model = 1 /* Multiple APIC */,
150 .rtc_century = RTC_CENTURY,
151 .plvl2_lat = 0xfff /* C2 state not supported */,
152 .plvl3_lat = 0xfff /* C3 state not supported */,
153 .smi_cmd = ACPI_PORT_SMI_CMD,
154 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
155 .acpi_enable_cmd =
156 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL),
157 .acpi_disable_cmd =
158 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL),
159 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
160 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
161 .address = io + 0x04 },
162 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
163 .gpe0_blk = { .space_id = as, .bit_width =
164 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
165 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
166 },
167 };
168 *data = fadt;
169 }
170
171 static Object *object_resolve_type_unambiguous(const char *typename)
172 {
173 bool ambig;
174 Object *o = object_resolve_path_type("", typename, &ambig);
175
176 if (ambig || !o) {
177 return NULL;
178 }
179 return o;
180 }
181
182 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
183 {
184 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
185 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
186 Object *obj = piix ? piix : lpc;
187 QObject *o;
188 pm->cpu_hp_io_base = 0;
189 pm->pcihp_io_base = 0;
190 pm->pcihp_io_len = 0;
191
192 assert(obj);
193 init_common_fadt_data(machine, obj, &pm->fadt);
194 if (piix) {
195 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
196 pm->fadt.rev = 1;
197 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
198 pm->pcihp_io_base =
199 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
200 pm->pcihp_io_len =
201 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
202 }
203 if (lpc) {
204 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
205 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
206 pm->fadt.reset_reg = r;
207 pm->fadt.reset_val = 0xf;
208 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
209 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
210 }
211
212 /* The above need not be conditional on machine type because the reset port
213 * happens to be the same on PIIX (pc) and ICH9 (q35). */
214 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);
215
216 /* Fill in optional s3/s4 related properties */
217 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
218 if (o) {
219 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
220 } else {
221 pm->s3_disabled = false;
222 }
223 qobject_unref(o);
224 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
225 if (o) {
226 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
227 } else {
228 pm->s4_disabled = false;
229 }
230 qobject_unref(o);
231 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
232 if (o) {
233 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
234 } else {
235 pm->s4_val = false;
236 }
237 qobject_unref(o);
238
239 pm->pcihp_bridge_en =
240 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
241 NULL);
242 }
243
244 static void acpi_get_misc_info(AcpiMiscInfo *info)
245 {
246 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
247 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
248 assert(!!piix != !!lpc);
249
250 if (piix) {
251 info->is_piix4 = true;
252 }
253 if (lpc) {
254 info->is_piix4 = false;
255 }
256
257 info->has_hpet = hpet_find();
258 info->tpm_version = tpm_get_version(tpm_find());
259 info->pvpanic_port = pvpanic_port();
260 info->applesmc_io_base = applesmc_port();
261 }
262
263 /*
264 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
265 * On i386 arch we only have two pci hosts, so we can look only for them.
266 */
267 static Object *acpi_get_i386_pci_host(void)
268 {
269 PCIHostState *host;
270
271 host = OBJECT_CHECK(PCIHostState,
272 object_resolve_path("/machine/i440fx", NULL),
273 TYPE_PCI_HOST_BRIDGE);
274 if (!host) {
275 host = OBJECT_CHECK(PCIHostState,
276 object_resolve_path("/machine/q35", NULL),
277 TYPE_PCI_HOST_BRIDGE);
278 }
279
280 return OBJECT(host);
281 }
282
283 static void acpi_get_pci_holes(Range *hole, Range *hole64)
284 {
285 Object *pci_host;
286
287 pci_host = acpi_get_i386_pci_host();
288 g_assert(pci_host);
289
290 range_set_bounds1(hole,
291 object_property_get_uint(pci_host,
292 PCI_HOST_PROP_PCI_HOLE_START,
293 NULL),
294 object_property_get_uint(pci_host,
295 PCI_HOST_PROP_PCI_HOLE_END,
296 NULL));
297 range_set_bounds1(hole64,
298 object_property_get_uint(pci_host,
299 PCI_HOST_PROP_PCI_HOLE64_START,
300 NULL),
301 object_property_get_uint(pci_host,
302 PCI_HOST_PROP_PCI_HOLE64_END,
303 NULL));
304 }
305
306 static void acpi_align_size(GArray *blob, unsigned align)
307 {
308 /* Align size to multiple of given size. This reduces the chance
309 * we need to change size in the future (breaking cross version migration).
310 */
311 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
312 }
313
314 /* FACS */
315 static void
316 build_facs(GArray *table_data)
317 {
318 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
319 memcpy(&facs->signature, "FACS", 4);
320 facs->length = cpu_to_le32(sizeof(*facs));
321 }
322
323 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
324 const CPUArchIdList *apic_ids, GArray *entry)
325 {
326 uint32_t apic_id = apic_ids->cpus[uid].arch_id;
327
328 /* ACPI spec says that LAPIC entry for non present
329 * CPU may be omitted from MADT or it must be marked
330 * as disabled. However omitting non present CPU from
331 * MADT breaks hotplug on linux. So possible CPUs
332 * should be put in MADT but kept disabled.
333 */
334 if (apic_id < 255) {
335 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
336
337 apic->type = ACPI_APIC_PROCESSOR;
338 apic->length = sizeof(*apic);
339 apic->processor_id = uid;
340 apic->local_apic_id = apic_id;
341 if (apic_ids->cpus[uid].cpu != NULL) {
342 apic->flags = cpu_to_le32(1);
343 } else {
344 apic->flags = cpu_to_le32(0);
345 }
346 } else {
347 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic);
348
349 apic->type = ACPI_APIC_LOCAL_X2APIC;
350 apic->length = sizeof(*apic);
351 apic->uid = cpu_to_le32(uid);
352 apic->x2apic_id = cpu_to_le32(apic_id);
353 if (apic_ids->cpus[uid].cpu != NULL) {
354 apic->flags = cpu_to_le32(1);
355 } else {
356 apic->flags = cpu_to_le32(0);
357 }
358 }
359 }
360
361 static void
362 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
363 {
364 MachineClass *mc = MACHINE_GET_CLASS(pcms);
365 X86MachineState *x86ms = X86_MACHINE(pcms);
366 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
367 int madt_start = table_data->len;
368 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
369 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
370 bool x2apic_mode = false;
371
372 AcpiMultipleApicTable *madt;
373 AcpiMadtIoApic *io_apic;
374 AcpiMadtIntsrcovr *intsrcovr;
375 int i;
376
377 madt = acpi_data_push(table_data, sizeof *madt);
378 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
379 madt->flags = cpu_to_le32(1);
380
381 for (i = 0; i < apic_ids->len; i++) {
382 adevc->madt_cpu(adev, i, apic_ids, table_data);
383 if (apic_ids->cpus[i].arch_id > 254) {
384 x2apic_mode = true;
385 }
386 }
387
388 io_apic = acpi_data_push(table_data, sizeof *io_apic);
389 io_apic->type = ACPI_APIC_IO;
390 io_apic->length = sizeof(*io_apic);
391 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
392 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
393 io_apic->interrupt = cpu_to_le32(0);
394
395 if (x86ms->apic_xrupt_override) {
396 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
397 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
398 intsrcovr->length = sizeof(*intsrcovr);
399 intsrcovr->source = 0;
400 intsrcovr->gsi = cpu_to_le32(2);
401 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
402 }
403 for (i = 1; i < 16; i++) {
404 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
405 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
406 /* No need for a INT source override structure. */
407 continue;
408 }
409 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
410 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
411 intsrcovr->length = sizeof(*intsrcovr);
412 intsrcovr->source = i;
413 intsrcovr->gsi = cpu_to_le32(i);
414 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
415 }
416
417 if (x2apic_mode) {
418 AcpiMadtLocalX2ApicNmi *local_nmi;
419
420 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
421 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI;
422 local_nmi->length = sizeof(*local_nmi);
423 local_nmi->uid = 0xFFFFFFFF; /* all processors */
424 local_nmi->flags = cpu_to_le16(0);
425 local_nmi->lint = 1; /* ACPI_LINT1 */
426 } else {
427 AcpiMadtLocalNmi *local_nmi;
428
429 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
430 local_nmi->type = ACPI_APIC_LOCAL_NMI;
431 local_nmi->length = sizeof(*local_nmi);
432 local_nmi->processor_id = 0xff; /* all processors */
433 local_nmi->flags = cpu_to_le16(0);
434 local_nmi->lint = 1; /* ACPI_LINT1 */
435 }
436
437 build_header(linker, table_data,
438 (void *)(table_data->data + madt_start), "APIC",
439 table_data->len - madt_start, 1, NULL, NULL);
440 }
441
442 static void build_append_pcihp_notify_entry(Aml *method, int slot)
443 {
444 Aml *if_ctx;
445 int32_t devfn = PCI_DEVFN(slot, 0);
446
447 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
448 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
449 aml_append(method, if_ctx);
450 }
451
452 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
453 bool pcihp_bridge_en)
454 {
455 Aml *dev, *notify_method = NULL, *method;
456 QObject *bsel;
457 PCIBus *sec;
458 int i;
459
460 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
461 if (bsel) {
462 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
463
464 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
465 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
466 }
467
468 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
469 DeviceClass *dc;
470 PCIDeviceClass *pc;
471 PCIDevice *pdev = bus->devices[i];
472 int slot = PCI_SLOT(i);
473 bool hotplug_enabled_dev;
474 bool bridge_in_acpi;
475
476 if (!pdev) {
477 if (bsel) { /* add hotplug slots for non present devices */
478 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
479 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
480 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
481 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
482 aml_append(method,
483 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
484 );
485 aml_append(dev, method);
486 aml_append(parent_scope, dev);
487
488 build_append_pcihp_notify_entry(notify_method, slot);
489 }
490 continue;
491 }
492
493 pc = PCI_DEVICE_GET_CLASS(pdev);
494 dc = DEVICE_GET_CLASS(pdev);
495
496 /* When hotplug for bridges is enabled, bridges are
497 * described in ACPI separately (see build_pci_bus_end).
498 * In this case they aren't themselves hot-pluggable.
499 * Hotplugged bridges *are* hot-pluggable.
500 */
501 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
502 !DEVICE(pdev)->hotplugged;
503
504 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
505
506 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
507 continue;
508 }
509
510 /* start to compose PCI slot descriptor */
511 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
512 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
513
514 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
515 /* add VGA specific AML methods */
516 int s3d;
517
518 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
519 s3d = 3;
520 } else {
521 s3d = 0;
522 }
523
524 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
525 aml_append(method, aml_return(aml_int(0)));
526 aml_append(dev, method);
527
528 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
529 aml_append(method, aml_return(aml_int(0)));
530 aml_append(dev, method);
531
532 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
533 aml_append(method, aml_return(aml_int(s3d)));
534 aml_append(dev, method);
535 } else if (hotplug_enabled_dev) {
536 /* add _SUN/_EJ0 to make slot hotpluggable */
537 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
538
539 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
540 aml_append(method,
541 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
542 );
543 aml_append(dev, method);
544
545 if (bsel) {
546 build_append_pcihp_notify_entry(notify_method, slot);
547 }
548 } else if (bridge_in_acpi) {
549 /*
550 * device is coldplugged bridge,
551 * add child device descriptions into its scope
552 */
553 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
554
555 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
556 }
557 /* slot descriptor has been composed, add it into parent context */
558 aml_append(parent_scope, dev);
559 }
560
561 if (bsel) {
562 aml_append(parent_scope, notify_method);
563 }
564
565 /* Append PCNT method to notify about events on local and child buses.
566 * Add unconditionally for root since DSDT expects it.
567 */
568 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
569
570 /* If bus supports hotplug select it and notify about local events */
571 if (bsel) {
572 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
573
574 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
575 aml_append(method,
576 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
577 );
578 aml_append(method,
579 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
580 );
581 }
582
583 /* Notify about child bus events in any case */
584 if (pcihp_bridge_en) {
585 QLIST_FOREACH(sec, &bus->child, sibling) {
586 int32_t devfn = sec->parent_dev->devfn;
587
588 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
589 continue;
590 }
591
592 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
593 }
594 }
595 aml_append(parent_scope, method);
596 qobject_unref(bsel);
597 }
598
599 /**
600 * build_prt_entry:
601 * @link_name: link name for PCI route entry
602 *
603 * build AML package containing a PCI route entry for @link_name
604 */
605 static Aml *build_prt_entry(const char *link_name)
606 {
607 Aml *a_zero = aml_int(0);
608 Aml *pkg = aml_package(4);
609 aml_append(pkg, a_zero);
610 aml_append(pkg, a_zero);
611 aml_append(pkg, aml_name("%s", link_name));
612 aml_append(pkg, a_zero);
613 return pkg;
614 }
615
616 /*
617 * initialize_route - Initialize the interrupt routing rule
618 * through a specific LINK:
619 * if (lnk_idx == idx)
620 * route using link 'link_name'
621 */
622 static Aml *initialize_route(Aml *route, const char *link_name,
623 Aml *lnk_idx, int idx)
624 {
625 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
626 Aml *pkg = build_prt_entry(link_name);
627
628 aml_append(if_ctx, aml_store(pkg, route));
629
630 return if_ctx;
631 }
632
633 /*
634 * build_prt - Define interrupt rounting rules
635 *
636 * Returns an array of 128 routes, one for each device,
637 * based on device location.
638 * The main goal is to equaly distribute the interrupts
639 * over the 4 existing ACPI links (works only for i440fx).
640 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
641 *
642 */
643 static Aml *build_prt(bool is_pci0_prt)
644 {
645 Aml *method, *while_ctx, *pin, *res;
646
647 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
648 res = aml_local(0);
649 pin = aml_local(1);
650 aml_append(method, aml_store(aml_package(128), res));
651 aml_append(method, aml_store(aml_int(0), pin));
652
653 /* while (pin < 128) */
654 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
655 {
656 Aml *slot = aml_local(2);
657 Aml *lnk_idx = aml_local(3);
658 Aml *route = aml_local(4);
659
660 /* slot = pin >> 2 */
661 aml_append(while_ctx,
662 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
663 /* lnk_idx = (slot + pin) & 3 */
664 aml_append(while_ctx,
665 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
666 lnk_idx));
667
668 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
669 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
670 if (is_pci0_prt) {
671 Aml *if_device_1, *if_pin_4, *else_pin_4;
672
673 /* device 1 is the power-management device, needs SCI */
674 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
675 {
676 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
677 {
678 aml_append(if_pin_4,
679 aml_store(build_prt_entry("LNKS"), route));
680 }
681 aml_append(if_device_1, if_pin_4);
682 else_pin_4 = aml_else();
683 {
684 aml_append(else_pin_4,
685 aml_store(build_prt_entry("LNKA"), route));
686 }
687 aml_append(if_device_1, else_pin_4);
688 }
689 aml_append(while_ctx, if_device_1);
690 } else {
691 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
692 }
693 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
694 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
695
696 /* route[0] = 0x[slot]FFFF */
697 aml_append(while_ctx,
698 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
699 NULL),
700 aml_index(route, aml_int(0))));
701 /* route[1] = pin & 3 */
702 aml_append(while_ctx,
703 aml_store(aml_and(pin, aml_int(3), NULL),
704 aml_index(route, aml_int(1))));
705 /* res[pin] = route */
706 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
707 /* pin++ */
708 aml_append(while_ctx, aml_increment(pin));
709 }
710 aml_append(method, while_ctx);
711 /* return res*/
712 aml_append(method, aml_return(res));
713
714 return method;
715 }
716
717 typedef struct CrsRangeEntry {
718 uint64_t base;
719 uint64_t limit;
720 } CrsRangeEntry;
721
722 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
723 {
724 CrsRangeEntry *entry;
725
726 entry = g_malloc(sizeof(*entry));
727 entry->base = base;
728 entry->limit = limit;
729
730 g_ptr_array_add(ranges, entry);
731 }
732
733 static void crs_range_free(gpointer data)
734 {
735 CrsRangeEntry *entry = (CrsRangeEntry *)data;
736 g_free(entry);
737 }
738
739 typedef struct CrsRangeSet {
740 GPtrArray *io_ranges;
741 GPtrArray *mem_ranges;
742 GPtrArray *mem_64bit_ranges;
743 } CrsRangeSet;
744
745 static void crs_range_set_init(CrsRangeSet *range_set)
746 {
747 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
748 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
749 range_set->mem_64bit_ranges =
750 g_ptr_array_new_with_free_func(crs_range_free);
751 }
752
753 static void crs_range_set_free(CrsRangeSet *range_set)
754 {
755 g_ptr_array_free(range_set->io_ranges, true);
756 g_ptr_array_free(range_set->mem_ranges, true);
757 g_ptr_array_free(range_set->mem_64bit_ranges, true);
758 }
759
760 static gint crs_range_compare(gconstpointer a, gconstpointer b)
761 {
762 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
763 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
764
765 if (entry_a->base < entry_b->base) {
766 return -1;
767 } else if (entry_a->base > entry_b->base) {
768 return 1;
769 } else {
770 return 0;
771 }
772 }
773
774 /*
775 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
776 * interval, computes the 'free' ranges from the same interval.
777 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
778 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
779 */
780 static void crs_replace_with_free_ranges(GPtrArray *ranges,
781 uint64_t start, uint64_t end)
782 {
783 GPtrArray *free_ranges = g_ptr_array_new();
784 uint64_t free_base = start;
785 int i;
786
787 g_ptr_array_sort(ranges, crs_range_compare);
788 for (i = 0; i < ranges->len; i++) {
789 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
790
791 if (free_base < used->base) {
792 crs_range_insert(free_ranges, free_base, used->base - 1);
793 }
794
795 free_base = used->limit + 1;
796 }
797
798 if (free_base < end) {
799 crs_range_insert(free_ranges, free_base, end);
800 }
801
802 g_ptr_array_set_size(ranges, 0);
803 for (i = 0; i < free_ranges->len; i++) {
804 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
805 }
806
807 g_ptr_array_free(free_ranges, true);
808 }
809
810 /*
811 * crs_range_merge - merges adjacent ranges in the given array.
812 * Array elements are deleted and replaced with the merged ranges.
813 */
814 static void crs_range_merge(GPtrArray *range)
815 {
816 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
817 CrsRangeEntry *entry;
818 uint64_t range_base, range_limit;
819 int i;
820
821 if (!range->len) {
822 return;
823 }
824
825 g_ptr_array_sort(range, crs_range_compare);
826
827 entry = g_ptr_array_index(range, 0);
828 range_base = entry->base;
829 range_limit = entry->limit;
830 for (i = 1; i < range->len; i++) {
831 entry = g_ptr_array_index(range, i);
832 if (entry->base - 1 == range_limit) {
833 range_limit = entry->limit;
834 } else {
835 crs_range_insert(tmp, range_base, range_limit);
836 range_base = entry->base;
837 range_limit = entry->limit;
838 }
839 }
840 crs_range_insert(tmp, range_base, range_limit);
841
842 g_ptr_array_set_size(range, 0);
843 for (i = 0; i < tmp->len; i++) {
844 entry = g_ptr_array_index(tmp, i);
845 crs_range_insert(range, entry->base, entry->limit);
846 }
847 g_ptr_array_free(tmp, true);
848 }
849
850 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
851 {
852 Aml *crs = aml_resource_template();
853 CrsRangeSet temp_range_set;
854 CrsRangeEntry *entry;
855 uint8_t max_bus = pci_bus_num(host->bus);
856 uint8_t type;
857 int devfn;
858 int i;
859
860 crs_range_set_init(&temp_range_set);
861 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
862 uint64_t range_base, range_limit;
863 PCIDevice *dev = host->bus->devices[devfn];
864
865 if (!dev) {
866 continue;
867 }
868
869 for (i = 0; i < PCI_NUM_REGIONS; i++) {
870 PCIIORegion *r = &dev->io_regions[i];
871
872 range_base = r->addr;
873 range_limit = r->addr + r->size - 1;
874
875 /*
876 * Work-around for old bioses
877 * that do not support multiple root buses
878 */
879 if (!range_base || range_base > range_limit) {
880 continue;
881 }
882
883 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
884 crs_range_insert(temp_range_set.io_ranges,
885 range_base, range_limit);
886 } else { /* "memory" */
887 crs_range_insert(temp_range_set.mem_ranges,
888 range_base, range_limit);
889 }
890 }
891
892 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
893 if (type == PCI_HEADER_TYPE_BRIDGE) {
894 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
895 if (subordinate > max_bus) {
896 max_bus = subordinate;
897 }
898
899 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
900 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
901
902 /*
903 * Work-around for old bioses
904 * that do not support multiple root buses
905 */
906 if (range_base && range_base <= range_limit) {
907 crs_range_insert(temp_range_set.io_ranges,
908 range_base, range_limit);
909 }
910
911 range_base =
912 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
913 range_limit =
914 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
915
916 /*
917 * Work-around for old bioses
918 * that do not support multiple root buses
919 */
920 if (range_base && range_base <= range_limit) {
921 uint64_t length = range_limit - range_base + 1;
922 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
923 crs_range_insert(temp_range_set.mem_ranges,
924 range_base, range_limit);
925 } else {
926 crs_range_insert(temp_range_set.mem_64bit_ranges,
927 range_base, range_limit);
928 }
929 }
930
931 range_base =
932 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
933 range_limit =
934 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
935
936 /*
937 * Work-around for old bioses
938 * that do not support multiple root buses
939 */
940 if (range_base && range_base <= range_limit) {
941 uint64_t length = range_limit - range_base + 1;
942 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
943 crs_range_insert(temp_range_set.mem_ranges,
944 range_base, range_limit);
945 } else {
946 crs_range_insert(temp_range_set.mem_64bit_ranges,
947 range_base, range_limit);
948 }
949 }
950 }
951 }
952
953 crs_range_merge(temp_range_set.io_ranges);
954 for (i = 0; i < temp_range_set.io_ranges->len; i++) {
955 entry = g_ptr_array_index(temp_range_set.io_ranges, i);
956 aml_append(crs,
957 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
958 AML_POS_DECODE, AML_ENTIRE_RANGE,
959 0, entry->base, entry->limit, 0,
960 entry->limit - entry->base + 1));
961 crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
962 }
963
964 crs_range_merge(temp_range_set.mem_ranges);
965 for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
966 entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
967 aml_append(crs,
968 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
969 AML_MAX_FIXED, AML_NON_CACHEABLE,
970 AML_READ_WRITE,
971 0, entry->base, entry->limit, 0,
972 entry->limit - entry->base + 1));
973 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
974 }
975
976 crs_range_merge(temp_range_set.mem_64bit_ranges);
977 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
978 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
979 aml_append(crs,
980 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
981 AML_MAX_FIXED, AML_NON_CACHEABLE,
982 AML_READ_WRITE,
983 0, entry->base, entry->limit, 0,
984 entry->limit - entry->base + 1));
985 crs_range_insert(range_set->mem_64bit_ranges,
986 entry->base, entry->limit);
987 }
988
989 crs_range_set_free(&temp_range_set);
990
991 aml_append(crs,
992 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
993 0,
994 pci_bus_num(host->bus),
995 max_bus,
996 0,
997 max_bus - pci_bus_num(host->bus) + 1));
998
999 return crs;
1000 }
1001
1002 static void build_hpet_aml(Aml *table)
1003 {
1004 Aml *crs;
1005 Aml *field;
1006 Aml *method;
1007 Aml *if_ctx;
1008 Aml *scope = aml_scope("_SB");
1009 Aml *dev = aml_device("HPET");
1010 Aml *zero = aml_int(0);
1011 Aml *id = aml_local(0);
1012 Aml *period = aml_local(1);
1013
1014 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1015 aml_append(dev, aml_name_decl("_UID", zero));
1016
1017 aml_append(dev,
1018 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1019 HPET_LEN));
1020 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1021 aml_append(field, aml_named_field("VEND", 32));
1022 aml_append(field, aml_named_field("PRD", 32));
1023 aml_append(dev, field);
1024
1025 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1026 aml_append(method, aml_store(aml_name("VEND"), id));
1027 aml_append(method, aml_store(aml_name("PRD"), period));
1028 aml_append(method, aml_shiftright(id, aml_int(16), id));
1029 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1030 aml_equal(id, aml_int(0xffff))));
1031 {
1032 aml_append(if_ctx, aml_return(zero));
1033 }
1034 aml_append(method, if_ctx);
1035
1036 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1037 aml_lgreater(period, aml_int(100000000))));
1038 {
1039 aml_append(if_ctx, aml_return(zero));
1040 }
1041 aml_append(method, if_ctx);
1042
1043 aml_append(method, aml_return(aml_int(0x0F)));
1044 aml_append(dev, method);
1045
1046 crs = aml_resource_template();
1047 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1048 aml_append(dev, aml_name_decl("_CRS", crs));
1049
1050 aml_append(scope, dev);
1051 aml_append(table, scope);
1052 }
1053
1054 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
1055 {
1056 Aml *dev, *fdi;
1057 uint8_t maxc, maxh, maxs;
1058
1059 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1060
1061 dev = aml_device("FLP%c", 'A' + idx);
1062
1063 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1064
1065 fdi = aml_package(16);
1066 aml_append(fdi, aml_int(idx)); /* Drive Number */
1067 aml_append(fdi,
1068 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1069 /*
1070 * the values below are the limits of the drive, and are thus independent
1071 * of the inserted media
1072 */
1073 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1074 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1075 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1076 /*
1077 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1078 * the drive type, so shall we
1079 */
1080 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1081 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1082 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1083 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1084 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1085 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1086 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1087 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1088 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1089 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1090 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1091
1092 aml_append(dev, aml_name_decl("_FDI", fdi));
1093 return dev;
1094 }
1095
1096 static Aml *build_fdc_device_aml(ISADevice *fdc)
1097 {
1098 int i;
1099 Aml *dev;
1100 Aml *crs;
1101
1102 #define ACPI_FDE_MAX_FD 4
1103 uint32_t fde_buf[5] = {
1104 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1105 cpu_to_le32(2) /* tape presence (2 == never present) */
1106 };
1107
1108 dev = aml_device("FDC0");
1109 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1110
1111 crs = aml_resource_template();
1112 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1113 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1114 aml_append(crs, aml_irq_no_flags(6));
1115 aml_append(crs,
1116 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1117 aml_append(dev, aml_name_decl("_CRS", crs));
1118
1119 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1120 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1121
1122 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1123 fde_buf[i] = cpu_to_le32(1); /* drive present */
1124 aml_append(dev, build_fdinfo_aml(i, type));
1125 }
1126 }
1127 aml_append(dev, aml_name_decl("_FDE",
1128 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1129
1130 return dev;
1131 }
1132
1133 static Aml *build_rtc_device_aml(void)
1134 {
1135 Aml *dev;
1136 Aml *crs;
1137
1138 dev = aml_device("RTC");
1139 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1140 crs = aml_resource_template();
1141 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1142 aml_append(crs, aml_irq_no_flags(8));
1143 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1144 aml_append(dev, aml_name_decl("_CRS", crs));
1145
1146 return dev;
1147 }
1148
1149 static Aml *build_kbd_device_aml(void)
1150 {
1151 Aml *dev;
1152 Aml *crs;
1153 Aml *method;
1154
1155 dev = aml_device("KBD");
1156 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1157
1158 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1159 aml_append(method, aml_return(aml_int(0x0f)));
1160 aml_append(dev, method);
1161
1162 crs = aml_resource_template();
1163 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1164 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1165 aml_append(crs, aml_irq_no_flags(1));
1166 aml_append(dev, aml_name_decl("_CRS", crs));
1167
1168 return dev;
1169 }
1170
1171 static Aml *build_mouse_device_aml(void)
1172 {
1173 Aml *dev;
1174 Aml *crs;
1175 Aml *method;
1176
1177 dev = aml_device("MOU");
1178 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1179
1180 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1181 aml_append(method, aml_return(aml_int(0x0f)));
1182 aml_append(dev, method);
1183
1184 crs = aml_resource_template();
1185 aml_append(crs, aml_irq_no_flags(12));
1186 aml_append(dev, aml_name_decl("_CRS", crs));
1187
1188 return dev;
1189 }
1190
1191 static Aml *build_lpt_device_aml(void)
1192 {
1193 Aml *dev;
1194 Aml *crs;
1195 Aml *method;
1196 Aml *if_ctx;
1197 Aml *else_ctx;
1198 Aml *zero = aml_int(0);
1199 Aml *is_present = aml_local(0);
1200
1201 dev = aml_device("LPT");
1202 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1203
1204 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1205 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1206 if_ctx = aml_if(aml_equal(is_present, zero));
1207 {
1208 aml_append(if_ctx, aml_return(aml_int(0x00)));
1209 }
1210 aml_append(method, if_ctx);
1211 else_ctx = aml_else();
1212 {
1213 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1214 }
1215 aml_append(method, else_ctx);
1216 aml_append(dev, method);
1217
1218 crs = aml_resource_template();
1219 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1220 aml_append(crs, aml_irq_no_flags(7));
1221 aml_append(dev, aml_name_decl("_CRS", crs));
1222
1223 return dev;
1224 }
1225
1226 static Aml *build_com_device_aml(uint8_t uid)
1227 {
1228 Aml *dev;
1229 Aml *crs;
1230 Aml *method;
1231 Aml *if_ctx;
1232 Aml *else_ctx;
1233 Aml *zero = aml_int(0);
1234 Aml *is_present = aml_local(0);
1235 const char *enabled_field = "CAEN";
1236 uint8_t irq = 4;
1237 uint16_t io_port = 0x03F8;
1238
1239 assert(uid == 1 || uid == 2);
1240 if (uid == 2) {
1241 enabled_field = "CBEN";
1242 irq = 3;
1243 io_port = 0x02F8;
1244 }
1245
1246 dev = aml_device("COM%d", uid);
1247 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1248 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1249
1250 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1251 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1252 if_ctx = aml_if(aml_equal(is_present, zero));
1253 {
1254 aml_append(if_ctx, aml_return(aml_int(0x00)));
1255 }
1256 aml_append(method, if_ctx);
1257 else_ctx = aml_else();
1258 {
1259 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1260 }
1261 aml_append(method, else_ctx);
1262 aml_append(dev, method);
1263
1264 crs = aml_resource_template();
1265 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1266 aml_append(crs, aml_irq_no_flags(irq));
1267 aml_append(dev, aml_name_decl("_CRS", crs));
1268
1269 return dev;
1270 }
1271
1272 static void build_isa_devices_aml(Aml *table)
1273 {
1274 ISADevice *fdc = pc_find_fdc0();
1275 bool ambiguous;
1276
1277 Aml *scope = aml_scope("_SB.PCI0.ISA");
1278 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
1279
1280 aml_append(scope, build_rtc_device_aml());
1281 aml_append(scope, build_kbd_device_aml());
1282 aml_append(scope, build_mouse_device_aml());
1283 if (fdc) {
1284 aml_append(scope, build_fdc_device_aml(fdc));
1285 }
1286 aml_append(scope, build_lpt_device_aml());
1287 aml_append(scope, build_com_device_aml(1));
1288 aml_append(scope, build_com_device_aml(2));
1289
1290 if (ambiguous) {
1291 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1292 } else if (!obj) {
1293 error_report("No ISA bus, unable to define IPMI ACPI data");
1294 } else {
1295 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA");
1296 }
1297
1298 aml_append(table, scope);
1299 }
1300
1301 static void build_dbg_aml(Aml *table)
1302 {
1303 Aml *field;
1304 Aml *method;
1305 Aml *while_ctx;
1306 Aml *scope = aml_scope("\\");
1307 Aml *buf = aml_local(0);
1308 Aml *len = aml_local(1);
1309 Aml *idx = aml_local(2);
1310
1311 aml_append(scope,
1312 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1313 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1314 aml_append(field, aml_named_field("DBGB", 8));
1315 aml_append(scope, field);
1316
1317 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1318
1319 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1320 aml_append(method, aml_to_buffer(buf, buf));
1321 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1322 aml_append(method, aml_store(aml_int(0), idx));
1323
1324 while_ctx = aml_while(aml_lless(idx, len));
1325 aml_append(while_ctx,
1326 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1327 aml_append(while_ctx, aml_increment(idx));
1328 aml_append(method, while_ctx);
1329
1330 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1331 aml_append(scope, method);
1332
1333 aml_append(table, scope);
1334 }
1335
1336 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1337 {
1338 Aml *dev;
1339 Aml *crs;
1340 Aml *method;
1341 uint32_t irqs[] = {5, 10, 11};
1342
1343 dev = aml_device("%s", name);
1344 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1345 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1346
1347 crs = aml_resource_template();
1348 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1349 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1350 aml_append(dev, aml_name_decl("_PRS", crs));
1351
1352 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1353 aml_append(method, aml_return(aml_call1("IQST", reg)));
1354 aml_append(dev, method);
1355
1356 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1357 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1358 aml_append(dev, method);
1359
1360 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1361 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1362 aml_append(dev, method);
1363
1364 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1365 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1366 aml_append(method, aml_store(aml_name("PRRI"), reg));
1367 aml_append(dev, method);
1368
1369 return dev;
1370 }
1371
1372 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1373 {
1374 Aml *dev;
1375 Aml *crs;
1376 Aml *method;
1377 uint32_t irqs;
1378
1379 dev = aml_device("%s", name);
1380 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1381 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1382
1383 crs = aml_resource_template();
1384 irqs = gsi;
1385 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1386 AML_SHARED, &irqs, 1));
1387 aml_append(dev, aml_name_decl("_PRS", crs));
1388
1389 aml_append(dev, aml_name_decl("_CRS", crs));
1390
1391 /*
1392 * _DIS can be no-op because the interrupt cannot be disabled.
1393 */
1394 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1395 aml_append(dev, method);
1396
1397 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1398 aml_append(dev, method);
1399
1400 return dev;
1401 }
1402
1403 /* _CRS method - get current settings */
1404 static Aml *build_iqcr_method(bool is_piix4)
1405 {
1406 Aml *if_ctx;
1407 uint32_t irqs;
1408 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1409 Aml *crs = aml_resource_template();
1410
1411 irqs = 0;
1412 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1413 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1414 aml_append(method, aml_name_decl("PRR0", crs));
1415
1416 aml_append(method,
1417 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1418
1419 if (is_piix4) {
1420 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1421 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1422 aml_append(method, if_ctx);
1423 } else {
1424 aml_append(method,
1425 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1426 aml_name("PRRI")));
1427 }
1428
1429 aml_append(method, aml_return(aml_name("PRR0")));
1430 return method;
1431 }
1432
1433 /* _STA method - get status */
1434 static Aml *build_irq_status_method(void)
1435 {
1436 Aml *if_ctx;
1437 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1438
1439 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1440 aml_append(if_ctx, aml_return(aml_int(0x09)));
1441 aml_append(method, if_ctx);
1442 aml_append(method, aml_return(aml_int(0x0B)));
1443 return method;
1444 }
1445
1446 static void build_piix4_pci0_int(Aml *table)
1447 {
1448 Aml *dev;
1449 Aml *crs;
1450 Aml *field;
1451 Aml *method;
1452 uint32_t irqs;
1453 Aml *sb_scope = aml_scope("_SB");
1454 Aml *pci0_scope = aml_scope("PCI0");
1455
1456 aml_append(pci0_scope, build_prt(true));
1457 aml_append(sb_scope, pci0_scope);
1458
1459 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1460 aml_append(field, aml_named_field("PRQ0", 8));
1461 aml_append(field, aml_named_field("PRQ1", 8));
1462 aml_append(field, aml_named_field("PRQ2", 8));
1463 aml_append(field, aml_named_field("PRQ3", 8));
1464 aml_append(sb_scope, field);
1465
1466 aml_append(sb_scope, build_irq_status_method());
1467 aml_append(sb_scope, build_iqcr_method(true));
1468
1469 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1470 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1471 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1472 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1473
1474 dev = aml_device("LNKS");
1475 {
1476 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1477 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1478
1479 crs = aml_resource_template();
1480 irqs = 9;
1481 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1482 AML_ACTIVE_HIGH, AML_SHARED,
1483 &irqs, 1));
1484 aml_append(dev, aml_name_decl("_PRS", crs));
1485
1486 /* The SCI cannot be disabled and is always attached to GSI 9,
1487 * so these are no-ops. We only need this link to override the
1488 * polarity to active high and match the content of the MADT.
1489 */
1490 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1491 aml_append(method, aml_return(aml_int(0x0b)));
1492 aml_append(dev, method);
1493
1494 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1495 aml_append(dev, method);
1496
1497 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1498 aml_append(method, aml_return(aml_name("_PRS")));
1499 aml_append(dev, method);
1500
1501 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1502 aml_append(dev, method);
1503 }
1504 aml_append(sb_scope, dev);
1505
1506 aml_append(table, sb_scope);
1507 }
1508
1509 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1510 {
1511 int i;
1512 int head;
1513 Aml *pkg;
1514 char base = name[3] < 'E' ? 'A' : 'E';
1515 char *s = g_strdup(name);
1516 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1517
1518 assert(strlen(s) == 4);
1519
1520 head = name[3] - base;
1521 for (i = 0; i < 4; i++) {
1522 if (head + i > 3) {
1523 head = i * -1;
1524 }
1525 s[3] = base + head + i;
1526 pkg = aml_package(4);
1527 aml_append(pkg, a_nr);
1528 aml_append(pkg, aml_int(i));
1529 aml_append(pkg, aml_name("%s", s));
1530 aml_append(pkg, aml_int(0));
1531 aml_append(ctx, pkg);
1532 }
1533 g_free(s);
1534 }
1535
1536 static Aml *build_q35_routing_table(const char *str)
1537 {
1538 int i;
1539 Aml *pkg;
1540 char *name = g_strdup_printf("%s ", str);
1541
1542 pkg = aml_package(128);
1543 for (i = 0; i < 0x18; i++) {
1544 name[3] = 'E' + (i & 0x3);
1545 append_q35_prt_entry(pkg, i, name);
1546 }
1547
1548 name[3] = 'E';
1549 append_q35_prt_entry(pkg, 0x18, name);
1550
1551 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1552 for (i = 0x0019; i < 0x1e; i++) {
1553 name[3] = 'A';
1554 append_q35_prt_entry(pkg, i, name);
1555 }
1556
1557 /* PCIe->PCI bridge. use PIRQ[E-H] */
1558 name[3] = 'E';
1559 append_q35_prt_entry(pkg, 0x1e, name);
1560 name[3] = 'A';
1561 append_q35_prt_entry(pkg, 0x1f, name);
1562
1563 g_free(name);
1564 return pkg;
1565 }
1566
1567 static void build_q35_pci0_int(Aml *table)
1568 {
1569 Aml *field;
1570 Aml *method;
1571 Aml *sb_scope = aml_scope("_SB");
1572 Aml *pci0_scope = aml_scope("PCI0");
1573
1574 /* Zero => PIC mode, One => APIC Mode */
1575 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1576 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1577 {
1578 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1579 }
1580 aml_append(table, method);
1581
1582 aml_append(pci0_scope,
1583 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1584 aml_append(pci0_scope,
1585 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1586
1587 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1588 {
1589 Aml *if_ctx;
1590 Aml *else_ctx;
1591
1592 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1593 section 6.2.8.1 */
1594 /* Note: we provide the same info as the PCI routing
1595 table of the Bochs BIOS */
1596 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1597 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1598 aml_append(method, if_ctx);
1599 else_ctx = aml_else();
1600 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1601 aml_append(method, else_ctx);
1602 }
1603 aml_append(pci0_scope, method);
1604 aml_append(sb_scope, pci0_scope);
1605
1606 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1607 aml_append(field, aml_named_field("PRQA", 8));
1608 aml_append(field, aml_named_field("PRQB", 8));
1609 aml_append(field, aml_named_field("PRQC", 8));
1610 aml_append(field, aml_named_field("PRQD", 8));
1611 aml_append(field, aml_reserved_field(0x20));
1612 aml_append(field, aml_named_field("PRQE", 8));
1613 aml_append(field, aml_named_field("PRQF", 8));
1614 aml_append(field, aml_named_field("PRQG", 8));
1615 aml_append(field, aml_named_field("PRQH", 8));
1616 aml_append(sb_scope, field);
1617
1618 aml_append(sb_scope, build_irq_status_method());
1619 aml_append(sb_scope, build_iqcr_method(false));
1620
1621 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1622 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1623 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1624 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1625 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1626 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1627 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1628 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1629
1630 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1631 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1632 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1633 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1634 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1635 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1636 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1637 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1638
1639 aml_append(table, sb_scope);
1640 }
1641
1642 static void build_q35_isa_bridge(Aml *table)
1643 {
1644 Aml *dev;
1645 Aml *scope;
1646 Aml *field;
1647
1648 scope = aml_scope("_SB.PCI0");
1649 dev = aml_device("ISA");
1650 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1651
1652 /* ICH9 PCI to ISA irq remapping */
1653 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1654 aml_int(0x60), 0x0C));
1655
1656 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1657 aml_int(0x80), 0x02));
1658 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1659 aml_append(field, aml_named_field("COMA", 3));
1660 aml_append(field, aml_reserved_field(1));
1661 aml_append(field, aml_named_field("COMB", 3));
1662 aml_append(field, aml_reserved_field(1));
1663 aml_append(field, aml_named_field("LPTD", 2));
1664 aml_append(dev, field);
1665
1666 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1667 aml_int(0x82), 0x02));
1668 /* enable bits */
1669 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1670 aml_append(field, aml_named_field("CAEN", 1));
1671 aml_append(field, aml_named_field("CBEN", 1));
1672 aml_append(field, aml_named_field("LPEN", 1));
1673 aml_append(dev, field);
1674
1675 aml_append(scope, dev);
1676 aml_append(table, scope);
1677 }
1678
1679 static void build_piix4_pm(Aml *table)
1680 {
1681 Aml *dev;
1682 Aml *scope;
1683
1684 scope = aml_scope("_SB.PCI0");
1685 dev = aml_device("PX13");
1686 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1687
1688 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1689 aml_int(0x00), 0xff));
1690 aml_append(scope, dev);
1691 aml_append(table, scope);
1692 }
1693
1694 static void build_piix4_isa_bridge(Aml *table)
1695 {
1696 Aml *dev;
1697 Aml *scope;
1698 Aml *field;
1699
1700 scope = aml_scope("_SB.PCI0");
1701 dev = aml_device("ISA");
1702 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1703
1704 /* PIIX PCI to ISA irq remapping */
1705 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1706 aml_int(0x60), 0x04));
1707 /* enable bits */
1708 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1709 /* Offset(0x5f),, 7, */
1710 aml_append(field, aml_reserved_field(0x2f8));
1711 aml_append(field, aml_reserved_field(7));
1712 aml_append(field, aml_named_field("LPEN", 1));
1713 /* Offset(0x67),, 3, */
1714 aml_append(field, aml_reserved_field(0x38));
1715 aml_append(field, aml_reserved_field(3));
1716 aml_append(field, aml_named_field("CAEN", 1));
1717 aml_append(field, aml_reserved_field(3));
1718 aml_append(field, aml_named_field("CBEN", 1));
1719 aml_append(dev, field);
1720
1721 aml_append(scope, dev);
1722 aml_append(table, scope);
1723 }
1724
1725 static void build_piix4_pci_hotplug(Aml *table)
1726 {
1727 Aml *scope;
1728 Aml *field;
1729 Aml *method;
1730
1731 scope = aml_scope("_SB.PCI0");
1732
1733 aml_append(scope,
1734 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1735 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1736 aml_append(field, aml_named_field("PCIU", 32));
1737 aml_append(field, aml_named_field("PCID", 32));
1738 aml_append(scope, field);
1739
1740 aml_append(scope,
1741 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1742 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1743 aml_append(field, aml_named_field("B0EJ", 32));
1744 aml_append(scope, field);
1745
1746 aml_append(scope,
1747 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1748 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1749 aml_append(field, aml_named_field("BNUM", 32));
1750 aml_append(scope, field);
1751
1752 aml_append(scope, aml_mutex("BLCK", 0));
1753
1754 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1755 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1756 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1757 aml_append(method,
1758 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1759 aml_append(method, aml_release(aml_name("BLCK")));
1760 aml_append(method, aml_return(aml_int(0)));
1761 aml_append(scope, method);
1762
1763 aml_append(table, scope);
1764 }
1765
1766 static Aml *build_q35_osc_method(void)
1767 {
1768 Aml *if_ctx;
1769 Aml *if_ctx2;
1770 Aml *else_ctx;
1771 Aml *method;
1772 Aml *a_cwd1 = aml_name("CDW1");
1773 Aml *a_ctrl = aml_local(0);
1774
1775 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1776 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1777
1778 if_ctx = aml_if(aml_equal(
1779 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1780 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1781 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1782
1783 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1784
1785 /*
1786 * Always allow native PME, AER (no dependencies)
1787 * Allow SHPC (PCI bridges can have SHPC controller)
1788 */
1789 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
1790
1791 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1792 /* Unknown revision */
1793 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1794 aml_append(if_ctx, if_ctx2);
1795
1796 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1797 /* Capabilities bits were masked */
1798 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1799 aml_append(if_ctx, if_ctx2);
1800
1801 /* Update DWORD3 in the buffer */
1802 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1803 aml_append(method, if_ctx);
1804
1805 else_ctx = aml_else();
1806 /* Unrecognized UUID */
1807 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1808 aml_append(method, else_ctx);
1809
1810 aml_append(method, aml_return(aml_arg(3)));
1811 return method;
1812 }
1813
1814 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func)
1815 {
1816 Aml *scope = aml_scope("_SB.PCI0");
1817 Aml *dev = aml_device("SMB0");
1818
1819 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func)));
1820 build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0");
1821 aml_append(scope, dev);
1822 aml_append(table, scope);
1823 }
1824
1825 static void
1826 build_dsdt(GArray *table_data, BIOSLinker *linker,
1827 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1828 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1829 {
1830 CrsRangeEntry *entry;
1831 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1832 CrsRangeSet crs_range_set;
1833 PCMachineState *pcms = PC_MACHINE(machine);
1834 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1835 X86MachineState *x86ms = X86_MACHINE(machine);
1836 AcpiMcfgInfo mcfg;
1837 uint32_t nr_mem = machine->ram_slots;
1838 int root_bus_limit = 0xFF;
1839 PCIBus *bus = NULL;
1840 TPMIf *tpm = tpm_find();
1841 int i;
1842
1843 dsdt = init_aml_allocator();
1844
1845 /* Reserve space for header */
1846 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1847
1848 build_dbg_aml(dsdt);
1849 if (misc->is_piix4) {
1850 sb_scope = aml_scope("_SB");
1851 dev = aml_device("PCI0");
1852 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1853 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1854 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1855 aml_append(sb_scope, dev);
1856 aml_append(dsdt, sb_scope);
1857
1858 build_hpet_aml(dsdt);
1859 build_piix4_pm(dsdt);
1860 build_piix4_isa_bridge(dsdt);
1861 build_isa_devices_aml(dsdt);
1862 build_piix4_pci_hotplug(dsdt);
1863 build_piix4_pci0_int(dsdt);
1864 } else {
1865 sb_scope = aml_scope("_SB");
1866 dev = aml_device("PCI0");
1867 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1868 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1869 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1870 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1871 aml_append(dev, build_q35_osc_method());
1872 aml_append(sb_scope, dev);
1873 aml_append(dsdt, sb_scope);
1874
1875 build_hpet_aml(dsdt);
1876 build_q35_isa_bridge(dsdt);
1877 build_isa_devices_aml(dsdt);
1878 build_q35_pci0_int(dsdt);
1879 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) {
1880 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC);
1881 }
1882 }
1883
1884 if (pcmc->legacy_cpu_hotplug) {
1885 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1886 } else {
1887 CPUHotplugFeatures opts = {
1888 .acpi_1_compatible = true, .has_legacy_cphp = true
1889 };
1890 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1891 "\\_SB.PCI0", "\\_GPE._E02");
1892 }
1893
1894 if (pcms->memhp_io_base && nr_mem) {
1895 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
1896 "\\_GPE._E03", AML_SYSTEM_IO,
1897 pcms->memhp_io_base);
1898 }
1899
1900 scope = aml_scope("_GPE");
1901 {
1902 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1903
1904 if (misc->is_piix4) {
1905 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1906 aml_append(method,
1907 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1908 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1909 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1910 aml_append(scope, method);
1911 }
1912
1913 if (machine->nvdimms_state->is_enabled) {
1914 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1915 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1916 aml_int(0x80)));
1917 aml_append(scope, method);
1918 }
1919 }
1920 aml_append(dsdt, scope);
1921
1922 crs_range_set_init(&crs_range_set);
1923 bus = PC_MACHINE(machine)->bus;
1924 if (bus) {
1925 QLIST_FOREACH(bus, &bus->child, sibling) {
1926 uint8_t bus_num = pci_bus_num(bus);
1927 uint8_t numa_node = pci_bus_numa_node(bus);
1928
1929 /* look only for expander root buses */
1930 if (!pci_bus_is_root(bus)) {
1931 continue;
1932 }
1933
1934 if (bus_num < root_bus_limit) {
1935 root_bus_limit = bus_num - 1;
1936 }
1937
1938 scope = aml_scope("\\_SB");
1939 dev = aml_device("PC%.02X", bus_num);
1940 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1941 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1942 if (pci_bus_is_express(bus)) {
1943 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1944 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1945 aml_append(dev, build_q35_osc_method());
1946 } else {
1947 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1948 }
1949
1950 if (numa_node != NUMA_NODE_UNASSIGNED) {
1951 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1952 }
1953
1954 aml_append(dev, build_prt(false));
1955 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
1956 aml_append(dev, aml_name_decl("_CRS", crs));
1957 aml_append(scope, dev);
1958 aml_append(dsdt, scope);
1959 }
1960 }
1961
1962 /*
1963 * At this point crs_range_set has all the ranges used by pci
1964 * busses *other* than PCI0. These ranges will be excluded from
1965 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1966 * too.
1967 */
1968 if (acpi_get_mcfg(&mcfg)) {
1969 crs_range_insert(crs_range_set.mem_ranges,
1970 mcfg.base, mcfg.base + mcfg.size - 1);
1971 }
1972
1973 scope = aml_scope("\\_SB.PCI0");
1974 /* build PCI0._CRS */
1975 crs = aml_resource_template();
1976 aml_append(crs,
1977 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1978 0x0000, 0x0, root_bus_limit,
1979 0x0000, root_bus_limit + 1));
1980 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1981
1982 aml_append(crs,
1983 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1984 AML_POS_DECODE, AML_ENTIRE_RANGE,
1985 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1986
1987 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1988 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1989 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1990 aml_append(crs,
1991 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1992 AML_POS_DECODE, AML_ENTIRE_RANGE,
1993 0x0000, entry->base, entry->limit,
1994 0x0000, entry->limit - entry->base + 1));
1995 }
1996
1997 aml_append(crs,
1998 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1999 AML_CACHEABLE, AML_READ_WRITE,
2000 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2001
2002 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
2003 range_lob(pci_hole),
2004 range_upb(pci_hole));
2005 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
2006 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
2007 aml_append(crs,
2008 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2009 AML_NON_CACHEABLE, AML_READ_WRITE,
2010 0, entry->base, entry->limit,
2011 0, entry->limit - entry->base + 1));
2012 }
2013
2014 if (!range_is_empty(pci_hole64)) {
2015 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
2016 range_lob(pci_hole64),
2017 range_upb(pci_hole64));
2018 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
2019 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
2020 aml_append(crs,
2021 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
2022 AML_MAX_FIXED,
2023 AML_CACHEABLE, AML_READ_WRITE,
2024 0, entry->base, entry->limit,
2025 0, entry->limit - entry->base + 1));
2026 }
2027 }
2028
2029 if (TPM_IS_TIS(tpm_find())) {
2030 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2031 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2032 }
2033 aml_append(scope, aml_name_decl("_CRS", crs));
2034
2035 /* reserve GPE0 block resources */
2036 dev = aml_device("GPE0");
2037 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2038 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2039 /* device present, functioning, decoding, not shown in UI */
2040 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2041 crs = aml_resource_template();
2042 aml_append(crs,
2043 aml_io(
2044 AML_DECODE16,
2045 pm->fadt.gpe0_blk.address,
2046 pm->fadt.gpe0_blk.address,
2047 1,
2048 pm->fadt.gpe0_blk.bit_width / 8)
2049 );
2050 aml_append(dev, aml_name_decl("_CRS", crs));
2051 aml_append(scope, dev);
2052
2053 crs_range_set_free(&crs_range_set);
2054
2055 /* reserve PCIHP resources */
2056 if (pm->pcihp_io_len) {
2057 dev = aml_device("PHPR");
2058 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2059 aml_append(dev,
2060 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2061 /* device present, functioning, decoding, not shown in UI */
2062 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2063 crs = aml_resource_template();
2064 aml_append(crs,
2065 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2066 pm->pcihp_io_len)
2067 );
2068 aml_append(dev, aml_name_decl("_CRS", crs));
2069 aml_append(scope, dev);
2070 }
2071 aml_append(dsdt, scope);
2072
2073 /* create S3_ / S4_ / S5_ packages if necessary */
2074 scope = aml_scope("\\");
2075 if (!pm->s3_disabled) {
2076 pkg = aml_package(4);
2077 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2078 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2079 aml_append(pkg, aml_int(0)); /* reserved */
2080 aml_append(pkg, aml_int(0)); /* reserved */
2081 aml_append(scope, aml_name_decl("_S3", pkg));
2082 }
2083
2084 if (!pm->s4_disabled) {
2085 pkg = aml_package(4);
2086 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2087 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2088 aml_append(pkg, aml_int(pm->s4_val));
2089 aml_append(pkg, aml_int(0)); /* reserved */
2090 aml_append(pkg, aml_int(0)); /* reserved */
2091 aml_append(scope, aml_name_decl("_S4", pkg));
2092 }
2093
2094 pkg = aml_package(4);
2095 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2096 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2097 aml_append(pkg, aml_int(0)); /* reserved */
2098 aml_append(pkg, aml_int(0)); /* reserved */
2099 aml_append(scope, aml_name_decl("_S5", pkg));
2100 aml_append(dsdt, scope);
2101
2102 /* create fw_cfg node, unconditionally */
2103 {
2104 /* when using port i/o, the 8-bit data register *always* overlaps
2105 * with half of the 16-bit control register. Hence, the total size
2106 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2107 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2108 uint8_t io_size = object_property_get_bool(OBJECT(x86ms->fw_cfg),
2109 "dma_enabled", NULL) ?
2110 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2111 FW_CFG_CTL_SIZE;
2112
2113 scope = aml_scope("\\_SB.PCI0");
2114 dev = aml_device("FWCF");
2115
2116 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2117
2118 /* device present, functioning, decoding, not shown in UI */
2119 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2120
2121 crs = aml_resource_template();
2122 aml_append(crs,
2123 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2124 );
2125 aml_append(dev, aml_name_decl("_CRS", crs));
2126
2127 aml_append(scope, dev);
2128 aml_append(dsdt, scope);
2129 }
2130
2131 if (misc->applesmc_io_base) {
2132 scope = aml_scope("\\_SB.PCI0.ISA");
2133 dev = aml_device("SMC");
2134
2135 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2136 /* device present, functioning, decoding, not shown in UI */
2137 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2138
2139 crs = aml_resource_template();
2140 aml_append(crs,
2141 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2142 0x01, APPLESMC_MAX_DATA_LENGTH)
2143 );
2144 aml_append(crs, aml_irq_no_flags(6));
2145 aml_append(dev, aml_name_decl("_CRS", crs));
2146
2147 aml_append(scope, dev);
2148 aml_append(dsdt, scope);
2149 }
2150
2151 if (misc->pvpanic_port) {
2152 scope = aml_scope("\\_SB.PCI0.ISA");
2153
2154 dev = aml_device("PEVT");
2155 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2156
2157 crs = aml_resource_template();
2158 aml_append(crs,
2159 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2160 );
2161 aml_append(dev, aml_name_decl("_CRS", crs));
2162
2163 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2164 aml_int(misc->pvpanic_port), 1));
2165 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2166 aml_append(field, aml_named_field("PEPT", 8));
2167 aml_append(dev, field);
2168
2169 /* device present, functioning, decoding, shown in UI */
2170 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2171
2172 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2173 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2174 aml_append(method, aml_return(aml_local(0)));
2175 aml_append(dev, method);
2176
2177 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2178 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2179 aml_append(dev, method);
2180
2181 aml_append(scope, dev);
2182 aml_append(dsdt, scope);
2183 }
2184
2185 sb_scope = aml_scope("\\_SB");
2186 {
2187 Object *pci_host;
2188 PCIBus *bus = NULL;
2189
2190 pci_host = acpi_get_i386_pci_host();
2191 if (pci_host) {
2192 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2193 }
2194
2195 if (bus) {
2196 Aml *scope = aml_scope("PCI0");
2197 /* Scan all PCI buses. Generate tables to support hotplug. */
2198 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2199
2200 if (TPM_IS_TIS(tpm)) {
2201 if (misc->tpm_version == TPM_VERSION_2_0) {
2202 dev = aml_device("TPM");
2203 aml_append(dev, aml_name_decl("_HID",
2204 aml_string("MSFT0101")));
2205 } else {
2206 dev = aml_device("ISA.TPM");
2207 aml_append(dev, aml_name_decl("_HID",
2208 aml_eisaid("PNP0C31")));
2209 }
2210
2211 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2212 crs = aml_resource_template();
2213 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2214 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2215 /*
2216 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2217 Rewrite to take IRQ from TPM device model and
2218 fix default IRQ value there to use some unused IRQ
2219 */
2220 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2221 aml_append(dev, aml_name_decl("_CRS", crs));
2222
2223 tpm_build_ppi_acpi(tpm, dev);
2224
2225 aml_append(scope, dev);
2226 }
2227
2228 aml_append(sb_scope, scope);
2229 }
2230 }
2231
2232 if (TPM_IS_CRB(tpm)) {
2233 dev = aml_device("TPM");
2234 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
2235 crs = aml_resource_template();
2236 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
2237 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
2238 aml_append(dev, aml_name_decl("_CRS", crs));
2239
2240 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
2241 aml_append(method, aml_return(aml_int(0x0f)));
2242 aml_append(dev, method);
2243
2244 tpm_build_ppi_acpi(tpm, dev);
2245
2246 aml_append(sb_scope, dev);
2247 }
2248
2249 aml_append(dsdt, sb_scope);
2250
2251 /* copy AML table into ACPI tables blob and patch header there */
2252 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
2253 build_header(linker, table_data,
2254 (void *)(table_data->data + table_data->len - dsdt->buf->len),
2255 "DSDT", dsdt->buf->len, 1, NULL, NULL);
2256 free_aml_allocator();
2257 }
2258
2259 static void
2260 build_hpet(GArray *table_data, BIOSLinker *linker)
2261 {
2262 Acpi20Hpet *hpet;
2263
2264 hpet = acpi_data_push(table_data, sizeof(*hpet));
2265 /* Note timer_block_id value must be kept in sync with value advertised by
2266 * emulated hpet
2267 */
2268 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2269 hpet->addr.address = cpu_to_le64(HPET_BASE);
2270 build_header(linker, table_data,
2271 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
2272 }
2273
2274 static void
2275 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2276 {
2277 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2278 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
2279 unsigned log_addr_offset =
2280 (char *)&tcpa->log_area_start_address - table_data->data;
2281
2282 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2283 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2284 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
2285
2286 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
2287 false /* high memory */);
2288
2289 /* log area start address to be filled by Guest linker */
2290 bios_linker_loader_add_pointer(linker,
2291 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
2292 ACPI_BUILD_TPMLOG_FILE, 0);
2293
2294 build_header(linker, table_data,
2295 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
2296 }
2297
2298 static void
2299 build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2300 {
2301 Acpi20TPM2 *tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2302 unsigned log_addr_size = sizeof(tpm2_ptr->log_area_start_address);
2303 unsigned log_addr_offset =
2304 (char *)&tpm2_ptr->log_area_start_address - table_data->data;
2305
2306 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2307 if (TPM_IS_TIS(tpm_find())) {
2308 tpm2_ptr->control_area_address = cpu_to_le64(0);
2309 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2310 } else if (TPM_IS_CRB(tpm_find())) {
2311 tpm2_ptr->control_area_address = cpu_to_le64(TPM_CRB_ADDR_CTRL);
2312 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_CRB);
2313 } else {
2314 g_warn_if_reached();
2315 }
2316
2317 tpm2_ptr->log_area_minimum_length =
2318 cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2319
2320 /* log area start address to be filled by Guest linker */
2321 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
2322 log_addr_offset, log_addr_size,
2323 ACPI_BUILD_TPMLOG_FILE, 0);
2324 build_header(linker, table_data,
2325 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
2326 }
2327
2328 #define HOLE_640K_START (640 * KiB)
2329 #define HOLE_640K_END (1 * MiB)
2330
2331 static void
2332 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
2333 {
2334 AcpiSystemResourceAffinityTable *srat;
2335 AcpiSratMemoryAffinity *numamem;
2336
2337 int i;
2338 int srat_start, numa_start, slots;
2339 uint64_t mem_len, mem_base, next_base;
2340 MachineClass *mc = MACHINE_GET_CLASS(machine);
2341 X86MachineState *x86ms = X86_MACHINE(machine);
2342 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
2343 PCMachineState *pcms = PC_MACHINE(machine);
2344 ram_addr_t hotplugabble_address_space_size =
2345 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
2346 NULL);
2347
2348 srat_start = table_data->len;
2349
2350 srat = acpi_data_push(table_data, sizeof *srat);
2351 srat->reserved1 = cpu_to_le32(1);
2352
2353 for (i = 0; i < apic_ids->len; i++) {
2354 int node_id = apic_ids->cpus[i].props.node_id;
2355 uint32_t apic_id = apic_ids->cpus[i].arch_id;
2356
2357 if (apic_id < 255) {
2358 AcpiSratProcessorAffinity *core;
2359
2360 core = acpi_data_push(table_data, sizeof *core);
2361 core->type = ACPI_SRAT_PROCESSOR_APIC;
2362 core->length = sizeof(*core);
2363 core->local_apic_id = apic_id;
2364 core->proximity_lo = node_id;
2365 memset(core->proximity_hi, 0, 3);
2366 core->local_sapic_eid = 0;
2367 core->flags = cpu_to_le32(1);
2368 } else {
2369 AcpiSratProcessorX2ApicAffinity *core;
2370
2371 core = acpi_data_push(table_data, sizeof *core);
2372 core->type = ACPI_SRAT_PROCESSOR_x2APIC;
2373 core->length = sizeof(*core);
2374 core->x2apic_id = cpu_to_le32(apic_id);
2375 core->proximity_domain = cpu_to_le32(node_id);
2376 core->flags = cpu_to_le32(1);
2377 }
2378 }
2379
2380
2381 /* the memory map is a bit tricky, it contains at least one hole
2382 * from 640k-1M and possibly another one from 3.5G-4G.
2383 */
2384 next_base = 0;
2385 numa_start = table_data->len;
2386
2387 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2388 mem_base = next_base;
2389 mem_len = pcms->node_mem[i - 1];
2390 next_base = mem_base + mem_len;
2391
2392 /* Cut out the 640K hole */
2393 if (mem_base <= HOLE_640K_START &&
2394 next_base > HOLE_640K_START) {
2395 mem_len -= next_base - HOLE_640K_START;
2396 if (mem_len > 0) {
2397 numamem = acpi_data_push(table_data, sizeof *numamem);
2398 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2399 MEM_AFFINITY_ENABLED);
2400 }
2401
2402 /* Check for the rare case: 640K < RAM < 1M */
2403 if (next_base <= HOLE_640K_END) {
2404 next_base = HOLE_640K_END;
2405 continue;
2406 }
2407 mem_base = HOLE_640K_END;
2408 mem_len = next_base - HOLE_640K_END;
2409 }
2410
2411 /* Cut out the ACPI_PCI hole */
2412 if (mem_base <= x86ms->below_4g_mem_size &&
2413 next_base > x86ms->below_4g_mem_size) {
2414 mem_len -= next_base - x86ms->below_4g_mem_size;
2415 if (mem_len > 0) {
2416 numamem = acpi_data_push(table_data, sizeof *numamem);
2417 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2418 MEM_AFFINITY_ENABLED);
2419 }
2420 mem_base = 1ULL << 32;
2421 mem_len = next_base - x86ms->below_4g_mem_size;
2422 next_base = mem_base + mem_len;
2423 }
2424
2425 if (mem_len > 0) {
2426 numamem = acpi_data_push(table_data, sizeof *numamem);
2427 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2428 MEM_AFFINITY_ENABLED);
2429 }
2430 }
2431 slots = (table_data->len - numa_start) / sizeof *numamem;
2432 for (; slots < pcms->numa_nodes + 2; slots++) {
2433 numamem = acpi_data_push(table_data, sizeof *numamem);
2434 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2435 }
2436
2437 /*
2438 * Entry is required for Windows to enable memory hotplug in OS
2439 * and for Linux to enable SWIOTLB when booted with less than
2440 * 4G of RAM. Windows works better if the entry sets proximity
2441 * to the highest NUMA node in the machine.
2442 * Memory devices may override proximity set by this entry,
2443 * providing _PXM method if necessary.
2444 */
2445 if (hotplugabble_address_space_size) {
2446 numamem = acpi_data_push(table_data, sizeof *numamem);
2447 build_srat_memory(numamem, machine->device_memory->base,
2448 hotplugabble_address_space_size, pcms->numa_nodes - 1,
2449 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2450 }
2451
2452 build_header(linker, table_data,
2453 (void *)(table_data->data + srat_start),
2454 "SRAT",
2455 table_data->len - srat_start, 1, NULL, NULL);
2456 }
2457
2458 /*
2459 * VT-d spec 8.1 DMA Remapping Reporting Structure
2460 * (version Oct. 2014 or later)
2461 */
2462 static void
2463 build_dmar_q35(GArray *table_data, BIOSLinker *linker)
2464 {
2465 int dmar_start = table_data->len;
2466
2467 AcpiTableDmar *dmar;
2468 AcpiDmarHardwareUnit *drhd;
2469 AcpiDmarRootPortATS *atsr;
2470 uint8_t dmar_flags = 0;
2471 X86IOMMUState *iommu = x86_iommu_get_default();
2472 AcpiDmarDeviceScope *scope = NULL;
2473 /* Root complex IOAPIC use one path[0] only */
2474 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
2475 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2476
2477 assert(iommu);
2478 if (x86_iommu_ir_supported(iommu)) {
2479 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2480 }
2481
2482 dmar = acpi_data_push(table_data, sizeof(*dmar));
2483 dmar->host_address_width = intel_iommu->aw_bits - 1;
2484 dmar->flags = dmar_flags;
2485
2486 /* DMAR Remapping Hardware Unit Definition structure */
2487 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
2488 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2489 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
2490 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2491 drhd->pci_segment = cpu_to_le16(0);
2492 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2493
2494 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2495 * 8.3.1 (version Oct. 2014 or later). */
2496 scope = &drhd->scope[0];
2497 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
2498 scope->length = ioapic_scope_size;
2499 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2500 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
2501 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
2502 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
2503
2504 if (iommu->dt_supported) {
2505 atsr = acpi_data_push(table_data, sizeof(*atsr));
2506 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
2507 atsr->length = cpu_to_le16(sizeof(*atsr));
2508 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
2509 atsr->pci_segment = cpu_to_le16(0);
2510 }
2511
2512 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2513 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2514 }
2515 /*
2516 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2517 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2518 */
2519 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2520
2521 /*
2522 * Insert IVHD entry for device and recurse, insert alias, or insert range as
2523 * necessary for the PCI topology.
2524 */
2525 static void
2526 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque)
2527 {
2528 GArray *table_data = opaque;
2529 uint32_t entry;
2530
2531 /* "Select" IVHD entry, type 0x2 */
2532 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2;
2533 build_append_int_noprefix(table_data, entry, 4);
2534
2535 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2536 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
2537 uint8_t sec = pci_bus_num(sec_bus);
2538 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS];
2539
2540 if (pci_bus_is_express(sec_bus)) {
2541 /*
2542 * Walk the bus if there are subordinates, otherwise use a range
2543 * to cover an entire leaf bus. We could potentially also use a
2544 * range for traversed buses, but we'd need to take care not to
2545 * create both Select and Range entries covering the same device.
2546 * This is easier and potentially more compact.
2547 *
2548 * An example bare metal system seems to use Select entries for
2549 * root ports without a slot (ie. built-ins) and Range entries
2550 * when there is a slot. The same system also only hard-codes
2551 * the alias range for an onboard PCIe-to-PCI bridge, apparently
2552 * making no effort to support nested bridges. We attempt to
2553 * be more thorough here.
2554 */
2555 if (sec == sub) { /* leaf bus */
2556 /* "Start of Range" IVHD entry, type 0x3 */
2557 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3;
2558 build_append_int_noprefix(table_data, entry, 4);
2559 /* "End of Range" IVHD entry, type 0x4 */
2560 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2561 build_append_int_noprefix(table_data, entry, 4);
2562 } else {
2563 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data);
2564 }
2565 } else {
2566 /*
2567 * If the secondary bus is conventional, then we need to create an
2568 * Alias range for everything downstream. The range covers the
2569 * first devfn on the secondary bus to the last devfn on the
2570 * subordinate bus. The alias target depends on legacy versus
2571 * express bridges, just as in pci_device_iommu_address_space().
2572 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
2573 */
2574 uint16_t dev_id_a, dev_id_b;
2575
2576 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0));
2577
2578 if (pci_is_express(dev) &&
2579 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
2580 dev_id_b = dev_id_a;
2581 } else {
2582 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn);
2583 }
2584
2585 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
2586 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4);
2587 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4);
2588
2589 /* "End of Range" IVHD entry, type 0x4 */
2590 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2591 build_append_int_noprefix(table_data, entry, 4);
2592 }
2593 }
2594 }
2595
2596 /* For all PCI host bridges, walk and insert IVHD entries */
2597 static int
2598 ivrs_host_bridges(Object *obj, void *opaque)
2599 {
2600 GArray *ivhd_blob = opaque;
2601
2602 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2603 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2604
2605 if (bus) {
2606 pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob);
2607 }
2608 }
2609
2610 return 0;
2611 }
2612
2613 static void
2614 build_amd_iommu(GArray *table_data, BIOSLinker *linker)
2615 {
2616 int ivhd_table_len = 24;
2617 int iommu_start = table_data->len;
2618 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2619 GArray *ivhd_blob = g_array_new(false, true, 1);
2620
2621 /* IVRS header */
2622 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2623 /* IVinfo - IO virtualization information common to all
2624 * IOMMU units in a system
2625 */
2626 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2627 /* reserved */
2628 build_append_int_noprefix(table_data, 0, 8);
2629
2630 /* IVHD definition - type 10h */
2631 build_append_int_noprefix(table_data, 0x10, 1);
2632 /* virtualization flags */
2633 build_append_int_noprefix(table_data,
2634 (1UL << 0) | /* HtTunEn */
2635 (1UL << 4) | /* iotblSup */
2636 (1UL << 6) | /* PrefSup */
2637 (1UL << 7), /* PPRSup */
2638 1);
2639
2640 /*
2641 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2642 * complete set of IVHD entries. Do this into a separate blob so that we
2643 * can calculate the total IVRS table length here and then append the new
2644 * blob further below. Fall back to an entry covering all devices, which
2645 * is sufficient when no aliases are present.
2646 */
2647 object_child_foreach_recursive(object_get_root(),
2648 ivrs_host_bridges, ivhd_blob);
2649
2650 if (!ivhd_blob->len) {
2651 /*
2652 * Type 1 device entry reporting all devices
2653 * These are 4-byte device entries currently reporting the range of
2654 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2655 */
2656 build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
2657 }
2658
2659 ivhd_table_len += ivhd_blob->len;
2660
2661 /*
2662 * When interrupt remapping is supported, we add a special IVHD device
2663 * for type IO-APIC.
2664 */
2665 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2666 ivhd_table_len += 8;
2667 }
2668
2669 /* IVHD length */
2670 build_append_int_noprefix(table_data, ivhd_table_len, 2);
2671 /* DeviceID */
2672 build_append_int_noprefix(table_data, s->devid, 2);
2673 /* Capability offset */
2674 build_append_int_noprefix(table_data, s->capab_offset, 2);
2675 /* IOMMU base address */
2676 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2677 /* PCI Segment Group */
2678 build_append_int_noprefix(table_data, 0, 2);
2679 /* IOMMU info */
2680 build_append_int_noprefix(table_data, 0, 2);
2681 /* IOMMU Feature Reporting */
2682 build_append_int_noprefix(table_data,
2683 (48UL << 30) | /* HATS */
2684 (48UL << 28) | /* GATS */
2685 (1UL << 2) | /* GTSup */
2686 (1UL << 6), /* GASup */
2687 4);
2688
2689 /* IVHD entries as found above */
2690 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
2691 g_array_free(ivhd_blob, TRUE);
2692
2693 /*
2694 * Add a special IVHD device type.
2695 * Refer to spec - Table 95: IVHD device entry type codes
2696 *
2697 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2698 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2699 */
2700 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2701 build_append_int_noprefix(table_data,
2702 (0x1ull << 56) | /* type IOAPIC */
2703 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
2704 0x48, /* special device */
2705 8);
2706 }
2707
2708 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2709 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2710 }
2711
2712 typedef
2713 struct AcpiBuildState {
2714 /* Copy of table in RAM (for patching). */
2715 MemoryRegion *table_mr;
2716 /* Is table patched? */
2717 uint8_t patched;
2718 void *rsdp;
2719 MemoryRegion *rsdp_mr;
2720 MemoryRegion *linker_mr;
2721 } AcpiBuildState;
2722
2723 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2724 {
2725 Object *pci_host;
2726 QObject *o;
2727
2728 pci_host = acpi_get_i386_pci_host();
2729 g_assert(pci_host);
2730
2731 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2732 if (!o) {
2733 return false;
2734 }
2735 mcfg->base = qnum_get_uint(qobject_to(QNum, o));
2736 qobject_unref(o);
2737 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
2738 return false;
2739 }
2740
2741 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2742 assert(o);
2743 mcfg->size = qnum_get_uint(qobject_to(QNum, o));
2744 qobject_unref(o);
2745 return true;
2746 }
2747
2748 static
2749 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2750 {
2751 PCMachineState *pcms = PC_MACHINE(machine);
2752 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2753 X86MachineState *x86ms = X86_MACHINE(machine);
2754 GArray *table_offsets;
2755 unsigned facs, dsdt, rsdt, fadt;
2756 AcpiPmInfo pm;
2757 AcpiMiscInfo misc;
2758 AcpiMcfgInfo mcfg;
2759 Range pci_hole, pci_hole64;
2760 uint8_t *u;
2761 size_t aml_len = 0;
2762 GArray *tables_blob = tables->table_data;
2763 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2764 Object *vmgenid_dev;
2765
2766 acpi_get_pm_info(machine, &pm);
2767 acpi_get_misc_info(&misc);
2768 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2769 acpi_get_slic_oem(&slic_oem);
2770
2771 table_offsets = g_array_new(false, true /* clear */,
2772 sizeof(uint32_t));
2773 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2774
2775 bios_linker_loader_alloc(tables->linker,
2776 ACPI_BUILD_TABLE_FILE, tables_blob,
2777 64 /* Ensure FACS is aligned */,
2778 false /* high memory */);
2779
2780 /*
2781 * FACS is pointed to by FADT.
2782 * We place it first since it's the only table that has alignment
2783 * requirements.
2784 */
2785 facs = tables_blob->len;
2786 build_facs(tables_blob);
2787
2788 /* DSDT is pointed to by FADT */
2789 dsdt = tables_blob->len;
2790 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2791 &pci_hole, &pci_hole64, machine);
2792
2793 /* Count the size of the DSDT and SSDT, we will need it for legacy
2794 * sizing of ACPI tables.
2795 */
2796 aml_len += tables_blob->len - dsdt;
2797
2798 /* ACPI tables pointed to by RSDT */
2799 fadt = tables_blob->len;
2800 acpi_add_table(table_offsets, tables_blob);
2801 pm.fadt.facs_tbl_offset = &facs;
2802 pm.fadt.dsdt_tbl_offset = &dsdt;
2803 pm.fadt.xdsdt_tbl_offset = &dsdt;
2804 build_fadt(tables_blob, tables->linker, &pm.fadt,
2805 slic_oem.id, slic_oem.table_id);
2806 aml_len += tables_blob->len - fadt;
2807
2808 acpi_add_table(table_offsets, tables_blob);
2809 build_madt(tables_blob, tables->linker, pcms);
2810
2811 vmgenid_dev = find_vmgenid_dev();
2812 if (vmgenid_dev) {
2813 acpi_add_table(table_offsets, tables_blob);
2814 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2815 tables->vmgenid, tables->linker);
2816 }
2817
2818 if (misc.has_hpet) {
2819 acpi_add_table(table_offsets, tables_blob);
2820 build_hpet(tables_blob, tables->linker);
2821 }
2822 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2823 acpi_add_table(table_offsets, tables_blob);
2824 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2825
2826 if (misc.tpm_version == TPM_VERSION_2_0) {
2827 acpi_add_table(table_offsets, tables_blob);
2828 build_tpm2(tables_blob, tables->linker, tables->tcpalog);
2829 }
2830 }
2831 if (pcms->numa_nodes) {
2832 acpi_add_table(table_offsets, tables_blob);
2833 build_srat(tables_blob, tables->linker, machine);
2834 if (machine->numa_state->have_numa_distance) {
2835 acpi_add_table(table_offsets, tables_blob);
2836 build_slit(tables_blob, tables->linker, machine);
2837 }
2838 if (machine->numa_state->hmat_enabled) {
2839 acpi_add_table(table_offsets, tables_blob);
2840 build_hmat(tables_blob, tables->linker, machine->numa_state);
2841 }
2842 }
2843 if (acpi_get_mcfg(&mcfg)) {
2844 acpi_add_table(table_offsets, tables_blob);
2845 build_mcfg(tables_blob, tables->linker, &mcfg);
2846 }
2847 if (x86_iommu_get_default()) {
2848 IommuType IOMMUType = x86_iommu_get_type();
2849 if (IOMMUType == TYPE_AMD) {
2850 acpi_add_table(table_offsets, tables_blob);
2851 build_amd_iommu(tables_blob, tables->linker);
2852 } else if (IOMMUType == TYPE_INTEL) {
2853 acpi_add_table(table_offsets, tables_blob);
2854 build_dmar_q35(tables_blob, tables->linker);
2855 }
2856 }
2857 if (machine->nvdimms_state->is_enabled) {
2858 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2859 machine->nvdimms_state, machine->ram_slots);
2860 }
2861
2862 /* Add tables supplied by user (if any) */
2863 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2864 unsigned len = acpi_table_len(u);
2865
2866 acpi_add_table(table_offsets, tables_blob);
2867 g_array_append_vals(tables_blob, u, len);
2868 }
2869
2870 /* RSDT is pointed to by RSDP */
2871 rsdt = tables_blob->len;
2872 build_rsdt(tables_blob, tables->linker, table_offsets,
2873 slic_oem.id, slic_oem.table_id);
2874
2875 /* RSDP is in FSEG memory, so allocate it separately */
2876 {
2877 AcpiRsdpData rsdp_data = {
2878 .revision = 0,
2879 .oem_id = ACPI_BUILD_APPNAME6,
2880 .xsdt_tbl_offset = NULL,
2881 .rsdt_tbl_offset = &rsdt,
2882 };
2883 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2884 if (!pcmc->rsdp_in_ram) {
2885 /* We used to allocate some extra space for RSDP revision 2 but
2886 * only used the RSDP revision 0 space. The extra bytes were
2887 * zeroed out and not used.
2888 * Here we continue wasting those extra 16 bytes to make sure we
2889 * don't break migration for machine types 2.2 and older due to
2890 * RSDP blob size mismatch.
2891 */
2892 build_append_int_noprefix(tables->rsdp, 0, 16);
2893 }
2894 }
2895
2896 /* We'll expose it all to Guest so we want to reduce
2897 * chance of size changes.
2898 *
2899 * We used to align the tables to 4k, but of course this would
2900 * too simple to be enough. 4k turned out to be too small an
2901 * alignment very soon, and in fact it is almost impossible to
2902 * keep the table size stable for all (max_cpus, max_memory_slots)
2903 * combinations. So the table size is always 64k for pc-i440fx-2.1
2904 * and we give an error if the table grows beyond that limit.
2905 *
2906 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2907 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2908 * than 2.0 and we can always pad the smaller tables with zeros. We can
2909 * then use the exact size of the 2.0 tables.
2910 *
2911 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2912 */
2913 if (pcmc->legacy_acpi_table_size) {
2914 /* Subtracting aml_len gives the size of fixed tables. Then add the
2915 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2916 */
2917 int legacy_aml_len =
2918 pcmc->legacy_acpi_table_size +
2919 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit;
2920 int legacy_table_size =
2921 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2922 ACPI_BUILD_ALIGN_SIZE);
2923 if (tables_blob->len > legacy_table_size) {
2924 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2925 warn_report("ACPI table size %u exceeds %d bytes,"
2926 " migration may not work",
2927 tables_blob->len, legacy_table_size);
2928 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2929 " or PCI bridges.");
2930 }
2931 g_array_set_size(tables_blob, legacy_table_size);
2932 } else {
2933 /* Make sure we have a buffer in case we need to resize the tables. */
2934 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2935 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2936 warn_report("ACPI table size %u exceeds %d bytes,"
2937 " migration may not work",
2938 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2939 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2940 " or PCI bridges.");
2941 }
2942 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2943 }
2944
2945 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2946
2947 /* Cleanup memory that's no longer used. */
2948 g_array_free(table_offsets, true);
2949 }
2950
2951 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2952 {
2953 uint32_t size = acpi_data_len(data);
2954
2955 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2956 memory_region_ram_resize(mr, size, &error_abort);
2957
2958 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2959 memory_region_set_dirty(mr, 0, size);
2960 }
2961
2962 static void acpi_build_update(void *build_opaque)
2963 {
2964 AcpiBuildState *build_state = build_opaque;
2965 AcpiBuildTables tables;
2966
2967 /* No state to update or already patched? Nothing to do. */
2968 if (!build_state || build_state->patched) {
2969 return;
2970 }
2971 build_state->patched = 1;
2972
2973 acpi_build_tables_init(&tables);
2974
2975 acpi_build(&tables, MACHINE(qdev_get_machine()));
2976
2977 acpi_ram_update(build_state->table_mr, tables.table_data);
2978
2979 if (build_state->rsdp) {
2980 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2981 } else {
2982 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2983 }
2984
2985 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2986 acpi_build_tables_cleanup(&tables, true);
2987 }
2988
2989 static void acpi_build_reset(void *build_opaque)
2990 {
2991 AcpiBuildState *build_state = build_opaque;
2992 build_state->patched = 0;
2993 }
2994
2995 static const VMStateDescription vmstate_acpi_build = {
2996 .name = "acpi_build",
2997 .version_id = 1,
2998 .minimum_version_id = 1,
2999 .fields = (VMStateField[]) {
3000 VMSTATE_UINT8(patched, AcpiBuildState),
3001 VMSTATE_END_OF_LIST()
3002 },
3003 };
3004
3005 void acpi_setup(void)
3006 {
3007 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
3008 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
3009 X86MachineState *x86ms = X86_MACHINE(pcms);
3010 AcpiBuildTables tables;
3011 AcpiBuildState *build_state;
3012 Object *vmgenid_dev;
3013 TPMIf *tpm;
3014 static FwCfgTPMConfig tpm_config;
3015
3016 if (!x86ms->fw_cfg) {
3017 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
3018 return;
3019 }
3020
3021 if (!pcms->acpi_build_enabled) {
3022 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
3023 return;
3024 }
3025
3026 if (!acpi_enabled) {
3027 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
3028 return;
3029 }
3030
3031 build_state = g_malloc0(sizeof *build_state);
3032
3033 acpi_build_tables_init(&tables);
3034 acpi_build(&tables, MACHINE(pcms));
3035
3036 /* Now expose it all to Guest */
3037 build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
3038 build_state, tables.table_data,
3039 ACPI_BUILD_TABLE_FILE,
3040 ACPI_BUILD_TABLE_MAX_SIZE);
3041 assert(build_state->table_mr != NULL);
3042
3043 build_state->linker_mr =
3044 acpi_add_rom_blob(acpi_build_update, build_state,
3045 tables.linker->cmd_blob, "etc/table-loader", 0);
3046
3047 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
3048 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
3049
3050 tpm = tpm_find();
3051 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
3052 tpm_config = (FwCfgTPMConfig) {
3053 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
3054 .tpm_version = tpm_get_version(tpm),
3055 .tpmppi_version = TPM_PPI_VERSION_1_30
3056 };
3057 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
3058 &tpm_config, sizeof tpm_config);
3059 }
3060
3061 vmgenid_dev = find_vmgenid_dev();
3062 if (vmgenid_dev) {
3063 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
3064 tables.vmgenid);
3065 }
3066
3067 if (!pcmc->rsdp_in_ram) {
3068 /*
3069 * Keep for compatibility with old machine types.
3070 * Though RSDP is small, its contents isn't immutable, so
3071 * we'll update it along with the rest of tables on guest access.
3072 */
3073 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
3074
3075 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
3076 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE,
3077 acpi_build_update, NULL, build_state,
3078 build_state->rsdp, rsdp_size, true);
3079 build_state->rsdp_mr = NULL;
3080 } else {
3081 build_state->rsdp = NULL;
3082 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
3083 build_state, tables.rsdp,
3084 ACPI_BUILD_RSDP_FILE, 0);
3085 }
3086
3087 qemu_register_reset(acpi_build_reset, build_state);
3088 acpi_build_reset(build_state);
3089 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
3090
3091 /* Cleanup tables but don't free the memory: we track it
3092 * in build_state.
3093 */
3094 acpi_build_tables_cleanup(&tables, false);
3095 }
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