1 /* Support for generating ACPI tables and passing them to Guests
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
7 * Author: Michael S. Tsirkin <mst@redhat.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "acpi-build.h"
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
31 #include "hw/i386/pc.h"
32 #include "target/i386/cpu.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/acpi/cpu.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "sysemu/tpm_backend.h"
46 #include "hw/timer/mc146818rtc_regs.h"
47 #include "sysemu/numa.h"
49 /* Supported chipsets: */
50 #include "hw/acpi/piix4.h"
51 #include "hw/acpi/pcihp.h"
52 #include "hw/i386/ich9.h"
53 #include "hw/pci/pci_bus.h"
54 #include "hw/pci-host/q35.h"
55 #include "hw/i386/x86-iommu.h"
57 #include "hw/acpi/aml-build.h"
59 #include "qapi/qmp/qint.h"
60 #include "qom/qom-qobject.h"
61 #include "hw/i386/amd_iommu.h"
62 #include "hw/i386/intel_iommu.h"
64 #include "hw/acpi/ipmi.h"
66 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
67 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
68 * a little bit, there should be plenty of free space since the DSDT
69 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
71 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
72 #define ACPI_BUILD_ALIGN_SIZE 0x1000
74 #define ACPI_BUILD_TABLE_SIZE 0x20000
76 /* #define DEBUG_ACPI_BUILD */
77 #ifdef DEBUG_ACPI_BUILD
78 #define ACPI_BUILD_DPRINTF(fmt, ...) \
79 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
81 #define ACPI_BUILD_DPRINTF(fmt, ...)
84 /* Default IOAPIC ID */
85 #define ACPI_BUILD_IOAPIC_ID 0x0
87 typedef struct AcpiMcfgInfo
{
92 typedef struct AcpiPmInfo
{
98 uint8_t acpi_enable_cmd
;
99 uint8_t acpi_disable_cmd
;
101 uint32_t gpe0_blk_len
;
103 uint16_t cpu_hp_io_base
;
104 uint16_t pcihp_io_base
;
105 uint16_t pcihp_io_len
;
108 typedef struct AcpiMiscInfo
{
111 TPMVersion tpm_version
;
112 const unsigned char *dsdt_code
;
114 uint16_t pvpanic_port
;
115 uint16_t applesmc_io_base
;
118 typedef struct AcpiBuildPciBusHotplugState
{
119 GArray
*device_table
;
120 GArray
*notify_table
;
121 struct AcpiBuildPciBusHotplugState
*parent
;
122 bool pcihp_bridge_en
;
123 } AcpiBuildPciBusHotplugState
;
125 static void acpi_get_pm_info(AcpiPmInfo
*pm
)
127 Object
*piix
= piix4_pm_find();
128 Object
*lpc
= ich9_lpc_find();
132 pm
->cpu_hp_io_base
= 0;
133 pm
->pcihp_io_base
= 0;
134 pm
->pcihp_io_len
= 0;
137 pm
->cpu_hp_io_base
= PIIX4_CPU_HOTPLUG_IO_BASE
;
139 object_property_get_int(obj
, ACPI_PCIHP_IO_BASE_PROP
, NULL
);
141 object_property_get_int(obj
, ACPI_PCIHP_IO_LEN_PROP
, NULL
);
145 pm
->cpu_hp_io_base
= ICH9_CPU_HOTPLUG_IO_BASE
;
149 /* Fill in optional s3/s4 related properties */
150 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S3_DISABLED
, NULL
);
152 pm
->s3_disabled
= qint_get_int(qobject_to_qint(o
));
154 pm
->s3_disabled
= false;
157 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_DISABLED
, NULL
);
159 pm
->s4_disabled
= qint_get_int(qobject_to_qint(o
));
161 pm
->s4_disabled
= false;
164 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_VAL
, NULL
);
166 pm
->s4_val
= qint_get_int(qobject_to_qint(o
));
172 /* Fill in mandatory properties */
173 pm
->sci_int
= object_property_get_int(obj
, ACPI_PM_PROP_SCI_INT
, NULL
);
175 pm
->acpi_enable_cmd
= object_property_get_int(obj
,
176 ACPI_PM_PROP_ACPI_ENABLE_CMD
,
178 pm
->acpi_disable_cmd
= object_property_get_int(obj
,
179 ACPI_PM_PROP_ACPI_DISABLE_CMD
,
181 pm
->io_base
= object_property_get_int(obj
, ACPI_PM_PROP_PM_IO_BASE
,
183 pm
->gpe0_blk
= object_property_get_int(obj
, ACPI_PM_PROP_GPE0_BLK
,
185 pm
->gpe0_blk_len
= object_property_get_int(obj
, ACPI_PM_PROP_GPE0_BLK_LEN
,
187 pm
->pcihp_bridge_en
=
188 object_property_get_bool(obj
, "acpi-pci-hotplug-with-bridge-support",
192 static void acpi_get_misc_info(AcpiMiscInfo
*info
)
194 Object
*piix
= piix4_pm_find();
195 Object
*lpc
= ich9_lpc_find();
196 assert(!!piix
!= !!lpc
);
199 info
->is_piix4
= true;
202 info
->is_piix4
= false;
205 info
->has_hpet
= hpet_find();
206 info
->tpm_version
= tpm_get_version();
207 info
->pvpanic_port
= pvpanic_port();
208 info
->applesmc_io_base
= applesmc_port();
212 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
213 * On i386 arch we only have two pci hosts, so we can look only for them.
215 static Object
*acpi_get_i386_pci_host(void)
219 host
= OBJECT_CHECK(PCIHostState
,
220 object_resolve_path("/machine/i440fx", NULL
),
221 TYPE_PCI_HOST_BRIDGE
);
223 host
= OBJECT_CHECK(PCIHostState
,
224 object_resolve_path("/machine/q35", NULL
),
225 TYPE_PCI_HOST_BRIDGE
);
231 static void acpi_get_pci_holes(Range
*hole
, Range
*hole64
)
235 pci_host
= acpi_get_i386_pci_host();
238 range_set_bounds1(hole
,
239 object_property_get_int(pci_host
,
240 PCI_HOST_PROP_PCI_HOLE_START
,
242 object_property_get_int(pci_host
,
243 PCI_HOST_PROP_PCI_HOLE_END
,
245 range_set_bounds1(hole64
,
246 object_property_get_int(pci_host
,
247 PCI_HOST_PROP_PCI_HOLE64_START
,
249 object_property_get_int(pci_host
,
250 PCI_HOST_PROP_PCI_HOLE64_END
,
254 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
256 static void acpi_align_size(GArray
*blob
, unsigned align
)
258 /* Align size to multiple of given size. This reduces the chance
259 * we need to change size in the future (breaking cross version migration).
261 g_array_set_size(blob
, ROUND_UP(acpi_data_len(blob
), align
));
266 build_facs(GArray
*table_data
, BIOSLinker
*linker
)
268 AcpiFacsDescriptorRev1
*facs
= acpi_data_push(table_data
, sizeof *facs
);
269 memcpy(&facs
->signature
, "FACS", 4);
270 facs
->length
= cpu_to_le32(sizeof(*facs
));
273 /* Load chipset information in FADT */
274 static void fadt_setup(AcpiFadtDescriptorRev1
*fadt
, AcpiPmInfo
*pm
)
278 fadt
->sci_int
= cpu_to_le16(pm
->sci_int
);
279 fadt
->smi_cmd
= cpu_to_le32(ACPI_PORT_SMI_CMD
);
280 fadt
->acpi_enable
= pm
->acpi_enable_cmd
;
281 fadt
->acpi_disable
= pm
->acpi_disable_cmd
;
282 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
283 fadt
->pm1a_evt_blk
= cpu_to_le32(pm
->io_base
);
284 fadt
->pm1a_cnt_blk
= cpu_to_le32(pm
->io_base
+ 0x04);
285 fadt
->pm_tmr_blk
= cpu_to_le32(pm
->io_base
+ 0x08);
286 fadt
->gpe0_blk
= cpu_to_le32(pm
->gpe0_blk
);
287 /* EVT, CNT, TMR length matches hw/acpi/core.c */
288 fadt
->pm1_evt_len
= 4;
289 fadt
->pm1_cnt_len
= 2;
290 fadt
->pm_tmr_len
= 4;
291 fadt
->gpe0_blk_len
= pm
->gpe0_blk_len
;
292 fadt
->plvl2_lat
= cpu_to_le16(0xfff); /* C2 state not supported */
293 fadt
->plvl3_lat
= cpu_to_le16(0xfff); /* C3 state not supported */
294 fadt
->flags
= cpu_to_le32((1 << ACPI_FADT_F_WBINVD
) |
295 (1 << ACPI_FADT_F_PROC_C1
) |
296 (1 << ACPI_FADT_F_SLP_BUTTON
) |
297 (1 << ACPI_FADT_F_RTC_S4
));
298 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK
);
299 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
300 * For more than 8 CPUs, "Clustered Logical" mode has to be used
303 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL
);
305 fadt
->century
= RTC_CENTURY
;
311 build_fadt(GArray
*table_data
, BIOSLinker
*linker
, AcpiPmInfo
*pm
,
312 unsigned facs_tbl_offset
, unsigned dsdt_tbl_offset
,
313 const char *oem_id
, const char *oem_table_id
)
315 AcpiFadtDescriptorRev1
*fadt
= acpi_data_push(table_data
, sizeof(*fadt
));
316 unsigned fw_ctrl_offset
= (char *)&fadt
->firmware_ctrl
- table_data
->data
;
317 unsigned dsdt_entry_offset
= (char *)&fadt
->dsdt
- table_data
->data
;
319 /* FACS address to be filled by Guest linker */
320 bios_linker_loader_add_pointer(linker
,
321 ACPI_BUILD_TABLE_FILE
, fw_ctrl_offset
, sizeof(fadt
->firmware_ctrl
),
322 ACPI_BUILD_TABLE_FILE
, facs_tbl_offset
);
324 /* DSDT address to be filled by Guest linker */
325 fadt_setup(fadt
, pm
);
326 bios_linker_loader_add_pointer(linker
,
327 ACPI_BUILD_TABLE_FILE
, dsdt_entry_offset
, sizeof(fadt
->dsdt
),
328 ACPI_BUILD_TABLE_FILE
, dsdt_tbl_offset
);
330 build_header(linker
, table_data
,
331 (void *)fadt
, "FACP", sizeof(*fadt
), 1, oem_id
, oem_table_id
);
334 void pc_madt_cpu_entry(AcpiDeviceIf
*adev
, int uid
,
335 CPUArchIdList
*apic_ids
, GArray
*entry
)
337 uint32_t apic_id
= apic_ids
->cpus
[uid
].arch_id
;
339 /* ACPI spec says that LAPIC entry for non present
340 * CPU may be omitted from MADT or it must be marked
341 * as disabled. However omitting non present CPU from
342 * MADT breaks hotplug on linux. So possible CPUs
343 * should be put in MADT but kept disabled.
346 AcpiMadtProcessorApic
*apic
= acpi_data_push(entry
, sizeof *apic
);
348 apic
->type
= ACPI_APIC_PROCESSOR
;
349 apic
->length
= sizeof(*apic
);
350 apic
->processor_id
= uid
;
351 apic
->local_apic_id
= apic_id
;
352 if (apic_ids
->cpus
[uid
].cpu
!= NULL
) {
353 apic
->flags
= cpu_to_le32(1);
355 apic
->flags
= cpu_to_le32(0);
358 AcpiMadtProcessorX2Apic
*apic
= acpi_data_push(entry
, sizeof *apic
);
360 apic
->type
= ACPI_APIC_LOCAL_X2APIC
;
361 apic
->length
= sizeof(*apic
);
362 apic
->uid
= cpu_to_le32(uid
);
363 apic
->x2apic_id
= cpu_to_le32(apic_id
);
364 if (apic_ids
->cpus
[uid
].cpu
!= NULL
) {
365 apic
->flags
= cpu_to_le32(1);
367 apic
->flags
= cpu_to_le32(0);
373 build_madt(GArray
*table_data
, BIOSLinker
*linker
, PCMachineState
*pcms
)
375 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
376 CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(MACHINE(pcms
));
377 int madt_start
= table_data
->len
;
378 AcpiDeviceIfClass
*adevc
= ACPI_DEVICE_IF_GET_CLASS(pcms
->acpi_dev
);
379 AcpiDeviceIf
*adev
= ACPI_DEVICE_IF(pcms
->acpi_dev
);
380 bool x2apic_mode
= false;
382 AcpiMultipleApicTable
*madt
;
383 AcpiMadtIoApic
*io_apic
;
384 AcpiMadtIntsrcovr
*intsrcovr
;
387 madt
= acpi_data_push(table_data
, sizeof *madt
);
388 madt
->local_apic_address
= cpu_to_le32(APIC_DEFAULT_ADDRESS
);
389 madt
->flags
= cpu_to_le32(1);
391 for (i
= 0; i
< apic_ids
->len
; i
++) {
392 adevc
->madt_cpu(adev
, i
, apic_ids
, table_data
);
393 if (apic_ids
->cpus
[i
].arch_id
> 254) {
399 io_apic
= acpi_data_push(table_data
, sizeof *io_apic
);
400 io_apic
->type
= ACPI_APIC_IO
;
401 io_apic
->length
= sizeof(*io_apic
);
402 io_apic
->io_apic_id
= ACPI_BUILD_IOAPIC_ID
;
403 io_apic
->address
= cpu_to_le32(IO_APIC_DEFAULT_ADDRESS
);
404 io_apic
->interrupt
= cpu_to_le32(0);
406 if (pcms
->apic_xrupt_override
) {
407 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
408 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
409 intsrcovr
->length
= sizeof(*intsrcovr
);
410 intsrcovr
->source
= 0;
411 intsrcovr
->gsi
= cpu_to_le32(2);
412 intsrcovr
->flags
= cpu_to_le16(0); /* conforms to bus specifications */
414 for (i
= 1; i
< 16; i
++) {
415 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
416 if (!(ACPI_BUILD_PCI_IRQS
& (1 << i
))) {
417 /* No need for a INT source override structure. */
420 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
421 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
422 intsrcovr
->length
= sizeof(*intsrcovr
);
423 intsrcovr
->source
= i
;
424 intsrcovr
->gsi
= cpu_to_le32(i
);
425 intsrcovr
->flags
= cpu_to_le16(0xd); /* active high, level triggered */
429 AcpiMadtLocalX2ApicNmi
*local_nmi
;
431 local_nmi
= acpi_data_push(table_data
, sizeof *local_nmi
);
432 local_nmi
->type
= ACPI_APIC_LOCAL_X2APIC_NMI
;
433 local_nmi
->length
= sizeof(*local_nmi
);
434 local_nmi
->uid
= 0xFFFFFFFF; /* all processors */
435 local_nmi
->flags
= cpu_to_le16(0);
436 local_nmi
->lint
= 1; /* ACPI_LINT1 */
438 AcpiMadtLocalNmi
*local_nmi
;
440 local_nmi
= acpi_data_push(table_data
, sizeof *local_nmi
);
441 local_nmi
->type
= ACPI_APIC_LOCAL_NMI
;
442 local_nmi
->length
= sizeof(*local_nmi
);
443 local_nmi
->processor_id
= 0xff; /* all processors */
444 local_nmi
->flags
= cpu_to_le16(0);
445 local_nmi
->lint
= 1; /* ACPI_LINT1 */
448 build_header(linker
, table_data
,
449 (void *)(table_data
->data
+ madt_start
), "APIC",
450 table_data
->len
- madt_start
, 1, NULL
, NULL
);
453 /* Assign BSEL property to all buses. In the future, this can be changed
454 * to only assign to buses that support hotplug.
456 static void *acpi_set_bsel(PCIBus
*bus
, void *opaque
)
458 unsigned *bsel_alloc
= opaque
;
461 if (qbus_is_hotpluggable(BUS(bus
))) {
462 bus_bsel
= g_malloc(sizeof *bus_bsel
);
464 *bus_bsel
= (*bsel_alloc
)++;
465 object_property_add_uint32_ptr(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
,
472 static void acpi_set_pci_info(void)
474 PCIBus
*bus
= find_i440fx(); /* TODO: Q35 support */
475 unsigned bsel_alloc
= 0;
478 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
479 pci_for_each_bus_depth_first(bus
, acpi_set_bsel
, NULL
, &bsel_alloc
);
483 static void build_append_pcihp_notify_entry(Aml
*method
, int slot
)
486 int32_t devfn
= PCI_DEVFN(slot
, 0);
488 if_ctx
= aml_if(aml_and(aml_arg(0), aml_int(0x1U
<< slot
), NULL
));
489 aml_append(if_ctx
, aml_notify(aml_name("S%.02X", devfn
), aml_arg(1)));
490 aml_append(method
, if_ctx
);
493 static void build_append_pci_bus_devices(Aml
*parent_scope
, PCIBus
*bus
,
494 bool pcihp_bridge_en
)
496 Aml
*dev
, *notify_method
, *method
;
501 bsel
= object_property_get_qobject(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
, NULL
);
503 int64_t bsel_val
= qint_get_int(qobject_to_qint(bsel
));
505 aml_append(parent_scope
, aml_name_decl("BSEL", aml_int(bsel_val
)));
506 notify_method
= aml_method("DVNT", 2, AML_NOTSERIALIZED
);
509 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); i
+= PCI_FUNC_MAX
) {
512 PCIDevice
*pdev
= bus
->devices
[i
];
513 int slot
= PCI_SLOT(i
);
514 bool hotplug_enabled_dev
;
518 if (bsel
) { /* add hotplug slots for non present devices */
519 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
520 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
521 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
522 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
524 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
526 aml_append(dev
, method
);
527 aml_append(parent_scope
, dev
);
529 build_append_pcihp_notify_entry(notify_method
, slot
);
534 pc
= PCI_DEVICE_GET_CLASS(pdev
);
535 dc
= DEVICE_GET_CLASS(pdev
);
537 /* When hotplug for bridges is enabled, bridges are
538 * described in ACPI separately (see build_pci_bus_end).
539 * In this case they aren't themselves hot-pluggable.
540 * Hotplugged bridges *are* hot-pluggable.
542 bridge_in_acpi
= pc
->is_bridge
&& pcihp_bridge_en
&&
543 !DEVICE(pdev
)->hotplugged
;
545 hotplug_enabled_dev
= bsel
&& dc
->hotpluggable
&& !bridge_in_acpi
;
547 if (pc
->class_id
== PCI_CLASS_BRIDGE_ISA
) {
551 /* start to compose PCI slot descriptor */
552 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
553 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
555 if (pc
->class_id
== PCI_CLASS_DISPLAY_VGA
) {
556 /* add VGA specific AML methods */
559 if (object_dynamic_cast(OBJECT(pdev
), "qxl-vga")) {
565 method
= aml_method("_S1D", 0, AML_NOTSERIALIZED
);
566 aml_append(method
, aml_return(aml_int(0)));
567 aml_append(dev
, method
);
569 method
= aml_method("_S2D", 0, AML_NOTSERIALIZED
);
570 aml_append(method
, aml_return(aml_int(0)));
571 aml_append(dev
, method
);
573 method
= aml_method("_S3D", 0, AML_NOTSERIALIZED
);
574 aml_append(method
, aml_return(aml_int(s3d
)));
575 aml_append(dev
, method
);
576 } else if (hotplug_enabled_dev
) {
577 /* add _SUN/_EJ0 to make slot hotpluggable */
578 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
580 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
582 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
584 aml_append(dev
, method
);
587 build_append_pcihp_notify_entry(notify_method
, slot
);
589 } else if (bridge_in_acpi
) {
591 * device is coldplugged bridge,
592 * add child device descriptions into its scope
594 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
596 build_append_pci_bus_devices(dev
, sec_bus
, pcihp_bridge_en
);
598 /* slot descriptor has been composed, add it into parent context */
599 aml_append(parent_scope
, dev
);
603 aml_append(parent_scope
, notify_method
);
606 /* Append PCNT method to notify about events on local and child buses.
607 * Add unconditionally for root since DSDT expects it.
609 method
= aml_method("PCNT", 0, AML_NOTSERIALIZED
);
611 /* If bus supports hotplug select it and notify about local events */
613 int64_t bsel_val
= qint_get_int(qobject_to_qint(bsel
));
614 aml_append(method
, aml_store(aml_int(bsel_val
), aml_name("BNUM")));
616 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
619 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
623 /* Notify about child bus events in any case */
624 if (pcihp_bridge_en
) {
625 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
626 int32_t devfn
= sec
->parent_dev
->devfn
;
628 if (pci_bus_is_root(sec
) || pci_bus_is_express(sec
)) {
632 aml_append(method
, aml_name("^S%.02X.PCNT", devfn
));
635 aml_append(parent_scope
, method
);
636 qobject_decref(bsel
);
641 * @link_name: link name for PCI route entry
643 * build AML package containing a PCI route entry for @link_name
645 static Aml
*build_prt_entry(const char *link_name
)
647 Aml
*a_zero
= aml_int(0);
648 Aml
*pkg
= aml_package(4);
649 aml_append(pkg
, a_zero
);
650 aml_append(pkg
, a_zero
);
651 aml_append(pkg
, aml_name("%s", link_name
));
652 aml_append(pkg
, a_zero
);
657 * initialize_route - Initialize the interrupt routing rule
658 * through a specific LINK:
659 * if (lnk_idx == idx)
660 * route using link 'link_name'
662 static Aml
*initialize_route(Aml
*route
, const char *link_name
,
663 Aml
*lnk_idx
, int idx
)
665 Aml
*if_ctx
= aml_if(aml_equal(lnk_idx
, aml_int(idx
)));
666 Aml
*pkg
= build_prt_entry(link_name
);
668 aml_append(if_ctx
, aml_store(pkg
, route
));
674 * build_prt - Define interrupt rounting rules
676 * Returns an array of 128 routes, one for each device,
677 * based on device location.
678 * The main goal is to equaly distribute the interrupts
679 * over the 4 existing ACPI links (works only for i440fx).
680 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
683 static Aml
*build_prt(bool is_pci0_prt
)
685 Aml
*method
, *while_ctx
, *pin
, *res
;
687 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
690 aml_append(method
, aml_store(aml_package(128), res
));
691 aml_append(method
, aml_store(aml_int(0), pin
));
693 /* while (pin < 128) */
694 while_ctx
= aml_while(aml_lless(pin
, aml_int(128)));
696 Aml
*slot
= aml_local(2);
697 Aml
*lnk_idx
= aml_local(3);
698 Aml
*route
= aml_local(4);
700 /* slot = pin >> 2 */
701 aml_append(while_ctx
,
702 aml_store(aml_shiftright(pin
, aml_int(2), NULL
), slot
));
703 /* lnk_idx = (slot + pin) & 3 */
704 aml_append(while_ctx
,
705 aml_store(aml_and(aml_add(pin
, slot
, NULL
), aml_int(3), NULL
),
708 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
709 aml_append(while_ctx
, initialize_route(route
, "LNKD", lnk_idx
, 0));
711 Aml
*if_device_1
, *if_pin_4
, *else_pin_4
;
713 /* device 1 is the power-management device, needs SCI */
714 if_device_1
= aml_if(aml_equal(lnk_idx
, aml_int(1)));
716 if_pin_4
= aml_if(aml_equal(pin
, aml_int(4)));
719 aml_store(build_prt_entry("LNKS"), route
));
721 aml_append(if_device_1
, if_pin_4
);
722 else_pin_4
= aml_else();
724 aml_append(else_pin_4
,
725 aml_store(build_prt_entry("LNKA"), route
));
727 aml_append(if_device_1
, else_pin_4
);
729 aml_append(while_ctx
, if_device_1
);
731 aml_append(while_ctx
, initialize_route(route
, "LNKA", lnk_idx
, 1));
733 aml_append(while_ctx
, initialize_route(route
, "LNKB", lnk_idx
, 2));
734 aml_append(while_ctx
, initialize_route(route
, "LNKC", lnk_idx
, 3));
736 /* route[0] = 0x[slot]FFFF */
737 aml_append(while_ctx
,
738 aml_store(aml_or(aml_shiftleft(slot
, aml_int(16)), aml_int(0xFFFF),
740 aml_index(route
, aml_int(0))));
741 /* route[1] = pin & 3 */
742 aml_append(while_ctx
,
743 aml_store(aml_and(pin
, aml_int(3), NULL
),
744 aml_index(route
, aml_int(1))));
745 /* res[pin] = route */
746 aml_append(while_ctx
, aml_store(route
, aml_index(res
, pin
)));
748 aml_append(while_ctx
, aml_increment(pin
));
750 aml_append(method
, while_ctx
);
752 aml_append(method
, aml_return(res
));
757 typedef struct CrsRangeEntry
{
762 static void crs_range_insert(GPtrArray
*ranges
, uint64_t base
, uint64_t limit
)
764 CrsRangeEntry
*entry
;
766 entry
= g_malloc(sizeof(*entry
));
768 entry
->limit
= limit
;
770 g_ptr_array_add(ranges
, entry
);
773 static void crs_range_free(gpointer data
)
775 CrsRangeEntry
*entry
= (CrsRangeEntry
*)data
;
779 typedef struct CrsRangeSet
{
780 GPtrArray
*io_ranges
;
781 GPtrArray
*mem_ranges
;
782 GPtrArray
*mem_64bit_ranges
;
785 static void crs_range_set_init(CrsRangeSet
*range_set
)
787 range_set
->io_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
788 range_set
->mem_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
789 range_set
->mem_64bit_ranges
=
790 g_ptr_array_new_with_free_func(crs_range_free
);
793 static void crs_range_set_free(CrsRangeSet
*range_set
)
795 g_ptr_array_free(range_set
->io_ranges
, true);
796 g_ptr_array_free(range_set
->mem_ranges
, true);
797 g_ptr_array_free(range_set
->mem_64bit_ranges
, true);
800 static gint
crs_range_compare(gconstpointer a
, gconstpointer b
)
802 CrsRangeEntry
*entry_a
= *(CrsRangeEntry
**)a
;
803 CrsRangeEntry
*entry_b
= *(CrsRangeEntry
**)b
;
805 return (int64_t)entry_a
->base
- (int64_t)entry_b
->base
;
809 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
810 * interval, computes the 'free' ranges from the same interval.
811 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
812 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
814 static void crs_replace_with_free_ranges(GPtrArray
*ranges
,
815 uint64_t start
, uint64_t end
)
817 GPtrArray
*free_ranges
= g_ptr_array_new();
818 uint64_t free_base
= start
;
821 g_ptr_array_sort(ranges
, crs_range_compare
);
822 for (i
= 0; i
< ranges
->len
; i
++) {
823 CrsRangeEntry
*used
= g_ptr_array_index(ranges
, i
);
825 if (free_base
< used
->base
) {
826 crs_range_insert(free_ranges
, free_base
, used
->base
- 1);
829 free_base
= used
->limit
+ 1;
832 if (free_base
< end
) {
833 crs_range_insert(free_ranges
, free_base
, end
);
836 g_ptr_array_set_size(ranges
, 0);
837 for (i
= 0; i
< free_ranges
->len
; i
++) {
838 g_ptr_array_add(ranges
, g_ptr_array_index(free_ranges
, i
));
841 g_ptr_array_free(free_ranges
, true);
845 * crs_range_merge - merges adjacent ranges in the given array.
846 * Array elements are deleted and replaced with the merged ranges.
848 static void crs_range_merge(GPtrArray
*range
)
850 GPtrArray
*tmp
= g_ptr_array_new_with_free_func(crs_range_free
);
851 CrsRangeEntry
*entry
;
852 uint64_t range_base
, range_limit
;
859 g_ptr_array_sort(range
, crs_range_compare
);
861 entry
= g_ptr_array_index(range
, 0);
862 range_base
= entry
->base
;
863 range_limit
= entry
->limit
;
864 for (i
= 1; i
< range
->len
; i
++) {
865 entry
= g_ptr_array_index(range
, i
);
866 if (entry
->base
- 1 == range_limit
) {
867 range_limit
= entry
->limit
;
869 crs_range_insert(tmp
, range_base
, range_limit
);
870 range_base
= entry
->base
;
871 range_limit
= entry
->limit
;
874 crs_range_insert(tmp
, range_base
, range_limit
);
876 g_ptr_array_set_size(range
, 0);
877 for (i
= 0; i
< tmp
->len
; i
++) {
878 entry
= g_ptr_array_index(tmp
, i
);
879 crs_range_insert(range
, entry
->base
, entry
->limit
);
881 g_ptr_array_free(tmp
, true);
884 static Aml
*build_crs(PCIHostState
*host
, CrsRangeSet
*range_set
)
886 Aml
*crs
= aml_resource_template();
887 CrsRangeSet temp_range_set
;
888 CrsRangeEntry
*entry
;
889 uint8_t max_bus
= pci_bus_num(host
->bus
);
894 crs_range_set_init(&temp_range_set
);
895 for (devfn
= 0; devfn
< ARRAY_SIZE(host
->bus
->devices
); devfn
++) {
896 uint64_t range_base
, range_limit
;
897 PCIDevice
*dev
= host
->bus
->devices
[devfn
];
903 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
904 PCIIORegion
*r
= &dev
->io_regions
[i
];
906 range_base
= r
->addr
;
907 range_limit
= r
->addr
+ r
->size
- 1;
910 * Work-around for old bioses
911 * that do not support multiple root buses
913 if (!range_base
|| range_base
> range_limit
) {
917 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
918 crs_range_insert(temp_range_set
.io_ranges
,
919 range_base
, range_limit
);
920 } else { /* "memory" */
921 crs_range_insert(temp_range_set
.mem_ranges
,
922 range_base
, range_limit
);
926 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
927 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
928 uint8_t subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
929 if (subordinate
> max_bus
) {
930 max_bus
= subordinate
;
933 range_base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
934 range_limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
937 * Work-around for old bioses
938 * that do not support multiple root buses
940 if (range_base
&& range_base
<= range_limit
) {
941 crs_range_insert(temp_range_set
.io_ranges
,
942 range_base
, range_limit
);
946 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
948 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
951 * Work-around for old bioses
952 * that do not support multiple root buses
954 if (range_base
&& range_base
<= range_limit
) {
955 uint64_t length
= range_limit
- range_base
+ 1;
956 if (range_limit
<= UINT32_MAX
&& length
<= UINT32_MAX
) {
957 crs_range_insert(temp_range_set
.mem_ranges
,
958 range_base
, range_limit
);
960 crs_range_insert(temp_range_set
.mem_64bit_ranges
,
961 range_base
, range_limit
);
966 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
968 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
971 * Work-around for old bioses
972 * that do not support multiple root buses
974 if (range_base
&& range_base
<= range_limit
) {
975 uint64_t length
= range_limit
- range_base
+ 1;
976 if (range_limit
<= UINT32_MAX
&& length
<= UINT32_MAX
) {
977 crs_range_insert(temp_range_set
.mem_ranges
,
978 range_base
, range_limit
);
980 crs_range_insert(temp_range_set
.mem_64bit_ranges
,
981 range_base
, range_limit
);
987 crs_range_merge(temp_range_set
.io_ranges
);
988 for (i
= 0; i
< temp_range_set
.io_ranges
->len
; i
++) {
989 entry
= g_ptr_array_index(temp_range_set
.io_ranges
, i
);
991 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
992 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
993 0, entry
->base
, entry
->limit
, 0,
994 entry
->limit
- entry
->base
+ 1));
995 crs_range_insert(range_set
->io_ranges
, entry
->base
, entry
->limit
);
998 crs_range_merge(temp_range_set
.mem_ranges
);
999 for (i
= 0; i
< temp_range_set
.mem_ranges
->len
; i
++) {
1000 entry
= g_ptr_array_index(temp_range_set
.mem_ranges
, i
);
1002 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
1003 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
1005 0, entry
->base
, entry
->limit
, 0,
1006 entry
->limit
- entry
->base
+ 1));
1007 crs_range_insert(range_set
->mem_ranges
, entry
->base
, entry
->limit
);
1010 crs_range_merge(temp_range_set
.mem_64bit_ranges
);
1011 for (i
= 0; i
< temp_range_set
.mem_64bit_ranges
->len
; i
++) {
1012 entry
= g_ptr_array_index(temp_range_set
.mem_64bit_ranges
, i
);
1014 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
1015 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
1017 0, entry
->base
, entry
->limit
, 0,
1018 entry
->limit
- entry
->base
+ 1));
1019 crs_range_insert(range_set
->mem_64bit_ranges
,
1020 entry
->base
, entry
->limit
);
1023 crs_range_set_free(&temp_range_set
);
1026 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
1028 pci_bus_num(host
->bus
),
1031 max_bus
- pci_bus_num(host
->bus
) + 1));
1036 static void build_hpet_aml(Aml
*table
)
1042 Aml
*scope
= aml_scope("_SB");
1043 Aml
*dev
= aml_device("HPET");
1044 Aml
*zero
= aml_int(0);
1045 Aml
*id
= aml_local(0);
1046 Aml
*period
= aml_local(1);
1048 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1049 aml_append(dev
, aml_name_decl("_UID", zero
));
1052 aml_operation_region("HPTM", AML_SYSTEM_MEMORY
, aml_int(HPET_BASE
),
1054 field
= aml_field("HPTM", AML_DWORD_ACC
, AML_LOCK
, AML_PRESERVE
);
1055 aml_append(field
, aml_named_field("VEND", 32));
1056 aml_append(field
, aml_named_field("PRD", 32));
1057 aml_append(dev
, field
);
1059 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1060 aml_append(method
, aml_store(aml_name("VEND"), id
));
1061 aml_append(method
, aml_store(aml_name("PRD"), period
));
1062 aml_append(method
, aml_shiftright(id
, aml_int(16), id
));
1063 if_ctx
= aml_if(aml_lor(aml_equal(id
, zero
),
1064 aml_equal(id
, aml_int(0xffff))));
1066 aml_append(if_ctx
, aml_return(zero
));
1068 aml_append(method
, if_ctx
);
1070 if_ctx
= aml_if(aml_lor(aml_equal(period
, zero
),
1071 aml_lgreater(period
, aml_int(100000000))));
1073 aml_append(if_ctx
, aml_return(zero
));
1075 aml_append(method
, if_ctx
);
1077 aml_append(method
, aml_return(aml_int(0x0F)));
1078 aml_append(dev
, method
);
1080 crs
= aml_resource_template();
1081 aml_append(crs
, aml_memory32_fixed(HPET_BASE
, HPET_LEN
, AML_READ_ONLY
));
1082 aml_append(dev
, aml_name_decl("_CRS", crs
));
1084 aml_append(scope
, dev
);
1085 aml_append(table
, scope
);
1088 static Aml
*build_fdinfo_aml(int idx
, FloppyDriveType type
)
1091 uint8_t maxc
, maxh
, maxs
;
1093 isa_fdc_get_drive_max_chs(type
, &maxc
, &maxh
, &maxs
);
1095 dev
= aml_device("FLP%c", 'A' + idx
);
1097 aml_append(dev
, aml_name_decl("_ADR", aml_int(idx
)));
1099 fdi
= aml_package(16);
1100 aml_append(fdi
, aml_int(idx
)); /* Drive Number */
1102 aml_int(cmos_get_fd_drive_type(type
))); /* Device Type */
1104 * the values below are the limits of the drive, and are thus independent
1105 * of the inserted media
1107 aml_append(fdi
, aml_int(maxc
)); /* Maximum Cylinder Number */
1108 aml_append(fdi
, aml_int(maxs
)); /* Maximum Sector Number */
1109 aml_append(fdi
, aml_int(maxh
)); /* Maximum Head Number */
1111 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1112 * the drive type, so shall we
1114 aml_append(fdi
, aml_int(0xAF)); /* disk_specify_1 */
1115 aml_append(fdi
, aml_int(0x02)); /* disk_specify_2 */
1116 aml_append(fdi
, aml_int(0x25)); /* disk_motor_wait */
1117 aml_append(fdi
, aml_int(0x02)); /* disk_sector_siz */
1118 aml_append(fdi
, aml_int(0x12)); /* disk_eot */
1119 aml_append(fdi
, aml_int(0x1B)); /* disk_rw_gap */
1120 aml_append(fdi
, aml_int(0xFF)); /* disk_dtl */
1121 aml_append(fdi
, aml_int(0x6C)); /* disk_formt_gap */
1122 aml_append(fdi
, aml_int(0xF6)); /* disk_fill */
1123 aml_append(fdi
, aml_int(0x0F)); /* disk_head_sttl */
1124 aml_append(fdi
, aml_int(0x08)); /* disk_motor_strt */
1126 aml_append(dev
, aml_name_decl("_FDI", fdi
));
1130 static Aml
*build_fdc_device_aml(ISADevice
*fdc
)
1136 #define ACPI_FDE_MAX_FD 4
1137 uint32_t fde_buf
[5] = {
1138 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1139 cpu_to_le32(2) /* tape presence (2 == never present) */
1142 dev
= aml_device("FDC0");
1143 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1145 crs
= aml_resource_template();
1146 aml_append(crs
, aml_io(AML_DECODE16
, 0x03F2, 0x03F2, 0x00, 0x04));
1147 aml_append(crs
, aml_io(AML_DECODE16
, 0x03F7, 0x03F7, 0x00, 0x01));
1148 aml_append(crs
, aml_irq_no_flags(6));
1150 aml_dma(AML_COMPATIBILITY
, AML_NOTBUSMASTER
, AML_TRANSFER8
, 2));
1151 aml_append(dev
, aml_name_decl("_CRS", crs
));
1153 for (i
= 0; i
< MIN(MAX_FD
, ACPI_FDE_MAX_FD
); i
++) {
1154 FloppyDriveType type
= isa_fdc_get_drive_type(fdc
, i
);
1156 if (type
< FLOPPY_DRIVE_TYPE_NONE
) {
1157 fde_buf
[i
] = cpu_to_le32(1); /* drive present */
1158 aml_append(dev
, build_fdinfo_aml(i
, type
));
1161 aml_append(dev
, aml_name_decl("_FDE",
1162 aml_buffer(sizeof(fde_buf
), (uint8_t *)fde_buf
)));
1167 static Aml
*build_rtc_device_aml(void)
1172 dev
= aml_device("RTC");
1173 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1174 crs
= aml_resource_template();
1175 aml_append(crs
, aml_io(AML_DECODE16
, 0x0070, 0x0070, 0x10, 0x02));
1176 aml_append(crs
, aml_irq_no_flags(8));
1177 aml_append(crs
, aml_io(AML_DECODE16
, 0x0072, 0x0072, 0x02, 0x06));
1178 aml_append(dev
, aml_name_decl("_CRS", crs
));
1183 static Aml
*build_kbd_device_aml(void)
1189 dev
= aml_device("KBD");
1190 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1192 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1193 aml_append(method
, aml_return(aml_int(0x0f)));
1194 aml_append(dev
, method
);
1196 crs
= aml_resource_template();
1197 aml_append(crs
, aml_io(AML_DECODE16
, 0x0060, 0x0060, 0x01, 0x01));
1198 aml_append(crs
, aml_io(AML_DECODE16
, 0x0064, 0x0064, 0x01, 0x01));
1199 aml_append(crs
, aml_irq_no_flags(1));
1200 aml_append(dev
, aml_name_decl("_CRS", crs
));
1205 static Aml
*build_mouse_device_aml(void)
1211 dev
= aml_device("MOU");
1212 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1214 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1215 aml_append(method
, aml_return(aml_int(0x0f)));
1216 aml_append(dev
, method
);
1218 crs
= aml_resource_template();
1219 aml_append(crs
, aml_irq_no_flags(12));
1220 aml_append(dev
, aml_name_decl("_CRS", crs
));
1225 static Aml
*build_lpt_device_aml(void)
1232 Aml
*zero
= aml_int(0);
1233 Aml
*is_present
= aml_local(0);
1235 dev
= aml_device("LPT");
1236 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1238 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1239 aml_append(method
, aml_store(aml_name("LPEN"), is_present
));
1240 if_ctx
= aml_if(aml_equal(is_present
, zero
));
1242 aml_append(if_ctx
, aml_return(aml_int(0x00)));
1244 aml_append(method
, if_ctx
);
1245 else_ctx
= aml_else();
1247 aml_append(else_ctx
, aml_return(aml_int(0x0f)));
1249 aml_append(method
, else_ctx
);
1250 aml_append(dev
, method
);
1252 crs
= aml_resource_template();
1253 aml_append(crs
, aml_io(AML_DECODE16
, 0x0378, 0x0378, 0x08, 0x08));
1254 aml_append(crs
, aml_irq_no_flags(7));
1255 aml_append(dev
, aml_name_decl("_CRS", crs
));
1260 static Aml
*build_com_device_aml(uint8_t uid
)
1267 Aml
*zero
= aml_int(0);
1268 Aml
*is_present
= aml_local(0);
1269 const char *enabled_field
= "CAEN";
1271 uint16_t io_port
= 0x03F8;
1273 assert(uid
== 1 || uid
== 2);
1275 enabled_field
= "CBEN";
1280 dev
= aml_device("COM%d", uid
);
1281 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1282 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1284 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1285 aml_append(method
, aml_store(aml_name("%s", enabled_field
), is_present
));
1286 if_ctx
= aml_if(aml_equal(is_present
, zero
));
1288 aml_append(if_ctx
, aml_return(aml_int(0x00)));
1290 aml_append(method
, if_ctx
);
1291 else_ctx
= aml_else();
1293 aml_append(else_ctx
, aml_return(aml_int(0x0f)));
1295 aml_append(method
, else_ctx
);
1296 aml_append(dev
, method
);
1298 crs
= aml_resource_template();
1299 aml_append(crs
, aml_io(AML_DECODE16
, io_port
, io_port
, 0x00, 0x08));
1300 aml_append(crs
, aml_irq_no_flags(irq
));
1301 aml_append(dev
, aml_name_decl("_CRS", crs
));
1306 static void build_isa_devices_aml(Aml
*table
)
1308 ISADevice
*fdc
= pc_find_fdc0();
1311 Aml
*scope
= aml_scope("_SB.PCI0.ISA");
1312 Object
*obj
= object_resolve_path_type("", TYPE_ISA_BUS
, &ambiguous
);
1314 aml_append(scope
, build_rtc_device_aml());
1315 aml_append(scope
, build_kbd_device_aml());
1316 aml_append(scope
, build_mouse_device_aml());
1318 aml_append(scope
, build_fdc_device_aml(fdc
));
1320 aml_append(scope
, build_lpt_device_aml());
1321 aml_append(scope
, build_com_device_aml(1));
1322 aml_append(scope
, build_com_device_aml(2));
1325 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1327 error_report("No ISA bus, unable to define IPMI ACPI data");
1329 build_acpi_ipmi_devices(scope
, BUS(obj
));
1332 aml_append(table
, scope
);
1335 static void build_dbg_aml(Aml
*table
)
1340 Aml
*scope
= aml_scope("\\");
1341 Aml
*buf
= aml_local(0);
1342 Aml
*len
= aml_local(1);
1343 Aml
*idx
= aml_local(2);
1346 aml_operation_region("DBG", AML_SYSTEM_IO
, aml_int(0x0402), 0x01));
1347 field
= aml_field("DBG", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1348 aml_append(field
, aml_named_field("DBGB", 8));
1349 aml_append(scope
, field
);
1351 method
= aml_method("DBUG", 1, AML_NOTSERIALIZED
);
1353 aml_append(method
, aml_to_hexstring(aml_arg(0), buf
));
1354 aml_append(method
, aml_to_buffer(buf
, buf
));
1355 aml_append(method
, aml_subtract(aml_sizeof(buf
), aml_int(1), len
));
1356 aml_append(method
, aml_store(aml_int(0), idx
));
1358 while_ctx
= aml_while(aml_lless(idx
, len
));
1359 aml_append(while_ctx
,
1360 aml_store(aml_derefof(aml_index(buf
, idx
)), aml_name("DBGB")));
1361 aml_append(while_ctx
, aml_increment(idx
));
1362 aml_append(method
, while_ctx
);
1364 aml_append(method
, aml_store(aml_int(0x0A), aml_name("DBGB")));
1365 aml_append(scope
, method
);
1367 aml_append(table
, scope
);
1370 static Aml
*build_link_dev(const char *name
, uint8_t uid
, Aml
*reg
)
1375 uint32_t irqs
[] = {5, 10, 11};
1377 dev
= aml_device("%s", name
);
1378 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1379 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1381 crs
= aml_resource_template();
1382 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1383 AML_SHARED
, irqs
, ARRAY_SIZE(irqs
)));
1384 aml_append(dev
, aml_name_decl("_PRS", crs
));
1386 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1387 aml_append(method
, aml_return(aml_call1("IQST", reg
)));
1388 aml_append(dev
, method
);
1390 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1391 aml_append(method
, aml_or(reg
, aml_int(0x80), reg
));
1392 aml_append(dev
, method
);
1394 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1395 aml_append(method
, aml_return(aml_call1("IQCR", reg
)));
1396 aml_append(dev
, method
);
1398 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1399 aml_append(method
, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1400 aml_append(method
, aml_store(aml_name("PRRI"), reg
));
1401 aml_append(dev
, method
);
1406 static Aml
*build_gsi_link_dev(const char *name
, uint8_t uid
, uint8_t gsi
)
1413 dev
= aml_device("%s", name
);
1414 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1415 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1417 crs
= aml_resource_template();
1419 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1420 AML_SHARED
, &irqs
, 1));
1421 aml_append(dev
, aml_name_decl("_PRS", crs
));
1423 aml_append(dev
, aml_name_decl("_CRS", crs
));
1426 * _DIS can be no-op because the interrupt cannot be disabled.
1428 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1429 aml_append(dev
, method
);
1431 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1432 aml_append(dev
, method
);
1437 /* _CRS method - get current settings */
1438 static Aml
*build_iqcr_method(bool is_piix4
)
1442 Aml
*method
= aml_method("IQCR", 1, AML_SERIALIZED
);
1443 Aml
*crs
= aml_resource_template();
1446 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1447 AML_ACTIVE_HIGH
, AML_SHARED
, &irqs
, 1));
1448 aml_append(method
, aml_name_decl("PRR0", crs
));
1451 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1454 if_ctx
= aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1455 aml_append(if_ctx
, aml_store(aml_arg(0), aml_name("PRRI")));
1456 aml_append(method
, if_ctx
);
1459 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL
),
1463 aml_append(method
, aml_return(aml_name("PRR0")));
1467 /* _STA method - get status */
1468 static Aml
*build_irq_status_method(void)
1471 Aml
*method
= aml_method("IQST", 1, AML_NOTSERIALIZED
);
1473 if_ctx
= aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL
));
1474 aml_append(if_ctx
, aml_return(aml_int(0x09)));
1475 aml_append(method
, if_ctx
);
1476 aml_append(method
, aml_return(aml_int(0x0B)));
1480 static void build_piix4_pci0_int(Aml
*table
)
1487 Aml
*sb_scope
= aml_scope("_SB");
1488 Aml
*pci0_scope
= aml_scope("PCI0");
1490 aml_append(pci0_scope
, build_prt(true));
1491 aml_append(sb_scope
, pci0_scope
);
1493 field
= aml_field("PCI0.ISA.P40C", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1494 aml_append(field
, aml_named_field("PRQ0", 8));
1495 aml_append(field
, aml_named_field("PRQ1", 8));
1496 aml_append(field
, aml_named_field("PRQ2", 8));
1497 aml_append(field
, aml_named_field("PRQ3", 8));
1498 aml_append(sb_scope
, field
);
1500 aml_append(sb_scope
, build_irq_status_method());
1501 aml_append(sb_scope
, build_iqcr_method(true));
1503 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1504 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1505 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1506 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1508 dev
= aml_device("LNKS");
1510 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1511 aml_append(dev
, aml_name_decl("_UID", aml_int(4)));
1513 crs
= aml_resource_template();
1515 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1516 AML_ACTIVE_HIGH
, AML_SHARED
,
1518 aml_append(dev
, aml_name_decl("_PRS", crs
));
1520 /* The SCI cannot be disabled and is always attached to GSI 9,
1521 * so these are no-ops. We only need this link to override the
1522 * polarity to active high and match the content of the MADT.
1524 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1525 aml_append(method
, aml_return(aml_int(0x0b)));
1526 aml_append(dev
, method
);
1528 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1529 aml_append(dev
, method
);
1531 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1532 aml_append(method
, aml_return(aml_name("_PRS")));
1533 aml_append(dev
, method
);
1535 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1536 aml_append(dev
, method
);
1538 aml_append(sb_scope
, dev
);
1540 aml_append(table
, sb_scope
);
1543 static void append_q35_prt_entry(Aml
*ctx
, uint32_t nr
, const char *name
)
1548 char base
= name
[3] < 'E' ? 'A' : 'E';
1549 char *s
= g_strdup(name
);
1550 Aml
*a_nr
= aml_int((nr
<< 16) | 0xffff);
1552 assert(strlen(s
) == 4);
1554 head
= name
[3] - base
;
1555 for (i
= 0; i
< 4; i
++) {
1559 s
[3] = base
+ head
+ i
;
1560 pkg
= aml_package(4);
1561 aml_append(pkg
, a_nr
);
1562 aml_append(pkg
, aml_int(i
));
1563 aml_append(pkg
, aml_name("%s", s
));
1564 aml_append(pkg
, aml_int(0));
1565 aml_append(ctx
, pkg
);
1570 static Aml
*build_q35_routing_table(const char *str
)
1574 char *name
= g_strdup_printf("%s ", str
);
1576 pkg
= aml_package(128);
1577 for (i
= 0; i
< 0x18; i
++) {
1578 name
[3] = 'E' + (i
& 0x3);
1579 append_q35_prt_entry(pkg
, i
, name
);
1583 append_q35_prt_entry(pkg
, 0x18, name
);
1585 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1586 for (i
= 0x0019; i
< 0x1e; i
++) {
1588 append_q35_prt_entry(pkg
, i
, name
);
1591 /* PCIe->PCI bridge. use PIRQ[E-H] */
1593 append_q35_prt_entry(pkg
, 0x1e, name
);
1595 append_q35_prt_entry(pkg
, 0x1f, name
);
1601 static void build_q35_pci0_int(Aml
*table
)
1605 Aml
*sb_scope
= aml_scope("_SB");
1606 Aml
*pci0_scope
= aml_scope("PCI0");
1608 /* Zero => PIC mode, One => APIC Mode */
1609 aml_append(table
, aml_name_decl("PICF", aml_int(0)));
1610 method
= aml_method("_PIC", 1, AML_NOTSERIALIZED
);
1612 aml_append(method
, aml_store(aml_arg(0), aml_name("PICF")));
1614 aml_append(table
, method
);
1616 aml_append(pci0_scope
,
1617 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1618 aml_append(pci0_scope
,
1619 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1621 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
1626 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1628 /* Note: we provide the same info as the PCI routing
1629 table of the Bochs BIOS */
1630 if_ctx
= aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1631 aml_append(if_ctx
, aml_return(aml_name("PRTP")));
1632 aml_append(method
, if_ctx
);
1633 else_ctx
= aml_else();
1634 aml_append(else_ctx
, aml_return(aml_name("PRTA")));
1635 aml_append(method
, else_ctx
);
1637 aml_append(pci0_scope
, method
);
1638 aml_append(sb_scope
, pci0_scope
);
1640 field
= aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1641 aml_append(field
, aml_named_field("PRQA", 8));
1642 aml_append(field
, aml_named_field("PRQB", 8));
1643 aml_append(field
, aml_named_field("PRQC", 8));
1644 aml_append(field
, aml_named_field("PRQD", 8));
1645 aml_append(field
, aml_reserved_field(0x20));
1646 aml_append(field
, aml_named_field("PRQE", 8));
1647 aml_append(field
, aml_named_field("PRQF", 8));
1648 aml_append(field
, aml_named_field("PRQG", 8));
1649 aml_append(field
, aml_named_field("PRQH", 8));
1650 aml_append(sb_scope
, field
);
1652 aml_append(sb_scope
, build_irq_status_method());
1653 aml_append(sb_scope
, build_iqcr_method(false));
1655 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQA")));
1656 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQB")));
1657 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQC")));
1658 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQD")));
1659 aml_append(sb_scope
, build_link_dev("LNKE", 4, aml_name("PRQE")));
1660 aml_append(sb_scope
, build_link_dev("LNKF", 5, aml_name("PRQF")));
1661 aml_append(sb_scope
, build_link_dev("LNKG", 6, aml_name("PRQG")));
1662 aml_append(sb_scope
, build_link_dev("LNKH", 7, aml_name("PRQH")));
1664 aml_append(sb_scope
, build_gsi_link_dev("GSIA", 0x10, 0x10));
1665 aml_append(sb_scope
, build_gsi_link_dev("GSIB", 0x11, 0x11));
1666 aml_append(sb_scope
, build_gsi_link_dev("GSIC", 0x12, 0x12));
1667 aml_append(sb_scope
, build_gsi_link_dev("GSID", 0x13, 0x13));
1668 aml_append(sb_scope
, build_gsi_link_dev("GSIE", 0x14, 0x14));
1669 aml_append(sb_scope
, build_gsi_link_dev("GSIF", 0x15, 0x15));
1670 aml_append(sb_scope
, build_gsi_link_dev("GSIG", 0x16, 0x16));
1671 aml_append(sb_scope
, build_gsi_link_dev("GSIH", 0x17, 0x17));
1673 aml_append(table
, sb_scope
);
1676 static void build_q35_isa_bridge(Aml
*table
)
1682 scope
= aml_scope("_SB.PCI0");
1683 dev
= aml_device("ISA");
1684 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x001F0000)));
1686 /* ICH9 PCI to ISA irq remapping */
1687 aml_append(dev
, aml_operation_region("PIRQ", AML_PCI_CONFIG
,
1688 aml_int(0x60), 0x0C));
1690 aml_append(dev
, aml_operation_region("LPCD", AML_PCI_CONFIG
,
1691 aml_int(0x80), 0x02));
1692 field
= aml_field("LPCD", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1693 aml_append(field
, aml_named_field("COMA", 3));
1694 aml_append(field
, aml_reserved_field(1));
1695 aml_append(field
, aml_named_field("COMB", 3));
1696 aml_append(field
, aml_reserved_field(1));
1697 aml_append(field
, aml_named_field("LPTD", 2));
1698 aml_append(dev
, field
);
1700 aml_append(dev
, aml_operation_region("LPCE", AML_PCI_CONFIG
,
1701 aml_int(0x82), 0x02));
1703 field
= aml_field("LPCE", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1704 aml_append(field
, aml_named_field("CAEN", 1));
1705 aml_append(field
, aml_named_field("CBEN", 1));
1706 aml_append(field
, aml_named_field("LPEN", 1));
1707 aml_append(dev
, field
);
1709 aml_append(scope
, dev
);
1710 aml_append(table
, scope
);
1713 static void build_piix4_pm(Aml
*table
)
1718 scope
= aml_scope("_SB.PCI0");
1719 dev
= aml_device("PX13");
1720 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010003)));
1722 aml_append(dev
, aml_operation_region("P13C", AML_PCI_CONFIG
,
1723 aml_int(0x00), 0xff));
1724 aml_append(scope
, dev
);
1725 aml_append(table
, scope
);
1728 static void build_piix4_isa_bridge(Aml
*table
)
1734 scope
= aml_scope("_SB.PCI0");
1735 dev
= aml_device("ISA");
1736 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010000)));
1738 /* PIIX PCI to ISA irq remapping */
1739 aml_append(dev
, aml_operation_region("P40C", AML_PCI_CONFIG
,
1740 aml_int(0x60), 0x04));
1742 field
= aml_field("^PX13.P13C", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1743 /* Offset(0x5f),, 7, */
1744 aml_append(field
, aml_reserved_field(0x2f8));
1745 aml_append(field
, aml_reserved_field(7));
1746 aml_append(field
, aml_named_field("LPEN", 1));
1747 /* Offset(0x67),, 3, */
1748 aml_append(field
, aml_reserved_field(0x38));
1749 aml_append(field
, aml_reserved_field(3));
1750 aml_append(field
, aml_named_field("CAEN", 1));
1751 aml_append(field
, aml_reserved_field(3));
1752 aml_append(field
, aml_named_field("CBEN", 1));
1753 aml_append(dev
, field
);
1755 aml_append(scope
, dev
);
1756 aml_append(table
, scope
);
1759 static void build_piix4_pci_hotplug(Aml
*table
)
1765 scope
= aml_scope("_SB.PCI0");
1768 aml_operation_region("PCST", AML_SYSTEM_IO
, aml_int(0xae00), 0x08));
1769 field
= aml_field("PCST", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1770 aml_append(field
, aml_named_field("PCIU", 32));
1771 aml_append(field
, aml_named_field("PCID", 32));
1772 aml_append(scope
, field
);
1775 aml_operation_region("SEJ", AML_SYSTEM_IO
, aml_int(0xae08), 0x04));
1776 field
= aml_field("SEJ", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1777 aml_append(field
, aml_named_field("B0EJ", 32));
1778 aml_append(scope
, field
);
1781 aml_operation_region("BNMR", AML_SYSTEM_IO
, aml_int(0xae10), 0x04));
1782 field
= aml_field("BNMR", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1783 aml_append(field
, aml_named_field("BNUM", 32));
1784 aml_append(scope
, field
);
1786 aml_append(scope
, aml_mutex("BLCK", 0));
1788 method
= aml_method("PCEJ", 2, AML_NOTSERIALIZED
);
1789 aml_append(method
, aml_acquire(aml_name("BLCK"), 0xFFFF));
1790 aml_append(method
, aml_store(aml_arg(0), aml_name("BNUM")));
1792 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1793 aml_append(method
, aml_release(aml_name("BLCK")));
1794 aml_append(method
, aml_return(aml_int(0)));
1795 aml_append(scope
, method
);
1797 aml_append(table
, scope
);
1800 static Aml
*build_q35_osc_method(void)
1806 Aml
*a_cwd1
= aml_name("CDW1");
1807 Aml
*a_ctrl
= aml_name("CTRL");
1809 method
= aml_method("_OSC", 4, AML_NOTSERIALIZED
);
1810 aml_append(method
, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1812 if_ctx
= aml_if(aml_equal(
1813 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1814 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1815 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1817 aml_append(if_ctx
, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1818 aml_append(if_ctx
, aml_store(aml_name("CDW3"), a_ctrl
));
1821 * Always allow native PME, AER (no dependencies)
1822 * Never allow SHPC (no SHPC controller in this system)
1824 aml_append(if_ctx
, aml_and(a_ctrl
, aml_int(0x1D), a_ctrl
));
1826 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1827 /* Unknown revision */
1828 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x08), a_cwd1
));
1829 aml_append(if_ctx
, if_ctx2
);
1831 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl
)));
1832 /* Capabilities bits were masked */
1833 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x10), a_cwd1
));
1834 aml_append(if_ctx
, if_ctx2
);
1836 /* Update DWORD3 in the buffer */
1837 aml_append(if_ctx
, aml_store(a_ctrl
, aml_name("CDW3")));
1838 aml_append(method
, if_ctx
);
1840 else_ctx
= aml_else();
1841 /* Unrecognized UUID */
1842 aml_append(else_ctx
, aml_or(a_cwd1
, aml_int(4), a_cwd1
));
1843 aml_append(method
, else_ctx
);
1845 aml_append(method
, aml_return(aml_arg(3)));
1850 build_dsdt(GArray
*table_data
, BIOSLinker
*linker
,
1851 AcpiPmInfo
*pm
, AcpiMiscInfo
*misc
,
1852 Range
*pci_hole
, Range
*pci_hole64
, MachineState
*machine
)
1854 CrsRangeEntry
*entry
;
1855 Aml
*dsdt
, *sb_scope
, *scope
, *dev
, *method
, *field
, *pkg
, *crs
;
1856 CrsRangeSet crs_range_set
;
1857 PCMachineState
*pcms
= PC_MACHINE(machine
);
1858 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(machine
);
1859 uint32_t nr_mem
= machine
->ram_slots
;
1860 int root_bus_limit
= 0xFF;
1864 dsdt
= init_aml_allocator();
1866 /* Reserve space for header */
1867 acpi_data_push(dsdt
->buf
, sizeof(AcpiTableHeader
));
1869 build_dbg_aml(dsdt
);
1870 if (misc
->is_piix4
) {
1871 sb_scope
= aml_scope("_SB");
1872 dev
= aml_device("PCI0");
1873 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1874 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
1875 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
1876 aml_append(sb_scope
, dev
);
1877 aml_append(dsdt
, sb_scope
);
1879 build_hpet_aml(dsdt
);
1880 build_piix4_pm(dsdt
);
1881 build_piix4_isa_bridge(dsdt
);
1882 build_isa_devices_aml(dsdt
);
1883 build_piix4_pci_hotplug(dsdt
);
1884 build_piix4_pci0_int(dsdt
);
1886 sb_scope
= aml_scope("_SB");
1887 aml_append(sb_scope
,
1888 aml_operation_region("PCST", AML_SYSTEM_IO
, aml_int(0xae00), 0x0c));
1889 aml_append(sb_scope
,
1890 aml_operation_region("PCSB", AML_SYSTEM_IO
, aml_int(0xae0c), 0x01));
1891 field
= aml_field("PCSB", AML_ANY_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1892 aml_append(field
, aml_named_field("PCIB", 8));
1893 aml_append(sb_scope
, field
);
1894 aml_append(dsdt
, sb_scope
);
1896 sb_scope
= aml_scope("_SB");
1897 dev
= aml_device("PCI0");
1898 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1899 aml_append(dev
, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1900 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
1901 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
1902 aml_append(dev
, aml_name_decl("SUPP", aml_int(0)));
1903 aml_append(dev
, aml_name_decl("CTRL", aml_int(0)));
1904 aml_append(dev
, build_q35_osc_method());
1905 aml_append(sb_scope
, dev
);
1906 aml_append(dsdt
, sb_scope
);
1908 build_hpet_aml(dsdt
);
1909 build_q35_isa_bridge(dsdt
);
1910 build_isa_devices_aml(dsdt
);
1911 build_q35_pci0_int(dsdt
);
1914 if (pcmc
->legacy_cpu_hotplug
) {
1915 build_legacy_cpu_hotplug_aml(dsdt
, machine
, pm
->cpu_hp_io_base
);
1917 CPUHotplugFeatures opts
= {
1918 .apci_1_compatible
= true, .has_legacy_cphp
= true
1920 build_cpus_aml(dsdt
, machine
, opts
, pm
->cpu_hp_io_base
,
1921 "\\_SB.PCI0", "\\_GPE._E02");
1923 build_memory_hotplug_aml(dsdt
, nr_mem
, "\\_SB.PCI0", "\\_GPE._E03");
1925 scope
= aml_scope("_GPE");
1927 aml_append(scope
, aml_name_decl("_HID", aml_string("ACPI0006")));
1929 if (misc
->is_piix4
) {
1930 method
= aml_method("_E01", 0, AML_NOTSERIALIZED
);
1932 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1933 aml_append(method
, aml_call0("\\_SB.PCI0.PCNT"));
1934 aml_append(method
, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1935 aml_append(scope
, method
);
1938 if (pcms
->acpi_nvdimm_state
.is_enabled
) {
1939 method
= aml_method("_E04", 0, AML_NOTSERIALIZED
);
1940 aml_append(method
, aml_notify(aml_name("\\_SB.NVDR"),
1942 aml_append(scope
, method
);
1945 aml_append(dsdt
, scope
);
1947 crs_range_set_init(&crs_range_set
);
1948 bus
= PC_MACHINE(machine
)->bus
;
1950 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
1951 uint8_t bus_num
= pci_bus_num(bus
);
1952 uint8_t numa_node
= pci_bus_numa_node(bus
);
1954 /* look only for expander root buses */
1955 if (!pci_bus_is_root(bus
)) {
1959 if (bus_num
< root_bus_limit
) {
1960 root_bus_limit
= bus_num
- 1;
1963 scope
= aml_scope("\\_SB");
1964 dev
= aml_device("PC%.02X", bus_num
);
1965 aml_append(dev
, aml_name_decl("_UID", aml_int(bus_num
)));
1966 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1967 aml_append(dev
, aml_name_decl("_BBN", aml_int(bus_num
)));
1969 if (numa_node
!= NUMA_NODE_UNASSIGNED
) {
1970 aml_append(dev
, aml_name_decl("_PXM", aml_int(numa_node
)));
1973 aml_append(dev
, build_prt(false));
1974 crs
= build_crs(PCI_HOST_BRIDGE(BUS(bus
)->parent
), &crs_range_set
);
1975 aml_append(dev
, aml_name_decl("_CRS", crs
));
1976 aml_append(scope
, dev
);
1977 aml_append(dsdt
, scope
);
1981 scope
= aml_scope("\\_SB.PCI0");
1982 /* build PCI0._CRS */
1983 crs
= aml_resource_template();
1985 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
1986 0x0000, 0x0, root_bus_limit
,
1987 0x0000, root_bus_limit
+ 1));
1988 aml_append(crs
, aml_io(AML_DECODE16
, 0x0CF8, 0x0CF8, 0x01, 0x08));
1991 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
1992 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
1993 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1995 crs_replace_with_free_ranges(crs_range_set
.io_ranges
, 0x0D00, 0xFFFF);
1996 for (i
= 0; i
< crs_range_set
.io_ranges
->len
; i
++) {
1997 entry
= g_ptr_array_index(crs_range_set
.io_ranges
, i
);
1999 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
2000 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
2001 0x0000, entry
->base
, entry
->limit
,
2002 0x0000, entry
->limit
- entry
->base
+ 1));
2006 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
2007 AML_CACHEABLE
, AML_READ_WRITE
,
2008 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2010 crs_replace_with_free_ranges(crs_range_set
.mem_ranges
,
2011 range_lob(pci_hole
),
2012 range_upb(pci_hole
));
2013 for (i
= 0; i
< crs_range_set
.mem_ranges
->len
; i
++) {
2014 entry
= g_ptr_array_index(crs_range_set
.mem_ranges
, i
);
2016 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
2017 AML_NON_CACHEABLE
, AML_READ_WRITE
,
2018 0, entry
->base
, entry
->limit
,
2019 0, entry
->limit
- entry
->base
+ 1));
2022 if (!range_is_empty(pci_hole64
)) {
2023 crs_replace_with_free_ranges(crs_range_set
.mem_64bit_ranges
,
2024 range_lob(pci_hole64
),
2025 range_upb(pci_hole64
));
2026 for (i
= 0; i
< crs_range_set
.mem_64bit_ranges
->len
; i
++) {
2027 entry
= g_ptr_array_index(crs_range_set
.mem_64bit_ranges
, i
);
2029 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
2031 AML_CACHEABLE
, AML_READ_WRITE
,
2032 0, entry
->base
, entry
->limit
,
2033 0, entry
->limit
- entry
->base
+ 1));
2037 if (misc
->tpm_version
!= TPM_VERSION_UNSPEC
) {
2038 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
2039 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
2041 aml_append(scope
, aml_name_decl("_CRS", crs
));
2043 /* reserve GPE0 block resources */
2044 dev
= aml_device("GPE0");
2045 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
2046 aml_append(dev
, aml_name_decl("_UID", aml_string("GPE0 resources")));
2047 /* device present, functioning, decoding, not shown in UI */
2048 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2049 crs
= aml_resource_template();
2051 aml_io(AML_DECODE16
, pm
->gpe0_blk
, pm
->gpe0_blk
, 1, pm
->gpe0_blk_len
)
2053 aml_append(dev
, aml_name_decl("_CRS", crs
));
2054 aml_append(scope
, dev
);
2056 crs_range_set_free(&crs_range_set
);
2058 /* reserve PCIHP resources */
2059 if (pm
->pcihp_io_len
) {
2060 dev
= aml_device("PHPR");
2061 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
2063 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2064 /* device present, functioning, decoding, not shown in UI */
2065 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2066 crs
= aml_resource_template();
2068 aml_io(AML_DECODE16
, pm
->pcihp_io_base
, pm
->pcihp_io_base
, 1,
2071 aml_append(dev
, aml_name_decl("_CRS", crs
));
2072 aml_append(scope
, dev
);
2074 aml_append(dsdt
, scope
);
2076 /* create S3_ / S4_ / S5_ packages if necessary */
2077 scope
= aml_scope("\\");
2078 if (!pm
->s3_disabled
) {
2079 pkg
= aml_package(4);
2080 aml_append(pkg
, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2081 aml_append(pkg
, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2082 aml_append(pkg
, aml_int(0)); /* reserved */
2083 aml_append(pkg
, aml_int(0)); /* reserved */
2084 aml_append(scope
, aml_name_decl("_S3", pkg
));
2087 if (!pm
->s4_disabled
) {
2088 pkg
= aml_package(4);
2089 aml_append(pkg
, aml_int(pm
->s4_val
)); /* PM1a_CNT.SLP_TYP */
2090 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2091 aml_append(pkg
, aml_int(pm
->s4_val
));
2092 aml_append(pkg
, aml_int(0)); /* reserved */
2093 aml_append(pkg
, aml_int(0)); /* reserved */
2094 aml_append(scope
, aml_name_decl("_S4", pkg
));
2097 pkg
= aml_package(4);
2098 aml_append(pkg
, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2099 aml_append(pkg
, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2100 aml_append(pkg
, aml_int(0)); /* reserved */
2101 aml_append(pkg
, aml_int(0)); /* reserved */
2102 aml_append(scope
, aml_name_decl("_S5", pkg
));
2103 aml_append(dsdt
, scope
);
2105 /* create fw_cfg node, unconditionally */
2107 /* when using port i/o, the 8-bit data register *always* overlaps
2108 * with half of the 16-bit control register. Hence, the total size
2109 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2110 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2111 uint8_t io_size
= object_property_get_bool(OBJECT(pcms
->fw_cfg
),
2112 "dma_enabled", NULL
) ?
2113 ROUND_UP(FW_CFG_CTL_SIZE
, 4) + sizeof(dma_addr_t
) :
2116 scope
= aml_scope("\\_SB.PCI0");
2117 dev
= aml_device("FWCF");
2119 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0002")));
2121 /* device present, functioning, decoding, not shown in UI */
2122 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2124 crs
= aml_resource_template();
2126 aml_io(AML_DECODE16
, FW_CFG_IO_BASE
, FW_CFG_IO_BASE
, 0x01, io_size
)
2128 aml_append(dev
, aml_name_decl("_CRS", crs
));
2130 aml_append(scope
, dev
);
2131 aml_append(dsdt
, scope
);
2134 if (misc
->applesmc_io_base
) {
2135 scope
= aml_scope("\\_SB.PCI0.ISA");
2136 dev
= aml_device("SMC");
2138 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("APP0001")));
2139 /* device present, functioning, decoding, not shown in UI */
2140 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2142 crs
= aml_resource_template();
2144 aml_io(AML_DECODE16
, misc
->applesmc_io_base
, misc
->applesmc_io_base
,
2145 0x01, APPLESMC_MAX_DATA_LENGTH
)
2147 aml_append(crs
, aml_irq_no_flags(6));
2148 aml_append(dev
, aml_name_decl("_CRS", crs
));
2150 aml_append(scope
, dev
);
2151 aml_append(dsdt
, scope
);
2154 if (misc
->pvpanic_port
) {
2155 scope
= aml_scope("\\_SB.PCI0.ISA");
2157 dev
= aml_device("PEVT");
2158 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0001")));
2160 crs
= aml_resource_template();
2162 aml_io(AML_DECODE16
, misc
->pvpanic_port
, misc
->pvpanic_port
, 1, 1)
2164 aml_append(dev
, aml_name_decl("_CRS", crs
));
2166 aml_append(dev
, aml_operation_region("PEOR", AML_SYSTEM_IO
,
2167 aml_int(misc
->pvpanic_port
), 1));
2168 field
= aml_field("PEOR", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
2169 aml_append(field
, aml_named_field("PEPT", 8));
2170 aml_append(dev
, field
);
2172 /* device present, functioning, decoding, shown in UI */
2173 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
2175 method
= aml_method("RDPT", 0, AML_NOTSERIALIZED
);
2176 aml_append(method
, aml_store(aml_name("PEPT"), aml_local(0)));
2177 aml_append(method
, aml_return(aml_local(0)));
2178 aml_append(dev
, method
);
2180 method
= aml_method("WRPT", 1, AML_NOTSERIALIZED
);
2181 aml_append(method
, aml_store(aml_arg(0), aml_name("PEPT")));
2182 aml_append(dev
, method
);
2184 aml_append(scope
, dev
);
2185 aml_append(dsdt
, scope
);
2188 sb_scope
= aml_scope("\\_SB");
2193 pci_host
= acpi_get_i386_pci_host();
2195 bus
= PCI_HOST_BRIDGE(pci_host
)->bus
;
2199 Aml
*scope
= aml_scope("PCI0");
2200 /* Scan all PCI buses. Generate tables to support hotplug. */
2201 build_append_pci_bus_devices(scope
, bus
, pm
->pcihp_bridge_en
);
2203 if (misc
->tpm_version
!= TPM_VERSION_UNSPEC
) {
2204 dev
= aml_device("ISA.TPM");
2205 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2206 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
2207 crs
= aml_resource_template();
2208 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
2209 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
2211 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2212 Rewrite to take IRQ from TPM device model and
2213 fix default IRQ value there to use some unused IRQ
2215 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2216 aml_append(dev
, aml_name_decl("_CRS", crs
));
2217 aml_append(scope
, dev
);
2220 aml_append(sb_scope
, scope
);
2223 aml_append(dsdt
, sb_scope
);
2225 /* copy AML table into ACPI tables blob and patch header there */
2226 g_array_append_vals(table_data
, dsdt
->buf
->data
, dsdt
->buf
->len
);
2227 build_header(linker
, table_data
,
2228 (void *)(table_data
->data
+ table_data
->len
- dsdt
->buf
->len
),
2229 "DSDT", dsdt
->buf
->len
, 1, NULL
, NULL
);
2230 free_aml_allocator();
2234 build_hpet(GArray
*table_data
, BIOSLinker
*linker
)
2238 hpet
= acpi_data_push(table_data
, sizeof(*hpet
));
2239 /* Note timer_block_id value must be kept in sync with value advertised by
2242 hpet
->timer_block_id
= cpu_to_le32(0x8086a201);
2243 hpet
->addr
.address
= cpu_to_le64(HPET_BASE
);
2244 build_header(linker
, table_data
,
2245 (void *)hpet
, "HPET", sizeof(*hpet
), 1, NULL
, NULL
);
2249 build_tpm_tcpa(GArray
*table_data
, BIOSLinker
*linker
, GArray
*tcpalog
)
2251 Acpi20Tcpa
*tcpa
= acpi_data_push(table_data
, sizeof *tcpa
);
2252 unsigned log_addr_size
= sizeof(tcpa
->log_area_start_address
);
2253 unsigned log_addr_offset
=
2254 (char *)&tcpa
->log_area_start_address
- table_data
->data
;
2256 tcpa
->platform_class
= cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT
);
2257 tcpa
->log_area_minimum_length
= cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE
);
2258 acpi_data_push(tcpalog
, le32_to_cpu(tcpa
->log_area_minimum_length
));
2260 bios_linker_loader_alloc(linker
, ACPI_BUILD_TPMLOG_FILE
, tcpalog
, 1,
2261 false /* high memory */);
2263 /* log area start address to be filled by Guest linker */
2264 bios_linker_loader_add_pointer(linker
,
2265 ACPI_BUILD_TABLE_FILE
, log_addr_offset
, log_addr_size
,
2266 ACPI_BUILD_TPMLOG_FILE
, 0);
2268 build_header(linker
, table_data
,
2269 (void *)tcpa
, "TCPA", sizeof(*tcpa
), 2, NULL
, NULL
);
2273 build_tpm2(GArray
*table_data
, BIOSLinker
*linker
)
2275 Acpi20TPM2
*tpm2_ptr
;
2277 tpm2_ptr
= acpi_data_push(table_data
, sizeof *tpm2_ptr
);
2279 tpm2_ptr
->platform_class
= cpu_to_le16(TPM2_ACPI_CLASS_CLIENT
);
2280 tpm2_ptr
->control_area_address
= cpu_to_le64(0);
2281 tpm2_ptr
->start_method
= cpu_to_le32(TPM2_START_METHOD_MMIO
);
2283 build_header(linker
, table_data
,
2284 (void *)tpm2_ptr
, "TPM2", sizeof(*tpm2_ptr
), 4, NULL
, NULL
);
2288 build_srat(GArray
*table_data
, BIOSLinker
*linker
, MachineState
*machine
)
2290 AcpiSystemResourceAffinityTable
*srat
;
2291 AcpiSratMemoryAffinity
*numamem
;
2294 int srat_start
, numa_start
, slots
;
2295 uint64_t mem_len
, mem_base
, next_base
;
2296 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2297 CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(machine
);
2298 PCMachineState
*pcms
= PC_MACHINE(machine
);
2299 ram_addr_t hotplugabble_address_space_size
=
2300 object_property_get_int(OBJECT(pcms
), PC_MACHINE_MEMHP_REGION_SIZE
,
2303 srat_start
= table_data
->len
;
2305 srat
= acpi_data_push(table_data
, sizeof *srat
);
2306 srat
->reserved1
= cpu_to_le32(1);
2308 for (i
= 0; i
< apic_ids
->len
; i
++) {
2309 int j
= numa_get_node_for_cpu(i
);
2310 uint32_t apic_id
= apic_ids
->cpus
[i
].arch_id
;
2312 if (apic_id
< 255) {
2313 AcpiSratProcessorAffinity
*core
;
2315 core
= acpi_data_push(table_data
, sizeof *core
);
2316 core
->type
= ACPI_SRAT_PROCESSOR_APIC
;
2317 core
->length
= sizeof(*core
);
2318 core
->local_apic_id
= apic_id
;
2319 if (j
< nb_numa_nodes
) {
2320 core
->proximity_lo
= j
;
2322 memset(core
->proximity_hi
, 0, 3);
2323 core
->local_sapic_eid
= 0;
2324 core
->flags
= cpu_to_le32(1);
2326 AcpiSratProcessorX2ApicAffinity
*core
;
2328 core
= acpi_data_push(table_data
, sizeof *core
);
2329 core
->type
= ACPI_SRAT_PROCESSOR_x2APIC
;
2330 core
->length
= sizeof(*core
);
2331 core
->x2apic_id
= cpu_to_le32(apic_id
);
2332 if (j
< nb_numa_nodes
) {
2333 core
->proximity_domain
= cpu_to_le32(j
);
2335 core
->flags
= cpu_to_le32(1);
2340 /* the memory map is a bit tricky, it contains at least one hole
2341 * from 640k-1M and possibly another one from 3.5G-4G.
2344 numa_start
= table_data
->len
;
2346 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2347 build_srat_memory(numamem
, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED
);
2348 next_base
= 1024 * 1024;
2349 for (i
= 1; i
< pcms
->numa_nodes
+ 1; ++i
) {
2350 mem_base
= next_base
;
2351 mem_len
= pcms
->node_mem
[i
- 1];
2353 mem_len
-= 1024 * 1024;
2355 next_base
= mem_base
+ mem_len
;
2357 /* Cut out the ACPI_PCI hole */
2358 if (mem_base
<= pcms
->below_4g_mem_size
&&
2359 next_base
> pcms
->below_4g_mem_size
) {
2360 mem_len
-= next_base
- pcms
->below_4g_mem_size
;
2362 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2363 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2364 MEM_AFFINITY_ENABLED
);
2366 mem_base
= 1ULL << 32;
2367 mem_len
= next_base
- pcms
->below_4g_mem_size
;
2368 next_base
+= (1ULL << 32) - pcms
->below_4g_mem_size
;
2370 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2371 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2372 MEM_AFFINITY_ENABLED
);
2374 slots
= (table_data
->len
- numa_start
) / sizeof *numamem
;
2375 for (; slots
< pcms
->numa_nodes
+ 2; slots
++) {
2376 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2377 build_srat_memory(numamem
, 0, 0, 0, MEM_AFFINITY_NOFLAGS
);
2381 * Entry is required for Windows to enable memory hotplug in OS.
2382 * Memory devices may override proximity set by this entry,
2383 * providing _PXM method if necessary.
2385 if (hotplugabble_address_space_size
) {
2386 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2387 build_srat_memory(numamem
, pcms
->hotplug_memory
.base
,
2388 hotplugabble_address_space_size
, 0,
2389 MEM_AFFINITY_HOTPLUGGABLE
| MEM_AFFINITY_ENABLED
);
2392 build_header(linker
, table_data
,
2393 (void *)(table_data
->data
+ srat_start
),
2395 table_data
->len
- srat_start
, 1, NULL
, NULL
);
2400 build_mcfg_q35(GArray
*table_data
, BIOSLinker
*linker
, AcpiMcfgInfo
*info
)
2402 AcpiTableMcfg
*mcfg
;
2404 int len
= sizeof(*mcfg
) + 1 * sizeof(mcfg
->allocation
[0]);
2406 mcfg
= acpi_data_push(table_data
, len
);
2407 mcfg
->allocation
[0].address
= cpu_to_le64(info
->mcfg_base
);
2408 /* Only a single allocation so no need to play with segments */
2409 mcfg
->allocation
[0].pci_segment
= cpu_to_le16(0);
2410 mcfg
->allocation
[0].start_bus_number
= 0;
2411 mcfg
->allocation
[0].end_bus_number
= PCIE_MMCFG_BUS(info
->mcfg_size
- 1);
2413 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2414 * To avoid table size changes (which create migration issues),
2415 * always create the table even if there are no allocations,
2416 * but set the signature to a reserved value in this case.
2417 * ACPI spec requires OSPMs to ignore such tables.
2419 if (info
->mcfg_base
== PCIE_BASE_ADDR_UNMAPPED
) {
2420 /* Reserved signature: ignored by OSPM */
2425 build_header(linker
, table_data
, (void *)mcfg
, sig
, len
, 1, NULL
, NULL
);
2429 * VT-d spec 8.1 DMA Remapping Reporting Structure
2430 * (version Oct. 2014 or later)
2433 build_dmar_q35(GArray
*table_data
, BIOSLinker
*linker
)
2435 int dmar_start
= table_data
->len
;
2437 AcpiTableDmar
*dmar
;
2438 AcpiDmarHardwareUnit
*drhd
;
2439 AcpiDmarRootPortATS
*atsr
;
2440 uint8_t dmar_flags
= 0;
2441 X86IOMMUState
*iommu
= x86_iommu_get_default();
2442 AcpiDmarDeviceScope
*scope
= NULL
;
2443 /* Root complex IOAPIC use one path[0] only */
2444 size_t ioapic_scope_size
= sizeof(*scope
) + sizeof(scope
->path
[0]);
2447 if (iommu
->intr_supported
) {
2448 dmar_flags
|= 0x1; /* Flags: 0x1: INT_REMAP */
2451 dmar
= acpi_data_push(table_data
, sizeof(*dmar
));
2452 dmar
->host_address_width
= VTD_HOST_ADDRESS_WIDTH
- 1;
2453 dmar
->flags
= dmar_flags
;
2455 /* DMAR Remapping Hardware Unit Definition structure */
2456 drhd
= acpi_data_push(table_data
, sizeof(*drhd
) + ioapic_scope_size
);
2457 drhd
->type
= cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT
);
2458 drhd
->length
= cpu_to_le16(sizeof(*drhd
) + ioapic_scope_size
);
2459 drhd
->flags
= ACPI_DMAR_INCLUDE_PCI_ALL
;
2460 drhd
->pci_segment
= cpu_to_le16(0);
2461 drhd
->address
= cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR
);
2463 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2464 * 8.3.1 (version Oct. 2014 or later). */
2465 scope
= &drhd
->scope
[0];
2466 scope
->entry_type
= 0x03; /* Type: 0x03 for IOAPIC */
2467 scope
->length
= ioapic_scope_size
;
2468 scope
->enumeration_id
= ACPI_BUILD_IOAPIC_ID
;
2469 scope
->bus
= Q35_PSEUDO_BUS_PLATFORM
;
2470 scope
->path
[0].device
= PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC
);
2471 scope
->path
[0].function
= PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC
);
2473 if (iommu
->dt_supported
) {
2474 atsr
= acpi_data_push(table_data
, sizeof(*atsr
));
2475 atsr
->type
= cpu_to_le16(ACPI_DMAR_TYPE_ATSR
);
2476 atsr
->length
= cpu_to_le16(sizeof(*atsr
));
2477 atsr
->flags
= ACPI_DMAR_ATSR_ALL_PORTS
;
2478 atsr
->pci_segment
= cpu_to_le16(0);
2481 build_header(linker
, table_data
, (void *)(table_data
->data
+ dmar_start
),
2482 "DMAR", table_data
->len
- dmar_start
, 1, NULL
, NULL
);
2485 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2486 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2489 build_amd_iommu(GArray
*table_data
, BIOSLinker
*linker
)
2491 int iommu_start
= table_data
->len
;
2492 AMDVIState
*s
= AMD_IOMMU_DEVICE(x86_iommu_get_default());
2495 acpi_data_push(table_data
, sizeof(AcpiTableHeader
));
2496 /* IVinfo - IO virtualization information common to all
2497 * IOMMU units in a system
2499 build_append_int_noprefix(table_data
, 40UL << 8/* PASize */, 4);
2501 build_append_int_noprefix(table_data
, 0, 8);
2503 /* IVHD definition - type 10h */
2504 build_append_int_noprefix(table_data
, 0x10, 1);
2505 /* virtualization flags */
2506 build_append_int_noprefix(table_data
,
2507 (1UL << 0) | /* HtTunEn */
2508 (1UL << 4) | /* iotblSup */
2509 (1UL << 6) | /* PrefSup */
2510 (1UL << 7), /* PPRSup */
2513 build_append_int_noprefix(table_data
, 0x24, 2);
2515 build_append_int_noprefix(table_data
, s
->devid
, 2);
2516 /* Capability offset */
2517 build_append_int_noprefix(table_data
, s
->capab_offset
, 2);
2518 /* IOMMU base address */
2519 build_append_int_noprefix(table_data
, s
->mmio
.addr
, 8);
2520 /* PCI Segment Group */
2521 build_append_int_noprefix(table_data
, 0, 2);
2523 build_append_int_noprefix(table_data
, 0, 2);
2524 /* IOMMU Feature Reporting */
2525 build_append_int_noprefix(table_data
,
2526 (48UL << 30) | /* HATS */
2527 (48UL << 28) | /* GATS */
2528 (1UL << 2), /* GTSup */
2531 * Type 1 device entry reporting all devices
2532 * These are 4-byte device entries currently reporting the range of
2533 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2535 build_append_int_noprefix(table_data
, 0x0000001, 4);
2537 build_header(linker
, table_data
, (void *)(table_data
->data
+ iommu_start
),
2538 "IVRS", table_data
->len
- iommu_start
, 1, NULL
, NULL
);
2542 build_rsdp(GArray
*rsdp_table
, BIOSLinker
*linker
, unsigned rsdt_tbl_offset
)
2544 AcpiRsdpDescriptor
*rsdp
= acpi_data_push(rsdp_table
, sizeof *rsdp
);
2545 unsigned rsdt_pa_size
= sizeof(rsdp
->rsdt_physical_address
);
2546 unsigned rsdt_pa_offset
=
2547 (char *)&rsdp
->rsdt_physical_address
- rsdp_table
->data
;
2549 bios_linker_loader_alloc(linker
, ACPI_BUILD_RSDP_FILE
, rsdp_table
, 16,
2550 true /* fseg memory */);
2552 memcpy(&rsdp
->signature
, "RSD PTR ", 8);
2553 memcpy(rsdp
->oem_id
, ACPI_BUILD_APPNAME6
, 6);
2554 /* Address to be filled by Guest linker */
2555 bios_linker_loader_add_pointer(linker
,
2556 ACPI_BUILD_RSDP_FILE
, rsdt_pa_offset
, rsdt_pa_size
,
2557 ACPI_BUILD_TABLE_FILE
, rsdt_tbl_offset
);
2559 /* Checksum to be filled by Guest linker */
2560 bios_linker_loader_add_checksum(linker
, ACPI_BUILD_RSDP_FILE
,
2561 (char *)rsdp
- rsdp_table
->data
, sizeof *rsdp
,
2562 (char *)&rsdp
->checksum
- rsdp_table
->data
);
2568 struct AcpiBuildState
{
2569 /* Copy of table in RAM (for patching). */
2570 MemoryRegion
*table_mr
;
2571 /* Is table patched? */
2574 MemoryRegion
*rsdp_mr
;
2575 MemoryRegion
*linker_mr
;
2578 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
)
2583 pci_host
= acpi_get_i386_pci_host();
2586 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_BASE
, NULL
);
2590 mcfg
->mcfg_base
= qint_get_int(qobject_to_qint(o
));
2593 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_SIZE
, NULL
);
2595 mcfg
->mcfg_size
= qint_get_int(qobject_to_qint(o
));
2601 void acpi_build(AcpiBuildTables
*tables
, MachineState
*machine
)
2603 PCMachineState
*pcms
= PC_MACHINE(machine
);
2604 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2605 GArray
*table_offsets
;
2606 unsigned facs
, dsdt
, rsdt
, fadt
;
2610 Range pci_hole
, pci_hole64
;
2613 GArray
*tables_blob
= tables
->table_data
;
2614 AcpiSlicOem slic_oem
= { .id
= NULL
, .table_id
= NULL
};
2616 acpi_get_pm_info(&pm
);
2617 acpi_get_misc_info(&misc
);
2618 acpi_get_pci_holes(&pci_hole
, &pci_hole64
);
2619 acpi_get_slic_oem(&slic_oem
);
2621 table_offsets
= g_array_new(false, true /* clear */,
2623 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2625 bios_linker_loader_alloc(tables
->linker
,
2626 ACPI_BUILD_TABLE_FILE
, tables_blob
,
2627 64 /* Ensure FACS is aligned */,
2628 false /* high memory */);
2631 * FACS is pointed to by FADT.
2632 * We place it first since it's the only table that has alignment
2635 facs
= tables_blob
->len
;
2636 build_facs(tables_blob
, tables
->linker
);
2638 /* DSDT is pointed to by FADT */
2639 dsdt
= tables_blob
->len
;
2640 build_dsdt(tables_blob
, tables
->linker
, &pm
, &misc
,
2641 &pci_hole
, &pci_hole64
, machine
);
2643 /* Count the size of the DSDT and SSDT, we will need it for legacy
2644 * sizing of ACPI tables.
2646 aml_len
+= tables_blob
->len
- dsdt
;
2648 /* ACPI tables pointed to by RSDT */
2649 fadt
= tables_blob
->len
;
2650 acpi_add_table(table_offsets
, tables_blob
);
2651 build_fadt(tables_blob
, tables
->linker
, &pm
, facs
, dsdt
,
2652 slic_oem
.id
, slic_oem
.table_id
);
2653 aml_len
+= tables_blob
->len
- fadt
;
2655 acpi_add_table(table_offsets
, tables_blob
);
2656 build_madt(tables_blob
, tables
->linker
, pcms
);
2658 if (misc
.has_hpet
) {
2659 acpi_add_table(table_offsets
, tables_blob
);
2660 build_hpet(tables_blob
, tables
->linker
);
2662 if (misc
.tpm_version
!= TPM_VERSION_UNSPEC
) {
2663 acpi_add_table(table_offsets
, tables_blob
);
2664 build_tpm_tcpa(tables_blob
, tables
->linker
, tables
->tcpalog
);
2666 if (misc
.tpm_version
== TPM_VERSION_2_0
) {
2667 acpi_add_table(table_offsets
, tables_blob
);
2668 build_tpm2(tables_blob
, tables
->linker
);
2671 if (pcms
->numa_nodes
) {
2672 acpi_add_table(table_offsets
, tables_blob
);
2673 build_srat(tables_blob
, tables
->linker
, machine
);
2675 if (acpi_get_mcfg(&mcfg
)) {
2676 acpi_add_table(table_offsets
, tables_blob
);
2677 build_mcfg_q35(tables_blob
, tables
->linker
, &mcfg
);
2679 if (x86_iommu_get_default()) {
2680 IommuType IOMMUType
= x86_iommu_get_type();
2681 if (IOMMUType
== TYPE_AMD
) {
2682 acpi_add_table(table_offsets
, tables_blob
);
2683 build_amd_iommu(tables_blob
, tables
->linker
);
2684 } else if (IOMMUType
== TYPE_INTEL
) {
2685 acpi_add_table(table_offsets
, tables_blob
);
2686 build_dmar_q35(tables_blob
, tables
->linker
);
2689 if (pcms
->acpi_nvdimm_state
.is_enabled
) {
2690 nvdimm_build_acpi(table_offsets
, tables_blob
, tables
->linker
,
2691 &pcms
->acpi_nvdimm_state
, machine
->ram_slots
);
2694 /* Add tables supplied by user (if any) */
2695 for (u
= acpi_table_first(); u
; u
= acpi_table_next(u
)) {
2696 unsigned len
= acpi_table_len(u
);
2698 acpi_add_table(table_offsets
, tables_blob
);
2699 g_array_append_vals(tables_blob
, u
, len
);
2702 /* RSDT is pointed to by RSDP */
2703 rsdt
= tables_blob
->len
;
2704 build_rsdt(tables_blob
, tables
->linker
, table_offsets
,
2705 slic_oem
.id
, slic_oem
.table_id
);
2707 /* RSDP is in FSEG memory, so allocate it separately */
2708 build_rsdp(tables
->rsdp
, tables
->linker
, rsdt
);
2710 /* We'll expose it all to Guest so we want to reduce
2711 * chance of size changes.
2713 * We used to align the tables to 4k, but of course this would
2714 * too simple to be enough. 4k turned out to be too small an
2715 * alignment very soon, and in fact it is almost impossible to
2716 * keep the table size stable for all (max_cpus, max_memory_slots)
2717 * combinations. So the table size is always 64k for pc-i440fx-2.1
2718 * and we give an error if the table grows beyond that limit.
2720 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2721 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2722 * than 2.0 and we can always pad the smaller tables with zeros. We can
2723 * then use the exact size of the 2.0 tables.
2725 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2727 if (pcmc
->legacy_acpi_table_size
) {
2728 /* Subtracting aml_len gives the size of fixed tables. Then add the
2729 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2731 int legacy_aml_len
=
2732 pcmc
->legacy_acpi_table_size
+
2733 ACPI_BUILD_LEGACY_CPU_AML_SIZE
* pcms
->apic_id_limit
;
2734 int legacy_table_size
=
2735 ROUND_UP(tables_blob
->len
- aml_len
+ legacy_aml_len
,
2736 ACPI_BUILD_ALIGN_SIZE
);
2737 if (tables_blob
->len
> legacy_table_size
) {
2738 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2739 error_report("Warning: migration may not work.");
2741 g_array_set_size(tables_blob
, legacy_table_size
);
2743 /* Make sure we have a buffer in case we need to resize the tables. */
2744 if (tables_blob
->len
> ACPI_BUILD_TABLE_SIZE
/ 2) {
2745 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2746 error_report("Warning: ACPI tables are larger than 64k.");
2747 error_report("Warning: migration may not work.");
2748 error_report("Warning: please remove CPUs, NUMA nodes, "
2749 "memory slots or PCI bridges.");
2751 acpi_align_size(tables_blob
, ACPI_BUILD_TABLE_SIZE
);
2754 acpi_align_size(tables
->linker
->cmd_blob
, ACPI_BUILD_ALIGN_SIZE
);
2756 /* Cleanup memory that's no longer used. */
2757 g_array_free(table_offsets
, true);
2760 static void acpi_ram_update(MemoryRegion
*mr
, GArray
*data
)
2762 uint32_t size
= acpi_data_len(data
);
2764 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2765 memory_region_ram_resize(mr
, size
, &error_abort
);
2767 memcpy(memory_region_get_ram_ptr(mr
), data
->data
, size
);
2768 memory_region_set_dirty(mr
, 0, size
);
2771 static void acpi_build_update(void *build_opaque
)
2773 AcpiBuildState
*build_state
= build_opaque
;
2774 AcpiBuildTables tables
;
2776 /* No state to update or already patched? Nothing to do. */
2777 if (!build_state
|| build_state
->patched
) {
2780 build_state
->patched
= 1;
2782 acpi_build_tables_init(&tables
);
2784 acpi_build(&tables
, MACHINE(qdev_get_machine()));
2786 acpi_ram_update(build_state
->table_mr
, tables
.table_data
);
2788 if (build_state
->rsdp
) {
2789 memcpy(build_state
->rsdp
, tables
.rsdp
->data
, acpi_data_len(tables
.rsdp
));
2791 acpi_ram_update(build_state
->rsdp_mr
, tables
.rsdp
);
2794 acpi_ram_update(build_state
->linker_mr
, tables
.linker
->cmd_blob
);
2795 acpi_build_tables_cleanup(&tables
, true);
2798 static void acpi_build_reset(void *build_opaque
)
2800 AcpiBuildState
*build_state
= build_opaque
;
2801 build_state
->patched
= 0;
2804 static MemoryRegion
*acpi_add_rom_blob(AcpiBuildState
*build_state
,
2805 GArray
*blob
, const char *name
,
2808 return rom_add_blob(name
, blob
->data
, acpi_data_len(blob
), max_size
, -1,
2809 name
, acpi_build_update
, build_state
, NULL
, true);
2812 static const VMStateDescription vmstate_acpi_build
= {
2813 .name
= "acpi_build",
2815 .minimum_version_id
= 1,
2816 .fields
= (VMStateField
[]) {
2817 VMSTATE_UINT8(patched
, AcpiBuildState
),
2818 VMSTATE_END_OF_LIST()
2822 void acpi_setup(void)
2824 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
2825 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2826 AcpiBuildTables tables
;
2827 AcpiBuildState
*build_state
;
2829 if (!pcms
->fw_cfg
) {
2830 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2834 if (!pcms
->acpi_build_enabled
) {
2835 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2839 if (!acpi_enabled
) {
2840 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2844 build_state
= g_malloc0(sizeof *build_state
);
2846 acpi_set_pci_info();
2848 acpi_build_tables_init(&tables
);
2849 acpi_build(&tables
, MACHINE(pcms
));
2851 /* Now expose it all to Guest */
2852 build_state
->table_mr
= acpi_add_rom_blob(build_state
, tables
.table_data
,
2853 ACPI_BUILD_TABLE_FILE
,
2854 ACPI_BUILD_TABLE_MAX_SIZE
);
2855 assert(build_state
->table_mr
!= NULL
);
2857 build_state
->linker_mr
=
2858 acpi_add_rom_blob(build_state
, tables
.linker
->cmd_blob
,
2859 "etc/table-loader", 0);
2861 fw_cfg_add_file(pcms
->fw_cfg
, ACPI_BUILD_TPMLOG_FILE
,
2862 tables
.tcpalog
->data
, acpi_data_len(tables
.tcpalog
));
2864 if (!pcmc
->rsdp_in_ram
) {
2866 * Keep for compatibility with old machine types.
2867 * Though RSDP is small, its contents isn't immutable, so
2868 * we'll update it along with the rest of tables on guest access.
2870 uint32_t rsdp_size
= acpi_data_len(tables
.rsdp
);
2872 build_state
->rsdp
= g_memdup(tables
.rsdp
->data
, rsdp_size
);
2873 fw_cfg_add_file_callback(pcms
->fw_cfg
, ACPI_BUILD_RSDP_FILE
,
2874 acpi_build_update
, build_state
,
2875 build_state
->rsdp
, rsdp_size
, true);
2876 build_state
->rsdp_mr
= NULL
;
2878 build_state
->rsdp
= NULL
;
2879 build_state
->rsdp_mr
= acpi_add_rom_blob(build_state
, tables
.rsdp
,
2880 ACPI_BUILD_RSDP_FILE
, 0);
2883 qemu_register_reset(acpi_build_reset
, build_state
);
2884 acpi_build_reset(build_state
);
2885 vmstate_register(NULL
, 0, &vmstate_acpi_build
, build_state
);
2887 /* Cleanup tables but don't free the memory: we track it
2890 acpi_build_tables_cleanup(&tables
, false);