hw/i386/kvmvapic.c

   1 /*
   2  * TPR optimization for 32-bit Windows guests (XP and Server 2003)
   3  *
   4  * Copyright (C) 2007-2008 Qumranet Technologies
   5  * Copyright (C) 2012      Jan Kiszka, Siemens AG
   6  *
   7  * This work is licensed under the terms of the GNU GPL version 2, or
   8  * (at your option) any later version. See the COPYING file in the
   9  * top-level directory.
  10  */
  11 #include "sysemu/sysemu.h"
  12 #include "sysemu/cpus.h"
  13 #include "sysemu/kvm.h"
  14 #include "hw/i386/apic_internal.h"
  15
  16 #define VAPIC_IO_PORT           0x7e
  17
  18 #define VAPIC_CPU_SHIFT         7
  19
  20 #define ROM_BLOCK_SIZE          512
  21 #define ROM_BLOCK_MASK          (~(ROM_BLOCK_SIZE - 1))
  22
  23 typedef enum VAPICMode {
  24     VAPIC_INACTIVE = 0,
  25     VAPIC_ACTIVE   = 1,
  26     VAPIC_STANDBY  = 2,
  27 } VAPICMode;
  28
  29 typedef struct VAPICHandlers {
  30     uint32_t set_tpr;
  31     uint32_t set_tpr_eax;
  32     uint32_t get_tpr[8];
  33     uint32_t get_tpr_stack;
  34 } QEMU_PACKED VAPICHandlers;
  35
  36 typedef struct GuestROMState {
  37     char signature[8];
  38     uint32_t vaddr;
  39     uint32_t fixup_start;
  40     uint32_t fixup_end;
  41     uint32_t vapic_vaddr;
  42     uint32_t vapic_size;
  43     uint32_t vcpu_shift;
  44     uint32_t real_tpr_addr;
  45     VAPICHandlers up;
  46     VAPICHandlers mp;
  47 } QEMU_PACKED GuestROMState;
  48
  49 typedef struct VAPICROMState {
  50     SysBusDevice busdev;
  51     MemoryRegion io;
  52     MemoryRegion rom;
  53     uint32_t state;
  54     uint32_t rom_state_paddr;
  55     uint32_t rom_state_vaddr;
  56     uint32_t vapic_paddr;
  57     uint32_t real_tpr_addr;
  58     GuestROMState rom_state;
  59     size_t rom_size;
  60     bool rom_mapped_writable;
  61 } VAPICROMState;
  62
  63 #define TYPE_VAPIC "kvmvapic"
  64 #define VAPIC(obj) OBJECT_CHECK(VAPICROMState, (obj), TYPE_VAPIC)
  65
  66 #define TPR_INSTR_ABS_MODRM             0x1
  67 #define TPR_INSTR_MATCH_MODRM_REG       0x2
  68
  69 typedef struct TPRInstruction {
  70     uint8_t opcode;
  71     uint8_t modrm_reg;
  72     unsigned int flags;
  73     TPRAccess access;
  74     size_t length;
  75     off_t addr_offset;
  76 } TPRInstruction;
  77
  78 /* must be sorted by length, shortest first */
  79 static const TPRInstruction tpr_instr[] = {
  80     { /* mov abs to eax */
  81         .opcode = 0xa1,
  82         .access = TPR_ACCESS_READ,
  83         .length = 5,
  84         .addr_offset = 1,
  85     },
  86     { /* mov eax to abs */
  87         .opcode = 0xa3,
  88         .access = TPR_ACCESS_WRITE,
  89         .length = 5,
  90         .addr_offset = 1,
  91     },
  92     { /* mov r32 to r/m32 */
  93         .opcode = 0x89,
  94         .flags = TPR_INSTR_ABS_MODRM,
  95         .access = TPR_ACCESS_WRITE,
  96         .length = 6,
  97         .addr_offset = 2,
  98     },
  99     { /* mov r/m32 to r32 */
 100         .opcode = 0x8b,
 101         .flags = TPR_INSTR_ABS_MODRM,
 102         .access = TPR_ACCESS_READ,
 103         .length = 6,
 104         .addr_offset = 2,
 105     },
 106     { /* push r/m32 */
 107         .opcode = 0xff,
 108         .modrm_reg = 6,
 109         .flags = TPR_INSTR_ABS_MODRM | TPR_INSTR_MATCH_MODRM_REG,
 110         .access = TPR_ACCESS_READ,
 111         .length = 6,
 112         .addr_offset = 2,
 113     },
 114     { /* mov imm32, r/m32 (c7/0) */
 115         .opcode = 0xc7,
 116         .modrm_reg = 0,
 117         .flags = TPR_INSTR_ABS_MODRM | TPR_INSTR_MATCH_MODRM_REG,
 118         .access = TPR_ACCESS_WRITE,
 119         .length = 10,
 120         .addr_offset = 2,
 121     },
 122 };
 123
 124 static void read_guest_rom_state(VAPICROMState *s)
 125 {
 126     cpu_physical_memory_rw(s->rom_state_paddr, (void *)&s->rom_state,
 127                            sizeof(GuestROMState), 0);
 128 }
 129
 130 static void write_guest_rom_state(VAPICROMState *s)
 131 {
 132     cpu_physical_memory_rw(s->rom_state_paddr, (void *)&s->rom_state,
 133                            sizeof(GuestROMState), 1);
 134 }
 135
 136 static void update_guest_rom_state(VAPICROMState *s)
 137 {
 138     read_guest_rom_state(s);
 139
 140     s->rom_state.real_tpr_addr = cpu_to_le32(s->real_tpr_addr);
 141     s->rom_state.vcpu_shift = cpu_to_le32(VAPIC_CPU_SHIFT);
 142
 143     write_guest_rom_state(s);
 144 }
 145
 146 static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env)
 147 {
 148     hwaddr paddr;
 149     target_ulong addr;
 150
 151     if (s->state == VAPIC_ACTIVE) {
 152         return 0;
 153     }
 154     /*
 155      * If there is no prior TPR access instruction we could analyze (which is
 156      * the case after resume from hibernation), we need to scan the possible
 157      * virtual address space for the APIC mapping.
 158      */
 159     for (addr = 0xfffff000; addr >= 0x80000000; addr -= TARGET_PAGE_SIZE) {
 160         paddr = cpu_get_phys_page_debug(env, addr);
 161         if (paddr != APIC_DEFAULT_ADDRESS) {
 162             continue;
 163         }
 164         s->real_tpr_addr = addr + 0x80;
 165         update_guest_rom_state(s);
 166         return 0;
 167     }
 168     return -1;
 169 }
 170
 171 static uint8_t modrm_reg(uint8_t modrm)
 172 {
 173     return (modrm >> 3) & 7;
 174 }
 175
 176 static bool is_abs_modrm(uint8_t modrm)
 177 {
 178     return (modrm & 0xc7) == 0x05;
 179 }
 180
 181 static bool opcode_matches(uint8_t *opcode, const TPRInstruction *instr)
 182 {
 183     return opcode[0] == instr->opcode &&
 184         (!(instr->flags & TPR_INSTR_ABS_MODRM) || is_abs_modrm(opcode[1])) &&
 185         (!(instr->flags & TPR_INSTR_MATCH_MODRM_REG) ||
 186          modrm_reg(opcode[1]) == instr->modrm_reg);
 187 }
 188
 189 static int evaluate_tpr_instruction(VAPICROMState *s, CPUX86State *env,
 190                                     target_ulong *pip, TPRAccess access)
 191 {
 192     const TPRInstruction *instr;
 193     target_ulong ip = *pip;
 194     uint8_t opcode[2];
 195     uint32_t real_tpr_addr;
 196     int i;
 197
 198     if ((ip & 0xf0000000ULL) != 0x80000000ULL &&
 199         (ip & 0xf0000000ULL) != 0xe0000000ULL) {
 200         return -1;
 201     }
 202
 203     /*
 204      * Early Windows 2003 SMP initialization contains a
 205      *
 206      *   mov imm32, r/m32
 207      *
 208      * instruction that is patched by TPR optimization. The problem is that
 209      * RSP, used by the patched instruction, is zero, so the guest gets a
 210      * double fault and dies.
 211      */
 212     if (env->regs[R_ESP] == 0) {
 213         return -1;
 214     }
 215
 216     if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
 217         /*
 218          * KVM without kernel-based TPR access reporting will pass an IP that
 219          * points after the accessing instruction. So we need to look backward
 220          * to find the reason.
 221          */
 222         for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) {
 223             instr = &tpr_instr[i];
 224             if (instr->access != access) {
 225                 continue;
 226             }
 227             if (cpu_memory_rw_debug(env, ip - instr->length, opcode,
 228                                     sizeof(opcode), 0) < 0) {
 229                 return -1;
 230             }
 231             if (opcode_matches(opcode, instr)) {
 232                 ip -= instr->length;
 233                 goto instruction_ok;
 234             }
 235         }
 236         return -1;
 237     } else {
 238         if (cpu_memory_rw_debug(env, ip, opcode, sizeof(opcode), 0) < 0) {
 239             return -1;
 240         }
 241         for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) {
 242             instr = &tpr_instr[i];
 243             if (opcode_matches(opcode, instr)) {
 244                 goto instruction_ok;
 245             }
 246         }
 247         return -1;
 248     }
 249
 250 instruction_ok:
 251     /*
 252      * Grab the virtual TPR address from the instruction
 253      * and update the cached values.
 254      */
 255     if (cpu_memory_rw_debug(env, ip + instr->addr_offset,
 256                             (void *)&real_tpr_addr,
 257                             sizeof(real_tpr_addr), 0) < 0) {
 258         return -1;
 259     }
 260     real_tpr_addr = le32_to_cpu(real_tpr_addr);
 261     if ((real_tpr_addr & 0xfff) != 0x80) {
 262         return -1;
 263     }
 264     s->real_tpr_addr = real_tpr_addr;
 265     update_guest_rom_state(s);
 266
 267     *pip = ip;
 268     return 0;
 269 }
 270
 271 static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong ip)
 272 {
 273     hwaddr paddr;
 274     uint32_t rom_state_vaddr;
 275     uint32_t pos, patch, offset;
 276
 277     /* nothing to do if already activated */
 278     if (s->state == VAPIC_ACTIVE) {
 279         return 0;
 280     }
 281
 282     /* bail out if ROM init code was not executed (missing ROM?) */
 283     if (s->state == VAPIC_INACTIVE) {
 284         return -1;
 285     }
 286
 287     /* find out virtual address of the ROM */
 288     rom_state_vaddr = s->rom_state_paddr + (ip & 0xf0000000);
 289     paddr = cpu_get_phys_page_debug(env, rom_state_vaddr);
 290     if (paddr == -1) {
 291         return -1;
 292     }
 293     paddr += rom_state_vaddr & ~TARGET_PAGE_MASK;
 294     if (paddr != s->rom_state_paddr) {
 295         return -1;
 296     }
 297     read_guest_rom_state(s);
 298     if (memcmp(s->rom_state.signature, "kvm aPiC", 8) != 0) {
 299         return -1;
 300     }
 301     s->rom_state_vaddr = rom_state_vaddr;
 302
 303     /* fixup addresses in ROM if needed */
 304     if (rom_state_vaddr == le32_to_cpu(s->rom_state.vaddr)) {
 305         return 0;
 306     }
 307     for (pos = le32_to_cpu(s->rom_state.fixup_start);
 308          pos < le32_to_cpu(s->rom_state.fixup_end);
 309          pos += 4) {
 310         cpu_physical_memory_rw(paddr + pos - s->rom_state.vaddr,
 311                                (void *)&offset, sizeof(offset), 0);
 312         offset = le32_to_cpu(offset);
 313         cpu_physical_memory_rw(paddr + offset, (void *)&patch,
 314                                sizeof(patch), 0);
 315         patch = le32_to_cpu(patch);
 316         patch += rom_state_vaddr - le32_to_cpu(s->rom_state.vaddr);
 317         patch = cpu_to_le32(patch);
 318         cpu_physical_memory_rw(paddr + offset, (void *)&patch,
 319                                sizeof(patch), 1);
 320     }
 321     read_guest_rom_state(s);
 322     s->vapic_paddr = paddr + le32_to_cpu(s->rom_state.vapic_vaddr) -
 323         le32_to_cpu(s->rom_state.vaddr);
 324
 325     return 0;
 326 }
 327
 328 /*
 329  * Tries to read the unique processor number from the Kernel Processor Control
 330  * Region (KPCR) of 32-bit Windows XP and Server 2003. Returns -1 if the KPCR
 331  * cannot be accessed or is considered invalid. This also ensures that we are
 332  * not patching the wrong guest.
 333  */
 334 static int get_kpcr_number(CPUX86State *env)
 335 {
 336     struct kpcr {
 337         uint8_t  fill1[0x1c];
 338         uint32_t self;
 339         uint8_t  fill2[0x31];
 340         uint8_t  number;
 341     } QEMU_PACKED kpcr;
 342
 343     if (cpu_memory_rw_debug(env, env->segs[R_FS].base,
 344                             (void *)&kpcr, sizeof(kpcr), 0) < 0 ||
 345         kpcr.self != env->segs[R_FS].base) {
 346         return -1;
 347     }
 348     return kpcr.number;
 349 }
 350
 351 static int vapic_enable(VAPICROMState *s, CPUX86State *env)
 352 {
 353     int cpu_number = get_kpcr_number(env);
 354     hwaddr vapic_paddr;
 355     static const uint8_t enabled = 1;
 356
 357     if (cpu_number < 0) {
 358         return -1;
 359     }
 360     vapic_paddr = s->vapic_paddr +
 361         (((hwaddr)cpu_number) << VAPIC_CPU_SHIFT);
 362     cpu_physical_memory_rw(vapic_paddr + offsetof(VAPICState, enabled),
 363                            (void *)&enabled, sizeof(enabled), 1);
 364     apic_enable_vapic(env->apic_state, vapic_paddr);
 365
 366     s->state = VAPIC_ACTIVE;
 367
 368     return 0;
 369 }
 370
 371 static void patch_byte(CPUX86State *env, target_ulong addr, uint8_t byte)
 372 {
 373     cpu_memory_rw_debug(env, addr, &byte, 1, 1);
 374 }
 375
 376 static void patch_call(VAPICROMState *s, CPUX86State *env, target_ulong ip,
 377                        uint32_t target)
 378 {
 379     uint32_t offset;
 380
 381     offset = cpu_to_le32(target - ip - 5);
 382     patch_byte(env, ip, 0xe8); /* call near */
 383     cpu_memory_rw_debug(env, ip + 1, (void *)&offset, sizeof(offset), 1);
 384 }
 385
 386 static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
 387 {
 388     CPUState *cs = CPU(cpu);
 389     CPUX86State *env = &cpu->env;
 390     VAPICHandlers *handlers;
 391     uint8_t opcode[2];
 392     uint32_t imm32;
 393     target_ulong current_pc = 0;
 394     target_ulong current_cs_base = 0;
 395     int current_flags = 0;
 396
 397     if (smp_cpus == 1) {
 398         handlers = &s->rom_state.up;
 399     } else {
 400         handlers = &s->rom_state.mp;
 401     }
 402
 403     if (!kvm_enabled()) {
 404         cpu_restore_state(env, env->mem_io_pc);
 405         cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
 406                              &current_flags);
 407     }
 408
 409     pause_all_vcpus();
 410
 411     cpu_memory_rw_debug(env, ip, opcode, sizeof(opcode), 0);
 412
 413     switch (opcode[0]) {
 414     case 0x89: /* mov r32 to r/m32 */
 415         patch_byte(env, ip, 0x50 + modrm_reg(opcode[1]));  /* push reg */
 416         patch_call(s, env, ip + 1, handlers->set_tpr);
 417         break;
 418     case 0x8b: /* mov r/m32 to r32 */
 419         patch_byte(env, ip, 0x90);
 420         patch_call(s, env, ip + 1, handlers->get_tpr[modrm_reg(opcode[1])]);
 421         break;
 422     case 0xa1: /* mov abs to eax */
 423         patch_call(s, env, ip, handlers->get_tpr[0]);
 424         break;
 425     case 0xa3: /* mov eax to abs */
 426         patch_call(s, env, ip, handlers->set_tpr_eax);
 427         break;
 428     case 0xc7: /* mov imm32, r/m32 (c7/0) */
 429         patch_byte(env, ip, 0x68);  /* push imm32 */
 430         cpu_memory_rw_debug(env, ip + 6, (void *)&imm32, sizeof(imm32), 0);
 431         cpu_memory_rw_debug(env, ip + 1, (void *)&imm32, sizeof(imm32), 1);
 432         patch_call(s, env, ip + 5, handlers->set_tpr);
 433         break;
 434     case 0xff: /* push r/m32 */
 435         patch_byte(env, ip, 0x50); /* push eax */
 436         patch_call(s, env, ip + 1, handlers->get_tpr_stack);
 437         break;
 438     default:
 439         abort();
 440     }
 441
 442     resume_all_vcpus();
 443
 444     if (!kvm_enabled()) {
 445         cs->current_tb = NULL;
 446         tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
 447         cpu_resume_from_signal(env, NULL);
 448     }
 449 }
 450
 451 void vapic_report_tpr_access(DeviceState *dev, CPUState *cs, target_ulong ip,
 452                              TPRAccess access)
 453 {
 454     VAPICROMState *s = DO_UPCAST(VAPICROMState, busdev.qdev, dev);
 455     X86CPU *cpu = X86_CPU(cs);
 456     CPUX86State *env = &cpu->env;
 457
 458     cpu_synchronize_state(env);
 459
 460     if (evaluate_tpr_instruction(s, env, &ip, access) < 0) {
 461         if (s->state == VAPIC_ACTIVE) {
 462             vapic_enable(s, env);
 463         }
 464         return;
 465     }
 466     if (update_rom_mapping(s, env, ip) < 0) {
 467         return;
 468     }
 469     if (vapic_enable(s, env) < 0) {
 470         return;
 471     }
 472     patch_instruction(s, cpu, ip);
 473 }
 474
 475 typedef struct VAPICEnableTPRReporting {
 476     DeviceState *apic;
 477     bool enable;
 478 } VAPICEnableTPRReporting;
 479
 480 static void vapic_do_enable_tpr_reporting(void *data)
 481 {
 482     VAPICEnableTPRReporting *info = data;
 483
 484     apic_enable_tpr_access_reporting(info->apic, info->enable);
 485 }
 486
 487 static void vapic_enable_tpr_reporting(bool enable)
 488 {
 489     VAPICEnableTPRReporting info = {
 490         .enable = enable,
 491     };
 492     X86CPU *cpu;
 493     CPUX86State *env;
 494
 495     for (env = first_cpu; env != NULL; env = env->next_cpu) {
 496         cpu = x86_env_get_cpu(env);
 497         info.apic = env->apic_state;
 498         run_on_cpu(CPU(cpu), vapic_do_enable_tpr_reporting, &info);
 499     }
 500 }
 501
 502 static void vapic_reset(DeviceState *dev)
 503 {
 504     VAPICROMState *s = DO_UPCAST(VAPICROMState, busdev.qdev, dev);
 505
 506     if (s->state == VAPIC_ACTIVE) {
 507         s->state = VAPIC_STANDBY;
 508     }
 509     vapic_enable_tpr_reporting(false);
 510 }
 511
 512 /*
 513  * Set the IRQ polling hypercalls to the supported variant:
 514  *  - vmcall if using KVM in-kernel irqchip
 515  *  - 32-bit VAPIC port write otherwise
 516  */
 517 static int patch_hypercalls(VAPICROMState *s)
 518 {
 519     hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
 520     static const uint8_t vmcall_pattern[] = { /* vmcall */
 521         0xb8, 0x1, 0, 0, 0, 0xf, 0x1, 0xc1
 522     };
 523     static const uint8_t outl_pattern[] = { /* nop; outl %eax,0x7e */
 524         0xb8, 0x1, 0, 0, 0, 0x90, 0xe7, 0x7e
 525     };
 526     uint8_t alternates[2];
 527     const uint8_t *pattern;
 528     const uint8_t *patch;
 529     int patches = 0;
 530     off_t pos;
 531     uint8_t *rom;
 532
 533     rom = g_malloc(s->rom_size);
 534     cpu_physical_memory_rw(rom_paddr, rom, s->rom_size, 0);
 535
 536     for (pos = 0; pos < s->rom_size - sizeof(vmcall_pattern); pos++) {
 537         if (kvm_irqchip_in_kernel()) {
 538             pattern = outl_pattern;
 539             alternates[0] = outl_pattern[7];
 540             alternates[1] = outl_pattern[7];
 541             patch = &vmcall_pattern[5];
 542         } else {
 543             pattern = vmcall_pattern;
 544             alternates[0] = vmcall_pattern[7];
 545             alternates[1] = 0xd9; /* AMD's VMMCALL */
 546             patch = &outl_pattern[5];
 547         }
 548         if (memcmp(rom + pos, pattern, 7) == 0 &&
 549             (rom[pos + 7] == alternates[0] || rom[pos + 7] == alternates[1])) {
 550             cpu_physical_memory_rw(rom_paddr + pos + 5, (uint8_t *)patch,
 551                                    3, 1);
 552             /*
 553              * Don't flush the tb here. Under ordinary conditions, the patched
 554              * calls are miles away from the current IP. Under malicious
 555              * conditions, the guest could trick us to crash.
 556              */
 557         }
 558     }
 559
 560     g_free(rom);
 561
 562     if (patches != 0 && patches != 2) {
 563         return -1;
 564     }
 565
 566     return 0;
 567 }
 568
 569 /*
 570  * For TCG mode or the time KVM honors read-only memory regions, we need to
 571  * enable write access to the option ROM so that variables can be updated by
 572  * the guest.
 573  */
 574 static void vapic_map_rom_writable(VAPICROMState *s)
 575 {
 576     hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
 577     MemoryRegionSection section;
 578     MemoryRegion *as;
 579     size_t rom_size;
 580     uint8_t *ram;
 581
 582     as = sysbus_address_space(&s->busdev);
 583
 584     if (s->rom_mapped_writable) {
 585         memory_region_del_subregion(as, &s->rom);
 586         memory_region_destroy(&s->rom);
 587     }
 588
 589     /* grab RAM memory region (region @rom_paddr may still be pc.rom) */
 590     section = memory_region_find(as, 0, 1);
 591
 592     /* read ROM size from RAM region */
 593     ram = memory_region_get_ram_ptr(section.mr);
 594     rom_size = ram[rom_paddr + 2] * ROM_BLOCK_SIZE;
 595     s->rom_size = rom_size;
 596
 597     /* We need to round to avoid creating subpages
 598      * from which we cannot run code. */
 599     rom_size += rom_paddr & ~TARGET_PAGE_MASK;
 600     rom_paddr &= TARGET_PAGE_MASK;
 601     rom_size = TARGET_PAGE_ALIGN(rom_size);
 602
 603     memory_region_init_alias(&s->rom, "kvmvapic-rom", section.mr, rom_paddr,
 604                              rom_size);
 605     memory_region_add_subregion_overlap(as, rom_paddr, &s->rom, 1000);
 606     s->rom_mapped_writable = true;
 607 }
 608
 609 static int vapic_prepare(VAPICROMState *s)
 610 {
 611     vapic_map_rom_writable(s);
 612
 613     if (patch_hypercalls(s) < 0) {
 614         return -1;
 615     }
 616
 617     vapic_enable_tpr_reporting(true);
 618
 619     return 0;
 620 }
 621
 622 static void vapic_write(void *opaque, hwaddr addr, uint64_t data,
 623                         unsigned int size)
 624 {
 625     CPUX86State *env = cpu_single_env;
 626     hwaddr rom_paddr;
 627     VAPICROMState *s = opaque;
 628
 629     cpu_synchronize_state(env);
 630
 631     /*
 632      * The VAPIC supports two PIO-based hypercalls, both via port 0x7E.
 633      *  o 16-bit write access:
 634      *    Reports the option ROM initialization to the hypervisor. Written
 635      *    value is the offset of the state structure in the ROM.
 636      *  o 8-bit write access:
 637      *    Reactivates the VAPIC after a guest hibernation, i.e. after the
 638      *    option ROM content has been re-initialized by a guest power cycle.
 639      *  o 32-bit write access:
 640      *    Poll for pending IRQs, considering the current VAPIC state.
 641      */
 642     switch (size) {
 643     case 2:
 644         if (s->state == VAPIC_INACTIVE) {
 645             rom_paddr = (env->segs[R_CS].base + env->eip) & ROM_BLOCK_MASK;
 646             s->rom_state_paddr = rom_paddr + data;
 647
 648             s->state = VAPIC_STANDBY;
 649         }
 650         if (vapic_prepare(s) < 0) {
 651             s->state = VAPIC_INACTIVE;
 652             break;
 653         }
 654         break;
 655     case 1:
 656         if (kvm_enabled()) {
 657             /*
 658              * Disable triggering instruction in ROM by writing a NOP.
 659              *
 660              * We cannot do this in TCG mode as the reported IP is not
 661              * accurate.
 662              */
 663             pause_all_vcpus();
 664             patch_byte(env, env->eip - 2, 0x66);
 665             patch_byte(env, env->eip - 1, 0x90);
 666             resume_all_vcpus();
 667         }
 668
 669         if (s->state == VAPIC_ACTIVE) {
 670             break;
 671         }
 672         if (update_rom_mapping(s, env, env->eip) < 0) {
 673             break;
 674         }
 675         if (find_real_tpr_addr(s, env) < 0) {
 676             break;
 677         }
 678         vapic_enable(s, env);
 679         break;
 680     default:
 681     case 4:
 682         if (!kvm_irqchip_in_kernel()) {
 683             apic_poll_irq(env->apic_state);
 684         }
 685         break;
 686     }
 687 }
 688
 689 static const MemoryRegionOps vapic_ops = {
 690     .write = vapic_write,
 691     .endianness = DEVICE_NATIVE_ENDIAN,
 692 };
 693
 694 static int vapic_init(SysBusDevice *dev)
 695 {
 696     VAPICROMState *s = VAPIC(dev);
 697
 698     memory_region_init_io(&s->io, &vapic_ops, s, "kvmvapic", 2);
 699     sysbus_add_io(dev, VAPIC_IO_PORT, &s->io);
 700     sysbus_init_ioports(dev, VAPIC_IO_PORT, 2);
 701
 702     option_rom[nb_option_roms].name = "kvmvapic.bin";
 703     option_rom[nb_option_roms].bootindex = -1;
 704     nb_option_roms++;
 705
 706     return 0;
 707 }
 708
 709 static void do_vapic_enable(void *data)
 710 {
 711     VAPICROMState *s = data;
 712
 713     vapic_enable(s, first_cpu);
 714 }
 715
 716 static int vapic_post_load(void *opaque, int version_id)
 717 {
 718     VAPICROMState *s = opaque;
 719     uint8_t *zero;
 720
 721     /*
 722      * The old implementation of qemu-kvm did not provide the state
 723      * VAPIC_STANDBY. Reconstruct it.
 724      */
 725     if (s->state == VAPIC_INACTIVE && s->rom_state_paddr != 0) {
 726         s->state = VAPIC_STANDBY;
 727     }
 728
 729     if (s->state != VAPIC_INACTIVE) {
 730         if (vapic_prepare(s) < 0) {
 731             return -1;
 732         }
 733     }
 734     if (s->state == VAPIC_ACTIVE) {
 735         if (smp_cpus == 1) {
 736             run_on_cpu(ENV_GET_CPU(first_cpu), do_vapic_enable, s);
 737         } else {
 738             zero = g_malloc0(s->rom_state.vapic_size);
 739             cpu_physical_memory_rw(s->vapic_paddr, zero,
 740                                    s->rom_state.vapic_size, 1);
 741             g_free(zero);
 742         }
 743     }
 744
 745     return 0;
 746 }
 747
 748 static const VMStateDescription vmstate_handlers = {
 749     .name = "kvmvapic-handlers",
 750     .version_id = 1,
 751     .minimum_version_id = 1,
 752     .minimum_version_id_old = 1,
 753     .fields = (VMStateField[]) {
 754         VMSTATE_UINT32(set_tpr, VAPICHandlers),
 755         VMSTATE_UINT32(set_tpr_eax, VAPICHandlers),
 756         VMSTATE_UINT32_ARRAY(get_tpr, VAPICHandlers, 8),
 757         VMSTATE_UINT32(get_tpr_stack, VAPICHandlers),
 758         VMSTATE_END_OF_LIST()
 759     }
 760 };
 761
 762 static const VMStateDescription vmstate_guest_rom = {
 763     .name = "kvmvapic-guest-rom",
 764     .version_id = 1,
 765     .minimum_version_id = 1,
 766     .minimum_version_id_old = 1,
 767     .fields = (VMStateField[]) {
 768         VMSTATE_UNUSED(8),     /* signature */
 769         VMSTATE_UINT32(vaddr, GuestROMState),
 770         VMSTATE_UINT32(fixup_start, GuestROMState),
 771         VMSTATE_UINT32(fixup_end, GuestROMState),
 772         VMSTATE_UINT32(vapic_vaddr, GuestROMState),
 773         VMSTATE_UINT32(vapic_size, GuestROMState),
 774         VMSTATE_UINT32(vcpu_shift, GuestROMState),
 775         VMSTATE_UINT32(real_tpr_addr, GuestROMState),
 776         VMSTATE_STRUCT(up, GuestROMState, 0, vmstate_handlers, VAPICHandlers),
 777         VMSTATE_STRUCT(mp, GuestROMState, 0, vmstate_handlers, VAPICHandlers),
 778         VMSTATE_END_OF_LIST()
 779     }
 780 };
 781
 782 static const VMStateDescription vmstate_vapic = {
 783     .name = "kvm-tpr-opt",      /* compatible with qemu-kvm VAPIC */
 784     .version_id = 1,
 785     .minimum_version_id = 1,
 786     .minimum_version_id_old = 1,
 787     .post_load = vapic_post_load,
 788     .fields = (VMStateField[]) {
 789         VMSTATE_STRUCT(rom_state, VAPICROMState, 0, vmstate_guest_rom,
 790                        GuestROMState),
 791         VMSTATE_UINT32(state, VAPICROMState),
 792         VMSTATE_UINT32(real_tpr_addr, VAPICROMState),
 793         VMSTATE_UINT32(rom_state_vaddr, VAPICROMState),
 794         VMSTATE_UINT32(vapic_paddr, VAPICROMState),
 795         VMSTATE_UINT32(rom_state_paddr, VAPICROMState),
 796         VMSTATE_END_OF_LIST()
 797     }
 798 };
 799
 800 static void vapic_class_init(ObjectClass *klass, void *data)
 801 {
 802     SysBusDeviceClass *sc = SYS_BUS_DEVICE_CLASS(klass);
 803     DeviceClass *dc = DEVICE_CLASS(klass);
 804
 805     dc->no_user = 1;
 806     dc->reset   = vapic_reset;
 807     dc->vmsd    = &vmstate_vapic;
 808     sc->init    = vapic_init;
 809 }
 810
 811 static const TypeInfo vapic_type = {
 812     .name          = TYPE_VAPIC,
 813     .parent        = TYPE_SYS_BUS_DEVICE,
 814     .instance_size = sizeof(VAPICROMState),
 815     .class_init    = vapic_class_init,
 816 };
 817
 818 static void vapic_register(void)
 819 {
 820     type_register_static(&vapic_type);
 821 }
 822
 823 type_init(vapic_register);