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[mirror_qemu.git] / hw / i386 / pc.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/hw.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "sysemu/cpus.h"
34 #include "hw/block/fdc.h"
35 #include "hw/ide.h"
36 #include "hw/pci/pci.h"
37 #include "hw/pci/pci_bus.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/timer/hpet.h"
40 #include "hw/firmware/smbios.h"
41 #include "hw/loader.h"
42 #include "elf.h"
43 #include "multiboot.h"
44 #include "hw/timer/mc146818rtc.h"
45 #include "hw/dma/i8257.h"
46 #include "hw/timer/i8254.h"
47 #include "hw/input/i8042.h"
48 #include "hw/audio/pcspk.h"
49 #include "hw/pci/msi.h"
50 #include "hw/sysbus.h"
51 #include "sysemu/sysemu.h"
52 #include "sysemu/numa.h"
53 #include "sysemu/kvm.h"
54 #include "sysemu/qtest.h"
55 #include "kvm_i386.h"
56 #include "hw/xen/xen.h"
57 #include "ui/qemu-spice.h"
58 #include "exec/memory.h"
59 #include "exec/address-spaces.h"
60 #include "sysemu/arch_init.h"
61 #include "qemu/bitmap.h"
62 #include "qemu/config-file.h"
63 #include "qemu/error-report.h"
64 #include "qemu/option.h"
65 #include "hw/acpi/acpi.h"
66 #include "hw/acpi/cpu_hotplug.h"
67 #include "hw/boards.h"
68 #include "acpi-build.h"
69 #include "hw/mem/pc-dimm.h"
70 #include "qapi/error.h"
71 #include "qapi/qapi-visit-common.h"
72 #include "qapi/visitor.h"
73 #include "qom/cpu.h"
74 #include "hw/nmi.h"
75 #include "hw/usb.h"
76 #include "hw/i386/intel_iommu.h"
77 #include "hw/net/ne2000-isa.h"
78
79 /* debug PC/ISA interrupts */
80 //#define DEBUG_IRQ
81
82 #ifdef DEBUG_IRQ
83 #define DPRINTF(fmt, ...) \
84 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
85 #else
86 #define DPRINTF(fmt, ...)
87 #endif
88
89 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
90 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
91 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
92 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
93 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
94
95 #define E820_NR_ENTRIES 16
96
97 struct e820_entry {
98 uint64_t address;
99 uint64_t length;
100 uint32_t type;
101 } QEMU_PACKED __attribute((__aligned__(4)));
102
103 struct e820_table {
104 uint32_t count;
105 struct e820_entry entry[E820_NR_ENTRIES];
106 } QEMU_PACKED __attribute((__aligned__(4)));
107
108 static struct e820_table e820_reserve;
109 static struct e820_entry *e820_table;
110 static unsigned e820_entries;
111 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
112
113 GlobalProperty pc_compat_3_1[] = {
114 { "intel-iommu", "dma-drain", "off" },
115 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
116 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
117 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
118 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
119 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
120 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
121 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
122 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
123 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
124 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
125 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
126 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
127 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
128 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
129 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
130 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
131 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
132 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
133 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
134 };
135 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
136
137 GlobalProperty pc_compat_3_0[] = {
138 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
139 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
140 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
141 };
142 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
143
144 GlobalProperty pc_compat_2_12[] = {
145 { TYPE_X86_CPU, "legacy-cache", "on" },
146 { TYPE_X86_CPU, "topoext", "off" },
147 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
148 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
149 };
150 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
151
152 GlobalProperty pc_compat_2_11[] = {
153 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
154 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
155 };
156 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
157
158 GlobalProperty pc_compat_2_10[] = {
159 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
160 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
161 { "q35-pcihost", "x-pci-hole64-fix", "off" },
162 };
163 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
164
165 GlobalProperty pc_compat_2_9[] = {
166 { "mch", "extended-tseg-mbytes", "0" },
167 };
168 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
169
170 GlobalProperty pc_compat_2_8[] = {
171 { TYPE_X86_CPU, "tcg-cpuid", "off" },
172 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
173 { "ICH9-LPC", "x-smi-broadcast", "off" },
174 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
175 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
176 };
177 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
178
179 GlobalProperty pc_compat_2_7[] = {
180 { TYPE_X86_CPU, "l3-cache", "off" },
181 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
182 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
183 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
184 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
185 { "isa-pcspk", "migrate", "off" },
186 };
187 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
188
189 GlobalProperty pc_compat_2_6[] = {
190 { TYPE_X86_CPU, "cpuid-0xb", "off" },
191 { "vmxnet3", "romfile", "" },
192 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
193 { "apic-common", "legacy-instance-id", "on", }
194 };
195 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
196
197 GlobalProperty pc_compat_2_5[] = {};
198 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
199
200 GlobalProperty pc_compat_2_4[] = {
201 PC_CPU_MODEL_IDS("2.4.0")
202 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
203 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
204 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
205 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
206 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
207 { TYPE_X86_CPU, "check", "off" },
208 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
209 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
210 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
211 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
212 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
213 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
214 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
215 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
216 };
217 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
218
219 GlobalProperty pc_compat_2_3[] = {
220 PC_CPU_MODEL_IDS("2.3.0")
221 { TYPE_X86_CPU, "arat", "off" },
222 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
223 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
224 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
225 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
226 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
227 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
228 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
229 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
230 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
231 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
232 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
233 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
234 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
235 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
236 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
237 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
238 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
239 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
240 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
241 };
242 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
243
244 GlobalProperty pc_compat_2_2[] = {
245 PC_CPU_MODEL_IDS("2.2.0")
246 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
247 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
248 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
249 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
250 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
251 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
252 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
253 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
254 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
255 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
256 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
257 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
258 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
259 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
260 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
261 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
262 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
263 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
264 };
265 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
266
267 GlobalProperty pc_compat_2_1[] = {
268 PC_CPU_MODEL_IDS("2.1.0")
269 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
270 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
271 };
272 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
273
274 GlobalProperty pc_compat_2_0[] = {
275 PC_CPU_MODEL_IDS("2.0.0")
276 { "virtio-scsi-pci", "any_layout", "off" },
277 { "PIIX4_PM", "memory-hotplug-support", "off" },
278 { "apic", "version", "0x11" },
279 { "nec-usb-xhci", "superspeed-ports-first", "off" },
280 { "nec-usb-xhci", "force-pcie-endcap", "on" },
281 { "pci-serial", "prog_if", "0" },
282 { "pci-serial-2x", "prog_if", "0" },
283 { "pci-serial-4x", "prog_if", "0" },
284 { "virtio-net-pci", "guest_announce", "off" },
285 { "ICH9-LPC", "memory-hotplug-support", "off" },
286 { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
287 { "ioh3420", COMPAT_PROP_PCP, "off" },
288 };
289 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
290
291 GlobalProperty pc_compat_1_7[] = {
292 PC_CPU_MODEL_IDS("1.7.0")
293 { TYPE_USB_DEVICE, "msos-desc", "no" },
294 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
295 { "hpet", HPET_INTCAP, "4" },
296 };
297 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
298
299 GlobalProperty pc_compat_1_6[] = {
300 PC_CPU_MODEL_IDS("1.6.0")
301 { "e1000", "mitigation", "off" },
302 { "qemu64-" TYPE_X86_CPU, "model", "2" },
303 { "qemu32-" TYPE_X86_CPU, "model", "3" },
304 { "i440FX-pcihost", "short_root_bus", "1" },
305 { "q35-pcihost", "short_root_bus", "1" },
306 };
307 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
308
309 GlobalProperty pc_compat_1_5[] = {
310 PC_CPU_MODEL_IDS("1.5.0")
311 { "Conroe-" TYPE_X86_CPU, "model", "2" },
312 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
313 { "Penryn-" TYPE_X86_CPU, "model", "2" },
314 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
315 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
316 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
317 { "virtio-net-pci", "any_layout", "off" },
318 { TYPE_X86_CPU, "pmu", "on" },
319 { "i440FX-pcihost", "short_root_bus", "0" },
320 { "q35-pcihost", "short_root_bus", "0" },
321 };
322 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
323
324 GlobalProperty pc_compat_1_4[] = {
325 PC_CPU_MODEL_IDS("1.4.0")
326 { "scsi-hd", "discard_granularity", "0" },
327 { "scsi-cd", "discard_granularity", "0" },
328 { "scsi-disk", "discard_granularity", "0" },
329 { "ide-hd", "discard_granularity", "0" },
330 { "ide-cd", "discard_granularity", "0" },
331 { "ide-drive", "discard_granularity", "0" },
332 { "virtio-blk-pci", "discard_granularity", "0" },
333 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
334 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
335 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
336 { "e1000", "romfile", "pxe-e1000.rom" },
337 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
338 { "pcnet", "romfile", "pxe-pcnet.rom" },
339 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
340 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
341 { "486-" TYPE_X86_CPU, "model", "0" },
342 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
343 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
344 };
345 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
346
347 void gsi_handler(void *opaque, int n, int level)
348 {
349 GSIState *s = opaque;
350
351 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
352 if (n < ISA_NUM_IRQS) {
353 qemu_set_irq(s->i8259_irq[n], level);
354 }
355 qemu_set_irq(s->ioapic_irq[n], level);
356 }
357
358 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
359 unsigned size)
360 {
361 }
362
363 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
364 {
365 return 0xffffffffffffffffULL;
366 }
367
368 /* MSDOS compatibility mode FPU exception support */
369 static qemu_irq ferr_irq;
370
371 void pc_register_ferr_irq(qemu_irq irq)
372 {
373 ferr_irq = irq;
374 }
375
376 /* XXX: add IGNNE support */
377 void cpu_set_ferr(CPUX86State *s)
378 {
379 qemu_irq_raise(ferr_irq);
380 }
381
382 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
383 unsigned size)
384 {
385 qemu_irq_lower(ferr_irq);
386 }
387
388 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
389 {
390 return 0xffffffffffffffffULL;
391 }
392
393 /* TSC handling */
394 uint64_t cpu_get_tsc(CPUX86State *env)
395 {
396 return cpu_get_ticks();
397 }
398
399 /* IRQ handling */
400 int cpu_get_pic_interrupt(CPUX86State *env)
401 {
402 X86CPU *cpu = x86_env_get_cpu(env);
403 int intno;
404
405 if (!kvm_irqchip_in_kernel()) {
406 intno = apic_get_interrupt(cpu->apic_state);
407 if (intno >= 0) {
408 return intno;
409 }
410 /* read the irq from the PIC */
411 if (!apic_accept_pic_intr(cpu->apic_state)) {
412 return -1;
413 }
414 }
415
416 intno = pic_read_irq(isa_pic);
417 return intno;
418 }
419
420 static void pic_irq_request(void *opaque, int irq, int level)
421 {
422 CPUState *cs = first_cpu;
423 X86CPU *cpu = X86_CPU(cs);
424
425 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
426 if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
427 CPU_FOREACH(cs) {
428 cpu = X86_CPU(cs);
429 if (apic_accept_pic_intr(cpu->apic_state)) {
430 apic_deliver_pic_intr(cpu->apic_state, level);
431 }
432 }
433 } else {
434 if (level) {
435 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
436 } else {
437 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
438 }
439 }
440 }
441
442 /* PC cmos mappings */
443
444 #define REG_EQUIPMENT_BYTE 0x14
445
446 int cmos_get_fd_drive_type(FloppyDriveType fd0)
447 {
448 int val;
449
450 switch (fd0) {
451 case FLOPPY_DRIVE_TYPE_144:
452 /* 1.44 Mb 3"5 drive */
453 val = 4;
454 break;
455 case FLOPPY_DRIVE_TYPE_288:
456 /* 2.88 Mb 3"5 drive */
457 val = 5;
458 break;
459 case FLOPPY_DRIVE_TYPE_120:
460 /* 1.2 Mb 5"5 drive */
461 val = 2;
462 break;
463 case FLOPPY_DRIVE_TYPE_NONE:
464 default:
465 val = 0;
466 break;
467 }
468 return val;
469 }
470
471 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
472 int16_t cylinders, int8_t heads, int8_t sectors)
473 {
474 rtc_set_memory(s, type_ofs, 47);
475 rtc_set_memory(s, info_ofs, cylinders);
476 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
477 rtc_set_memory(s, info_ofs + 2, heads);
478 rtc_set_memory(s, info_ofs + 3, 0xff);
479 rtc_set_memory(s, info_ofs + 4, 0xff);
480 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
481 rtc_set_memory(s, info_ofs + 6, cylinders);
482 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
483 rtc_set_memory(s, info_ofs + 8, sectors);
484 }
485
486 /* convert boot_device letter to something recognizable by the bios */
487 static int boot_device2nibble(char boot_device)
488 {
489 switch(boot_device) {
490 case 'a':
491 case 'b':
492 return 0x01; /* floppy boot */
493 case 'c':
494 return 0x02; /* hard drive boot */
495 case 'd':
496 return 0x03; /* CD-ROM boot */
497 case 'n':
498 return 0x04; /* Network boot */
499 }
500 return 0;
501 }
502
503 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
504 {
505 #define PC_MAX_BOOT_DEVICES 3
506 int nbds, bds[3] = { 0, };
507 int i;
508
509 nbds = strlen(boot_device);
510 if (nbds > PC_MAX_BOOT_DEVICES) {
511 error_setg(errp, "Too many boot devices for PC");
512 return;
513 }
514 for (i = 0; i < nbds; i++) {
515 bds[i] = boot_device2nibble(boot_device[i]);
516 if (bds[i] == 0) {
517 error_setg(errp, "Invalid boot device for PC: '%c'",
518 boot_device[i]);
519 return;
520 }
521 }
522 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
523 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
524 }
525
526 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
527 {
528 set_boot_dev(opaque, boot_device, errp);
529 }
530
531 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
532 {
533 int val, nb, i;
534 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
535 FLOPPY_DRIVE_TYPE_NONE };
536
537 /* floppy type */
538 if (floppy) {
539 for (i = 0; i < 2; i++) {
540 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
541 }
542 }
543 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
544 cmos_get_fd_drive_type(fd_type[1]);
545 rtc_set_memory(rtc_state, 0x10, val);
546
547 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
548 nb = 0;
549 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
550 nb++;
551 }
552 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
553 nb++;
554 }
555 switch (nb) {
556 case 0:
557 break;
558 case 1:
559 val |= 0x01; /* 1 drive, ready for boot */
560 break;
561 case 2:
562 val |= 0x41; /* 2 drives, ready for boot */
563 break;
564 }
565 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
566 }
567
568 typedef struct pc_cmos_init_late_arg {
569 ISADevice *rtc_state;
570 BusState *idebus[2];
571 } pc_cmos_init_late_arg;
572
573 typedef struct check_fdc_state {
574 ISADevice *floppy;
575 bool multiple;
576 } CheckFdcState;
577
578 static int check_fdc(Object *obj, void *opaque)
579 {
580 CheckFdcState *state = opaque;
581 Object *fdc;
582 uint32_t iobase;
583 Error *local_err = NULL;
584
585 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
586 if (!fdc) {
587 return 0;
588 }
589
590 iobase = object_property_get_uint(obj, "iobase", &local_err);
591 if (local_err || iobase != 0x3f0) {
592 error_free(local_err);
593 return 0;
594 }
595
596 if (state->floppy) {
597 state->multiple = true;
598 } else {
599 state->floppy = ISA_DEVICE(obj);
600 }
601 return 0;
602 }
603
604 static const char * const fdc_container_path[] = {
605 "/unattached", "/peripheral", "/peripheral-anon"
606 };
607
608 /*
609 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
610 * and ACPI objects.
611 */
612 ISADevice *pc_find_fdc0(void)
613 {
614 int i;
615 Object *container;
616 CheckFdcState state = { 0 };
617
618 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
619 container = container_get(qdev_get_machine(), fdc_container_path[i]);
620 object_child_foreach(container, check_fdc, &state);
621 }
622
623 if (state.multiple) {
624 warn_report("multiple floppy disk controllers with "
625 "iobase=0x3f0 have been found");
626 error_printf("the one being picked for CMOS setup might not reflect "
627 "your intent");
628 }
629
630 return state.floppy;
631 }
632
633 static void pc_cmos_init_late(void *opaque)
634 {
635 pc_cmos_init_late_arg *arg = opaque;
636 ISADevice *s = arg->rtc_state;
637 int16_t cylinders;
638 int8_t heads, sectors;
639 int val;
640 int i, trans;
641
642 val = 0;
643 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
644 &cylinders, &heads, &sectors) >= 0) {
645 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
646 val |= 0xf0;
647 }
648 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
649 &cylinders, &heads, &sectors) >= 0) {
650 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
651 val |= 0x0f;
652 }
653 rtc_set_memory(s, 0x12, val);
654
655 val = 0;
656 for (i = 0; i < 4; i++) {
657 /* NOTE: ide_get_geometry() returns the physical
658 geometry. It is always such that: 1 <= sects <= 63, 1
659 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
660 geometry can be different if a translation is done. */
661 if (arg->idebus[i / 2] &&
662 ide_get_geometry(arg->idebus[i / 2], i % 2,
663 &cylinders, &heads, &sectors) >= 0) {
664 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
665 assert((trans & ~3) == 0);
666 val |= trans << (i * 2);
667 }
668 }
669 rtc_set_memory(s, 0x39, val);
670
671 pc_cmos_init_floppy(s, pc_find_fdc0());
672
673 qemu_unregister_reset(pc_cmos_init_late, opaque);
674 }
675
676 void pc_cmos_init(PCMachineState *pcms,
677 BusState *idebus0, BusState *idebus1,
678 ISADevice *s)
679 {
680 int val;
681 static pc_cmos_init_late_arg arg;
682
683 /* various important CMOS locations needed by PC/Bochs bios */
684
685 /* memory size */
686 /* base memory (first MiB) */
687 val = MIN(pcms->below_4g_mem_size / KiB, 640);
688 rtc_set_memory(s, 0x15, val);
689 rtc_set_memory(s, 0x16, val >> 8);
690 /* extended memory (next 64MiB) */
691 if (pcms->below_4g_mem_size > 1 * MiB) {
692 val = (pcms->below_4g_mem_size - 1 * MiB) / KiB;
693 } else {
694 val = 0;
695 }
696 if (val > 65535)
697 val = 65535;
698 rtc_set_memory(s, 0x17, val);
699 rtc_set_memory(s, 0x18, val >> 8);
700 rtc_set_memory(s, 0x30, val);
701 rtc_set_memory(s, 0x31, val >> 8);
702 /* memory between 16MiB and 4GiB */
703 if (pcms->below_4g_mem_size > 16 * MiB) {
704 val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
705 } else {
706 val = 0;
707 }
708 if (val > 65535)
709 val = 65535;
710 rtc_set_memory(s, 0x34, val);
711 rtc_set_memory(s, 0x35, val >> 8);
712 /* memory above 4GiB */
713 val = pcms->above_4g_mem_size / 65536;
714 rtc_set_memory(s, 0x5b, val);
715 rtc_set_memory(s, 0x5c, val >> 8);
716 rtc_set_memory(s, 0x5d, val >> 16);
717
718 object_property_add_link(OBJECT(pcms), "rtc_state",
719 TYPE_ISA_DEVICE,
720 (Object **)&pcms->rtc,
721 object_property_allow_set_link,
722 OBJ_PROP_LINK_STRONG, &error_abort);
723 object_property_set_link(OBJECT(pcms), OBJECT(s),
724 "rtc_state", &error_abort);
725
726 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
727
728 val = 0;
729 val |= 0x02; /* FPU is there */
730 val |= 0x04; /* PS/2 mouse installed */
731 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
732
733 /* hard drives and FDC */
734 arg.rtc_state = s;
735 arg.idebus[0] = idebus0;
736 arg.idebus[1] = idebus1;
737 qemu_register_reset(pc_cmos_init_late, &arg);
738 }
739
740 #define TYPE_PORT92 "port92"
741 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
742
743 /* port 92 stuff: could be split off */
744 typedef struct Port92State {
745 ISADevice parent_obj;
746
747 MemoryRegion io;
748 uint8_t outport;
749 qemu_irq a20_out;
750 } Port92State;
751
752 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
753 unsigned size)
754 {
755 Port92State *s = opaque;
756 int oldval = s->outport;
757
758 DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
759 s->outport = val;
760 qemu_set_irq(s->a20_out, (val >> 1) & 1);
761 if ((val & 1) && !(oldval & 1)) {
762 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
763 }
764 }
765
766 static uint64_t port92_read(void *opaque, hwaddr addr,
767 unsigned size)
768 {
769 Port92State *s = opaque;
770 uint32_t ret;
771
772 ret = s->outport;
773 DPRINTF("port92: read 0x%02x\n", ret);
774 return ret;
775 }
776
777 static void port92_init(ISADevice *dev, qemu_irq a20_out)
778 {
779 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
780 }
781
782 static const VMStateDescription vmstate_port92_isa = {
783 .name = "port92",
784 .version_id = 1,
785 .minimum_version_id = 1,
786 .fields = (VMStateField[]) {
787 VMSTATE_UINT8(outport, Port92State),
788 VMSTATE_END_OF_LIST()
789 }
790 };
791
792 static void port92_reset(DeviceState *d)
793 {
794 Port92State *s = PORT92(d);
795
796 s->outport &= ~1;
797 }
798
799 static const MemoryRegionOps port92_ops = {
800 .read = port92_read,
801 .write = port92_write,
802 .impl = {
803 .min_access_size = 1,
804 .max_access_size = 1,
805 },
806 .endianness = DEVICE_LITTLE_ENDIAN,
807 };
808
809 static void port92_initfn(Object *obj)
810 {
811 Port92State *s = PORT92(obj);
812
813 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
814
815 s->outport = 0;
816
817 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
818 }
819
820 static void port92_realizefn(DeviceState *dev, Error **errp)
821 {
822 ISADevice *isadev = ISA_DEVICE(dev);
823 Port92State *s = PORT92(dev);
824
825 isa_register_ioport(isadev, &s->io, 0x92);
826 }
827
828 static void port92_class_initfn(ObjectClass *klass, void *data)
829 {
830 DeviceClass *dc = DEVICE_CLASS(klass);
831
832 dc->realize = port92_realizefn;
833 dc->reset = port92_reset;
834 dc->vmsd = &vmstate_port92_isa;
835 /*
836 * Reason: unlike ordinary ISA devices, this one needs additional
837 * wiring: its A20 output line needs to be wired up by
838 * port92_init().
839 */
840 dc->user_creatable = false;
841 }
842
843 static const TypeInfo port92_info = {
844 .name = TYPE_PORT92,
845 .parent = TYPE_ISA_DEVICE,
846 .instance_size = sizeof(Port92State),
847 .instance_init = port92_initfn,
848 .class_init = port92_class_initfn,
849 };
850
851 static void port92_register_types(void)
852 {
853 type_register_static(&port92_info);
854 }
855
856 type_init(port92_register_types)
857
858 static void handle_a20_line_change(void *opaque, int irq, int level)
859 {
860 X86CPU *cpu = opaque;
861
862 /* XXX: send to all CPUs ? */
863 /* XXX: add logic to handle multiple A20 line sources */
864 x86_cpu_set_a20(cpu, level);
865 }
866
867 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
868 {
869 int index = le32_to_cpu(e820_reserve.count);
870 struct e820_entry *entry;
871
872 if (type != E820_RAM) {
873 /* old FW_CFG_E820_TABLE entry -- reservations only */
874 if (index >= E820_NR_ENTRIES) {
875 return -EBUSY;
876 }
877 entry = &e820_reserve.entry[index++];
878
879 entry->address = cpu_to_le64(address);
880 entry->length = cpu_to_le64(length);
881 entry->type = cpu_to_le32(type);
882
883 e820_reserve.count = cpu_to_le32(index);
884 }
885
886 /* new "etc/e820" file -- include ram too */
887 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
888 e820_table[e820_entries].address = cpu_to_le64(address);
889 e820_table[e820_entries].length = cpu_to_le64(length);
890 e820_table[e820_entries].type = cpu_to_le32(type);
891 e820_entries++;
892
893 return e820_entries;
894 }
895
896 int e820_get_num_entries(void)
897 {
898 return e820_entries;
899 }
900
901 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
902 {
903 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
904 *address = le64_to_cpu(e820_table[idx].address);
905 *length = le64_to_cpu(e820_table[idx].length);
906 return true;
907 }
908 return false;
909 }
910
911 /* Enables contiguous-apic-ID mode, for compatibility */
912 static bool compat_apic_id_mode;
913
914 void enable_compat_apic_id_mode(void)
915 {
916 compat_apic_id_mode = true;
917 }
918
919 /* Calculates initial APIC ID for a specific CPU index
920 *
921 * Currently we need to be able to calculate the APIC ID from the CPU index
922 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
923 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
924 * all CPUs up to max_cpus.
925 */
926 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
927 {
928 uint32_t correct_id;
929 static bool warned;
930
931 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
932 if (compat_apic_id_mode) {
933 if (cpu_index != correct_id && !warned && !qtest_enabled()) {
934 error_report("APIC IDs set in compatibility mode, "
935 "CPU topology won't match the configuration");
936 warned = true;
937 }
938 return cpu_index;
939 } else {
940 return correct_id;
941 }
942 }
943
944 static void pc_build_smbios(PCMachineState *pcms)
945 {
946 uint8_t *smbios_tables, *smbios_anchor;
947 size_t smbios_tables_len, smbios_anchor_len;
948 struct smbios_phys_mem_area *mem_array;
949 unsigned i, array_count;
950 MachineState *ms = MACHINE(pcms);
951 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
952
953 /* tell smbios about cpuid version and features */
954 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
955
956 smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
957 if (smbios_tables) {
958 fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
959 smbios_tables, smbios_tables_len);
960 }
961
962 /* build the array of physical mem area from e820 table */
963 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
964 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
965 uint64_t addr, len;
966
967 if (e820_get_entry(i, E820_RAM, &addr, &len)) {
968 mem_array[array_count].address = addr;
969 mem_array[array_count].length = len;
970 array_count++;
971 }
972 }
973 smbios_get_tables(mem_array, array_count,
974 &smbios_tables, &smbios_tables_len,
975 &smbios_anchor, &smbios_anchor_len);
976 g_free(mem_array);
977
978 if (smbios_anchor) {
979 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables",
980 smbios_tables, smbios_tables_len);
981 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor",
982 smbios_anchor, smbios_anchor_len);
983 }
984 }
985
986 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
987 {
988 FWCfgState *fw_cfg;
989 uint64_t *numa_fw_cfg;
990 int i;
991 const CPUArchIdList *cpus;
992 MachineClass *mc = MACHINE_GET_CLASS(pcms);
993
994 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as);
995 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
996
997 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
998 *
999 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
1000 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
1001 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
1002 * for CPU hotplug also uses APIC ID and not "CPU index".
1003 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
1004 * but the "limit to the APIC ID values SeaBIOS may see".
1005 *
1006 * So for compatibility reasons with old BIOSes we are stuck with
1007 * "etc/max-cpus" actually being apic_id_limit
1008 */
1009 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit);
1010 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1011 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
1012 acpi_tables, acpi_tables_len);
1013 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
1014
1015 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
1016 &e820_reserve, sizeof(e820_reserve));
1017 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
1018 sizeof(struct e820_entry) * e820_entries);
1019
1020 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
1021 /* allocate memory for the NUMA channel: one (64bit) word for the number
1022 * of nodes, one word for each VCPU->node and one word for each node to
1023 * hold the amount of memory.
1024 */
1025 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes);
1026 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
1027 cpus = mc->possible_cpu_arch_ids(MACHINE(pcms));
1028 for (i = 0; i < cpus->len; i++) {
1029 unsigned int apic_id = cpus->cpus[i].arch_id;
1030 assert(apic_id < pcms->apic_id_limit);
1031 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
1032 }
1033 for (i = 0; i < nb_numa_nodes; i++) {
1034 numa_fw_cfg[pcms->apic_id_limit + 1 + i] =
1035 cpu_to_le64(numa_info[i].node_mem);
1036 }
1037 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
1038 (1 + pcms->apic_id_limit + nb_numa_nodes) *
1039 sizeof(*numa_fw_cfg));
1040
1041 return fw_cfg;
1042 }
1043
1044 static long get_file_size(FILE *f)
1045 {
1046 long where, size;
1047
1048 /* XXX: on Unix systems, using fstat() probably makes more sense */
1049
1050 where = ftell(f);
1051 fseek(f, 0, SEEK_END);
1052 size = ftell(f);
1053 fseek(f, where, SEEK_SET);
1054
1055 return size;
1056 }
1057
1058 /* setup_data types */
1059 #define SETUP_NONE 0
1060 #define SETUP_E820_EXT 1
1061 #define SETUP_DTB 2
1062 #define SETUP_PCI 3
1063 #define SETUP_EFI 4
1064
1065 struct setup_data {
1066 uint64_t next;
1067 uint32_t type;
1068 uint32_t len;
1069 uint8_t data[0];
1070 } __attribute__((packed));
1071
1072 static void load_linux(PCMachineState *pcms,
1073 FWCfgState *fw_cfg)
1074 {
1075 uint16_t protocol;
1076 int setup_size, kernel_size, cmdline_size;
1077 int dtb_size, setup_data_offset;
1078 uint32_t initrd_max;
1079 uint8_t header[8192], *setup, *kernel;
1080 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
1081 FILE *f;
1082 char *vmode;
1083 MachineState *machine = MACHINE(pcms);
1084 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1085 struct setup_data *setup_data;
1086 const char *kernel_filename = machine->kernel_filename;
1087 const char *initrd_filename = machine->initrd_filename;
1088 const char *dtb_filename = machine->dtb;
1089 const char *kernel_cmdline = machine->kernel_cmdline;
1090
1091 /* Align to 16 bytes as a paranoia measure */
1092 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
1093
1094 /* load the kernel header */
1095 f = fopen(kernel_filename, "rb");
1096 if (!f || !(kernel_size = get_file_size(f)) ||
1097 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
1098 MIN(ARRAY_SIZE(header), kernel_size)) {
1099 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
1100 kernel_filename, strerror(errno));
1101 exit(1);
1102 }
1103
1104 /* kernel protocol version */
1105 #if 0
1106 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
1107 #endif
1108 if (ldl_p(header+0x202) == 0x53726448) {
1109 protocol = lduw_p(header+0x206);
1110 } else {
1111 /* This looks like a multiboot kernel. If it is, let's stop
1112 treating it like a Linux kernel. */
1113 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
1114 kernel_cmdline, kernel_size, header)) {
1115 return;
1116 }
1117 protocol = 0;
1118 }
1119
1120 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
1121 /* Low kernel */
1122 real_addr = 0x90000;
1123 cmdline_addr = 0x9a000 - cmdline_size;
1124 prot_addr = 0x10000;
1125 } else if (protocol < 0x202) {
1126 /* High but ancient kernel */
1127 real_addr = 0x90000;
1128 cmdline_addr = 0x9a000 - cmdline_size;
1129 prot_addr = 0x100000;
1130 } else {
1131 /* High and recent kernel */
1132 real_addr = 0x10000;
1133 cmdline_addr = 0x20000;
1134 prot_addr = 0x100000;
1135 }
1136
1137 #if 0
1138 fprintf(stderr,
1139 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
1140 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
1141 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
1142 real_addr,
1143 cmdline_addr,
1144 prot_addr);
1145 #endif
1146
1147 /* highest address for loading the initrd */
1148 if (protocol >= 0x203) {
1149 initrd_max = ldl_p(header+0x22c);
1150 } else {
1151 initrd_max = 0x37ffffff;
1152 }
1153
1154 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
1155 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
1156 }
1157
1158 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
1159 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
1160 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1161
1162 if (protocol >= 0x202) {
1163 stl_p(header+0x228, cmdline_addr);
1164 } else {
1165 stw_p(header+0x20, 0xA33F);
1166 stw_p(header+0x22, cmdline_addr-real_addr);
1167 }
1168
1169 /* handle vga= parameter */
1170 vmode = strstr(kernel_cmdline, "vga=");
1171 if (vmode) {
1172 unsigned int video_mode;
1173 /* skip "vga=" */
1174 vmode += 4;
1175 if (!strncmp(vmode, "normal", 6)) {
1176 video_mode = 0xffff;
1177 } else if (!strncmp(vmode, "ext", 3)) {
1178 video_mode = 0xfffe;
1179 } else if (!strncmp(vmode, "ask", 3)) {
1180 video_mode = 0xfffd;
1181 } else {
1182 video_mode = strtol(vmode, NULL, 0);
1183 }
1184 stw_p(header+0x1fa, video_mode);
1185 }
1186
1187 /* loader type */
1188 /* High nybble = B reserved for QEMU; low nybble is revision number.
1189 If this code is substantially changed, you may want to consider
1190 incrementing the revision. */
1191 if (protocol >= 0x200) {
1192 header[0x210] = 0xB0;
1193 }
1194 /* heap */
1195 if (protocol >= 0x201) {
1196 header[0x211] |= 0x80; /* CAN_USE_HEAP */
1197 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
1198 }
1199
1200 /* load initrd */
1201 if (initrd_filename) {
1202 gsize initrd_size;
1203 gchar *initrd_data;
1204 GError *gerr = NULL;
1205
1206 if (protocol < 0x200) {
1207 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
1208 exit(1);
1209 }
1210
1211 if (!g_file_get_contents(initrd_filename, &initrd_data,
1212 &initrd_size, &gerr)) {
1213 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
1214 initrd_filename, gerr->message);
1215 exit(1);
1216 }
1217 if (initrd_size >= initrd_max) {
1218 fprintf(stderr, "qemu: initrd is too large, cannot support."
1219 "(max: %"PRIu32", need %"PRId64")\n",
1220 initrd_max, (uint64_t)initrd_size);
1221 exit(1);
1222 }
1223
1224 initrd_addr = (initrd_max-initrd_size) & ~4095;
1225
1226 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
1227 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1228 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
1229
1230 stl_p(header+0x218, initrd_addr);
1231 stl_p(header+0x21c, initrd_size);
1232 }
1233
1234 /* load kernel and setup */
1235 setup_size = header[0x1f1];
1236 if (setup_size == 0) {
1237 setup_size = 4;
1238 }
1239 setup_size = (setup_size+1)*512;
1240 if (setup_size > kernel_size) {
1241 fprintf(stderr, "qemu: invalid kernel header\n");
1242 exit(1);
1243 }
1244 kernel_size -= setup_size;
1245
1246 setup = g_malloc(setup_size);
1247 kernel = g_malloc(kernel_size);
1248 fseek(f, 0, SEEK_SET);
1249 if (fread(setup, 1, setup_size, f) != setup_size) {
1250 fprintf(stderr, "fread() failed\n");
1251 exit(1);
1252 }
1253 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
1254 fprintf(stderr, "fread() failed\n");
1255 exit(1);
1256 }
1257 fclose(f);
1258
1259 /* append dtb to kernel */
1260 if (dtb_filename) {
1261 if (protocol < 0x209) {
1262 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
1263 exit(1);
1264 }
1265
1266 dtb_size = get_image_size(dtb_filename);
1267 if (dtb_size <= 0) {
1268 fprintf(stderr, "qemu: error reading dtb %s: %s\n",
1269 dtb_filename, strerror(errno));
1270 exit(1);
1271 }
1272
1273 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
1274 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
1275 kernel = g_realloc(kernel, kernel_size);
1276
1277 stq_p(header+0x250, prot_addr + setup_data_offset);
1278
1279 setup_data = (struct setup_data *)(kernel + setup_data_offset);
1280 setup_data->next = 0;
1281 setup_data->type = cpu_to_le32(SETUP_DTB);
1282 setup_data->len = cpu_to_le32(dtb_size);
1283
1284 load_image_size(dtb_filename, setup_data->data, dtb_size);
1285 }
1286
1287 memcpy(setup, header, MIN(sizeof(header), setup_size));
1288
1289 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
1290 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1291 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1292
1293 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
1294 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
1295 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1296
1297 option_rom[nb_option_roms].bootindex = 0;
1298 option_rom[nb_option_roms].name = "linuxboot.bin";
1299 if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
1300 option_rom[nb_option_roms].name = "linuxboot_dma.bin";
1301 }
1302 nb_option_roms++;
1303 }
1304
1305 #define NE2000_NB_MAX 6
1306
1307 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
1308 0x280, 0x380 };
1309 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1310
1311 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
1312 {
1313 static int nb_ne2k = 0;
1314
1315 if (nb_ne2k == NE2000_NB_MAX)
1316 return;
1317 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
1318 ne2000_irq[nb_ne2k], nd);
1319 nb_ne2k++;
1320 }
1321
1322 DeviceState *cpu_get_current_apic(void)
1323 {
1324 if (current_cpu) {
1325 X86CPU *cpu = X86_CPU(current_cpu);
1326 return cpu->apic_state;
1327 } else {
1328 return NULL;
1329 }
1330 }
1331
1332 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
1333 {
1334 X86CPU *cpu = opaque;
1335
1336 if (level) {
1337 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
1338 }
1339 }
1340
1341 static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp)
1342 {
1343 Object *cpu = NULL;
1344 Error *local_err = NULL;
1345
1346 cpu = object_new(typename);
1347
1348 object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
1349 object_property_set_bool(cpu, true, "realized", &local_err);
1350
1351 object_unref(cpu);
1352 error_propagate(errp, local_err);
1353 }
1354
1355 void pc_hot_add_cpu(const int64_t id, Error **errp)
1356 {
1357 MachineState *ms = MACHINE(qdev_get_machine());
1358 int64_t apic_id = x86_cpu_apic_id_from_index(id);
1359 Error *local_err = NULL;
1360
1361 if (id < 0) {
1362 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
1363 return;
1364 }
1365
1366 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1367 error_setg(errp, "Unable to add CPU: %" PRIi64
1368 ", resulting APIC ID (%" PRIi64 ") is too large",
1369 id, apic_id);
1370 return;
1371 }
1372
1373 pc_new_cpu(ms->cpu_type, apic_id, &local_err);
1374 if (local_err) {
1375 error_propagate(errp, local_err);
1376 return;
1377 }
1378 }
1379
1380 void pc_cpus_init(PCMachineState *pcms)
1381 {
1382 int i;
1383 const CPUArchIdList *possible_cpus;
1384 MachineState *ms = MACHINE(pcms);
1385 MachineClass *mc = MACHINE_GET_CLASS(pcms);
1386
1387 /* Calculates the limit to CPU APIC ID values
1388 *
1389 * Limit for the APIC ID value, so that all
1390 * CPU APIC IDs are < pcms->apic_id_limit.
1391 *
1392 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1393 */
1394 pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
1395 possible_cpus = mc->possible_cpu_arch_ids(ms);
1396 for (i = 0; i < smp_cpus; i++) {
1397 pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id,
1398 &error_fatal);
1399 }
1400 }
1401
1402 static void pc_build_feature_control_file(PCMachineState *pcms)
1403 {
1404 MachineState *ms = MACHINE(pcms);
1405 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
1406 CPUX86State *env = &cpu->env;
1407 uint32_t unused, ecx, edx;
1408 uint64_t feature_control_bits = 0;
1409 uint64_t *val;
1410
1411 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
1412 if (ecx & CPUID_EXT_VMX) {
1413 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1414 }
1415
1416 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
1417 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
1418 (env->mcg_cap & MCG_LMCE_P)) {
1419 feature_control_bits |= FEATURE_CONTROL_LMCE;
1420 }
1421
1422 if (!feature_control_bits) {
1423 return;
1424 }
1425
1426 val = g_malloc(sizeof(*val));
1427 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
1428 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
1429 }
1430
1431 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
1432 {
1433 if (cpus_count > 0xff) {
1434 /* If the number of CPUs can't be represented in 8 bits, the
1435 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1436 * to make old BIOSes fail more predictably.
1437 */
1438 rtc_set_memory(rtc, 0x5f, 0);
1439 } else {
1440 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
1441 }
1442 }
1443
1444 static
1445 void pc_machine_done(Notifier *notifier, void *data)
1446 {
1447 PCMachineState *pcms = container_of(notifier,
1448 PCMachineState, machine_done);
1449 PCIBus *bus = pcms->bus;
1450
1451 /* set the number of CPUs */
1452 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1453
1454 if (bus) {
1455 int extra_hosts = 0;
1456
1457 QLIST_FOREACH(bus, &bus->child, sibling) {
1458 /* look for expander root buses */
1459 if (pci_bus_is_root(bus)) {
1460 extra_hosts++;
1461 }
1462 }
1463 if (extra_hosts && pcms->fw_cfg) {
1464 uint64_t *val = g_malloc(sizeof(*val));
1465 *val = cpu_to_le64(extra_hosts);
1466 fw_cfg_add_file(pcms->fw_cfg,
1467 "etc/extra-pci-roots", val, sizeof(*val));
1468 }
1469 }
1470
1471 acpi_setup();
1472 if (pcms->fw_cfg) {
1473 pc_build_smbios(pcms);
1474 pc_build_feature_control_file(pcms);
1475 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1476 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1477 }
1478
1479 if (pcms->apic_id_limit > 255 && !xen_enabled()) {
1480 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1481
1482 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
1483 iommu->intr_eim != ON_OFF_AUTO_ON) {
1484 error_report("current -smp configuration requires "
1485 "Extended Interrupt Mode enabled. "
1486 "You can add an IOMMU using: "
1487 "-device intel-iommu,intremap=on,eim=on");
1488 exit(EXIT_FAILURE);
1489 }
1490 }
1491 }
1492
1493 void pc_guest_info_init(PCMachineState *pcms)
1494 {
1495 int i;
1496
1497 pcms->apic_xrupt_override = kvm_allows_irq0_override();
1498 pcms->numa_nodes = nb_numa_nodes;
1499 pcms->node_mem = g_malloc0(pcms->numa_nodes *
1500 sizeof *pcms->node_mem);
1501 for (i = 0; i < nb_numa_nodes; i++) {
1502 pcms->node_mem[i] = numa_info[i].node_mem;
1503 }
1504
1505 pcms->machine_done.notify = pc_machine_done;
1506 qemu_add_machine_init_done_notifier(&pcms->machine_done);
1507 }
1508
1509 /* setup pci memory address space mapping into system address space */
1510 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1511 MemoryRegion *pci_address_space)
1512 {
1513 /* Set to lower priority than RAM */
1514 memory_region_add_subregion_overlap(system_memory, 0x0,
1515 pci_address_space, -1);
1516 }
1517
1518 void pc_acpi_init(const char *default_dsdt)
1519 {
1520 char *filename;
1521
1522 if (acpi_tables != NULL) {
1523 /* manually set via -acpitable, leave it alone */
1524 return;
1525 }
1526
1527 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1528 if (filename == NULL) {
1529 warn_report("failed to find %s", default_dsdt);
1530 } else {
1531 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0,
1532 &error_abort);
1533 Error *err = NULL;
1534
1535 qemu_opt_set(opts, "file", filename, &error_abort);
1536
1537 acpi_table_add_builtin(opts, &err);
1538 if (err) {
1539 warn_reportf_err(err, "failed to load %s: ", filename);
1540 }
1541 g_free(filename);
1542 }
1543 }
1544
1545 void xen_load_linux(PCMachineState *pcms)
1546 {
1547 int i;
1548 FWCfgState *fw_cfg;
1549
1550 assert(MACHINE(pcms)->kernel_filename != NULL);
1551
1552 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
1553 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1554 rom_set_fw(fw_cfg);
1555
1556 load_linux(pcms, fw_cfg);
1557 for (i = 0; i < nb_option_roms; i++) {
1558 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
1559 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1560 !strcmp(option_rom[i].name, "multiboot.bin"));
1561 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1562 }
1563 pcms->fw_cfg = fw_cfg;
1564 }
1565
1566 void pc_memory_init(PCMachineState *pcms,
1567 MemoryRegion *system_memory,
1568 MemoryRegion *rom_memory,
1569 MemoryRegion **ram_memory)
1570 {
1571 int linux_boot, i;
1572 MemoryRegion *ram, *option_rom_mr;
1573 MemoryRegion *ram_below_4g, *ram_above_4g;
1574 FWCfgState *fw_cfg;
1575 MachineState *machine = MACHINE(pcms);
1576 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1577
1578 assert(machine->ram_size == pcms->below_4g_mem_size +
1579 pcms->above_4g_mem_size);
1580
1581 linux_boot = (machine->kernel_filename != NULL);
1582
1583 /* Allocate RAM. We allocate it as a single memory region and use
1584 * aliases to address portions of it, mostly for backwards compatibility
1585 * with older qemus that used qemu_ram_alloc().
1586 */
1587 ram = g_malloc(sizeof(*ram));
1588 memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1589 machine->ram_size);
1590 *ram_memory = ram;
1591 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1592 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1593 0, pcms->below_4g_mem_size);
1594 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1595 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM);
1596 if (pcms->above_4g_mem_size > 0) {
1597 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1598 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1599 pcms->below_4g_mem_size,
1600 pcms->above_4g_mem_size);
1601 memory_region_add_subregion(system_memory, 0x100000000ULL,
1602 ram_above_4g);
1603 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM);
1604 }
1605
1606 if (!pcmc->has_reserved_memory &&
1607 (machine->ram_slots ||
1608 (machine->maxram_size > machine->ram_size))) {
1609 MachineClass *mc = MACHINE_GET_CLASS(machine);
1610
1611 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1612 mc->name);
1613 exit(EXIT_FAILURE);
1614 }
1615
1616 /* always allocate the device memory information */
1617 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1618
1619 /* initialize device memory address space */
1620 if (pcmc->has_reserved_memory &&
1621 (machine->ram_size < machine->maxram_size)) {
1622 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
1623
1624 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1625 error_report("unsupported amount of memory slots: %"PRIu64,
1626 machine->ram_slots);
1627 exit(EXIT_FAILURE);
1628 }
1629
1630 if (QEMU_ALIGN_UP(machine->maxram_size,
1631 TARGET_PAGE_SIZE) != machine->maxram_size) {
1632 error_report("maximum memory size must by aligned to multiple of "
1633 "%d bytes", TARGET_PAGE_SIZE);
1634 exit(EXIT_FAILURE);
1635 }
1636
1637 machine->device_memory->base =
1638 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB);
1639
1640 if (pcmc->enforce_aligned_dimm) {
1641 /* size device region assuming 1G page max alignment per slot */
1642 device_mem_size += (1 * GiB) * machine->ram_slots;
1643 }
1644
1645 if ((machine->device_memory->base + device_mem_size) <
1646 device_mem_size) {
1647 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1648 machine->maxram_size);
1649 exit(EXIT_FAILURE);
1650 }
1651
1652 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1653 "device-memory", device_mem_size);
1654 memory_region_add_subregion(system_memory, machine->device_memory->base,
1655 &machine->device_memory->mr);
1656 }
1657
1658 /* Initialize PC system firmware */
1659 pc_system_firmware_init(rom_memory, !pcmc->pci_enabled);
1660
1661 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1662 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1663 &error_fatal);
1664 if (pcmc->pci_enabled) {
1665 memory_region_set_readonly(option_rom_mr, true);
1666 }
1667 memory_region_add_subregion_overlap(rom_memory,
1668 PC_ROM_MIN_VGA,
1669 option_rom_mr,
1670 1);
1671
1672 fw_cfg = bochs_bios_init(&address_space_memory, pcms);
1673
1674 rom_set_fw(fw_cfg);
1675
1676 if (pcmc->has_reserved_memory && machine->device_memory->base) {
1677 uint64_t *val = g_malloc(sizeof(*val));
1678 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1679 uint64_t res_mem_end = machine->device_memory->base;
1680
1681 if (!pcmc->broken_reserved_end) {
1682 res_mem_end += memory_region_size(&machine->device_memory->mr);
1683 }
1684 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1685 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1686 }
1687
1688 if (linux_boot) {
1689 load_linux(pcms, fw_cfg);
1690 }
1691
1692 for (i = 0; i < nb_option_roms; i++) {
1693 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1694 }
1695 pcms->fw_cfg = fw_cfg;
1696
1697 /* Init default IOAPIC address space */
1698 pcms->ioapic_as = &address_space_memory;
1699 }
1700
1701 /*
1702 * The 64bit pci hole starts after "above 4G RAM" and
1703 * potentially the space reserved for memory hotplug.
1704 */
1705 uint64_t pc_pci_hole64_start(void)
1706 {
1707 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1708 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1709 MachineState *ms = MACHINE(pcms);
1710 uint64_t hole64_start = 0;
1711
1712 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1713 hole64_start = ms->device_memory->base;
1714 if (!pcmc->broken_reserved_end) {
1715 hole64_start += memory_region_size(&ms->device_memory->mr);
1716 }
1717 } else {
1718 hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
1719 }
1720
1721 return ROUND_UP(hole64_start, 1 * GiB);
1722 }
1723
1724 qemu_irq pc_allocate_cpu_irq(void)
1725 {
1726 return qemu_allocate_irq(pic_irq_request, NULL, 0);
1727 }
1728
1729 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1730 {
1731 DeviceState *dev = NULL;
1732
1733 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1734 if (pci_bus) {
1735 PCIDevice *pcidev = pci_vga_init(pci_bus);
1736 dev = pcidev ? &pcidev->qdev : NULL;
1737 } else if (isa_bus) {
1738 ISADevice *isadev = isa_vga_init(isa_bus);
1739 dev = isadev ? DEVICE(isadev) : NULL;
1740 }
1741 rom_reset_order_override();
1742 return dev;
1743 }
1744
1745 static const MemoryRegionOps ioport80_io_ops = {
1746 .write = ioport80_write,
1747 .read = ioport80_read,
1748 .endianness = DEVICE_NATIVE_ENDIAN,
1749 .impl = {
1750 .min_access_size = 1,
1751 .max_access_size = 1,
1752 },
1753 };
1754
1755 static const MemoryRegionOps ioportF0_io_ops = {
1756 .write = ioportF0_write,
1757 .read = ioportF0_read,
1758 .endianness = DEVICE_NATIVE_ENDIAN,
1759 .impl = {
1760 .min_access_size = 1,
1761 .max_access_size = 1,
1762 },
1763 };
1764
1765 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1766 {
1767 int i;
1768 DriveInfo *fd[MAX_FD];
1769 qemu_irq *a20_line;
1770 ISADevice *i8042, *port92, *vmmouse;
1771
1772 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1773 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1774
1775 for (i = 0; i < MAX_FD; i++) {
1776 fd[i] = drive_get(IF_FLOPPY, 0, i);
1777 create_fdctrl |= !!fd[i];
1778 }
1779 if (create_fdctrl) {
1780 fdctrl_init_isa(isa_bus, fd);
1781 }
1782
1783 i8042 = isa_create_simple(isa_bus, "i8042");
1784 if (!no_vmport) {
1785 vmport_init(isa_bus);
1786 vmmouse = isa_try_create(isa_bus, "vmmouse");
1787 } else {
1788 vmmouse = NULL;
1789 }
1790 if (vmmouse) {
1791 DeviceState *dev = DEVICE(vmmouse);
1792 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1793 qdev_init_nofail(dev);
1794 }
1795 port92 = isa_create_simple(isa_bus, "port92");
1796
1797 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1798 i8042_setup_a20_line(i8042, a20_line[0]);
1799 port92_init(port92, a20_line[1]);
1800 g_free(a20_line);
1801 }
1802
1803 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1804 ISADevice **rtc_state,
1805 bool create_fdctrl,
1806 bool no_vmport,
1807 bool has_pit,
1808 uint32_t hpet_irqs)
1809 {
1810 int i;
1811 DeviceState *hpet = NULL;
1812 int pit_isa_irq = 0;
1813 qemu_irq pit_alt_irq = NULL;
1814 qemu_irq rtc_irq = NULL;
1815 ISADevice *pit = NULL;
1816 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1817 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1818
1819 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1820 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1821
1822 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1823 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1824
1825 /*
1826 * Check if an HPET shall be created.
1827 *
1828 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1829 * when the HPET wants to take over. Thus we have to disable the latter.
1830 */
1831 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1832 /* In order to set property, here not using sysbus_try_create_simple */
1833 hpet = qdev_try_create(NULL, TYPE_HPET);
1834 if (hpet) {
1835 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1836 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1837 * IRQ8 and IRQ2.
1838 */
1839 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1840 HPET_INTCAP, NULL);
1841 if (!compat) {
1842 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1843 }
1844 qdev_init_nofail(hpet);
1845 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1846
1847 for (i = 0; i < GSI_NUM_PINS; i++) {
1848 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1849 }
1850 pit_isa_irq = -1;
1851 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1852 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1853 }
1854 }
1855 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1856
1857 qemu_register_boot_set(pc_boot_set, *rtc_state);
1858
1859 if (!xen_enabled() && has_pit) {
1860 if (kvm_pit_in_kernel()) {
1861 pit = kvm_pit_init(isa_bus, 0x40);
1862 } else {
1863 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1864 }
1865 if (hpet) {
1866 /* connect PIT to output control line of the HPET */
1867 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1868 }
1869 pcspk_init(isa_bus, pit);
1870 }
1871
1872 i8257_dma_init(isa_bus, 0);
1873
1874 /* Super I/O */
1875 pc_superio_init(isa_bus, create_fdctrl, no_vmport);
1876 }
1877
1878 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1879 {
1880 int i;
1881
1882 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1883 for (i = 0; i < nb_nics; i++) {
1884 NICInfo *nd = &nd_table[i];
1885 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1886
1887 if (g_str_equal(model, "ne2k_isa")) {
1888 pc_init_ne2k_isa(isa_bus, nd);
1889 } else {
1890 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1891 }
1892 }
1893 rom_reset_order_override();
1894 }
1895
1896 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1897 {
1898 DeviceState *dev;
1899 SysBusDevice *d;
1900 unsigned int i;
1901
1902 if (kvm_ioapic_in_kernel()) {
1903 dev = qdev_create(NULL, TYPE_KVM_IOAPIC);
1904 } else {
1905 dev = qdev_create(NULL, TYPE_IOAPIC);
1906 }
1907 if (parent_name) {
1908 object_property_add_child(object_resolve_path(parent_name, NULL),
1909 "ioapic", OBJECT(dev), NULL);
1910 }
1911 qdev_init_nofail(dev);
1912 d = SYS_BUS_DEVICE(dev);
1913 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1914
1915 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1916 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1917 }
1918 }
1919
1920 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1921 Error **errp)
1922 {
1923 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1924 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1925 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1926 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1927
1928 /*
1929 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1930 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1931 * addition to cover this case.
1932 */
1933 if (!pcms->acpi_dev || !acpi_enabled) {
1934 error_setg(errp,
1935 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1936 return;
1937 }
1938
1939 if (is_nvdimm && !pcms->acpi_nvdimm_state.is_enabled) {
1940 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1941 return;
1942 }
1943
1944 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1945 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1946 }
1947
1948 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1949 DeviceState *dev, Error **errp)
1950 {
1951 HotplugHandlerClass *hhc;
1952 Error *local_err = NULL;
1953 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1954 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1955
1956 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
1957 if (local_err) {
1958 goto out;
1959 }
1960
1961 if (is_nvdimm) {
1962 nvdimm_plug(&pcms->acpi_nvdimm_state);
1963 }
1964
1965 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1966 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
1967 out:
1968 error_propagate(errp, local_err);
1969 }
1970
1971 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1972 DeviceState *dev, Error **errp)
1973 {
1974 HotplugHandlerClass *hhc;
1975 Error *local_err = NULL;
1976 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1977
1978 /*
1979 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1980 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1981 * addition to cover this case.
1982 */
1983 if (!pcms->acpi_dev || !acpi_enabled) {
1984 error_setg(&local_err,
1985 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1986 goto out;
1987 }
1988
1989 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1990 error_setg(&local_err,
1991 "nvdimm device hot unplug is not supported yet.");
1992 goto out;
1993 }
1994
1995 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1996 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1997
1998 out:
1999 error_propagate(errp, local_err);
2000 }
2001
2002 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
2003 DeviceState *dev, Error **errp)
2004 {
2005 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2006 HotplugHandlerClass *hhc;
2007 Error *local_err = NULL;
2008
2009 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
2010 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2011
2012 if (local_err) {
2013 goto out;
2014 }
2015
2016 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
2017 object_unparent(OBJECT(dev));
2018
2019 out:
2020 error_propagate(errp, local_err);
2021 }
2022
2023 static int pc_apic_cmp(const void *a, const void *b)
2024 {
2025 CPUArchId *apic_a = (CPUArchId *)a;
2026 CPUArchId *apic_b = (CPUArchId *)b;
2027
2028 return apic_a->arch_id - apic_b->arch_id;
2029 }
2030
2031 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
2032 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
2033 * entry corresponding to CPU's apic_id returns NULL.
2034 */
2035 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2036 {
2037 CPUArchId apic_id, *found_cpu;
2038
2039 apic_id.arch_id = id;
2040 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
2041 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
2042 pc_apic_cmp);
2043 if (found_cpu && idx) {
2044 *idx = found_cpu - ms->possible_cpus->cpus;
2045 }
2046 return found_cpu;
2047 }
2048
2049 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
2050 DeviceState *dev, Error **errp)
2051 {
2052 CPUArchId *found_cpu;
2053 HotplugHandlerClass *hhc;
2054 Error *local_err = NULL;
2055 X86CPU *cpu = X86_CPU(dev);
2056 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2057
2058 if (pcms->acpi_dev) {
2059 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
2060 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2061 if (local_err) {
2062 goto out;
2063 }
2064 }
2065
2066 /* increment the number of CPUs */
2067 pcms->boot_cpus++;
2068 if (pcms->rtc) {
2069 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
2070 }
2071 if (pcms->fw_cfg) {
2072 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
2073 }
2074
2075 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
2076 found_cpu->cpu = OBJECT(dev);
2077 out:
2078 error_propagate(errp, local_err);
2079 }
2080 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
2081 DeviceState *dev, Error **errp)
2082 {
2083 int idx = -1;
2084 HotplugHandlerClass *hhc;
2085 Error *local_err = NULL;
2086 X86CPU *cpu = X86_CPU(dev);
2087 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2088
2089 if (!pcms->acpi_dev) {
2090 error_setg(&local_err, "CPU hot unplug not supported without ACPI");
2091 goto out;
2092 }
2093
2094 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
2095 assert(idx != -1);
2096 if (idx == 0) {
2097 error_setg(&local_err, "Boot CPU is unpluggable");
2098 goto out;
2099 }
2100
2101 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
2102 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2103
2104 if (local_err) {
2105 goto out;
2106 }
2107
2108 out:
2109 error_propagate(errp, local_err);
2110
2111 }
2112
2113 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
2114 DeviceState *dev, Error **errp)
2115 {
2116 CPUArchId *found_cpu;
2117 HotplugHandlerClass *hhc;
2118 Error *local_err = NULL;
2119 X86CPU *cpu = X86_CPU(dev);
2120 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2121
2122 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
2123 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2124
2125 if (local_err) {
2126 goto out;
2127 }
2128
2129 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
2130 found_cpu->cpu = NULL;
2131 object_unparent(OBJECT(dev));
2132
2133 /* decrement the number of CPUs */
2134 pcms->boot_cpus--;
2135 /* Update the number of CPUs in CMOS */
2136 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
2137 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
2138 out:
2139 error_propagate(errp, local_err);
2140 }
2141
2142 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
2143 DeviceState *dev, Error **errp)
2144 {
2145 int idx;
2146 CPUState *cs;
2147 CPUArchId *cpu_slot;
2148 X86CPUTopoInfo topo;
2149 X86CPU *cpu = X86_CPU(dev);
2150 MachineState *ms = MACHINE(hotplug_dev);
2151 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2152
2153 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
2154 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
2155 ms->cpu_type);
2156 return;
2157 }
2158
2159 /* if APIC ID is not set, set it based on socket/core/thread properties */
2160 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
2161 int max_socket = (max_cpus - 1) / smp_threads / smp_cores;
2162
2163 if (cpu->socket_id < 0) {
2164 error_setg(errp, "CPU socket-id is not set");
2165 return;
2166 } else if (cpu->socket_id > max_socket) {
2167 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
2168 cpu->socket_id, max_socket);
2169 return;
2170 }
2171 if (cpu->core_id < 0) {
2172 error_setg(errp, "CPU core-id is not set");
2173 return;
2174 } else if (cpu->core_id > (smp_cores - 1)) {
2175 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
2176 cpu->core_id, smp_cores - 1);
2177 return;
2178 }
2179 if (cpu->thread_id < 0) {
2180 error_setg(errp, "CPU thread-id is not set");
2181 return;
2182 } else if (cpu->thread_id > (smp_threads - 1)) {
2183 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
2184 cpu->thread_id, smp_threads - 1);
2185 return;
2186 }
2187
2188 topo.pkg_id = cpu->socket_id;
2189 topo.core_id = cpu->core_id;
2190 topo.smt_id = cpu->thread_id;
2191 cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo);
2192 }
2193
2194 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
2195 if (!cpu_slot) {
2196 MachineState *ms = MACHINE(pcms);
2197
2198 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
2199 error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
2200 " APIC ID %" PRIu32 ", valid index range 0:%d",
2201 topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id,
2202 ms->possible_cpus->len - 1);
2203 return;
2204 }
2205
2206 if (cpu_slot->cpu) {
2207 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
2208 idx, cpu->apic_id);
2209 return;
2210 }
2211
2212 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
2213 * so that machine_query_hotpluggable_cpus would show correct values
2214 */
2215 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
2216 * once -smp refactoring is complete and there will be CPU private
2217 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
2218 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
2219 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
2220 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
2221 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
2222 return;
2223 }
2224 cpu->socket_id = topo.pkg_id;
2225
2226 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
2227 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
2228 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
2229 return;
2230 }
2231 cpu->core_id = topo.core_id;
2232
2233 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
2234 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
2235 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
2236 return;
2237 }
2238 cpu->thread_id = topo.smt_id;
2239
2240 if (cpu->hyperv_vpindex && !kvm_hv_vpindex_settable()) {
2241 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
2242 return;
2243 }
2244
2245 cs = CPU(cpu);
2246 cs->cpu_index = idx;
2247
2248 numa_cpu_pre_plug(cpu_slot, dev, errp);
2249 }
2250
2251 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2252 DeviceState *dev, Error **errp)
2253 {
2254 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2255 pc_memory_pre_plug(hotplug_dev, dev, errp);
2256 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2257 pc_cpu_pre_plug(hotplug_dev, dev, errp);
2258 }
2259 }
2260
2261 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2262 DeviceState *dev, Error **errp)
2263 {
2264 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2265 pc_memory_plug(hotplug_dev, dev, errp);
2266 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2267 pc_cpu_plug(hotplug_dev, dev, errp);
2268 }
2269 }
2270
2271 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2272 DeviceState *dev, Error **errp)
2273 {
2274 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2275 pc_memory_unplug_request(hotplug_dev, dev, errp);
2276 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2277 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
2278 } else {
2279 error_setg(errp, "acpi: device unplug request for not supported device"
2280 " type: %s", object_get_typename(OBJECT(dev)));
2281 }
2282 }
2283
2284 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2285 DeviceState *dev, Error **errp)
2286 {
2287 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2288 pc_memory_unplug(hotplug_dev, dev, errp);
2289 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2290 pc_cpu_unplug_cb(hotplug_dev, dev, errp);
2291 } else {
2292 error_setg(errp, "acpi: device unplug for not supported device"
2293 " type: %s", object_get_typename(OBJECT(dev)));
2294 }
2295 }
2296
2297 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
2298 DeviceState *dev)
2299 {
2300 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2301 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2302 return HOTPLUG_HANDLER(machine);
2303 }
2304
2305 return NULL;
2306 }
2307
2308 static void
2309 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
2310 const char *name, void *opaque,
2311 Error **errp)
2312 {
2313 MachineState *ms = MACHINE(obj);
2314 int64_t value = memory_region_size(&ms->device_memory->mr);
2315
2316 visit_type_int(v, name, &value, errp);
2317 }
2318
2319 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
2320 const char *name, void *opaque,
2321 Error **errp)
2322 {
2323 PCMachineState *pcms = PC_MACHINE(obj);
2324 uint64_t value = pcms->max_ram_below_4g;
2325
2326 visit_type_size(v, name, &value, errp);
2327 }
2328
2329 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
2330 const char *name, void *opaque,
2331 Error **errp)
2332 {
2333 PCMachineState *pcms = PC_MACHINE(obj);
2334 Error *error = NULL;
2335 uint64_t value;
2336
2337 visit_type_size(v, name, &value, &error);
2338 if (error) {
2339 error_propagate(errp, error);
2340 return;
2341 }
2342 if (value > 4 * GiB) {
2343 error_setg(&error,
2344 "Machine option 'max-ram-below-4g=%"PRIu64
2345 "' expects size less than or equal to 4G", value);
2346 error_propagate(errp, error);
2347 return;
2348 }
2349
2350 if (value < 1 * MiB) {
2351 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
2352 "BIOS may not work with less than 1MiB", value);
2353 }
2354
2355 pcms->max_ram_below_4g = value;
2356 }
2357
2358 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
2359 void *opaque, Error **errp)
2360 {
2361 PCMachineState *pcms = PC_MACHINE(obj);
2362 OnOffAuto vmport = pcms->vmport;
2363
2364 visit_type_OnOffAuto(v, name, &vmport, errp);
2365 }
2366
2367 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
2368 void *opaque, Error **errp)
2369 {
2370 PCMachineState *pcms = PC_MACHINE(obj);
2371
2372 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
2373 }
2374
2375 bool pc_machine_is_smm_enabled(PCMachineState *pcms)
2376 {
2377 bool smm_available = false;
2378
2379 if (pcms->smm == ON_OFF_AUTO_OFF) {
2380 return false;
2381 }
2382
2383 if (tcg_enabled() || qtest_enabled()) {
2384 smm_available = true;
2385 } else if (kvm_enabled()) {
2386 smm_available = kvm_has_smm();
2387 }
2388
2389 if (smm_available) {
2390 return true;
2391 }
2392
2393 if (pcms->smm == ON_OFF_AUTO_ON) {
2394 error_report("System Management Mode not supported by this hypervisor.");
2395 exit(1);
2396 }
2397 return false;
2398 }
2399
2400 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name,
2401 void *opaque, Error **errp)
2402 {
2403 PCMachineState *pcms = PC_MACHINE(obj);
2404 OnOffAuto smm = pcms->smm;
2405
2406 visit_type_OnOffAuto(v, name, &smm, errp);
2407 }
2408
2409 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name,
2410 void *opaque, Error **errp)
2411 {
2412 PCMachineState *pcms = PC_MACHINE(obj);
2413
2414 visit_type_OnOffAuto(v, name, &pcms->smm, errp);
2415 }
2416
2417 static bool pc_machine_get_nvdimm(Object *obj, Error **errp)
2418 {
2419 PCMachineState *pcms = PC_MACHINE(obj);
2420
2421 return pcms->acpi_nvdimm_state.is_enabled;
2422 }
2423
2424 static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp)
2425 {
2426 PCMachineState *pcms = PC_MACHINE(obj);
2427
2428 pcms->acpi_nvdimm_state.is_enabled = value;
2429 }
2430
2431 static char *pc_machine_get_nvdimm_persistence(Object *obj, Error **errp)
2432 {
2433 PCMachineState *pcms = PC_MACHINE(obj);
2434
2435 return g_strdup(pcms->acpi_nvdimm_state.persistence_string);
2436 }
2437
2438 static void pc_machine_set_nvdimm_persistence(Object *obj, const char *value,
2439 Error **errp)
2440 {
2441 PCMachineState *pcms = PC_MACHINE(obj);
2442 AcpiNVDIMMState *nvdimm_state = &pcms->acpi_nvdimm_state;
2443
2444 if (strcmp(value, "cpu") == 0)
2445 nvdimm_state->persistence = 3;
2446 else if (strcmp(value, "mem-ctrl") == 0)
2447 nvdimm_state->persistence = 2;
2448 else {
2449 error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option",
2450 value);
2451 return;
2452 }
2453
2454 g_free(nvdimm_state->persistence_string);
2455 nvdimm_state->persistence_string = g_strdup(value);
2456 }
2457
2458 static bool pc_machine_get_smbus(Object *obj, Error **errp)
2459 {
2460 PCMachineState *pcms = PC_MACHINE(obj);
2461
2462 return pcms->smbus_enabled;
2463 }
2464
2465 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
2466 {
2467 PCMachineState *pcms = PC_MACHINE(obj);
2468
2469 pcms->smbus_enabled = value;
2470 }
2471
2472 static bool pc_machine_get_sata(Object *obj, Error **errp)
2473 {
2474 PCMachineState *pcms = PC_MACHINE(obj);
2475
2476 return pcms->sata_enabled;
2477 }
2478
2479 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
2480 {
2481 PCMachineState *pcms = PC_MACHINE(obj);
2482
2483 pcms->sata_enabled = value;
2484 }
2485
2486 static bool pc_machine_get_pit(Object *obj, Error **errp)
2487 {
2488 PCMachineState *pcms = PC_MACHINE(obj);
2489
2490 return pcms->pit_enabled;
2491 }
2492
2493 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
2494 {
2495 PCMachineState *pcms = PC_MACHINE(obj);
2496
2497 pcms->pit_enabled = value;
2498 }
2499
2500 static void pc_machine_initfn(Object *obj)
2501 {
2502 PCMachineState *pcms = PC_MACHINE(obj);
2503
2504 pcms->max_ram_below_4g = 0; /* use default */
2505 pcms->smm = ON_OFF_AUTO_AUTO;
2506 pcms->vmport = ON_OFF_AUTO_AUTO;
2507 /* nvdimm is disabled on default. */
2508 pcms->acpi_nvdimm_state.is_enabled = false;
2509 /* acpi build is enabled by default if machine supports it */
2510 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
2511 pcms->smbus_enabled = true;
2512 pcms->sata_enabled = true;
2513 pcms->pit_enabled = true;
2514 }
2515
2516 static void pc_machine_reset(void)
2517 {
2518 CPUState *cs;
2519 X86CPU *cpu;
2520
2521 qemu_devices_reset();
2522
2523 /* Reset APIC after devices have been reset to cancel
2524 * any changes that qemu_devices_reset() might have done.
2525 */
2526 CPU_FOREACH(cs) {
2527 cpu = X86_CPU(cs);
2528
2529 if (cpu->apic_state) {
2530 device_reset(cpu->apic_state);
2531 }
2532 }
2533 }
2534
2535 static CpuInstanceProperties
2536 pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2537 {
2538 MachineClass *mc = MACHINE_GET_CLASS(ms);
2539 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2540
2541 assert(cpu_index < possible_cpus->len);
2542 return possible_cpus->cpus[cpu_index].props;
2543 }
2544
2545 static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
2546 {
2547 X86CPUTopoInfo topo;
2548
2549 assert(idx < ms->possible_cpus->len);
2550 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
2551 smp_cores, smp_threads, &topo);
2552 return topo.pkg_id % nb_numa_nodes;
2553 }
2554
2555 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
2556 {
2557 int i;
2558
2559 if (ms->possible_cpus) {
2560 /*
2561 * make sure that max_cpus hasn't changed since the first use, i.e.
2562 * -smp hasn't been parsed after it
2563 */
2564 assert(ms->possible_cpus->len == max_cpus);
2565 return ms->possible_cpus;
2566 }
2567
2568 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2569 sizeof(CPUArchId) * max_cpus);
2570 ms->possible_cpus->len = max_cpus;
2571 for (i = 0; i < ms->possible_cpus->len; i++) {
2572 X86CPUTopoInfo topo;
2573
2574 ms->possible_cpus->cpus[i].type = ms->cpu_type;
2575 ms->possible_cpus->cpus[i].vcpus_count = 1;
2576 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
2577 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
2578 smp_cores, smp_threads, &topo);
2579 ms->possible_cpus->cpus[i].props.has_socket_id = true;
2580 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
2581 ms->possible_cpus->cpus[i].props.has_core_id = true;
2582 ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
2583 ms->possible_cpus->cpus[i].props.has_thread_id = true;
2584 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
2585 }
2586 return ms->possible_cpus;
2587 }
2588
2589 static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
2590 {
2591 /* cpu index isn't used */
2592 CPUState *cs;
2593
2594 CPU_FOREACH(cs) {
2595 X86CPU *cpu = X86_CPU(cs);
2596
2597 if (!cpu->apic_state) {
2598 cpu_interrupt(cs, CPU_INTERRUPT_NMI);
2599 } else {
2600 apic_deliver_nmi(cpu->apic_state);
2601 }
2602 }
2603 }
2604
2605 static void pc_machine_class_init(ObjectClass *oc, void *data)
2606 {
2607 MachineClass *mc = MACHINE_CLASS(oc);
2608 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2609 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2610 NMIClass *nc = NMI_CLASS(oc);
2611
2612 pcmc->pci_enabled = true;
2613 pcmc->has_acpi_build = true;
2614 pcmc->rsdp_in_ram = true;
2615 pcmc->smbios_defaults = true;
2616 pcmc->smbios_uuid_encoded = true;
2617 pcmc->gigabyte_align = true;
2618 pcmc->has_reserved_memory = true;
2619 pcmc->kvmclock_enabled = true;
2620 pcmc->enforce_aligned_dimm = true;
2621 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2622 * to be used at the moment, 32K should be enough for a while. */
2623 pcmc->acpi_data_size = 0x20000 + 0x8000;
2624 pcmc->save_tsc_khz = true;
2625 pcmc->linuxboot_dma_enabled = true;
2626 assert(!mc->get_hotplug_handler);
2627 mc->get_hotplug_handler = pc_get_hotplug_handler;
2628 mc->cpu_index_to_instance_props = pc_cpu_index_to_props;
2629 mc->get_default_cpu_node_id = pc_get_default_cpu_node_id;
2630 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
2631 mc->auto_enable_numa_with_memhp = true;
2632 mc->has_hotpluggable_cpus = true;
2633 mc->default_boot_order = "cad";
2634 mc->hot_add_cpu = pc_hot_add_cpu;
2635 mc->block_default_type = IF_IDE;
2636 mc->max_cpus = 255;
2637 mc->reset = pc_machine_reset;
2638 hc->pre_plug = pc_machine_device_pre_plug_cb;
2639 hc->plug = pc_machine_device_plug_cb;
2640 hc->unplug_request = pc_machine_device_unplug_request_cb;
2641 hc->unplug = pc_machine_device_unplug_cb;
2642 nc->nmi_monitor_handler = x86_nmi;
2643 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
2644
2645 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
2646 pc_machine_get_device_memory_region_size, NULL,
2647 NULL, NULL, &error_abort);
2648
2649 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
2650 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
2651 NULL, NULL, &error_abort);
2652
2653 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
2654 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort);
2655
2656 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto",
2657 pc_machine_get_smm, pc_machine_set_smm,
2658 NULL, NULL, &error_abort);
2659 object_class_property_set_description(oc, PC_MACHINE_SMM,
2660 "Enable SMM (pc & q35)", &error_abort);
2661
2662 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2663 pc_machine_get_vmport, pc_machine_set_vmport,
2664 NULL, NULL, &error_abort);
2665 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2666 "Enable vmport (pc & q35)", &error_abort);
2667
2668 object_class_property_add_bool(oc, PC_MACHINE_NVDIMM,
2669 pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort);
2670
2671 object_class_property_add_str(oc, PC_MACHINE_NVDIMM_PERSIST,
2672 pc_machine_get_nvdimm_persistence,
2673 pc_machine_set_nvdimm_persistence, &error_abort);
2674
2675 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
2676 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
2677
2678 object_class_property_add_bool(oc, PC_MACHINE_SATA,
2679 pc_machine_get_sata, pc_machine_set_sata, &error_abort);
2680
2681 object_class_property_add_bool(oc, PC_MACHINE_PIT,
2682 pc_machine_get_pit, pc_machine_set_pit, &error_abort);
2683 }
2684
2685 static const TypeInfo pc_machine_info = {
2686 .name = TYPE_PC_MACHINE,
2687 .parent = TYPE_MACHINE,
2688 .abstract = true,
2689 .instance_size = sizeof(PCMachineState),
2690 .instance_init = pc_machine_initfn,
2691 .class_size = sizeof(PCMachineClass),
2692 .class_init = pc_machine_class_init,
2693 .interfaces = (InterfaceInfo[]) {
2694 { TYPE_HOTPLUG_HANDLER },
2695 { TYPE_NMI },
2696 { }
2697 },
2698 };
2699
2700 static void pc_machine_register_types(void)
2701 {
2702 type_register_static(&pc_machine_info);
2703 }
2704
2705 type_init(pc_machine_register_types)
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